july 2003 the following document refers to spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to cu stomers of both amd and fujitsu. continuity of specifications there is no change to this document as a result of offering the device as a spansion product. any changes that have been made are the result of normal documentation impr ovements and are noted in the document revision summary, where supported. future routine revisions will occur when appro- priate, and changes will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with ?am? and ?mbm?. to order these products, please use on ly the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. utilizing 3 v flash in 5 v flash systems application note publication number 22282 revision a amendment 0 issue date november 1, 1998
publication# 22282 rev: a amendment/ 0 issue date: november 1998 8-43 utilizing 3 v flash in 5 v systems application note this document is intended to assist hardware design- ers in adapting 5 v embedded systems for use with low voltage flash devices. systems can benefit from ad- vanced architectures such as simultaneous read/ write (amd dl family), as well as decreased system power requirements. since many new high-density flash devices are being introduced in low voltage ap- plications, systems employing 5 v power planes and signals can benefit from these breakthrough devices. benefits of low voltage flash devices in order to facilitate low power designs, most new flash devices are designed to operate in lower voltage sys- tems (primarily systems using a 2.7 v to 3.6 v voltage source). low voltage systems are often battery pow- ered, needing components designed to draw low active current, with standby current requirements of less than 1 a per device. the latest generation of low voltage flash devices are manufactured using revolutionary 0.32 and 0.25 m process technologies, which provide for faster access times and lower power consumption. on average, 3 v am29lvxxx devices consume about 50% less current than the equivalent 5 v am29fxxx de- vices, in terms of active reads and writes. this correlates to an average sixty percent decrease in power consump- tion during active reads and writes. for systems designed for reduced power requirements, migrating from 5 v memory subsystems to 3 v can reduce overall power dissipation and parasitic heat generation. perhaps the greatest benefit is the inclusion of the ad- vanced architectural features, available in newer generation devices, into designs that previously could not support these low voltage family devices. amd?s true simultaneous read/write architecture (dl family) is available in 2.7 v technology devices, not 5 v. the si- multaneous read/write architecture allows code to be executed from the same physical memory as data, while being programmed or erased. this allows system designers to reduce or eliminate separate memory components like eprom, sram, or eprom, which would have been needed to separate programming code or data storage from the traditional flash memory system. now a single flash memory can serve both code and data storage needs. other enhancements available newer 2.7 v flash devices (but not in the 5.0 v flash devices) include 1 million erase cycle en- durance, enhanced control over sector protection, high security sectors, faster programming modes, and higher density with x8/x16 bus width. in addition to new architectures, a myriad of new pack- aging possibilities exist in low voltage devices. for systems that place a premium on system board space, the new generation of chip scale packaging offer greatly reduced package area requirements. this in- cludes fine-pitch ball grid array (fbga) and micro ball grid array (bga?) packages. however, most 5 v flash devices are not supported in these new ?small form factor? device packages. migration factors there are two main areas of concern when designing low voltage flash into 5 v systems. first, the 5 v power plane must be regulated down to the lower voltage supply requirements of the flash device. second, the 5 v signals that control the flash device (including data, address, and control signals, all at ttl levels) must be limited so as not to exceed the supply voltage provided to the flash mem- ory, without altering the function of the system. ideally, this voltage translation interface should be inexpensive, and require as little board area as possible. signal voltage level isolation/translation since amd low voltage flash is not 5v i/o tolerant (the only exception to this rule is the burst mode (bl) and page mode (pl) families), there must exist an interface that translates incoming control, data, and address sig- nals from 5 v i/o voltage levels down to 3 v. (amd low voltage flash devices are not 5 v i/o tolerant in order to minimize die size as well as to decrease leakage current). a common way of accomplishing this is through the use of a voltage level translator ic. the devices in the 74lcx244 and 74lcx245 low power, low voltage cmos families are ideal for this purpose. the 244 de- vices are unidirectional buffers/line drivers with 5 v tolerant i/o pins, suitable for address and control signal translation. the 245 family devices are bi-directional bus transceivers used for input/output data pins. thus through use of both these ics, all signal, address, and data lines can be level translated, with the additional benefit of a buffering layer to the rest of the system.
8-44 utilizing 3 v flash in 5 v systems the first step is to determine the total number of unidi- rectional buffer pins required by the system. there are 4 signal control pins (we#, oe#, ce# and reset#), and depending on the device density, between 17 and 23 address lines. figure 1 illu strates the connection of the first 16 address lines from the 5 v-address bus to the 3 v flash address pins. since the flash address and control pins are input only, the output enable lines of the buffer can be tied to ground, simplifying the control circuitry. figures 1 and 2 outline the connections for 20 address lines, along with the 4 required control signal lines. for systems employing multiple flash devices, it will be nec- essary to substitute the 16 bit version (74lcx16244) for the second buffer (74lcx244) in order to accommo- date additional chip select signals. the address and control signal system will require at maximum 27 translation lines, with 1 additional line for each device added to the system. figure 1. address translation circuitry (first 16 address lines) figure 2. address and control signal connections note: the a9, oe#, and reset# pins on amd flash devices are used in high voltage programming and autoselect modes, and are 12 v tolerant. if the system design requires additional translation pins, these three pins can be directly connected to 5 v signals, thereby freeing three translation lines for use by additional address/control signals. this can save expense by preventing the requirement of additional buffer ics. on the data side, the system requires a low voltage, 5 v tolerant transceiver/buffer, to allow for bi-directional data travel. the lcx family contains the 74lcx245 and 74lcx16245 for this purpose. in most ways, they function in the same way as the address buffers above, but they contain additional switch logic to distinguish between reads and writes from/to the flash device. see figure 3. figure 3. data bus transceiver i0 i1 i2 i3 i4 i5 i6 i7 i8 i9 i10 i11 i12 i13 i14 i15 oe1 o0 o1 o2 o3 oe2 o4 o5 o6 o7 oe3 o8 o9 o10 o11 oe4 o12 o13 o14 o15 74lcx16244 system address bus (5 v signals) flash address bus (3 v signals) to 3v v cc plane v cc i0 i1 i2 i3 i4 i5 i6 i7 oe1 o0 o1 o2 o3 oe2 o4 o5 o6 o7 74lcx244 system address bus flash address bus to 3v v cc plane reset# we# oe# ce# system reset# system write system read chip select logic v cc t/-r1 a0 a1 a2 a3 a4 a5 a6 a7 t/-r2 a8 a9 a10 a11 a12 a13 a14 a15 oe1 b0 b1 b2 b3 b4 b5 b6 b7 74lcx16245 system data (0...15) flash data (0...15) to 3v v cc plane v cc b12 b13 b14 b15 oe2 b8 b9 b10 b11 system w/r# 5 v signals 3 v signals flash chip select (ce#)
utilizing 3 v flash in 5 v systems 8-45 note: certain systems do not have a direct implementation of the w/r# signal. this signal distinguishes between a bus read and a bus write cycle. this signal can be synthesized from the system read and system write signals outlined in figure 2 with the circuit (assumes system read and sys- tem write are active low) in figure 4. figure 4. w/r# control circuitry it may also be possible to use the system read signal directly, so long as the system cannot assert both the read and write signals simultaneously. v cc power plane isolation to supply the correct operating voltage to the flash de- vice and the voltage translation buffers, the 5 v power plane must be regulated to 2.7-3.6 v nominal. this can be accomplished in several ways, depending on sys- tem board space and cost requirements. the simplest method of accomplishing this is to use three silicon diodes to provide an approximate 2.1 v drop from 5 v (yielding a v cc voltage of around 3 v). however, the nominal 5 v supply must be regulated to within 5% to ensure that the diode reduced voltage re- mains within the 2.7 v to 3.6 v range. capacitors c1 and c2 provide voltage conditioning, and keep the di- odes properly biased in case of v cc power glitches. see figure 5. virtually any silicon diode will function properly in this circuit: form factor or cost per unit will be the main driv- ing factors in selecting an appropriate diode. suggested parts are 1n4148 or 1n914. figure 5. voltage regulation using silicon diodes regulation can also be accomplished through use of a dedicated voltage regulator ic. fixed linear regulators from linear technologies, such as the lt1117cst-3.3, produce excellent results due to low load regulation. c1 and c2 provide transient stability to filter voltage fluctuations, as are taken from recommended values. resistor r1 provides a minimum load current of 1 ma, which is the minimum current draw at which the device guarantees regulation. see figure 6. figure 6. voltage regulation using fixed regulator ic of particular note is the current limiting protection of the regulators versus the diodes only solution. the lt1117 has internal over-current protection circuitry that will protect system components in case of power surges on the 5 v v cc power plane. this protection may justify the additional cost of the regulators over the diode so- lution, in systems that have strict power protection requirements. most regulators also have thermal shut- down benefits to prevent system damage due to excessive currents. the regulator may also be neces- sary in systems that cannot regulate the 5 v supply to within 5% tolerance. system read system write w/r# 5 v ~ 2.9 v d1 d2 d3 c1 0.1 f c2 0.1 f 5 v 3.3 v c1 10 f c2 22 f lt1117cst-3.3 32 1 gnd in out r1 3.3k
8-46 utilizing 3 v flash in 5 v systems
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