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TC9204M preliminary dat a sheet 4 - p o r t 10/100/1000 s m a r t e t h e r n e t s w i t c h features stand alone switch on a chip 4 ethernet 10/100/1000 ports mii/gmii interfac e for all ports four cl asse s of service (cos) sele cta b le for each port an d/or ch ecke d via ip head er and 802.1q vlan tag support 4 port-based vlans maximum throu ghp ut (wire spe e d ) , non head-of-line blocking architecture embedd ed ssram for packet bu ffer / address table, no external memory required 8k mac address table 25 mhz crystal input only each port i s configurable to 10 full/half d uplex, 100 full/half d uplex an d 10 00 full du plex mode flow-control ability is able to set for both full and half duplex mode broadcast throttling port mirroring s e rial eeprom interface, eeprom is optional mdio master for phy configuration / polling 0.18 micron technology 2.0v and 3.3v dual voltage power supply packaged in pqfp 208 general description tc92 04m is a fully integra t ed 4-port 10/100/10 00 sma r t e t hern e t swit ch con t roller de sig n ed f o r low co st and hig h perfo rman ce solution s. the chip embed s ne cessary ssra m for p a cket buf fering and mac ad dre ss t a ble. it provides mii / gmii interface for all port s . a store-and -f orward swit ching method using a non-blo cki ng archite c ture is implemen ted within tc92 04m t o improve the availability and band wi d t h. the chip e m bed s ssram p a cket buf fer , which it sup port s norm a l an d pri o rity queues for each transmission port. tc92 04m p r ovides evolv ed cos with four levels of priority . the priority can be che c ked via layer 2 (802.1 q vla n t aggin g ) a nd/or laye r 3 (ip head er t o s bit s ) p a cket s. port based p r io rity is also provide d to ensu r e tra n smi ssi on with p r ece den ce for all p a cke t s in comi ng from sele cte d port ( s). this fe ature allows im proved su p port for multimedia applications. the chip em bed s ieee 802.3 mac function s for each port and these functio n s sup p o r t full and half duplex mo de s for b o th 10 and 1 00 mb it s/s d a t a rates and full duplex fo r 1 000 mbit/ s . each p o rt inclu d e s dedi cated receive and tran smit fifos with ne ce ssa r y logi c to im plement flo w control for both full an d half dupl ex mode s. tc92 04m u s e s ieee 802.3x frame based flow cont rol for full duplex and backpressure for half duplex. tc92 04m ha ndle s an 8k add re ss-loo kup t able with sea r chi n g, self-l earnin g , and a u tom a tic agi ng at very high spe ed and e x cellent add ress sp ace coverage. f o rwarding ru les are imp l emented according to ieee 802.1d sp ecifications. filtering ca p abilitie s f o r b ad p a cket s and p a cket s with reserved group address da are also provided. a por t mirr or fe a t ur e , op tiona lly includ ing b a d fra m es , can be used for debugging network problems. the pi n co nfiguratio n i n terface co mpri se s 40 config uratio n s , which are share d with gmii output pins by latching the co nfiguratio n dat a durin g reset. an external eep rom device can al so b e use d to confi gure the t c 9 204m at power-up. with referen c e to pin co nfig uration i n terface, the eeprom extends the chip? s configuration ca p ability wi th new fe ature s an d e nable s a jumpe r-le s s config uratio n mode using a p a rallel interface for rep r og ram m i ng. a virtua l intern al eeprom mode is also provided to enabl e the use of the progra mming in terface in the abse n ce of external eeprom. TC9204M can make ef fective use by most of it s feature s usin g only the pin configuration interface. tc92 04m in clude s a physi cal layer confi guratio n / polling entity , whi c h it i s u s e to co nfigu r e the phy function s an d to monitor the physical layer transceive r ? s spe ed, duple x mode, link st atu s and full duplex flow cont rol abil i ty for each port. the chip p r ovide s four mod e s for phy co nfiguratio ns, whi c h these modes in clude auto - n egotiation disa ble p r o c e dure fo r 10/1 00 sp eed m o des. th e phy config u r ation info rmation is store d in eeprom s e tting. confidential. 1/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet the chip re q u ire s a 25 m h z syste m cl ock, dual 2.0v and 3.3 v power sup p l y and it is p a ckage d in 208 pqfp . block diagram fro m rx m a c 4 g m i i/m ii rx/ t x m a c' s a ddress loocku p & re s o l u t i o n un i t me m o r y int e rfac e & ar b i t e r q ueue m a n agem en t e e prom in terfa c e c onfi gurati o n regi st er e x t e r n a l phy' s TC9204M b l ock d i agram md i o in t e r f a c e to tx m a c r x fi fo tx fif o co nt r o l internal ssram bu f f e r confidential. 2/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet t a ble of content s features ....................................................................................................................... ....................................... 1 general description ............................................................................................................ ................................ 1 block diagram .................................................................................................................. ................................... 2 t a ble of cont ent s .............................................................................................................. ................................. 3 revis i on his t ory ............................................................................................................... ................................... 4 pins p l acement ................................................................................................................. .................................. 5 1 pin lis t ing (p qfp 2 08) .......................................................................................................... ...................... 6 2 ethernet media a ccess cont roller ............................................................................................... ............. 1 4 2.1 rec e ive mac .................................................................................................................... .1 4 2.2 t r ans m it ma c ................................................................................................................... .1 5 3 ma c a d dress handling ........................................................................................................... .................. 1 6 4 queue management ............................................................................................................... .................. 1 6 5 classes of s e rvice ............................................................................................................. ....................... 17 6 flow cont rol ................................................................................................................... ........................... 1 9 7 broadcas t throttling ........................................................................................................... ....................... 21 8 port mirroring ................................................................................................................. ............................ 2 1 9 phy s ical lay er configurat ion / p o lling ......................................................................................... ............. 22 10 eeprom int e rf ac e ............................................................................................................... .................... 23 10.1 reprogramming the eeprom for rec o nfi guration ............................................................ 23 10.2 eeprom addres s map ..................................................................................................... 24 10.3 regis t er de sc ription ........................................................................................................... 26 10.3.1 v a lidation re gis t er ................................................................................................ 26 10.3.2 port [ x ] configuratio n regis t er ............................................................................. 28 10.3.3 port [ x ] ifg configurati on regis t er ................................................................... 30 10.3.4 flow control regis t er ........................................................................................... 31 10.3.5 bac k press u re t i me v a lue regi s t er ....................................................................... 33 10.3.6 flow control port bas e addres s regis t er ............................................................ 33 10.3.7 broadc a s t configur ation regis t er ......................................................................... 34 10.3.8 ip priority m apping regi ster ................................................................................. 35 10.3.9 vlan priority m apping regi ster ........................................................................... 36 10.3.10 cos bandwid t h regis t er ....................................................................................... 37 10.3.1 1 res e rved regis t er ................................................................................................ 37 10.3.12 cos configurati on regis t er .................................................................................. 38 10.3.13 port mirrori ng regis t er .......................................................................................... 39 10.3.14 general conf igurat ion regis t er ............................................................................ 40 10.3.15 port vlan enabl e regi st er .................................................................................. 41 10.3.16 vlan [ y ] regis t er ................................................................................................. 41 10.4 w r iting / reading phy managem ent re gisters via eeprom interface ............................. 42 10.4.1 dat a w r ite regis t er ............................................................................................... 42 10.4.2 phys ic al layer devic e addres s regis t er .............................................................. 42 10.4.3 phys ic al layer ? s regis t er address regis t er ......................................................... 43 10.4.4 io s t atus contro l regi s t er.................................................................................. 43 10.4.5 dat a read regis t er .............................................................................................. 44 11 t i ming requirement s ............................................................................................................ .................... 4 5 11 . 1 gmii / mii rec e ive t i mi ng requir ement s .......................................................................... 45 11 . 2 gmii / mii t r ans mit t i ming ................................................................................................. 45 11 . 3 phy management (m dio) t i ming ..................................................................................... 46 11 . 4 eeprom t i ming ................................................................................................................ 47 12 elec t r ical s pec if ic at ions ...................................................................................................... ...................... 4 8 12.1 absolute maximu m ra tings ..................................................................................... 48 12.2 recommended ope r a t ing condi t ions ................................................................ 48 confidential. 3/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet 12.3 dc cha racter istics ................................................................................................... 48 13 pack age det a il ................................................................................................................. ......................... 49 revision history rev i sion # change description t c 9 2 0 4 - d s - r 0 4 tc9204-ds-r05 1. modify ?pin latched? fi eld in class of service section. 2. correct the register map of ?broadcast configuration register? 3. correct the junction temperature limit. confidential. 4/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet pins placement 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 gtx c k v dd 2. 0 bc s t l e d o v u nle d vs s 2 . 0 sy s c k res e t t x d27 t x d26 t x d25 t x d24 t x d23/ p r i b ndw 1 v dd 2. 0 t x d22/ p r i b ndw 0 t x d21/ p r i c l a s s 2 1 t x d20/ p r i c l a s s 2 0 t x en2 gt x c l k 2 vs s 2 . 0 tx e r 2 tx c l k2 cr s 2 co l 2 rx er 2 v dd 3. 3 r x cl k2 53 54 5 5 56 57 5 8 59 60 61 62 63 64 65 6 6 67 68 6 9 70 7 1 72 73 74 75 76 77 7 8 79 80 8 1 82 8 3 84 85 86 87 88 89 9 0 91 92 93 9 4 95 96 9 7 98 99 100 101 102 103 104 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 nc nc nc nc v dd 3. 3 t x d67 t x d66 t x d65 v ss 3 . 3 t x d64 t x d63 t x d62 v dd 3. 3 txd 6 1 / p r ic la s s 6 1 txd 6 0 / p r ic la s s 6 0 t x en6 gt x c l k 6 v ss 3 . 3 tx e r 6 t x cl k6 cr s 6 co l 6 rx e r 6 v dd 2. 0 r x cl k6 rx dv 6 171 17 2 173 17 4 17 5 176 177 178 179 180 18 1 182 183 18 4 185 18 6 18 7 188 189 190 191 192 19 3 194 195 19 6 197 19 8 19 9 200 201 202 203 204 20 5 206 207 20 8 157 158 15 9 160 16 1 16 2 163 16 4 165 166 167 168 169 170 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 rx dv 2 rx d20 rx d21 rx d22 vs s 3 . 3 rx d23 rx d24 rx d25 rx d26 rx d27 en l p p r ip to s m ap 1 ip to s m ap 0 en vl a n pr vl anpr map 1 v dd 3. 3 vl anpr ma p 0 vs s 3 . 3 gn d v dd 2. 0 gn d nc nc nc nc nc 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 rx d60 rx d61 rx d62 v ss 2 . 0 rx d63 rx d64 rx d65 rx d66 rx d67 v dd 3. 3 v ss 3 . 3 v dd 2. 0 v ss 2 . 0 v dd 3. 3 gn d v ss 3 . 3 gn d v dd 3. 3 v ss 3 . 3 nc nc nc nc nc nc nc TC9204M v d d 3.3 tx d 0 7 tx d 0 6 tx d 0 5 v ss 3 . 3 tx d 0 4 tx d 0 3 tx d 0 2 v d d 3.3 t x d0 1/ pr i c la s s 0 1 t x d0 0/ pr i c la s s 0 0 tx e n 0 gtxc l k 0 v ss 3 . 3 tx e r 0 t xclk0 cr s 0 co l 0 rx er0 v d d 2.0 r xclk0 rx dv 0 rx d0 0 rx d0 1 rx d0 2 v ss 2 . 0 rx d0 3 rx d0 4 rx d0 5 rx d0 6 rx d0 7 v d d 3.3 v ss 3 . 3 v d d 2.0 v ss 2 . 0 v d d 3.3 gn d v ss 3 . 3 gn d v d d 3.3 se l s c k nc nc nc nc nc nc nc nc nc nc nc tes t i n t sd a sc l v ss 2 . 0 mdi o md c v d d 2. 0 nc nc nc nc gn d v ss 2 . 0 gn d v d d 2. 0 disb pb k disf d f c v ss 3 . 3 frc f d f c nc disbk p r c a rrb p f u llb p v d d 3. 3 rx d 4 7 rx d 4 6 rx d 4 5 rx d 4 4 rx d 4 3 rx d 4 2 rx d 4 1 rx d 4 0 rx d v 4 r xclk4 v ss 3 . 3 rx er 4 co l4 cr s4 txclk4 tx e r 4 v d d 3. 3 gtxclk4 t x en 4/ re jr d a txd4 0/p r icla ss40 txd4 1/p r icla ss41 t x d 4 2 / en po rt pr v ss 2 . 0 tx d 4 3 txd4 4/fc b cst e n t x d 45/ f c b c s t m ode tx d 4 6 /o b m t e st txd4 7/b cstt h ro t confidential. 5/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet 1 pin listing (pqfp208) i ? digit a l input i s ? schmitt trigger digit a l input i pd ? digit a l input with internal pull down i/o ? digit a l bi-directional i/o pd ? digit a l bi-directional with internal pull down i/o pu ? digit a l bi-directional with internal pull up o ? digit a l output p ? power g ? ground no. pin label ty p e description 1 nc na reserved for future use 2 nc na reserved for future use 3 nc na reserved for future use 4 nc na reserved for future use 5 vdd 3.3 p digit a l +3.3v power supply for i/o 6 txd67 o gmii transmit dat a - bit s 7 7 txd66 o gmii transmit dat a - bit s 6 8 txd65 o gmii transmit dat a - bit s 5 9 vss 3.3 g digit a l ground for i/o 10 txd64 o gmii transmit dat a - bit s 4 1 1 txd63 o gmii/mii transmit dat a - bit s 3 12 txd62 o gmii/mii transmit dat a - bit s 2 13 vdd 3.3 p digit a l +3.3v power supply for i/o txd61 gmii/mii transmit dat a - bit 1 14 priclass61 i/o pd p r iorit y class - most signif i cant bit . txd60 gmii/mii transmit dat a - least significant bit 15 priclass60 i/o pu priority class - least significant bi t. set s priority level per port bas is . priclass[6] - '00' - port 6 low priority priclass[6] - '01' - port 6 has normal priority priclass[6] - '10' - port 6 has high priority priclass[6] - '1 1' - port 6 has very high priority priclass[6] is latched on reset 16 txen6 o gmii/mii transmit enable 17 gtxclk6 o gmii transmit clock 18 vss 3.3 g digit a l ground for i/o 1 9 t x e r 6 i/o pd t r ansmit e r r o r 20 txc l k 6 i mii trans mit c l oc k 2 1 c r s 6 i s mii carrier sense indication 2 2 c o l 6 i s mii collision indication 2 3 r x e r 6 i s r e c e i v e e r r o r 24 vdd 2.0 p digit a l +2.0v power supply for core 25 rx clk6 i mi i receiv e clock 2 6 r x d v 6 i s gmii/mii dat a valid 2 7 r x d 6 0 i s gmii receive dat a - least significant nibble. mii receive dat a 2 8 r x d 6 1 i s gmii receive dat a - least significant nibble. mii receive dat a confidential. 6/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet pin listing (continued) no. pin label ty p e description 2 9 r x d 6 2 i s gmii receive dat a - least significant nibble. mii receive dat a 30 vss 2.0 g digit a l ground for core 3 1 r x d 6 3 i s gmii receive dat a - least significant nibble. mii receive dat a 3 2 r x d 6 4 i s gmii receive dat a - most significant nibble 3 3 r x d 6 5 i s gmii receive dat a - most significant nibble 3 4 r x d 6 6 i s gmii receive dat a ? most significant nibble 3 5 r x d 6 7 i s gmii receive dat a ? most significant nibble 36 vdd 3.3 p digit a l +3.3v power supply for i/o 37 vss 3.3 g digit a l ground for i/o 38 vdd 2.0 p digit a l +2.0v power supply for core 39 vss 2.0 g digit a l ground for core 40 vdd 3.3 p digit a l +3.3v power supply for i/o 4 1 g n d i 42 vss 3.3 g digit a l ground for i/o 4 3 g n d i 44 vdd 3.3 p digit a l +3.3v power supply for i/o 45 vss 3.3 g digit a l ground for i/o 46 nc na reserved for future use 47 nc na reserved for future use 48 nc na reserved for future use 49 nc na reserved for future use 50 nc na reserved for future use 51 nc na reserved for future use 52 nc na reserved for future use 53 vdd 3.3 p digit a l +3.3v power supply for i/o 54 txd07 o gmii transmit dat a ? bit s 7 55 txd06 o gmii transmit dat a ? bit s 6 56 txd05 o gmii transmit dat a ? bit s 5 57 vss 3.3 g digit a l ground for i/o 58 txd04 o gmii transmit dat a ? bit s 4 59 txd03 o gmii/mii transmit dat a ? bit s 3 60 txd02 o gmii/mii transmit dat a ? bit s 2 61 vdd 3.3 p digit a l +3.3v power supply for i/o txd01 gmii/mii transmit dat a ? bit 1 62 priclass01 i/o pd priority class ? most significant bit. txd00 gmii/mii transmit dat a ? least significant bit 63 priclass00 i/o pu priority class ? least significant bi t. set s priority level per port bas is . priclass[0] ? ?00? ? port 0 has low priority priclass[0] ? ?01? ? port 0 has normal priority priclass[0] ? ?10? ? port 0 has high priority priclass[0] ? ?1 1? ? port 0 has very high priority priclass[0] is latched on reset confidential. 7/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet pin listing (continued) no. pin label ty p e description 64 txen0 o gmii/mii transmit enable 65 gtxclk0 o gmii transmit clock 66 vss 3.3 g digit a l ground for i/o 6 7 t x e r 0 i/o pd t r ansmit e r r o r 68 txc l k 0 i mii trans mit c l oc k 6 9 c r s 0 i s mii carrier sense indication 7 0 c o l 0 i s mii collision indication 7 1 r x e r 0 i s r e c e i v e e r r o r 72 vdd 2.0 p digit a l +2.0v power supply for core 73 rx clk0 i mi i receiv e clock 7 4 r x d v 0 i s gmii/mii dat a valid 7 5 r x d 0 0 i s gmii receive dat a ? least significant nibble. mii receive dat a 7 6 r x d 0 1 i s gmii receive dat a ? least significant nibble. mii receive dat a 7 7 r x d 0 2 i s gmii receive dat a ? least significant nibble. mii receive dat a 78 vss 2.0 g digit a l ground for core 7 9 r x d 0 3 i s gmii receive dat a ? least significant nibble. mii receive dat a 8 0 r x d 0 4 i s gmii receive dat a ? most significant nibble 8 1 r x d 0 5 i s gmii receive dat a ? most significant nibble 8 2 r x d 0 6 i s gmii receive dat a ? most significant nibble 8 3 r x d 0 7 i s gmii receive dat a ? most significant nibble 84 vdd 3.3 p digit a l +3.3v power supply for i/o 85 vss 3.3 g digit a l ground for i/o 86 vdd 2.0 p digit a l +2.0v power supply for core 87 vss 2.0 g digit a l ground for core 88 vdd 3.3 p digit a l +3.3v power supply for i/o 8 9 g n d i 90 vss 3.3 g digit a l ground for i/o 9 1 g n d i 92 vdd 3.3 p digit a l +3.3v power supply for i/o 9 3 s e l s c k i s s e lect s t he source f o r t he sy st em clock. s e lsck ? ?1? ? sy sck is driv en by a 25mhz ex t e rnal clock. 94 nc na reserved for future use 95 nc na reserved for future use 96 nc na reserved for future use 97 nc na reserved for future use 98 nc na reserved for future use 99 nc na reserved for future use 100 nc na reserved for future use confidential. 8/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet pin listing (continued) no. pin label ty p e description 101 nc na reserved for future use 102 nc na reserved for future use 103 nc na reserved for future use 104 nc na reserved for future use 105 gtxck i t h e 1 2 5 m h z r e f e r e n c e c l o c k f o r 1 0 0 0 m b p s operating mo de. this clo c k is used as a reference clock for the gmii transmission clock for every port. 106 vdd 2.0 p digit a l +2.0v power supply for core 1 0 7 b c s t l e d i/o pd the led can sign al either filteri ng of broad ca st fram es. also the l e d remains lit if the post tes t fails , whic h indic a tes a faulty c h ip. 108 ovunled o t h e l e d i s l i t w henever a u n icast p a cket s overflow co ndition is reached and some frames are dropped by the buf fer management engine. 109 vss 2.0 g digit a l ground for core 1 10 s y sck i the 25mhz sy st em clock. 111 r e s e t i pus general reset. active low . 1 1 2 t x d 2 7 i/o pd gmii transmit dat a - most significant bit 1 1 3 t x d 2 6 i/o pd gmii transmit dat a - bit 6 1 1 4 t x d 2 5 i/o pd gmii transmit dat a - bit 5 1 15 txd24 o gmii transmit dat a - bit 4 txd23 gmii/mii transmit dat a - bit 3 1 16 pribndw1 i/o pd priority bandwid th configuration pins. pribndw(1)is latched on reset 1 17 vdd 2.0 p digit a l +2.0v power supply for core txd22 gmii/mii transmit dat a - bit 2 1 18 pribndw0 i/o pu priority ba ndwid th configu r at ion pin s . th ese co nfigu r atio n pin s allo w t h e band wi d t h percent age a s sig ned to a p rio r ity p a cket queu e to be modifie d to cert ain ha rdwi re d levels. pribndw ch ooses betwe en 4 hardwi r ed spreading percent age schemes among t he 4 priority queues of each port. pribndw(0)is latched on reset txd21 gmii/mii transmit dat a - bit 1 priclass[2] is latched on reset 1 19 priclass21 i/o pd p r iorit y class - most signif i cant bit . txd20 gmii/mii transmit dat a - least significant bit 120 priclass20 i/o pu priority class - least significant bi t. set s priority level per port bas is . priclass[2] - '00' - port 2 low priority priclass[2] - '01' - port 2 has normal priority priclass[2] - '10' - port 2 has high priority priclass[2] - '1 1' - port 2 has very high priority priclass[2] is latched on reset 121 txen2 o gmii/mii transmit enable 122 gtxclk2 o gmii transmit clock 123 vss 2.0 g digit a l ground for core 1 2 4 t x e r 2 i/o pd t r ansmit e r r o r 125 txclk2 i mii transmit clock 1 2 6 c r s 2 i s mii carrier sense indication confidential. 9/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet pin listing (continued) no. pin label ty p e description 1 2 7 c o l 2 i s mii collision indication 1 2 8 r x e r 2 i s r e c e i v e e r r o r 129 vdd 3.3 p digit a l +3.3v power supply for i/o 130 rxclk2 i mii receive clock 1 3 1 r x d v 2 i s gmii/mii dat a valid 1 3 2 r x d 2 0 i s gmii receive dat a - least significant nibble. mii receive dat a 1 3 3 r x d 2 1 i s gmii receive dat a - least significant nibble. mii receive dat a 1 3 4 r x d 2 2 i s gmii receive dat a - least significant nibble. mii receive dat a 135 vss 3.3 g digit a l ground for i/o 1 3 6 r x d 2 3 i s gmii receive dat a - least significant nibble. mii receive dat a 1 3 7 r x d 2 4 i s gmii receive dat a - most significant nibble 1 3 8 r x d 2 5 i s gmii receive dat a - most significant nibble 1 3 9 r x d 2 6 i s gmii receive dat a - most significant nibble 1 4 0 r x d 2 7 i s gmii receive dat a - most significant nibble 1 4 1 e n l p p r i/o pd enable s ip prio ritizatio n . cos re solutio n will con s id er t o s precedence bit s from ip header . ?1? ? ip priority will be t a ken into consideration ?0? ? ip priority will be neglected enippr is latched on reset 1 4 2 i p t o s m a p 1 i/o pd ip type of service mapping - the most significant bit ipt o smap(1) is latched on reset 1 4 3 i p t o s m a p 0 i/o pu ip type o f ser v ice mapping - t he leas t sig n ifican t bit. th is configuratio n chooses between 4 hard-wired mapping schemes for the associatio ns of ip priority within the received p a cket and one o f th e 4 prior i ty le vels set b y pricla ss. the resolution func tion is used for the final priority class if the receiving port alread y has a priority le vel assigned b y priclass configuration, or the vlan prioritiz a tion is ac tive. ipt o smap(0) is latched on reset. 1 4 4 e n v l a n p r i/o pu enable s vlan prio ritizatio n . cos resolu tion will con s i der u s er p r iority bit s (tci field) from 802.1q vlan t ag header . ?1? ? vlan priority will be t a ken into consideration ?0? ? vlan priority will be neglected envlanpr is latched on reset 1 4 5 v l a n p r m a p 1 i/o pu vlan priority mapping vlanprmap(1)is latched on reset. 146 vdd 3.3 p digit a l +3.3v power supply for i/o confidential. 10/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet pin listing (continued) no. pin label ty p e description 1 4 7 v l a n p r m a p 0 i/o pu vlan priority mapping this co nfigu r ation cho o se s betwe en 4 hard - wire d mappin g sch e m es for the a s sociations of vl an prio rity wi thin the re cei v ed p a cket a n d one of the 4 prio rity levels set by pricla ss. the re sol u tion function is use d for the final priority class if the receiving po rt already ha s a prio rity level assig ned b y pricla ss config uratio n, or the vl an prioritiz a tion is ac tive. vlanprmap(0)is latched on reset. 148 vss 3.3 g digit a l ground for i/o 1 4 9 g n d i 150 vdd 2.0 p digit a l +2.0v power supply for core 1 5 1 g n d i 152 nc na reserved for future use 153 nc na reserved for future use 154 nc na reserved for future use 155 nc na reserved for future use 156 nc na reserved for future use txd47 gmii transmit dat a - bit 7 157 b cst throt i/o pd enables broadcast throttling. '1' ? enable '0' ? disable bcstthrot is latched on reset. 1 5 8 t x d 4 6 i/o pd gmii transmit dat a - bit 6 txd45 gmii transmit dat a - bit 5 159 fcbcstmode i/o pd this pin ch an ges the flow control thre shold? s behavi our if pin 160 is set to logic 1 (it enables broadcast function). ' 1 ' ? on ly th e flow c o n t ro l thres h o l d o n the b r oa dcas t qu eu e is co nsidere d ' 0' ? flow control threshold s a s soci ated to each sou r ce p o r t originatin g the broadcast frames are considered fcbcstmode is latched on reset. txd44 gmii transmit dat a - bit 4 160 fcb cst e n i/o pd enables/disables flow cont rol for broadcast p a cket s . '1' ? enabled '0' ? disabled fcbcsten is latched on reset. 1 6 1 t x d 4 3 i/o pd gmii/mii trans mit dat a - bit 3 162 vss 2.0 g digit a l ground for core 1 6 3 t x d 4 2 i/o pd gmii/mii trans mit dat a - bit 2 txd41 gmii/mii transmit dat a - bit 1 164 priclass41 i/o pd p r iorit y class - most signif i cant bit . priclass[4] is latched on reset. confidential. 1 1 /49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet pin listing (continued) no. pin label ty p e description txd40 gmii/mii transmit dat a - least significant bit 165 priclass40 i/o pd priority class - least significant bi t. set s priority level per port bas is . priclass[4] - '00' - port 4 low priority priclass[4] - '01' - port 4 has normal priority priclass[4] - '10' - port 4 has high priority priclass[4] - '1 1' - port 4 has very high priority priclass[4] is latched on reset txen4 gmii/mii transmit enable 166 rejrda i/o pd if this pin is set to '1' then all frames with 802.1 d re serve d group addre s s o r 8 02.3x full du plex p a use operation da will be filtered out. this set t ing is p r ovi ded for te sti ng pu rpo s e s only and it is recommended to set high during normal operation. rejrda is latched on reset. 167 gtxclk4 o gmii transmit clock 168 vdd 3.3 p digit a l +3.3v power supply for i/o 1 6 9 t x e r 4 i/o pd t r ansmit e r r o r 170 txclk4 i mii transmit clock 1 7 1 c r s 4 i s mii carrier sense indication 1 7 2 c o l 4 i s mii collision indication 1 7 3 r x e r 4 i s r e c e i v e e r r o r 174 vss 3.3 g digit a l ground for i/o 175 rxclk4 i mii receive clock 1 7 6 r x d v 4 i s gmii/mii dat a valid 1 7 7 r x d 4 0 i s gmii receive dat a - least significant nibble. mii receive dat a 1 7 8 r x d 4 1 i s gmii receive dat a - least significant nibble. mii receive dat a 1 7 9 r x d 4 2 i s gmii receive dat a - least significant nibble. mii receive dat a 1 8 0 r x d 4 3 i s gmii receive dat a - least significant nibble. mii receive dat a 1 8 1 r x d 4 4 i s gmii receive dat a - most significant nibble 1 8 2 r x d 4 5 i s gmii receive dat a - most significant nibble 1 8 3 r x d 4 6 i s gmii receive dat a - most significant nibble 1 8 4 r x d 4 7 i s gmii receive dat a - most significant nibble 185 vdd 3.3 p digit a l +3.3v power supply for i/o 1 8 6 f u l l b p i/o pd duri ng the normal op erati on, the bac kpre ssure pro c e ss is exe c uted until flow control con d itio n disapp ea rs or until the time limit fo r backp re ssure is rea c he d. t he ba ckpressure time li mit is ba se d in th e eeprom? s bpt i m e v a lue register . when this configuration is ?0? t he backpressure proc ess will al so be limited from excee d ing 2 8 - co nsecut ive colli sion s. th e default value (28) can be changed in the eeprom settings. fullbp is latched upon reset confidential. 12/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet pin listing (continued) no. pin label ty p e description 1 8 7 c a r r b p i/o pd enable / disable carrier based backpressure for half -duplex mode. '1' ? carrier based backpressure ?0' ? collision based backpressure. carrbp is latched on reset 1 8 8 d i s b k p r i/o pd setting this pin to ?1? will disabl e backpressure proce dure for all half duplex port s . disbkpr is latched upon reset. 1 8 9 n c 1 9 0 f r c f d f c i/o pd setting this bi t to ?1? will fo rce flo w control execution f o r 1 0 /100m b p s, no matter the auto negotiation result. frcfdfc is latched upon reset. 191 vss 3.3 g digit a l ground for i/o 1 9 2 d i s f d f c i/o pd setting this bit to '1' will disabl e flow-co n trol fo r full-du plex m ode (transmission of p ause frames). disfdfc is latched upon reset. 1 9 3 d i s b p b k i/o pd enable / disable backof f during backpressure. ' 1 ' ? n o back o f f execut ed. a not her collis ion w ill be forced again af t e r one minim um i f g time foll owi n g prev ious colli si on if carrier sense i s observed. ' 0 ' ? the mac randomly chooses between 0 and 1 slot times of backof f . disbkbp is latched during the reset operation. 194 vdd 2.0 p digit a l +2.0v power supply for core 1 9 5 g n d i 196 vss 2.0 g digit a l ground for core 1 9 7 g n d i 198 nc na reserved for future use 199 nc na reserved for future use 200 nc na reserved for future use 201 nc na reserved for future use 202 vdd 2.0 p digit a l +2.0v power supply for core 2 0 3 m d c o mdio c l o c k . 2 0 4 m d i o i/o pu m d i o dat a . 205 vss 2.0 g digit a l ground for core 2 0 6 s c l i/o pu eeprom's s e rial c l oc k . 2 0 7 s d a i/o pu eeprom's s e rial dat a. 2 0 8 t e s t i n t i/o pd t e stint - '0' - switch normal mode(default) t e stint -'1' - internal memory test mode. confidential. 13/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet 2 ethernet media access controller the tc9 204 m? s ethernet media acce ss controller (mac ) co nt ain s ieee 802.3 mac function s for 4 port s. it is able to o perate i n 10/1 00/100 0 full d uplex and 10/ 100 half d upl ex mode s for all port s . each port ha s it s dedi cated receive and tran smit fifo with nece s sary logic to impleme n t flow control for both duplex modes. the mac functions are specially desi gned for high speed and flexible interfacing. 2.1 receive mac whe n a fra m e is received from the ethern e t medi a th roug h the mii interface, it is then store d in a dedi cated re ceive fifo. this fifo act s as a tem porary buf fer b e twee n the re ceive ma c section and swit ch core int e rf ace. the re ceive mac layer e x tract s the valid ethern e t in formatio n by strippin g of f the prea mble sequ en ce and sfd of the received frame, which the frame wa s ac quired fro m the phy layer via either gmii or mii interface. the receive mac then sends p a cket s with valid information to the receive fifo. tc92 04m d e termin es the v a lidity of each received p a cket by che c king the c rc and p a cket le ngth. the bad p a cket s will be drop p ed either by the mac or by the queue manag er . oversi zed p a cket s are truncated to 1536 bytes a nd marked a s errone ou s p a cket s. un d e rsi z e d p a cket s are remo ved from the receive fifo without being rep o rted to the switch interface. therefore th e fifo sp a c e held by undersized p a cket s will be removed automatically . in full duple x mode the receive ma c can id entify any receive d frame as a flo w co ntrol fra m e having a valid crc. it will load it s internal p a u s e co unter with the ?p ause quant a? val ue extracted from the incomi ng frame. the flow control frame will be reject ed af ter the p a using peri od has been acquired. af te r the p a u s in g perio d ha s o b t a ine d from the flow co ntrol frame, the flow con t rol mechani sm insi de tc92 04m will set a d e crem ent al time r in the p a use co unter a c co rdi ng to the valu e of the p a u s i ng pe riod. a non-ze ro value set s in t he p a use co unter will i ssue the re cei v e mac to xoff (t ra nsm i t s t op) the t r a n smit ma c. the p a use cou n ter will decreme nt the ?p a u se q u ant a? value af ter each slot time until it rea c he s ze ro. if the p ause quant a value is equal to ze ro the flow co ntrol mechani sm will xon (t ra nsmit enable) the t r ansmit mac. if a frame tra n smi ssi on is i n prog re ss when the p a use frame is receive d , the tran smi ssi on is allowed to compl e te for the current transmitti ng frame but the transmi ssion f o r t he next frame(s) will hold until the re ceive mac generates a n xon comm a nd. the p a use time will be gin at the end of current tra n smi ssi on or st a r t imme diately if no transmi ssion is in the m ediu m wh en the p a use fram e is re ceived. if a p a u s e comm and is receive d while the transmitter is already in p a u s e, the new p a u s e time indicated by the ne w flow control frame will be loaded into the p ause register . the ma c is also able to reject frames cont aini ng ieee 802.1d reserved group destination addresses and frames with mac control t y pe (t ype 88-08) if selected through configuration settings. whe n the receive fifo is full and additional dat a ar e still inco ming from the mac, then the overrun con d ition o c curs a nd the frame is droppe d. if th e system cl ock frequ en cy is not lower than the recommended value this condition will never occur . confidential. 14/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet 2.2 t r ansmit mac the t r an smit mac se ctio n assembl e s the mac fra m es store d in the tran smi t fifo and control s their transmissio n onto the m e d i a via extern al phy entiti e s. it app end s the st a nda rd preambl e a nd st art of frame d e limit er to the tra n smitted p a cket s. the m a c al so con t rols th e inte rframe ga p time du ring transmissio n, maint a ini ng f o r defa u lt the st an dard mini mum interf ra me gap of 96 -bit time. this value ca n be changed in the eeprom register setting. for half du pl ex mode the t r a n smit ma c meet s csma/cd ieee 802.3 re quirement s. the fifo logi c manag es fra m e retra n smi ssi on for ea rl y collision co ndition s or di scard s the fra m e if late collision o c curs. it also follows the truncated binary exponential ba ckof f algorithm, collision and jamming procedures. the tra n smit fifo sto r e s the p a cket s which are rea d y for tran smi ssi on in the main mem o ry queu es. if there is no p a cket ready in the transmi t fifo befor e the current p a cket compl e tes it s transm i ssi on, an unde rrun co n d ition has o c curre d and the mecha n ism will generate a signal to i ndicate fifo underrun event, but if the swit ch core transfers the rest of the p a cket(s) into t he fifo, the t r ansmit mac will safel y discard it without af fecting the next p a cket. underrun con d ition s ne ver occu r if th e system is o peratin g at the recommended clock frequency or higher . f o r fu ll dup le x mode tc9 204 m imp l e m en t s th e flow c o n t r o l a l g o r i thm acco rd ing to the ieee 802. 3x s t a ndar d , u s i ng t he x o n/x o f f m e th od. f u l l d u p l e x flo w co ntrol can be co nfi g ure d a u to m a ti call y , by a u t o -ne g o ti ati o n result, or manually , pin configuration and/or eeprom settings, to enable/disable the function. the tc9 204 m executes backp re ssure algorithm for half duplex flow cont rol suppo rting bot h collision based a nd ca rrie r ba se d b a ckpressu re. both mode s are based on ca rrie r sen s e forced colli si ons and an aggressive b a ckof f algorit hm. the fo rced co nsecutive colli si on s g enerated for f l ow control p u rpo s e s can be limited to a maximum of 28 collisions if this opti on is selected. this feat ure hel p s to avoid hub p a rtitioning in heavy traf fic. the number of collisions can be adjusted in eeprom settings. mac block diagram rx f i fo rx m a c t x ma c flo w contr ol tx f i fo f i f o c o nt r o l lo g i c s y st em i n t e r f a c e ma c rm i i ph y l a y e r r m i i r x d a ta ( 2 ) tx d a t a ( 6 4 ) fc i n s e r t ti m e v a l u e ( 1 6 ) rx d a t a ( 6 4 ) r m i i t x d a ta ( 2 ) confidential. 15/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet 3 mac address handling af ter the fra m es a r e reco vered fro m m a c fifos th ey are tra n sf erred to the q ueue m ana g e ment entity . prior to thi s transfe r the da and sa are e x tract ed f r om each fra m e and p a ssed t o mac ad dre s s loo ku p t able and re solutio n engi ne (al r ). th e loo kup e n g i ne uses a propriet a ry ha shing alg o rith m to access it s 8k address t able. the en gine will update it s t able with ea ch sa, if it is fo und to be un known or mi grated. then it will upd ate the so urce p o r t and a g ing i n formatio n al ong with the new add re ss. this le arning pro c e ss will be exe c uted for all add re sse s exce pt for multica s t sa frames (b it 40 is ?1?). fo r stored ad dresse s, aging function i s execute d accordin g to the time intervals set in the ee prom regi st ers. defa ult a g ing time i s 6 00 second s. tc9024m also provide option to dis able the aging mec h anis m, pleas e refer to t he eeprom regis t er in section 15.3.14 for more det ails. de stination a ddre s s is al so analyzed in orde r to m a ke forwarding deci s io ns. if the de stinatio n add re ss is a broa dcast o r multica s t ad dre ss, the fra m e will flood to all port s except it s ori g ina t ed port (sou rce po rt). if only some po rt s are allow t o send tho s e frame(s) with broa dcast or multica s t add ress(e s ), the destin a tion port s will sea r ch the fo r the port(s) with corre c t addr ess(s) in the mac add re ss t able. if the address i s found to be u n kn own, the frame will be a l so floo ded to every port, ot herwise fram e(s) will be fo rwa r d ed to the legitimate port(s) only . TC9204M will filter following frames: erroneous frames. this includes : - - - - frames with crc error; undersized frames; oversized frames; frames that present s alignment error (this doesn?t include frames with dribble bit s ). 802.3x p a use frames. t h e s e frame s will be filtered af t e r exe c uting approp riate flow control act i ons; frame s with 802.3x full duplex flow con t rol p a use operatio n de stination add re ss. these fra m es are not re co g n ize d as p a u s e frame s if th e ma c type and subtype d oes not mat c h the ?880 800 01?h value; frames with 802.1d reserved gr oup address destination address; frames with mac control t y pe (8808); local fram es. if the port fo und to co rre spond to de st ination a ddress mat c he s th e so urce p o rt, then the frame is considered to be local and discarded. 4 queue management tc92 04m op erate s in a store and forwa r d mode impl em enting ef ficient switchin g method that minimizes the overall lat ency . th e qu eue man age r use s the firs t in first out forwa r di ng mod e , which gua rantee s to maint a in fra m e orde r . conge stion co ntrol i s im pl emented wit h in t c 92 04 m, whi c h wi ll eliminate head-of-line blocking conditions. the switch e m bed s a 2 mbit ssram a s a central fra m e buf fer poo l, which is divided into 208 byte buf fers to incre a se memory utilization ef ficien cy . no rmal a nd prio rity transmi ssion q ueue s are impleme n te d within t c 920 4m for ea ch port. all available fram e b u f f ers a r e sh ared between all transmission que ue s and ea ch qu e ue ca n fully extend to all buf fers. s t ill me mory re so urce utilizatio n is limited on receive po rt basis. evolved flow control and frame filt ering mech ani sm s are impl eme n ted ba sed o n sou r ce, tra n smit and global memory load to maximize performance and minimize p a cket loss. confidential. 16/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet 5 classes of service tc92 04m im plement s advanced cla ss of service (cos), su ppo rti ng both t r af fic prio rity and d e lay bou nd feature s . it provides fou r cl asse s of serv ice: cla ss 0 (l ow), cl as s 1 ( norm a l), cla s s 2 (high ) an d class 3 (very high). each cl ass of service ha s it s dedi cat ed tra n smi ssi on qu eue for each port. the fra m es assign with higher service class will arrive sooner at the destination. frame s in th e cla s s 0 p r io rity queue get the lowest transmi ssion b and wid t h percent age, whil e frame s in the class 3 priority queue s get the high est ba nd wi d t h pe rcent a g e . the b and wi d t h pe rcent a ge de pen ds on two element s: cos bandwid th weight s, and the corresponding class of all non-empty queues for the respective port. the cos we ight s can b e set by usin g pribnd w [1:0] sh are d config uratio n pins or by setting the eeprom registers. whi l e the pins provide only four predefi ned hardwi r ed combinations for th e transmission bandwi d t h percent a ge allocation am ong the queues, t he eeprom gives more flexibility over this configuration. when eeprom is not present, transmissi on bandwi d t h percent age di stri buti on am ong the queues for the case when all the queues are loaded can be seen in the t able below: eeprom is not present t r ansmission bandw id th percent a ge pribndw [1:0] class 0 priority (low est) class 1 priority class 2 priority class 3 priority (highest) 00 7 % 1 3 % 2 7 % 5 3 % 01 3 % 1 4 % 2 7 % 5 6 % 10 2 % 8 % 3 0 % 6 0 % 11 3 % 5 % 1 0 % 8 2 % the pe rcent a ge refe rs to the port? s ban dwi d th, whi c h is determi n ed by the cu rre nt operatin g spe ed. those value s are the guaranteed mini mum one s and the transmissi on ban d w id th pe rcent age ca nnot drop below specified value under any circum st ance. if eeprom is used, the user has m o re flexible adjustment of bandwid th weight s to choose from the eeprom register . a spe c ial e a r ly p a cket droppin g me ch anism i s al so impleme n ted to of fer more prote c ti on agai nst overflow con d itions for p r i o rity p a cke t s. if the global memory loa d excee d s a n o v erflow threshold, then all cla ss 0 prio rit y p a cket s will be dro ppe d from the sou r ce po rt(s) i n orde r to save sp ace for th e highe r prio rity p a cke t s. thi s will m i nimize th e probability of p a cket lo ss in prio rity flows for se nde rs that are not flow control cap able. the cos me cha n ism sup port s multiple prioriti zation source s: 80 2.1q vlan t ag he ade r (l ayer 2), ip hea der t o s bit s (laye r 3) and/or po rt based cos. for ip and vlan so urce s a mapping i s executed betwe en the values of th e fields extra c ted from ea ch frame an d one of the four cos provided by tc92 04m. t h is map p ing can be adj usted by using ipt o smap [1:0 ] and vl anprm ap [1 :0] shar ed configuration pins or the eeprom settings. while the pins provide just four predefined hard-wired mapping schemes, the eeprom gives a custom explicit mapping. und e r some circum st a n ce s, one o r mo re me cha n isms can be a c tived at sam e time (vla n, ip and/or port ba sed ) . in this ca se t here i s a re solution fun c tion that re sol v es the cos for ea ch inco ming frame. when eeprom is not present and ip and/or vlan prioritizat i ons are ena bled, the correspondi ng head ers of e a ch i n coming frame s a r e p a rsed. th e frame will be a ssi gne d the cos corre s p o nding to th e first he ade r p a rsed th at found valid. when b o th a b o v e prio ritizati ons are en ab led the se arch order is confidential. 17/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet determi ned by eeprom configurat ion (default is ip). if no head er i s found or correspondi ng prioritizations are disabl ed then port based priori ti zation is executed. when eeprom is present an addition al me thod of prio ritization i s avail able. this m e thod co nsi s t s of sele cting th e highe st se rvice cla s s from all cla s ses corre s po n d ing to the en abled p r ioriti zation so urce s (ip , vlan and port ba sed ) . for both method s, wh en no prio ritization sou r ce is available th e default co s is used (d e f ault is norma l priority ? cos1 but it can be also changed by eeprom configuration). the cos feature s can b e config ured by adjustin g sha r e d co nfiguratio n pi ns an d/or p r ogra mming eeprom register settings. vlan prioritization can be enabl ed by envlpr shared configu r ation pin or by eeprom regis t er settings , while eni ppr share d configuration p i n or the eeprom regi ste r setting s can enable ip prioritization. the shared conf iguration pins are sampled during reset. the pe r-port basi s cos can be set using priclass [x][1:0] sha r ed config ura t ion pins or config urin g eeprom regis t ers , where x st and s for port numb e r . the port - ba sed prio ritizati on can be di sabled from eeprom s e ttings only . configuration pins latched description p r i c l a s s [ x ] [ 1 : 0 ] t x d a t a x _ [ 1 : 0 ] set the priority class per port basis '00' ? the port has class 0 priority(lowest priority) '01' ? the port has class 1 priority '10' ? the port has class 2 priority '1 1' ? the port has class 3 priority(highest priority) e n i p p r enable/disable ip prioritization ?0? ? ip priority within the received p a cket (if exist s ) is ignored ?1? ? ip priority within the received p a cket (if exist s ) is considered envlpr enable/disable vlan prioritization ?0? ? vlan priority within the received p a cket (if exist s ) is ignored ?1? ? vlan priority within the rec e ived p a cket (if exist s ) is considered select s on e of four mappi ngs fo r the 8 level pre c ed e n ce extracte d from frame? s ip header to the 4 cos of fered by TC9204M (c0, c1, c2, c3 ? class 0, 1, 2, 3 of service) designated priority class ipt o smap[1:0] 0 1 2 3 4 5 6 7 00 c0 c0 c1 c1 c 2 c 2 c3 c3 01 c1 c2 c2 c2 c 3 c 3 c3 c3 10 c1 c1 c2 c2 c 2 c 3 c3 c3 ipt o s m a p [ 1 : 0 ] 11 c0 c1 c1 c2 c 2 c 3 c3 c3 select s one o f four mappin g s for the 8 level user_priority extracte d from the frame? s vl an t a g to the 4 le vel priority o f fered by tc92 0 4 m (c0, c1, c2, c3 ? class 0, 1, 2, 3 of service) designated priority class vlanprmap[1:0] 0 1 2 3 4 5 6 7 00 c0 c0 c1 c1 c 2 c 2 c3 c3 01 c1 c0 c0 c1 c 2 c 2 c3 c3 10 c0 c0 c0 c1 c 1 c 2 c3 c3 v l a n p r m a p [ 1 : 0 ] 11 c2 c0 c1 c2 c 3 c 3 c3 c3 confidential. 18/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet 6 flow control whe never th e memo ry loa d exce ed s preset th re shol ds , flow co ntrol com m an ds are i s sued b y the traf fic manag eme n t entity to th e transmit macs to prevent overflo w con d ition s occu rred. the overrun con d ition s are either lo cally or glob ally tr iggere d , depen din g on the traf fic mana ge ment entity config uratio n. t r an smit m a c ex ecuted those flow control comm and s dep end ing on the d uplex mode st atu s . tc9 2 04m execut e s backp re ssu r e for half du pl ex operatio n mode and it is ieee 802.3x complia n t for full duple x operation mode. in sp ecial conditio n s forward-pressure is also executed t o eliminate p a cket loss. for full duplex operation mode, TC9204M appli e s the xon/xoff method using ieee 802.3x p a use frame s . whe n a flow control comma nd i s intern ally generated, the transmit mac inse rt s a p ause frame immediately or af te r the current tra n sm issi on e n d s . on the re cei v ing sid e , if a flow co ntro l frame i s received, the transmit mac will stop tr ansmission for a number of sl ot ti mes, where the p a using time was extracted fro m the receiv ed p a u s e fra m e. the flow cont rol fun c tion of the receivin g side is always operational unless i s speci f ically disabled by eepr om on a per port basi s (if no eeprom is present the receive side f l ow-co n trol i s alway s op erational), whil e tran smi ssi o n of the p a u s e frame s obe ys the a u to negotiation result. tc92 04m recogni ze s flow control frame s from the incoming fram es and these fra m es shoul d also have a valid crc. the ieee 802.3x p a u se operation reserves destinati on add ress, mac cont rol type and p a use op co de (8 8-0 8 -00 - 01 ). the ch ip filters all frame s havin g p a use o peratio n re served da disrega rdin g the other fiel ds. if enable d , dire ct flow control add ressing can b e execute d . this impli e s inse rting the port add re ss as sa in each flow c ontrol frame gene rated by tc92 04m and re cogni zing a s flow control a ll received fra m es with the port? s add re ss as da, m a c co ntrol ty pe an d p a use opco de. af ter recogni zing an d exe c uting ap prop riate flow co n t rol action s these fram es will be also filtered. the port address is obt ained by adding the port? s number to the base address cont ained within eeprom. when no eeprom is pres ent and dis fdfc sha r ed configu r ation pin is co nfig ured to hi gh st ate, the swit ch will inhibit it s ability to send flow control p a ck et s on all port s while preserv i ng it s ability to receive and a c t upon the incomin g flow co ntro l p a cket s. if this pin i s co nfigure d to low st ate the switch will execute symmetrical p a use operation as defined in 802.3x. the function of enabli ng/di sabli ng the flow cont rol in the eeprom is now avail able on a per port basi s rathe r than setting flow co ntrol glob ally for all port s a nd se p a rate enabli ng/disa bling flow co ntrol ability can be performed on either receive or transmit side of a port. TC9204M ca n be ins t ructe d to ignore th e au to-negotiation result for full dup le x flo w control ab ility . when the frcfdfc shared configuration p i n or the equvalen t reg i ster in the eeprom is eq ual to 1 , the link p a rtne r will be consi dered to ha ve ful l duple x flow contro l cap able no matter of au to-negotia tion result. the frcfdfc se tting is e f fec t ive only for port s configured in 10/10 0 mbp s speed mod e s. when the frcgbfc and the equivalent regis t er in the eeprom is equa l to 1 , the link p a rtner w ill be considered symmetrically and asymme trically toward s link p a rtner full duple x flow control cap able no ma tter o f auto-negotia tion result. the frcgbfc setting is ef fective only for port s configured in 1000 mbp s speed mode. the t c 92 04 m executes backp re ssu r e al gorith m fo r half d uplex flow control, sup porting both colli sion -ba s e d and ca rri er-ba s ed b a ckpre ssure. for colli sion -ba s ed b a ckp r e s sure the switch will b e force d to sen d colli sion sig nals to the te rminal that se nds p a cket s to tc9 204 m. while t c 9 2 0 4 m dete c t s an incoming frame that i t wishes to backpressure with ca rri er sense signals, the switch will st art transmissio n to that port. if no p a cket is available at that moment for tran smi ssi on then the mac layer will gene rate sho r t jammin g frames. ad ditionally , an ag gre ssive ba ckof f will b e e x ecuted by the tra n smit mac af ter e a ch of the force d colli sio n s . the tran smit mac will cho s e between 0 and 1 slot times to backof f. this will grant a fa st re cove ry for the switc h's con g e s ted po rt and will se cure the ch ann el for the con g e s t ed po rt in ca se it wi she s t o t r an s m it (empt y it s buf fers). if desired, the ba ckof f can be compl e tely confidential. 19/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet disa bled usi n g sh ared co nfiguratio n pi n dis b pb k or eeprom. in this case the switch will st art transmitting with minimum ifg af ter carrier s ense is deasserted and followed af ter collision. for carrier-b a se d backp ressure the switch will u s e the deferra l mecha n ism rather than the collisi on backof f me chani sm. the transmit mac will ja m t he line by se nding contin uou s preamb l e. the lin k p a rtn e r will see the chan n e l busy and thus it will defer transmissi on without imposi ng any additional backof f delay . the jamming proce d u r e wi ll have short brea k to avoid jabber cond ition and the brea k will also b e short enou gh to prevent the oth e r st ation s fr o m st a r ting tra n smi ssi on. preamble ca n b e sent thi s way as long as ne ce ssary . if valid p a cket s became available for transmi ssi on during this p e riod then jamming will be interrupte d and the p a cket s will be tran sm itted wi th st and ard i f g (inter-fra me gap ) . in this ca se b a c kpre ssu r e i s executed the sa me wa y as colli sio n based me cha n ism. ca rrie r ba sed backpressure can be selected using shared configuration pin crbp or eeprom. backpressu re operation ca n be di sabl ed gl obally u s in g the shared config uratio n pin dis b kpr or pe r p o rt bas is us ing the eeprom. by default forwa r d pre s sure is also enabl ed whe never b a ckp r essure is enabl ed. forward p r essu re is exe c uted only in extr e m e co nge stio n co ndition s that normally do not o c cu r of ten. this flow control pro c ed ure is hig h ly ef ficient in minimizing the p a cket loss. if desire d , the forwa r d pres s u re c an be dis abled by the eeprom s e tting. if a hub is co nnected to many workst ations, one o f th e port s may b e p a rtitioned in hea vy traf fic when the switch e x ecutes backpressure. tc9204 m can pre v en t th is by d i scontinuing the b a ckpressu re process af te r a predefined number of co nsecutiv e collisions have r eached. this function can be enabled using the shared config uration p i n fu llbp or ad justing eeprom setting . un lik e other se ttin gs, to enable this feature the pin / bit sho u ld be set to ' 0 '. the respec tive number o f collisions default s to 28 an d can be specified using the eeprom. in addition , when this f eature is enable d the mac will either grant r e ceiving the n e xt p a cke t without colliding it, af ter which, it will resume the backpressure, or will comple tely q u it backpressure waitin g for a new xoff command from internal flow control management device. confidential. 20/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet 7 broadcast throttling in case of excessive broadcast, t c 9204m will throttle the broadcas t traf fic based on buf fer memory loadin g . both global buf fer pool l oadin g and so urce port lo adin g are co nsi dere d . the n u mb er of frame buf fers that can b e co nsumed by broad ca st p a cket s re ceive d from an i ndividual so urce po rt is permanently l i mited to the eeprom c o nfigurable val ue (cont ained by srcloadt rsh field from broad ca st configuration register). t he default value is 32 when the eeprom is not present. additionally , rega rdi ng the global asp e ct, broad ca st frame s a r e al ways dro ppe d by bro a d c a s t que ue s ov erflo w . t w o broa dcast q u eue s are impl emented with in tc9 204m, one for lo w a nd no rmal p r i o rity (cla sse s 0 and 1 ) and another for higher priorities (classes 2 and 3). both filtering mech ani sm s descri bed ab ove can be a v oided by enabling the flow cont rol for broa dcast pro c e ss. thi s mecha n ism can b e enabl ed usi ng the fcbc sten pi n sha r ed con f iguration o r by adjustin g the eeprom setting. in this case the loading th resholds will never be reached and as result no broa dcast p a cket will be drop ped alth ough the filt er ing m e cha n ism al way s remain s a c t i ve. if th e broa dcast flo w co ntrol is d i sabl ed tc92 04m is still cap a ble of t a ki ng co ntinuou s bro a d c a s t frame s from one port and deliver them to all the other port s at maximum speed without losing p a cket s . indepe nde nt of the throttling mech ani sm s, a band wi d t h based broa dca s t throttlin g can b e ena bled u s ing the bc stt h ro t pin or by ee prom settin g . whe n this pro c e s s is act i ve, the re cei v e bro adcast band wi d t h per po rt will be limited to a value betwee n 1% and 31% from the port? s ma ximum band wid t h. thi s percent age i s encod ed with in thrott r sh field from eeprom's broadc as t configuration regis t er . default value is 5 (%). when ever the b r oad ca st traf fic b and wid t h ex ceed s the ab ove limit so me bro a d c a s t frames will be randomly dropped in order to precisely meet the enforced bandwid th. TC9204M has the ability to give an in dication about it s st atus, from t he broadcast p a cket s handling i s sue pers p ec tive. it s bcs t le d pin can sig nal either if the incomi ng broa dcast p a cket s a r e d r oppe d or if broa dcast p a cket s overflo w a cert ai n thre shol d. du ring re set, this pin has th e meaning o f bcstcfg sha r ed config uration pi n. if this pin is sampled lo w at reset, the bcstle d will behave a s a broa dcast p a cket s dro p p ing indi cato r , it light s peri odically whe n e ver a b r oa d c a s t p a cket is dropp ed du e to buf fer overflow . if thi s pin is sam p l ed high at reset, the led will light periodi cally whenev er the percent age of the received broa dca s t p a cket s bandwi d th in the last se co nd to the who l e port band wid t h excee d s a cert ain threshold s p ec ified in the eeprom. the default val ue for this thres hold is 40% from the whole bandwid th per port. 8 port mirroring although t c 9204m i s a smart switch, it has the abil i ty to set a p a ir of mi rro rin g port s . thi s feature i s available only through eeprom settings. the port mi rrori ng feature can be enabl ed by setting a value o f ?1? in either entxmirror field from eeprom? s portmirrorco n fig regi ster o r en r x m i r r o r field from th e same register , or both. whe n po rt-mi rro ring feature ha s be en e nable d , the s ourcepor t field from eeprom? s po rt m i rr o r c o n f ig regi ster sele ct s the mo ni tored po rt while des t ina t ionport field from eeprom? s por t mirrorco n fig regi ster sele ct s the monito ring port. the traf fic on t he monitored (mi rro r source ) p o rt will be fo rwarded to the monitor port (mirror destination). both port s can be any of the TC9204M? s port s . if enrxmirro r field is set t o ?1? then all t he incoming t r af fic of the m i rror source port will be sim u lt aneousl y forwa r d ed to wards it s due destinatio n a nd to the monitoring p o rt. the bad crc / undersi ze d frame s will be filtered out. if entxmirror field is set to ?1? then all the outgoing traf fic of the mi rro r sou r ce port will be also forwa r ded to the monitoring port. confidential. 21/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet 9 phy s ical lay e r configuration / polling tc92 04m em bed s a phy s i c al l a yer mii manag eme n t config uratio n / polling e n tity whi c h p r ovid es spe ed, duplex, lin k st atu s a nd li nk p a rtner full dupl ex flow cont rol a b ility informa t ion to the switch. t h is informatio n is obt ained by contin uou sly polling the st at us of physical layer de vices through the serial management interface. t he entity is under control of eeprom settings and it can operate i n four dif f erent modes. the polling entity al so performs phy configuration proc edure at two seconds af ter reset and each time eeprom control information changes. the follo wing operating mo des are avail able pe r p o rt basi s (sel ect a ble by an mode field from eeprom's configregp[x] ): 00 ? normal mode (assumed by default when eeprom is not present): in this m ode the auto-negotiat i on enable bit from mii control regi ster (0.12) is ch ecked first. if it is found enabl ed then TC9204M will disabl e advertisem ent for 1000base-t half duplex technology (9.8) and will advertise the full duplex fl ow co ntrol a b ility (4.10: 1 1 ) according with internal f l ow co ntrol e nable setting s. auto-ne gotiation is rest a r ted l eaving un cha nged the re st of technolog y advertisem ent s. then auto -negotiation a d vertisem ent registe r (4), li nk partne r base page a b i lity register (5 ) and gmii registe r s (9:10 ) are polled contin uou sly at 2 seco nd s interv al in orde r to execute hig hest comm on de n o minato r re solution. if auto-neg otiation is disabl ed as re po rted by 0.12 then th e swit ch will co nfigure it self usin g bit s 0.1 3 and 0. 8 of control regi st er , and will consi der lin k p a rtne r full duplex flow control cap able. gigabit speed will be disabled. 01 ? adv e rtise one mode: auto -neg otiation enab le is checke d and if found to be disabled tc92 04m will attempt to e nable it. if successful the swit ch will force the po rt? s spe ed and d uplex mode by advertisin g only the technol o g y correspon ding to the s p eed and duplex fields from eeprom's configregp[x ] , otherwi se b i t s 0.8 an d 0. 13 will b e re a d for configu r ation and gig abi t spe ed will b e disabled. full dupl ex flow control a b ility is also advertised al ong with sel e cted techn o logy and then auto-negotiatio n is rest a r ted. an auto-neg otia ti on registe r polling is executed as in normal mode. 10 ? adv e rtise multiple modes: t h is mode i s simil a r with p r evio us on e exce p t that it advertises the tech nolo g y co rre sp on ding to the f o rced m ode and all l o wer positio n technolo g ies, do wn to 10base-t half duplex. 11 ? disable auto-negotiation: whe n this mo de is sele cted then auto-ne gotiation is di sabl ed by setting bit 0.12 to ?0? and the forced speed an d duplex mode will be writte n to configuration regi ste r , bit s 0.13, 0.6 and 0.8. this mode is availabl e only for 10/100 mbp s sp eed mode s so bit 0.6 will always be written as ?0?. link p a rtner will be considered full duplex flow control cap able. in addition to the force mo de feature, the tc9 204m i n ternal sp eed and du plex can be cho s e n betwee n enforced one s ( sp e e d a nd duplex fields from eeprom's con f ig regp[ x ] ) an d polling result s by mea n s of forceintmode configuration. indepe nde ntly of phy confi guratio n/polli ng op eratio n mode the lin k s t atu s is also perman entl y monitore d. if a physical device repo rt s lin k failu re via 1.2 st a t us bit then tc92 04m di sabl es tran smissi on o n asso ciated p o rt without h o lding any memory re so urces all o cated for it s tra n smi ssi on qu eue s. the reported link s t atus can be forced to ?1? using forcelink bit from the same configregp[x] register . confidential. 22/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet 10 eeprom interface TC9204M can be config ured using a serial eeprom device type a t 24c02a (2048 bit s organi zed as 208 p a g e s of 1 byte each). wi th this device the manufac turer can deli v er a pre-co n f igured syste m to their cu stome r s while the cu sto m ers can reconfigure the system and ret a in their preferen ce s. t c 9 204m al so provides a virtual internal eeprom mode, whic h enables the program m ing entity to write the configuration dat a directl y into the chip, wit hout using the ex ternal eeprom. in this mode the configuration dat a is lost af ter reset procedures. the tc920 4 m is a b le to o perate with ou t this devi c e a nd can m a ke ef fective use of it s featu r e s usin g o n ly the pin confi guratio n interface. the e eprom conf i guratio n pro v ides ad ditio nal features and it ca n overri de all pin interface settings of ferin g a jumper le ss configu r ati on mode. fo r this rea s on equivalent eeprom settings can be found for every configuration pin. a validation bit is provided for each one of the eepr om configuration regi ster s. a dedicated v a lidation regi ster i s re serve d for thi s pu rpo s e an d co rrespond i ng bit s from this re giste r must be set i n ord e r to enable the desired eeprom configurations. the eeprom configuration information is access ed by the TC9204M af ter each reset procedure. 10.1 reprogramming the eeprom for reconfiguration if the ?reset? pin is hold low the TC9204M?s eeprom interf ace will go into high impedance st ate. thi s feature enables easy reprogramming of the eeprom during inst allation or reconfiguration. the eeprom can be reprogramm ed using an external p a rallel port. a dedicated signal from this port can be used to hold the reset pin low . once the TC9204M interface pi ns have got to the high impedance st ate the eeprom can be programmed by the p a rallel port trough the sda and scl pins. t o enable the a t 24c02a d e vice to be a c cesse d by the tc9 204m it s p age a d d r ess inp u t pins must be hardwi r ed to ?0?. for virtual eeprom mode the programming can be done using the same a t 24c02a byte write protocol but p age address bit s must be ?100? (a2 downto a0). ee pr o m pa r a l l e l po r t sda scl re s e t tc 9204m confidential. 23/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet confidential. 24/49 july 29, 2003 copyright ? 2003, ic plus corp. tc 9204m-ds-r05 10.2 eeprom address map physical address bits register name validation bit description eeprom 00h [7:0] validreg [ 7 downto 0 ] - validation register 01h [7:0] validreg [ 15 downto 8 ] - validation register 02h [7:0] validreg [ 23 downto 16 ] - validation register 03h [7:0] validreg [ 24 downto 31 ] - validation register 04h [7:0] validreg [ 32 downto 39 ] - validation register 05h [7:0] configregp0 [ 7 downto 0 ] 06h [7:0] configregp0 [ 15 downto 8 ] configregp0 port 0 configuration register 07h [7:0] 08h [7:0] 09h [7:0] configregp2 [ 7 downto 0 ] 0ah [7:0] configregp2 [ 15 downto 8 ] configregp2 port 2 configuration register 0bh [7:0] 0ch [7:0] 0dh [7:0] configregp4 [ 7 downto 0 ] 0eh [7:0] configregp4 [ 15 downto 8 ] configregp4 port 4 configuration register 0fh [7:0] 10h [7:0] 11h [7:0] configregp6 [ 7 downto 0 ] 12h [7:0] configregp6 [ 15 downto 8 ] configregp6 port 6 configuration register 13h [7:0] 14h [7:0] 15h - 18h reserved 19h [7:0] ifgconfigp0 [7 downto 0] if gconfigp0 port 0 ifg configuration 1ah [7:0] 1bh [7:0] ifgconfigp2 [7 downto 0] if gconfigp2 port 2 ifg configuration 1ch [7:0] 1dh [7:0] ifgconfigp4 [7 downto 0] if gconfigp4 port 4 ifg configuration 1eh [7:0] 1fh [7:0] ifgconfigp6 [7 downto 0] if gconfigp6 port 6 ifg configuration 20h [7:0] 21h ? 2dh reserved 2eh [7:0] flowcontrolreg [7 downto 0] 2fh [7:0] flowcontrolreg [15 downto 8] flowcontrreg flow control register 30h [7:0] bptimevalue [7 downto 0] 31h [7:0] bptimevalue [15 downto 8] bptimevalue backpressure time value register 32h [7:0] fcbaseaddress [47 downto 40] 33h [7:0] fcbaseaddress [39 downto 32] 34h [7:0] fcbaseaddress [31 downto 24] 35h [7:0] fcbaseaddress [23 downto 16] 36h [7:0] fcbaseaddress [15 downto 8] 37h [7:0] fcbaseaddress [7 downto 0] fcbaseaddress flow control source base address register
TC9204M preliminary dat a sheet phy s ical address bit s register name v a lidation bit description eeprom 38h ? 3bh reserved 3c h [ 7 : 0 ] 3dh [7:0] broadcastconfig [ 7 downto 0 ] 3 e h [ 7 : 0 ] b r oadcastconfig [15 downto 8 ] broadcastconfig b r oadcast configuration register 3fh [7:0] ipt o smapping [ 7 downto 0 ] 40h [7:0] ipt o smapping [15 downto 8 ] ipt o smapping ip priority mapping register 41h [7:0] vlanprimapping [7 downto 0 ] 4 2 h [ 7 : 0 ] v l a n p r i m apping [15 downto 8 ] vlanprimapping v l a n p r i o r i t y m apping register 43h [7:0] cosbandwid th [7 downto 0 ] 44h [7:0] cosbandwid th [15 downto 8 ] cosbandwid th cos bandwid th register 45h [7:0] [7 downto 0 ] 46h [7:0] [15 downto 8 ] r e s e r v e d r e g i s t e r 47h [7:0] cosconfig [7 downto 0] cosc onfig cos configuration register 48h [7:0] portmirrorreg [7 downto 0 ] 49h [7:0] portmirrorreg [15 downto 8 ] portmirrorreg port mirroring configuration register 4ah [7:0] generalconfig [ 7 downto 0 ] gener alconfig general configuration register 4bh ? 4eh reserved 4 f h [ 7 : 0 ] p o r t v l a n e n portvlanen port vlan enable register 50h [7:0] vlan0reg [ 7 downto 0] pviden id 0 virtual lan register 5 1 h r e s e r v e d 52h [7:0] vlan1reg [ 7 downto 0] pviden id 1 virtual lan register 5 3 h r e s e r v e d 54h [7:0] vlan2reg [ 7 downto 0] pviden id 2 virtual lan register 5 5 h r e s e r v e d 56h [7:0] vlan3reg [ 7 downto 0] pviden id 3 virtual lan register 5 7 h r e s e r v e d 58h [7:0] vlan4reg [ 7 downto 0] pviden id 4 virtual lan register 5 9 h r e s e r v e d 5ah [7:0] vlan5reg [ 7 downto 0] pviden id 5 virtual lan register 5 b h r e s e r v e d 5ch [7:0] vlan6reg [ 7 downto 0] pviden id 6 virtual lan register 5 d h r e s e r v e d 5eh [7:0] vlan7reg [ 7 downto 0] pviden id 7 virtual lan register 5fh ? 6fh reserved 70h [7:0] dat a w r itereg [15 downto 8 ] 71h [7:0] dat a w r itereg [ 7 downto 0 ] - dat a w r ite register 72h [7:0] phyaddress [ 7 downto 0 ] - phy address register 73h [7:0] regaddress [ 7 downto 0 ] - phy's register address register 74h [7:0] iocontrol [ 7 downto 0 ] - io control register 75h [7:0] dat a readreg [ 7 downto 0 ] 76h [7:0] dat a readreg [ 15 downto 8 ] - dat a read register confidential. 25/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet 10.3 register description 10.3.1 v a lidation register confidential. 26/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05 - address: 00h - 04h 7 6 5 4 3 2 1 0 c onf i g r egp 0 re se r v e d c onf i g r egp 2 re se r v e d c onf i g r egp 4 re se r v e d c onf i g r egp 6 re se r v e d n o t us ed i f gc onfi g p 0 re se r v e d i f gc onfi g p 2 re se r v e d i f gc onfi g p 4 re se r v e d i f gc onfi g p 6 re se r v e d n o t us ed fl ow con t r r eg bp t i m e v a l u e re se r v e d b r oa dc as tc onfi g i p t o sm ap pi n g v l a n p r i m appi ng q o sba nd w i d t h re se r v e d qos c onfi g p o rt m i rr o r r e g ge neral c onf i g n o t us ed po r t vl a n e n n o t us ed v a lidatio nr eg 2 3 22 21 2 0 19 18 17 16 1 5 14 13 12 1 1 10 9 8 31 30 29 28 27 2 6 25 24 39 3 8 37 36 35 34 33 32
TC9204M preliminary dat a sheet bit(s) field description 39 ? 0 v a lidationreg eeprom? s configuration regis t ers v a lidation regis t er v a lidationreg ? each bit from this register corresponds to an eeprom configuration register . t o enable the use of a cert ain configu r at ion regi ster , a value of ?1? shall be written to it s corresponding bit from the validation register . configregp0 ? validation bit for port 0 configuration register reserv e d ? should be ?0? configregp2 ? validation bit for port 2 configuration register reserv e d ? should be ?0? configregp4 ? validation bit for port 4 configuration register reserv e d ? should be ?0? configregp6 ? validation bit for port 6 configuration register reserv e d ? should be ?0? ifgconfigp0 ? validation bit for port 0 ifg configuration register reserv e d ? should be ?0? ifgconfigp2 ? validation bit for port 2 ifg configuration register reserv e d ? should be ?0? ifgconfigp4 ? validation bit for port 4 ifg configuration register reserv e d ? should be ?0? ifgconfigp6 ? validation bit for port 6 ifg configuration register reserv e d ? should be ?0? flow contrreg ? validation bit for flow control register bpt i m e v a lue ? validation bit for back pressure t i me v a lue register t r unkconfig ? reserved register broadcastconfig ? validation bit for broadcast configuration register ipt o smapping ? validation bit for ip priority mapping register vlanprimapping ? validation bit for vlan priority mapping register cosbandw id th ? validation bit for cos bandwid th register reserv e d ? reserved register cosconfig ? validation bit for cos configuration register portmirrorreg ? validation bit for port mirroring register generalconfig ? validation bit for general configuration register portvlanen ? validation bit for port vlan enable register confidential. 27/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet 10.3.2 port [ x ] configuration register confidential. 28/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05 - - addresses: 05h - 14h note: x is in range 0 to 7 7 6 5 4 3 2 1 0 an m o d e f o r c ei ntmod e s p eed dupl ex f o r c eli nk n o t us ed t x di s abl e rx di s a b l e di s f dx f c t x di s f dx f crx d i s b a ckp r e s por t pr i o r i t y en por t pr i o r i t y conf i g re g p [x ] 15 14 13 12 11 1 0 9 8 bit(s) field description 1 - 0 anmode operating mode selection for the phy configuration/polling entity 2 forceintmode internal speed and duplex selection enforcement 4 - 3 s peed internal speed selection (10 mbp s /100mbp s/1000mbp s) 5 duplex internal duplex selection (full/half) 6 forcelnk force link s t atus to ?on? 7 not used not used 8 txdisable disable transmit mac 9 rxdisable disable receive mac 10 disfdxfctx disable flow control in full duplex on transmit side 1 1 disfdxfcrx disable flow cont rol in full duplex on receive side 12 disb ackp res disable backpressure 13 portpriorityen enable port priority 15 - 14 portpriority set s the priority cla ss(class 0, class 1, class 2, class 3) anmode this field select s the way auto-nego tia t i on ad ver t ise m ent s are co nfigured b y the TC9204M? s physical la yer management polling entity and the wa y phy speed and duplex mode s are extracted from man agem ent reg i sters. it can enable eeprom forced modes tha t also use duplex and s p eed bit s below to configure the phy mo de. 00 ? normal mode 01 ? advertise one mode 10 ? advertise multiple modes 1 1 ? disable auto-negotiation default is ?00?(0). forceintmode this bit select s the source of internal por t mode con f iguration. when this bit is ?0 ? the port' s speed a nd d uplex is con f igured acco rding to phy polling result s, otherwise it is set as indicated by following s p eed and duplex . default is ?0?.
TC9204M preliminary dat a sheet s p eed used by the physi cal layer manage men t polli ng entity to configure physical laye r ? s speed mode when eeprom forced modes are se lected. additionally this bit can be used to directly force the internal speed mode. 00 ? 10m 01 ? 100m 10 ? 1000m duplex used by the physi cal layer manage men t polli ng entity to configure physical laye r ? s duplex mode when eeprom forced m odes are sel e cted. additi onally this bit can be used to directly force the internal duplex mode. forcelnk setting this bit to '1' will force the interna l polled link st atus of the co rre sp ondi ng p o rt to ?on? . default is ?0?. txdisable setting this bit to '1' will disable the tr ansmi ssio n mac device, thus inhi bitin g transmission on the corresponding port. default is ?0?. rxdisable setting this bi t to '1' will disable the recei v ing mac device, thus inhibiting receivin g on the corresponding port. default is ?0?. disfdxfctx setting this bit to '1' will disable flow control ope ration for full duplex mode on transmit side (transmission of p aus e frames). default is ?0?. disfdxfcrx setting this bit to '1' will disable flow control ope ration for full duplex mode on receive side (p ausing frame transmission). default is ?0?. disbackpres setting this bit to '1' will disabl e flow co ntrol for half duplex mod e (backp re ssu r e). default value is it s corresponding disbkpr pin value. portpriority en setting this bit to '1' will fo rce the co rre s po ndin g port to the priority s e t within t he portpriority field, otherwise the pin configuration will be used. portpriority this bit will set one of the four priority classes on the corresponding port. confidential. 29/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet 10.3.3 port [ x ] ifg configuration register confidential. 30/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05 - addresses: 19h - 20h 7 6 5 4 3 2 1 0 if g c o n f i g r e dg bb n d w gb b n d w s e l no t us ed i f g c onf i g p [ x ] bit(s) field description 3 - 0 ifgconfig interframe gap configuration 4 redgbbndw reduced gigabit bandwid th 6 - 5 gbbndwsel gigabit bandwid th selection 7 not used not used ifgconfig these bit s are use d to set the minimum if g with 32-b i t time resolut i on. the defa u lt matches the st andard minimum ifg of 96-bit time: ?001 1? (3). ifgconfig ifg (bit time) 0 0 0 1 3 2 0 0 1 0 6 4 001 1 9 6 ( d e f a u l t ) 0 1 0 0 1 2 8 ? ? 1111 480 0 0 0 0 5 1 2 redgbbndw setting this bit to '1', wil l enable a 1 000mb p s po rt to redu ce i t s tran smi s si on band wi d t h to the percent a ge indicated by the gbbn d w s e l field. setting this bit to ?0?, the gbbn d w s e l field will be m eani ngle ss and th e port will ma ke u s e of it s full transmissio n band wi d t h. this bit is in e f fect only wh en the po rt? s spee d mod e is 1000mbp s. default is ?0?. gbbndw sel t r ansmission bandwid th enforcement when in 1000 mbp s mode. gbbndwsel t r ansmission bandwidth 0 0 5 0 % 0 1 6 6 % 1 0 8 0 % 1 1 9 0 % this feature can be u s ed to avoid conge stion in some lan no des with out flow control cap abilities or to avoid server overloads
TC9204M preliminary dat a sheet 10.3.4 flow control register confidential. 31/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05 - address: 2eh, 2fh 7 6 5 4 3 2 1 0 f u llb p bpm a x c o l bpsk i p 1 c a rrb p di sf w p r e s d i s bpbk fr c f d x f c fr c f d x f c g b di r f ca d r not us ed fl ow c ont r o lr e g 15 14 13 12 11 10 9 8 bit(s) f i e l d d e s c r i p t i o n 0 fullb p full backpressure 6 - 1 bpmaxcol maximum number of collisions for backpressure 7 bpskip1 skip one p a cket for backpressure operation 8 carrbp carrier backpressure 9 disfwpres disable forward p resure 10 dis bpbk dis able bac k o f f during bac k p res s u re 1 1 frcfdxfc force full duplex flow control in 10/100 mbp s 12 frcfdxfcgb force full duplex flow control in 1000 mbp s 13 dirfcadr direct flow control addressing 15 - 14 not used not used fullbp in normal o peratio n the backpressu r e pro c e ss i s executed u n til flow con t rol con d ition disa ppea rs o r until the time limit fo r backp re ssure is rea c h ed. this limit is based on eeprom? s bpt i mev a lue regi ster . whe n this config uration is ?0? the backp re ssure pro c e ss will be also limited from ex ce eding the val ue cont ain e d in bpmaxcol field. default value is it s corresponding fullbp pin value. bpmaxcol s pecifie s the numbe r of co nse c utive coll isio n s that wil l determi ne t c 92 04m to q u it backpressure (see the setting above). default is ?01 1 100? (28). bpskip1 if fu llbp setting is configur ed to ?0? and a number of b p maxcol collisions is reach ed, the m a c will ensure receivi ng the ne xt packet withou t colliding it i f th is bit is set to ?1?, af ter which will resume the backpressure. othe rwise it wil l comple tel y qui t backpressure waiting for a new xoff command from internal flow control entity . default is ?0?. carrbp setting this bit to ?1? wil l enabl e carrier-ba se d b a ckpressu re, otherwi se only colli sion -ba s e d ba ckpressure i s exe c uted. defa ult value is it s corre s po n d ing carrbp pin value.
TC9204M preliminary dat a sheet disfw p res whe never b a ckpressu re is en able d , in ca se of e x treme cong estion (me m ory overloa d ) fo rward p r e s sure is al so execut ed unl ess d eactivated by this bit. forward pre s sure is n e ver exe c ute d wh en ba ckpre ssur e is di sabl ed. setting this bit to ?1? wil l disable forward pressure for all half duplex port s . default is ?0?. disbpbk setting this bit to ?1? will cause no b a cko f f to be executed when a h a lf duplex port is in backpressure mod e . this mean s a new colli sio n can be forced immediately a f te r the previou s one if carri er sen s e is ob se rved. setting this bit to ?0? will enable a very aggressive backof f to be exe c uted (re co mmen ded). defa ul t value is it s corresponding disbpbk pin value. frcfdxfc setting this b i t to ?1? will instru ct tc920 4m to disreg ard the a u to-negotiatio n re sul t for the full du plex flow cont rol ability . link p a rt ner will be con s id ere d full duplex flow control able. this setting is ef fective only for port s conf igure d in 10/100 mbp s spe e d modes. default is ?0?. frcfdxfcgb setting this b i t to ?1? will instru ct tc920 4m to disreg ard the a u to-negotiatio n re sul t for the full duplex flow cont rol ability . link p a rtner will be consid ered able to execute symmetri c an d asymmet r ic towards lin k p a rtn e r full du plex flow co ntrol. this settin g is ef fective only for port s configured in 1000 mbp s speed mode. default is ?0?. dirfcadr setting this bi t to ?1? will enable di rect fl ow control addressing mechanism, otherwis e direct flow control addressing is disabled. default is ?0?. confidential. 32/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet 10.3.5 backpressure t i me v a lue register confidential. 33/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05 - address: 31h, 30h 7 6 5 4 3 2 1 0 b p t i m ev a l ue bp t i m e v a l u e 1 5 1 4 13 1 2 11 10 9 8 31h 30h bit(s) f i e l d description 15 ? 0 bpt imev alue backpressure time value bpt i m e v a lue a 16 bit valu e used to co mpute inte rn al time value for ba ckpre s sure ope rati on. default value is ?0000100000000000?(2048). 10.3.6 flow control port base address register - address: 32h, 33h, 34h, 35h, 36h, 37h 47 4 6 45 44 4 3 42 41 4 0 f c ba s e ad d r e s s f c b a seadd r e ss 31 3 0 29 28 2 7 26 25 2 4 3 9 38 3 7 36 35 3 4 33 32 7 6 5 4 3 2 1 0 23 22 2 1 20 19 1 8 17 16 15 14 13 12 11 10 9 8 bit(s) f i e l d description 47 ? 0 fcbaseaddress source port base address for flow control p a cket s fcbaseaddress cont ain s a 48 -bit mac a d d ress used to g enerate the in dividual po rt address u s e d in dire ct flow co ntrol add re ssing. the port addre s se s are obt ai ned b y increme n tin g this base add ress and a ssi gning the re sult to the tc9 204m? s port s st a r ting with port 0. the least significa nt 5 bit s of this addr ess will be ig nore d and re placed with ?0 ?, so these bit s will encode the port number in the actual port address.
TC9204M preliminary dat a sheet 10.3.7 broadcast configuration register confidential. 34/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05 - address: 3dh, 3eh 7 6 5 4 3 2 1 0 b r oa dc a s tc onf ig 15 14 13 12 11 10 9 8 s r cloadt rsh f c b cst e n f c b cst m o de not used th ro ttr s h bcstt h rot reserved not used bit(s) field description 4 - 0 srcloadt rsh source port loading limit for broadcast 5 fcbcsten flow control broadcast enable 6 fcbcstmode flow control broadcast mode 7 not used not used 1 1 -8 thrott rsh global buf fer pool loading threshold for broadcast 12 bcstthrot broadcast throttling (bandwid th) 14 - 13 reserved 15 not used not used srcloadt rsh the maximum number of frame buf fers used on each receiving port for broadcast. default is ?1 1000? (24). fcbcsten setting this bit to ?1? will enable flow control me chani sm for broad ca st fra m es. setting this bit to ?0? will cause b road ca st p a cket s to be dropp ed on queue overfl ow condition. default value is it s corresponding fcbcsten pin value. fcbcstmode this bit select s the source of fl ow control for broadcast operation: ?0? ? broadcast flow control is issued on source port basis ?1? ? broadcast flow control is iss ued by any of the two broadcast queues default value is it s corresponding fcbcstmode pin value. thrott r sh setting this bit to ?1? will enable b and wi d t h ba sed b r oad ca st throttling. the value rep r e s ent s the maximum percent age o f the full receiving band wid t h than ca n be used for broadcast. default is ?00101?(5%). bcstthrot setting this b i t to ?1? will enable th rottlin g for broad ca st frame s . de fault value is it s corresponding bcstthrot pin value.
TC9204M preliminary dat a sheet 10.3.8 ip priority mapping register confidential. 35/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05 - address: 3fh, 40h 7 6 5 4 3 2 1 0 i p tosmapping 15 14 1 3 12 11 10 9 8 to s 0 c l a s s to s 1 c l a s s to s 2 c l a s s to s 3 c l a s s to s 4 c l a s s to s 5 c l a s s to s 6 c l a s s to s 7 c l a s s bit(s) field description 1 - 0 t o s0class priority mapping for ip precedence 0 3 - 2 t o s1class priority mapping for ip precedence 1 5 - 4 t o s2class priority mapping for ip precedence 2 7 - 6 t o s3class priority mapping for ip precedence 3 9 - 8 t o s4class priority mapping for ip precedence 4 1 1 - 10 t o s5class priority mapping for ip precedence 5 13 - 12 t o s6class priority mapping for ip precedence 6 15 - 14 t o s7class priority mapping for ip precedence 7 t o s[x]class this field ma p s the ip prio rity level x fo und in the in coming fram e to one of the fou r priority classes. the t able bellow shows the mapping. t o s[x]class cos 00 class 0 priority 01 class 1 priority 10 class 2 priority 1 1 class 3 priority x ranges in the field 0 to 7.
TC9204M preliminary dat a sheet 10.3.9 vlan priority mapping register confidential. 36/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05 - address: 41h, 42h v l a n p r i mapping pr i 0 cl a s s pr i 1 cl a s s pr i 2 cl a s s pr i 3 cl a s s pr i 4 cl a s s pr i 5 cl a s s pr i 6 cl a s s pr i 7 cl a s s 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 bit(s) field description 1 - 0 pri0class priority mapping for vlan user_priority 0 3 - 2 pri1class priority mapping for vlan user_priority 1 5 - 4 pri2class priority mapping for vlan user_priority 2 7 - 6 pri3class priority mapping for vlan user_priority 3 9 - 8 pri4class priority mapping for vlan user_priority 4 1 1 - 10 pri5class priority mapping for vlan user_priority 5 13 - 12 pri6class priority mapping for vlan user_priority 6 15 - 14 pri7class priority mapping for vlan user_priority 7 pri[x]class this field map s the vlan prio rity level x found in th e incomin g frame to one of the four priority classes. the t able bellow shows the mapping. pri[x]class cos 00 class 0 priority 01 class 1 priority 10 class 2 priority 1 1 class 3 priority x ranges in the field 0 to 7.
TC9204M preliminary dat a sheet 10.3.10 cos bandw id th register confidential. 37/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05 - address: 43h, 44h co sb a n d w id t h co s0 w e i g ht n o t used co s1 w e i g ht n o t used co s2 w e i g ht n o t used co s3 w e i g ht n o t used 7 6 5 4 3 2 1 0 1 5 14 1 3 12 11 1 0 9 8 bit(s) field description 2 - 0 cos0w e ight 000 3 not used not used 6 - 4 cos1w e ight the weight for priority class 1 queue 7 not used not used 10 - 8 cos2w e ight the weight for priority class 2 queue 1 1 not used not used 14 - 12 cos3w e ight the weight for priority class 3 queue 15 not used not used cos[y ] w e ight this field se t s the weigh t for it s associate d prio ri ty queue. the transmission bandwid th percent age given to the associated queue is set by the formula below: 3 queue y ? s priority [%] = f (cos[ y ]w eight) * 100 / ( f (cos[n]w eight) ) n = 0 note: y ranges in 0 to 3 and f is a t abled function described bellow: f(?000?) = 1 f(?100?) = 16 f(?001?) = 2 f(?101?) = 32 f(?010?) = 4 f(?1 10?) = not used f(?01 1 ?) = 8 f(?1 1 1 ?) = not used 10.3.11 reserv e d register - address: 45h, 46h
TC9204M preliminary dat a sheet 10.3.12 cos configuration register confidential. 38/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05 - address: 47h 7 6 5 4 3 2 1 0 eni p p r envl a n pr cos r es ol u t i o n vlanpr ec def c o s no t us ed co s c o n f i g bit(s) field description 0 enippr enable ip priority 1 envlanpr enable vlan priority 2 cosresolution cos resolution mode 3 vlanprec vlan precedence 5 - 4 defcos default class of service 7 - 6 not used not used enippr setting this f i eld to ?1? wil l enabl e ip prio ritizatio n . cos resolut i on fun c tion will con s id er t o s preced ence bit s from ip heade r . def ault value is it s co rre sp ond ing enippr pin value. envlanpr setting this fi eld to ?1? will enabl e vlan pr ioritization. cos resol u tion function will con s id er u s e r -pri ority bit s (tci field) fro m 802.1q vl an t ag hea d er . defa ult value is it s corresponding envlanpr pin value. cosresolution when this bit is set to ?0? the cos reso l u tion function will assi gn to each frame the highest cos obt ained from all enabled prioritization sources. setting this fi eld to ?1?, the resolution function will perform a priori tized p a rsi n g o f cos so urce s, dependi ng o f vlanprec bit. the cos will be assigned consideri n g the first sou r ce that ha s b een foun d wit h in the frame (vlan or ip). if none of the vlan or ip p r ioriti zation source s have been fou nd th en the po rt base d prio ritization is co nsi dered if enabled, otherwise the frame will b e assign ed the default cos. default is ?1?. vlanprec if cosresol u tion field is set to ?0?, this field is meani ngle ss. wh en cosres olution field is set to ?1?, this field will set t he prioritization source s precedence for the resolution function. a value of ?1? will se t the following precedence (from highest t o lowest): vlan priority , ip priority , port priority . a val ue of ?0? will set the following pre c ed en ce (f rom high est to lowe st): ip priority , vlan priority , port priority . default is ?0?. defcos this i s the cos a fram e will receive when po rt based pri o ritization is di sabled and both vlan and ip head ers a r e not found (o r the corre s po n d ing vlan / ip prio ritizatio n s are also disabled ). this config uratio n can be u s ed esp e ci ally whe n cosresolution setting is ?0?. default is ?01? (cos 1).
TC9204M preliminary dat a sheet 10.3.13 port mirroring register confidential. 39/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05 - address: 48h, 49h p o rt m i rr o r r e g so u r ce p o r t no t used de st i nat i o n port no t used en r x m i r r o r en t x m i r r o r no t used no t used no t used 7 6 5 4 3 2 1 0 15 14 1 3 1 2 1 1 10 9 8 bit(s) field description 2 - 0 sourceport source port(monitored port) 3 not used not used 6 - 4 destinationport destination port(monitoring port) 7 not used not used 8 enrxmirror enable mirroring on receiving p a cket s 9 entxmirror enable mirroring on transmitting p a cket s 10 not used not used 1 1 not used not used 15 - 12 not used not used sourceport one of the eight port s of the switch t hat is intended for been monitored throug h port mirro rin g feature. if enable d , the traf fic on this port ca n be addition ally forwa r de d to the monitoring port. only one port can be monitored at a time. destinationport one of the eight port s add ress? s of the swit ch that is intende d to monitor on e of the other port s through port mirro ring feature. thi s port w ill receive all traf fic on the mirror source port. enrxmirror setting this bit to ?1?, the d e stination por t will mirror all the source port? s incomi ng traf fic . entxmirror setting this bit to ?1?, the d e stination por t will mirror all the source port? s outgoing traf fic .
TC9204M preliminary dat a sheet 10.3.14 general configuration register confidential. 40/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05 - address: 4ah 7 6 5 4 3 2 1 0 ge n e r a l c o n f i g aget i m er eg d i s a gi ng f w dbadc r c f w du nd er s i z e re j m ct re j r d a not us ed bit(s) field description 1 ? 0 aget imereg set s the aging time 2 disaging disable aging 3 fwdbadcrc forward bad crc p a cket s 4 fwdundersize forward undersized p a cket s 5 rejmct reject mac control t y pe frames 6 rejrda reject 802.1d reserved group addresses da frames 7 not used not used aget imereg allows 4 values for the aging time to be chosen from. 00 ? 300 seconds 01 ? 600 seconds 10 ? 900 seconds 1 1 ? 1200 seconds default is ?01?(600 seconds). disaging setting this bit to '1' will cause tc9 204 m to disable it s agin g me cha n ism fo r the stored mac addresses. default is '0'. fw dbadcrc setting this bit to ?1? will enable forwarding of bad crc p a cket s . default is '0'. fw dundersize setting this bit to ?1? will enable forwar ding of undersized p a cket s . default is '0' rejmct setting this bit to ?1? will configure the swit ch to filter all frames with mac control t y pe (type 8808). default is ?0?. rejrda setting this bit to ?1? will config ure th e switch to f ilter all fram es with 802. 1d re serve d g r oup destin ation addre ss except for bridge grou p address (01-80-c2-00-00-00). default value is it s corresponding rejrda pin value.
TC9204M preliminary dat a sheet 10.3.15 port vlan enable register confidential. 41/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05 - address: 4fh 7 6 5 4 3 2 1 0 vl an 0 vl an 1 vl an 2 vl an 3 por t vla n e n bit(s) field description 0 vlan0 vlan 0 enable 1 vlan1 vlan 1 enable 2 vlan2 vlan 2 enable 3 vlan3 vlan 3 enable vlan[y ] enables/disables vlan y . ( y is in range 0 to 3) 10.3.16 vlan [ y ] register - address: 50h, 52h, 54h, 56h, 58h, 5ah, 5ch, 5eh 7 6 5 4 3 2 1 0 v l a n [y ]r e g po r t 0 n/ a po r t 2 n/ a po r t 4 n/ a po r t 6 n/ a bit(s) field description 0 port0 port 0 membership to vlan y 1 n/a 2 port2 port 2 membership to vlan y 3 n/a 4 port4 port 4 membership to vlan y 5 n/a 6 port6 port 6 membership to vlan y 7 n/a port[x] port x members h ip to vlan y . ?0? ? port x is not a member of vlan y ?1? ? port x is a member of vlan y
TC9204M preliminary dat a sheet 10.4 w r iting / reading phy management registers via eeprom interface the follo wing set of re giste r s all o ws rea d /write o per ations th rou gh mdio inte rfa c e for dire ct managi ng of physical layer devices. this feature is available through virtual eeprom mode. 10.4.1 dat a w r ite register confidential. 42/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05 - address: 70h, 71h 7 6 5 4 3 2 1 0 da t a w r i t er e g d a t a w r i t er eg 15 14 13 12 11 10 9 8 bit(s) field description 15 - 0 dat a w r itereg mdio dat a w r ite register dat a w r itereg ? cont ains a 16 bit dat a word used to write a phy management register . 10.4.2 phy s ical lay e r dev i ce address register - address: 72h 7 6 5 4 3 2 1 0 d e vi ce a d d r e ss( 4 - 0 ) not u s ed p h yad d r ess bit(s) field description 4 ? 0 deviceaddress physical layer device address register 7 ? 5 not used not used dev i ceaddress ? cont ains a 5 bit word used as device address in mdio operations.
TC9204M preliminary dat a sheet 10.4.3 phy s ical lay e r ? s register address register confidential. 43/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05 - address: 73h 7 6 5 4 3 2 1 0 rega ddr es s( 4- 0) not u s ed regaddr es s bit(s) field description 4 ? 0 regaddress physical layer device? s register address register 7 ? 5 not used not used regaddress ? cont ains a 5 bit word used as r egister address in mdio operations. 10.4.4 io s t atus control register - address: 74h 7 6 5 4 3 2 1 0 rn ot w v a l i d d at are a d m d i o erro r not us e d io c o n t r o l bit(s) field description 0 rnotw operation code 1 v a liddat a read v a lid dat a read 2 mdioerror mdio error 3 ? 7 not used not used rnotw ? operation cod e . setting this bit to ? 1 ? will sele ct read o peratio n otherwise will sele ct write o peratio n. mdi o re ad / w r i t e operation i s st arte d by perfo rming a virtual eeprom write to iocontrol register . v a liddat a read ? i ndicat e s if dat a readreg register cont ains valid dat a. ?1?- dat a valid ?0?- read not performed yet mdioerror ? this bit signals errors on mdio line. ?1?- mdio error . ?0?- mdio read successful.
TC9204M preliminary dat a sheet 10.4.5 dat a read register confidential. 44/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05 - address: 76h, 75h 7 6 5 4 3 2 1 0 dat a readreg dataread reg 1 5 1 4 1 3 1 2 1 1 1 0 9 8 76h 75h bit(s) field description 15 ? 0 dat a readreg mdio dat a read register dat a readreg ? cont ains a 16 bit dat a word read from a phy management register . w r ite operation. before st arting a write operation the following registers need to be set : phy a ddress ? written with mdio device address regaddress ? written with mdio register address dat a w r itereg ? dat a word to be write to selected register the write operation is then st ar ted by performing a write to iocontrol register with bit 0 cleared. read operation. before st arting a read operation the following registers need to be set : phy a ddress ? written with mdio device address regaddress ? written with mdio register address the write operation is then st ar ted by performing a write to iocontrol regis t er with bit 0 s e t. subse que ntly , the iocontrol regi ster n eed s to be monitored in orde r to dete c t mdio o p e r ation e r ror repo rted via io c o nt r o l ? s b i t 2. the v a liddat a read bit is alway s read as ?1? unles s the eeprom line is driven at over 1mhz speed. if no error occurred then dat a can be read from dat a readreg .
TC9204M preliminary dat a sheet 11 t i ming requirement s 11.1 gmii / mii receive t i ming requirement s sy mbol description min. ty p . max. unit rx _clk receive clock period gmii - 8 - ns rx _clk receive clock period mii - 40 - ns t srx _ clk rxdv , rxdat a to rx_clk rising setup time 2 - - ns t hrx _ clk rxdv , rxdat a to rx_clk rising hold time 0.5 - - ns gm i i / m i i r e ceive rx _ c l k rx dv rx dat a t sr x _ c l k t hr x _ c l k t rx _ c l k 11.2 gmii / mii t r ansmit t i ming sy mbol description min. ty p . max. unit t tx _ c l k t r ansmit clock period gmii - 8 - ns t tx _ c l k t r ansmit clock period mii - 40 - ns t dt x _ clk tx_en, txdat a to tx_clk rising delay 1 - 4 ns g m ii / mi i t r a n s m i t t dt x _ c l k tx _c l k tx _e n tx d a t a t tx _ c l k confidential. 45/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet 11.3 phy management (mdio) t i ming sy mbol description min. ty p . max. unit t ch m d c k h i g h t i m e - 3 0 0 - n s t cl m d c k l o w t i m e - 3 0 0 - n s t cm m d c k p e r i o d - 6 0 0 - n s t md mdio output delay - - 50 ns t mh mdio hold time 10 - - ns md c l k md i o t ms t mh m d io wr ite cicle t cl t ch t cm t md m dcl k md i o m d io re ad cic l e confidential. 46/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet 11.4 eeprom t i ming sy mbol description min. ty p . max. unit f scl s c l f r e q u e n c y - 6 6 . 6 - k h z t low clock pulse wid t h low 10 - - us t high clock pulse wid t h high 10 - - us t buf t i me the bu s must be fre e before st arting a new transmission 5 - - u s t hd.st a s t art h o l d t i m e 5 - - u s t su.st a s t art s e t u p t i m e 5 - - u s t hd.da t d a t a h o l d t i m e 5 - - u s t su.da t d a t a s e t u p t i m e 5 - - u s t su.st o s t op s e t - u p t i m e 5 - - u s t aa clock low to dat a out v a lid - - 4.9 us t dh dat a out hold t i me 0 - - us sc l sda ( o u t put ) sd a ( i np ut ) va l i d t lo w t hi g h t su .s t a t hd. s t a t bu f ee pr o m i n t e rf a c e ti m i n g t hd. da t t su . d at t su . s t o t aa t dh va l i d va l i d v a l i d confidential. 47/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet 12 electrical s p ecifications 12.1 absolute maximum ra tings perman ent d e vice dam ag e may occur i f absolute ma ximum rating s are ex cee d ed. fun c tiona l operati o n sho u ld b e re stri cted to th e co ndition s as spe c ifi ed i n the re com m ende d o p e r ating co nditions se ction. exposure to the absolute maximum conditions fo r extended periods may af fect device reliability . p arameter symbol min. max. unit i / o v ddi/o ? 0 . 5 4 . 6 v supply v o lt age c o r e v d d c o r e ? 0.5 2.5 v input v o lt age v i ? 0 . 5 6 v output v o lt age v o ? 0 . 5 6 v s t orage t e mperature t st g - 6 5 + 1 5 0 c operation t e mperature t opt 0 7 0 c latch-up current i la t ch > 5 0 0 m a note: the maximum ratings are the limit value that must never be exceeded even for short time. 12.2 recommended opera t ing conditions the re comm ende d opera t ing conditio n s rep r e s e n t s recomme n ded value s that assure n o rmal logi c operation. as long as th e device i s use d within t he recom m en ded operating co ndition s, the electri c al characteristics (dc and ac characteristics) are guaranteed. p arameter symbol min. typ . max. unit i / o v ddi/o 3 . 0 3 . 3 3 . 6 v supply v o lt age c o r e v d d c o r e 1 . 9 5 2 . 0 2 . 0 5 v junction t e mperature t j 1 2 5 c low-level input volt age v i l - 0 . 5 1 . 0 v high-level input volt age v i h 2 . 0 5 . 5 v 12.3 dc characteristics p arameter symbol min. typ . max. unit output low volt age v ol 0 . 4 v output high volt age v oh 2 . 4 v low level output current @vol=0.4v i ol 8 . 8 1 4 . 1 1 7 . 0 m a high level output current @voh=2.4v i oh 1 2 . 8 2 5 . 7 4 0 . 0 m a input t r eshold point v t 1 . 4 6 1 . 6 0 1 . 7 6 v gmii input (schmitt trig.) low to hi gh treshold point *1 v t+ 1 . 6 6 1 . 7 5 1 . 7 9 v gmii input (schmitt trig.) high to lo w treshold point *1 v t- 0 . 9 3 1 . 0 1 1 . 0 6 v input leakage current (high and low) i i + / - 1 0 + / - 1 0 0 0 n a t r i-st ate o u tp ut leakag e current (hi gh and low) i oz + / - 1 0 + / - 1 0 0 0 n a pull-up resistor r pu 5 6 7 7 1 2 2 k ? pull-down resistor r pd 5 1 6 9 1 2 7 k ? note: *1 this refers to all input s described as gmii in the pin listing section. confidential. 48/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05
TC9204M preliminary dat a sheet confidential. 49/49 july 29, 2003 copyright ? 2003, i c p l u s c o r p . t c 9204m-ds-r05 13 package det a il lead pitch 0.50 mm package wid t h x package length 28 x 28 mm lead shape gullwing sealing method plastic mold ic plus corp. h e a d q u a r t e r s s a l e s o f f i c e 10f , no.47, lane 2, kwang-fu road, sec. 2, 4f , no. 106, hsin-t ai-w u road, sec.1, hsin-chu city , t a iwan 300, r.o.c. hsi-ch ih, t a ipei hsien, t a iwan 221, r.o.c. tel : 886-3-575-0275 f a x : 8 8 6 - 3 - 5 7 5 - 0 4 7 5 t e l : 886-2-2 696-166 9 f a x : 886-2 - 2696 -22 2 0 w ebsite : www . i cplus. com. t w

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