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1 features ? ntegrated single-chip 10/100 mbps ethernet switch ? 24 10/100 mbps autosensing, fast ethernet ports with rmii or serial interface (7ws). each port can independently use one of the two interfaces ? serial interface ? supports one frame buffer memory domain with sram at 100mhz ? supports sram domain memory size 1mb or 2mb ? applies centralized shared memory architecture ? up to 64k mac addresses ? maximum throughput is 2.4 gbps non-blocking ? high performance packet forwarding (3.571m packets per second) at full wire speed ? full duplex ethernet ieee 802.3x flow control ? backpressure flow control for half duplex ports ? supports ethernet multicasting and broadcasting and flooding control ? supports per-system option to enable flow control for best effort frames even on qos- enabled ports ? load sharing among trunked ports can be based on source mac and/or destination mac ? port mirroring to a dedicated mirroring port or port 23 in unmanaged mode ? full set of led signals provided by a serial interface ? 2 port trunking groups with up to 4 10/100 ports per group ? built-in self test for internal and external sram ? traffic classification ? 4 transmission priorities for fast ethernet ports with 2 dropping levels ? classification based on: -port based priority -vlan priority field in vlan tagged frame - ds/tos field in ip packet - udp/tcp logical ports: 8 hard-wired and 8 programmable ports, including one pro- grammable range ? the precedence of the above classifications is programmable ? qos support ds5774 issue 2 october 2002 ordering information MVTX2601Ag 553 pin bga -40c to 85c figure 1 - MVTX2601Ag system block diagram fdb interface frame data buffer a sram (1m / 2m) led search engine mct link frame engine fcb parallel / serial management module 24 x 10 / 100 rmii ports 0 - 23 vlan 1 mct MVTX2601Ag integrated 10/100 mbps ethernet switch data sheet
MVTX2601Ag data sheet 2 zarlink semiconductor inc. ? supports ieee 802.1p/q quality of service with 4 transmission priority queues with delay bounded, strict priority, and wfq service disciplines ? provides 2 levels of dropping precedence with wred mechanism ? user controls the wred thresholds. ? buffer management: per class and per port buffer reservations ? port-based priority: vlan priority in a tagged frame can be overwritten by the priority of port vlan id. ? hardware auto-negotiation through serial management interface (mdio) for ethernet ports ? built-in reset logic triggered by system malfunction ?i 2 c eeprom for configuration description the MVTX2601Ag is a high density, low cost, high performance, non-blocking ethernet switch chip. a single chip provides 24 ports at 10/100 mbps, and a cpu interface for managed and unmanaged switch applications. the chip supports up to 64k mac addresses. the centralized shared memory architecture permits a very high performance packet forwarding rate at up to 3.571m packets per second at full wire speed. the chip is optimized to provide low-cost, high-performance workgroup switching. the frame buffer memory domains utilize cost-effective, high-performance synchronous sram with aggregate bandwidth of 6.4 gbps to support full wire speed on all ports simultaneously. with delay bounded, strict priority, and/or wfq transmission scheduling, and wred dropping schemes, the MVTX2601Ag provides powerful qos functions for various multimedia and mission-critical applications. the chip provides 4 transmission priorities and 2 levels of dropping precedence. each packet is assigned a transmission priority and dropping precedence based on the vlan priority field in a vlan tagged frame, or the ds/tos field, or the udp/tcp logical port fields in ip packets. the MVTX2601Ag recognizes a total of 16 udp/tcp logical ports, 8 hard-wired and 8 programmable (including one programmable range). the MVTX2601Ag supports 2 groups of port trunking/load sharing. each 10/100 group can contain up to 4 ports. port trunking/load sharing can be used to group ports between interlinked switches to increase the effective network bandwidth. in half-duplex mode, all ports support backpressure flow control, to minimize the risk of losing data during long activity bursts. in full-duplex mode, ieee 802.3x flow control is provided. the MVTX2601Ag also supports a per-system option to enable flow control for best effort frames, even on qos-enabled ports. the MVTX2601Ag is fabricated using 0.25 micron technology. inputs, however, are 3.3 v tolerant, and the outputs are capable of directly interfacing to lvttl levels. the MVTX2601Ag is packaged in a 553-pin ball grid array package.
data sheet MVTX2601Ag 3 zarlink semiconductor inc. table of contents 1.0 block functionality ........................................................................................................ .. 11 1.1 frame data buffer (fdb) interfaces......................................................................................... ..................11 1.2 10/100 mac module (rmac)................................................................................................... ..................11 1.3 configuration interface module ............................................................................................. .....................11 1.4 frame engine ............................................................................................................... ..............................11 1.5 search engine .............................................................................................................. ..............................11 1.6 led interface.............................................................................................................. ................................11 1.7 internal memory............................................................................................................ ..............................11 2.0 system configuration ...................................................................................................... 1 1 2.1 configuration mode ......................................................................................................... ...........................11 2.2 i2c interface .............................................................................................................. .................................12 2.2.1 start condition .......................................................................................................... .......................... 12 2.2.2 address .................................................................................................................. ............................. 12 2.2.3 data direction ........................................................................................................... .......................... 12 2.2.4 acknowledgment ........................................................................................................... ...................... 12 2.2.5 data..................................................................................................................... ................................ 12 2.2.6 stop condition........................................................................................................... .......................... 12 2.3 synchronous serial interface ............................................................................................... ......................12 2.3.1 write command ............................................................................................................ ...................... 13 2.3.2 read command ............................................................................................................. ..................... 13 3.0 MVTX2601Ag data forwarding protocol ....................................................................... 13 3.1 unicast data frame forwarding.............................................................................................. ...................13 3.2 multicast data frame forwarding ............................................................................................ ..................14 4.0 memory interface........................................................................................................... ... 15 4.1 overview................................................................................................................... ..................................15 4.2 detailed memory information ................................................................................................ .....................15 4.3 memory requirements ........................................................................................................ .......................15 5.0 search engine .............................................................................................................. .... 16 5.1 search engine overview ..................................................................................................... .......................16 5.2 basic flow ................................................................................................................. .................................16 5.3 search, learning and aging ................................................................................................. ......................17 5.3.1 mac search ............................................................................................................... ......................... 17 5.3.2 learning ................................................................................................................. ............................. 17 5.3.3 aging .................................................................................................................... ............................... 17 5.4 quality of service ......................................................................................................... ..............................17 5.5 priority classification rule............................................................................................... ...........................18 5.6 port based vlan ............................................................................................................ ...........................18 5.7 memory configurations ...................................................................................................... ........................19 6.0 frame engine............................................................................................................... ..... 24 6.1 data forwarding summary.................................................................................................... .....................24 6.2 frame engine details ....................................................................................................... ..........................24 6.2.1 fcb manager .............................................................................................................. ........................ 24 6.2.2 rx interface ............................................................................................................. ............................ 25 6.2.3 rxdma .................................................................................................................... ............................ 25 6.2.4 txq manager .............................................................................................................. ........................ 25 6.3 port control ............................................................................................................... .................................25 6.4 txdma...................................................................................................................... ..................................25 7.0 quality of service and flow control............................................................................... 25 7.1 model...................................................................................................................... ....................................25 7.2 four qos configurations.................................................................................................... ........................27
MVTX2601Ag data sheet 4 zarlink semiconductor inc. table of contents 7.3 delay bound ................................................................................................................ .............................. 27 7.4 strict priority and best effort............................................................................................ .......................... 28 7.5 weighted fair queuing ...................................................................................................... ........................ 28 7.6 wred drop threshold management support..................................................................................... ...... 28 7.7 buffer management .......................................................................................................... ......................... 29 7.7.1 dropping when buffers are scarce ......................................................................................... ...........30 7.8 MVTX2601Ag flow control basics ............................................................................................. .............. 30 7.8.1 unicast flow control ..................................................................................................... ......................31 7.8.2 multicast flow control ................................................................................................... ......................31 7.9 mapping to ietf diffserv classes ........................................................................................... .................. 31 8.0 port trunking .............................................................................................................. ...... 32 8.1 features and restrictions .................................................................................................. ........................ 32 8.2 unicast packet forwarding .................................................................................................. ...................... 32 8.3 multicast packet forwarding................................................................................................ ...................... 32 8.4 trunking ................................................................................................................... .................................. 33 9.0 port mirroring............................................................................................................. ....... 33 9.1 port mirroring features .................................................................................................... .......................... 33 9.2 setting registers for port mirroring....................................................................................... ..................... 33 10.0 gpsi (7ws) interface ...................................................................................................... 34 10.1 gpsi connection ........................................................................................................... ........................... 34 10.2 scan link and scan col interface.......................................................................................... ........... 35 11.0 led interface............................................................................................................. ...... 35 11.1 led interface introduction ................................................................................................ ....................... 35 11.2 port status ............................................................................................................... ................................ 35 11.3 led interface timing diagram.............................................................................................. ................... 36 12.0 register definition....................................................................................................... ... 37 12.1 MVTX2601Ag register description ........................................................................................... ............. 37 12.2 group 0 address mac ports group ........................................................................................... ............. 42 12.2.1 ecr1pn: port n control register ......................................................................................... ............42 12.2.2 ecr2pn: port n control register ......................................................................................... ............43 12.3 group 1 address vlan group ............................................................................................... ................ 44 12.3.1 avtcl ? vlan type code register low ..................................................................................... ....44 12.3.2 avtch ? vlan type code register high.................................................................................... ....44 12.3.3 pvmap00_0 ? port 00 configuration register 0............................................................................ ...44 12.3.4 pvmap00_1 ? port 00 configuration register 1............................................................................ ...44 12.3.5 pvmap00_2 ? port 00 configuration register 2............................................................................ ...44 12.3.6 pvmap00_3 ? port 00 configuration register 3............................................................................ ...45 12.4 port configuration register............................................................................................... ....................... 45 12.4.1 pvmode .................................................................................................................. .........................46 12.5 group 2 address port trunking group ....................................................................................... ............. 46 12.5.1 trunk0_mode? trunk group 0 mode ......................................................................................... ...46 12.5.2 trunk1_mode ? trunk group 1 mode ........................................................................................ ...47 12.5.3 trunk1_hash0 ? trunk group 1 hash result 0 destination port number .......................................47 12.5.4 tx_age ? tx queue aging timer ........................................................................................... ..........47 12.6 group 4 address search engine group ....................................................................................... ........... 47 12.6.1 agetime_low ? mac address aging time low .............................................................................47 12.6.2 e_high ?mac address aging time high ..................................................................................... .....48 12.6.3 v_agetime ? vlan to port aging time ..................................................................................... ......48 12.6.4 se_opmode ? search engine operation mode .............................................................................48 12.8 group 5 address buffer control/qos group.................................................................................. ......... 49
data sheet MVTX2601Ag 5 zarlink semiconductor inc. table of contents 12.8.1 fcbat ? fcb aging timer ................................................................................................. .............. 49 12.8.2 qosc ? qos control ...................................................................................................... ................. 49 12.8.3 fcr ? flooding control register ......................................................................................... ............. 49 12.8.4 avpml ? vlan priority map ............................................................................................... ............. 50 12.8.5 avpmm ? vlan priority map ............................................................................................... ............ 50 12.8.6 avpmh ? vlan priority map ............................................................................................... ............. 51 12.8.7 tospml ? tos priority map ............................................................................................... ............. 51 12.8.8 tospmm ? tos priority map ............................................................................................... ............ 51 12.8.9 tospmh ? tos priority map ............................................................................................... ............ 52 12.8.10 avdm ? vlan discard map ................................................................................................ ........... 52 12.8.11 tosdml ? tos discard map............................................................................................... .......... 53 12.8.12 bmrc - broadcast/multicast rate control ................................................................................ ...... 53 12.8.13 ucc ? unicast congestion control....................................................................................... .......... 53 12.8.14 mcc ? multicast congestion control ..................................................................................... ......... 54 12.8.15 pr100 ? port reservation for 10/100 ports .............................................................................. ...... 54 12.8.16 sfcb ? share fcb size .................................................................................................. ............... 54 12.8.17 c2rs ? class 2 reserve size ............................................................................................ ............ 55 12.8.18 c3rs ? class 3 reserve size ............................................................................................ ............ 55 12.8.19 c4rs ? class 4 reserve size ............................................................................................ ............ 55 12.8.20 c5rs ? class 5 reserve size ............................................................................................ ............ 55 12.8.21 c6rs ? class 6 reserve size ............................................................................................ ............ 55 12.8.22 c7rs ? class 7 reserve size ............................................................................................ ............ 56 12.8.23 classes byte limit set 0 ............................................................................................... .................. 56 12.8.24 classes byte limit set 1 ............................................................................................... .................. 56 12.8.25 classes byte limit set 2 ............................................................................................... .................. 56 12.8.26 classes byte limit set 3 ............................................................................................... .................. 57 12.8.27 classes wfq credit set 0 ............................................................................................... ............... 57 12.8.28 classes wfq credit set 1 ............................................................................................... ............... 57 12.8.29 classes wfq credit set 2 ............................................................................................... ............... 57 12.8.30 classes wfq credit set 3 ............................................................................................... ............... 58 12.8.31 rdrc0 ? wred rate control 0............................................................................................ ......... 58 12.8.32 rdrc1 ? wred rate control 1............................................................................................ ......... 58 12.8.33 user defined logical ports and well known ports ........................................................................ .59 12.8.33.1 user_port0_(0~7) ? user define logical port (0~7) .........................................................59 12.8.33.2 user_port_[1:0]_priority - user define logic port 1 and 0 priority..............................60 12.8.33.3 user_port_[3:2]_priority - user define logic port 3 and 2 priority..............................60 12.8.33.4 user_port_[5:4]_priority - user define logic port 5 and 4 priority..............................60 12.8.33.5 user_port_[7:6]_priority - user define logic port 7 and 6 priority..............................60 12.8.33.6 user_port_enable [7:0] ? user define logic 7 to 0 port enables ..................................61 12.8.33.7 well_known_port [1:0] priority- well known logic port 1 and 0 priority .................61 12.8.33.8 well_known_port [3:2] priority- well known logic port 3 and 2 priority .................61 12.8.33.9 well_known_port [5:4] priority- well known logic port 5 and 4 priority .................61 12.8.33.10 well_known_port [7:6] priority- well known logic port 7 and 6 priority ...............62 12.8.33.11 well known_port_enable [7:0] ? well known logic 7 to 0 port enables .................62 12.8.33.12 rlowl ? user define range low bit 7:0 ............................................................................62 12.8.33.13 rlowh ? user define range low bit 15:8..........................................................................62 12.8.33.14 rhighl ? user define range high bit 7:0...........................................................................62 12.8.33.15 rhighh ? user define range high bit 15:8 ........................................................................62 12.8.33.16 rpriority ? user define range priority ............................................................................62 12.9 group 6 address misc group ............................................................................................... .................63 12.9.1 mii_op0 ? mii register option 0 ......................................................................................... ............. 63 12.9.2 mii_op1 ? mii register option 1 ......................................................................................... ............. 63
MVTX2601Ag data sheet 6 zarlink semiconductor inc. table of contents 12.9.3 fen ? feature register.................................................................................................. ...................64 12.9.4 miic0 ? mii command register 0 .......................................................................................... ...........64 12.9.5 miic1 ? mii command register 1 .......................................................................................... ...........64 12.9.6 miic2 ? mii command register 2 .......................................................................................... ...........64 12.9.7 miic3 ? mii command register 3 .......................................................................................... ...........65 12.9.8 miid0 ? mii data register 0 ............................................................................................. .................65 12.9.9 miid1 ? mii data register 1 ............................................................................................. .................65 12.9.10 led mode ? led control ................................................................................................. ...............65 12.9.11 device mode ............................................................................................................ .....................66 12.9.12 checksum - eeprom checksum ............................................................................................. ..66 12.10 group 7 address port mirroring group .................................................................................... ............. 66 12.10.1 mirror1_src ? port mirror source port .................................................................................. ....66 12.10.2 mirror1_dest ? port mirror destination ................................................................................. ....67 12.10.3 mirror2_src ? port mirror source port .................................................................................. ....67 12.10.4 mirror2_dest ? port mirror destination ................................................................................. ....67 12.11 group f address cpu access group ......................................................................................... .......... 67 12.11.1 gcr-global control register ............................................................................................ ..............67 12.11.2 dcr-device status and signature register............................................................................... .....68 12.11.3 dcr1-chip status....................................................................................................... .....................69 12.11.4 dpst ? device port status register..................................................................................... ..........69 12.11.5 dtst ? data read back register......................................................................................... .............70 12.11.6 da ? da register ....................................................................................................... .....................70 13.0 bga and ball signal descriptions ................................................................................ 71 13.1 bga views................................................................................................................. .............................. 71 13.1.1 encapsulated view ...................................................................................................... .....................71 13.1.2 power and ground distribution ........................................................................................... ..............72 13.2 ball ? signal descriptions ............................................................................................... ........................ 73 13.2.1 ball signal descriptions................................................................................................ .....................73 13.3 ball ? signal name ........................................................................................................ .......................... 81 13.4 ac/dc timing ............................................................................................................ ............................ 87 13.4.1 absolute maximum ratings................................................................................................ ...............87 13.4.2 dc electrical characteristics ........................................................................................... ..................87 13.4.3 recommended operation conditions ........................................................................................ .......88 13.5 local frame buffer sbram memory interface................................................................................. ....... 89 13.5.1 local sbram memory interface: ........................................................................................... ...........89 13.6 ac characteristics ........................................................................................................ ........................... 90 13.6.1 reduced media independent interface ..................................................................................... ........90 13.6.2 led interface........................................................................................................... ..........................91 13.6.3 scanlink scancol output delay timing ................................................................................... 91 13.6.4 mdio input setup and hold timing........................................................................................ ...........92 13.6.5 i 2 c input setup timing ........................................................................................................... ..........93 13.6.6 serial interface setup timing ........................................................................................... .................94
data sheet MVTX2601Ag 7 zarlink semiconductor inc. list of figures figure 1 - MVTX2601Ag system block diagram .................................................................................... ................1 figure 2 - data transfer format for i2c interface ............................................................................. .....................12 figure 3 - MVTX2601Ag sram interface block diagram (dmas for 10/1000 ports only) ...................................15 figure 4 - memory map ......................................................................................................... .................................16 figure 5 - priority classification rule ....................................................................................... ..............................18 figure 6 - memory configuration for 2 banks, 1 layer, 2mb total ............................................................... .........20 figure 7 - memory configuration for: 2 banks, 2 layers, 4mb total ............................................................. ........21 figure 8 - memory configuration for 2 banks, 1 layer, 4mb ..................................................................... ............22 figure 9 - memory configuration for: 2 banks, 2 layers 4mb total .............................................................. .........23 figure 10 - memory configuration for 2 banks, 1 layer, 4mb .................................................................... ...........24 figure 11 - buffer partition scheme used to implement MVTX2601Ag buffer management ...............................30 figure 12 - gpsi (7ws) mode connection diagram ................................................................................ ...............34 figure 13 - scan link and scan collison status diagram ........................................................................ ....35 figure 14 - timing diagram of led interface ................................................................................... .....................36 figure 15 - local memory interface ? input setup and hold timing .............................................................. ..........89 figure 16 - local memory interface - output valid delay timing ................................................................ .............89 figure 17 - ac characteristics ? reduced media independent interface .......................................................... ....90 figure 18 - ac characteristics ? reduced media independent interface .......................................................... ....90 figure 19 - ac characteristics ? led interface ................................................................................ .....................91 figure 20 - scanlink scancol output delay timing ............................................................................. .........91 figure 21 - scanlink, scancol setup timing .................................................................................... .............91 figure 22 - mdio input setup and hold timing .................................................................................. ...................92 figure 23 - mdio output delay timing .......................................................................................... .......................92 figure 24 - i 2 c input setup timing .......................................................................................................... ..............93 figure 25 - i 2 c output delay timing ......................................................................................................... .............93 figure 26 - serial interface setup timing ..................................................................................... .........................94 figure 27 - serial interface output delay timing .............................................................................. .....................94
MVTX2601Ag data sheet 8 zarlink semiconductor inc.
data sheet MVTX2601Ag 9 zarlink semiconductor inc. list of tables table 1 - memory configuration ................................................................................................. ............................15 table 2 - pvmap register ....................................................................................................... ...............................19 table 3 - supported memory configurations (sbram mode) ......................................................................... .......19 table 4 - options for memory configuration ..................................................................................... ......................19 table 5 - two dimensional world traffic ........................................................................................ ........................26 table 6 - four qos configurations for a 10/100mbps port ........................................................................ ............27 table 7 - wred drop thresholds ................................................................................................. .........................28 table 8 - mapping between MVTX2601Ag and ietf diffserv classes for 10/100 ports .......................................31 table 9 - MVTX2601Ag features enabling ietf diffserv standards ................................................................. ...32 table 10 - ac characteristics ? reduced media independent interface ............................................................ ....90 table 10 - ac characteristics ? led interface .................................................................................. .....................91 table 10 - scanlink, scancol timing............................................................................................ ..................92 table 10 - mdio timing......................................................................................................... .................................92 table 10 - i2c timing .......................................................................................................... ...................................93 table 10 - serial interface timing ............................................................................................. ..............................94
MVTX2601Ag data sheet 10 zarlink semiconductor inc.
MVTX2601Ag data sheet 11 zarlink semiconductor inc. 1.0 block functionality 1.1 frame data buffer (fdb) interfaces the fdb interface supports pipelined synchronous burst sram (sbram) memory at 100 mhz. to ensure a non-blocking switch, one memory domain with a 64 bit wide memory bus is required. at 100 mhz, the aggregate memory bandwidth is 6.4 gbps, which is enough to support 24 10/100 mbps. the switching database is also located in the external sbram; it is used for storing mac addresses and their physical port number. 1.2 10/100 mac module (rmac) the 10/100 media access control module provides the necessary buffers and control interface between the frame engine (fe) and the external physical device (phy). the MVTX2601Ag has two interfaces, rmii or serial (only for 10m). the 10/100 mac of the MVTX2601Ag device meets the ieee 802.3 specification. it is able to operate in either half or full duplex mode with a back pressure/flow control mechanism. in addition, it will automatically retransmit upon collision for up to 16 total transmissions. the phy addresses for 24 10/100 mac are from 08h to 1fh. 1.3 configuration interface module the MVTX2601Ag supports a serial and an i 2 c interface, which provides an easy way to configure the system. once configured, the resulting configuration can be stored in an i 2 c eeprom. 1.4 frame engine the main function of the frame engine is to forward a frame to its proper destination port or ports. when a frame arrives, the frame engine parses the frame header (64 bytes) and formulates a switching request, sent to the search engine, to resolve the destination port. the arriving frame is moved to the fdb. after receiving a switch response from the search engine, the frame engine performs transmission scheduling based on the frame?s priority. the frame engine forwards the frame to the mac module when the frame is ready to be sent. 1.5 search engine the search engine resolves the frame?s destination port or ports according to the destination mac address (l2). it also performs mac learning, priority assignment, and trunking functions. 1.6 led interface the led interface provides a serial interface for carrying 24 port status signals. 1.7 internal memory several internal tables are required and are described as follows: ? frame control block (fcb) - each fcb entry contains the control information of the associated frame stored in the fdb, e.g. frame size, read/write pointer, transmission priority, etc. ? mct link table - the mct link table stores the linked list of mct entries that have collisions in the external mac table. the external mac table is located in the fdb memory. note: the external mac table is located in the external sbram memory. 2.0 system configuration 2.1 configuration mode the MVTX2601Ag can be configured by eeprom (24c02 or compatible) via an i 2 c interface at boot time, or via a synchronous serial interface during operation.
MVTX2601Ag data sheet 12 zarlink semiconductor inc. 2.2 i 2 c interface the i 2 c interface uses two bus lines, a serial data line (sda) and a serial clock line (scl). the scl line carries the control signals that facilitate the transfer of information from eeprom to the switch. data transfer is 8-bit serial and bidirectional, at 50 kbps. data transfer is performed between master and slave ic using a request / acknowledgment style of protocol. the master ic generates the timing signals and terminates data transfer. figure 2 depicts the data transfer format. figure 2 - data transfer format for i 2 c interface 2.2.1 start condition generated by the master (in our case, the MVTX2601Ag). the bus is considered to be busy after the start condition is generated. the start condition occurs if while the scl line is high, there is a high-to-low transition of the sda line. other than in the start condition (and stop condition), the data on the sda line must be stable during the high period of scl. the high or low state of sda can only change when scl is low. in addition, when the i 2 c bus is free, both lines are high. 2.2.2 address the first byte after the start condition determines which slave the master will select. the slave in our case is the eeprom. the first seven bits of the first data byte make up the slave address. 2.2.3 data direction the eighth bit in the first byte after the start condition determines the direction (r/w) of the message. a master transmitter sets this bit to w; a master receiver sets this bit to r. 2.2.4 acknowledgment like all clock pulses, the acknowledgment-related clock pulse is generated by the master. however, the transmitter releases the sda line (high) during the acknowledgment clock pulse. furthermore, the receiver must pull down the sda line during the acknowledge pulse so that it remains stable low during the high period of this clock pulse. an acknowledgment pulse follows every byte transfer. if a slave receiver does not acknowledge after any byte, then the master generates a stop condition and aborts the transfer. if a master receiver does not acknowledge after any byte, then the slave transmitter must release the sda line to let the master generate the stop condition. 2.2.5 data after the first byte containing the address, all bytes that follow are data bytes. each byte must be followed by an acknowledge bit. data is transferred msb first. 2.2.6 stop condition generated by the master. the bus is considered to be free after the stop condition is generated. the stop condition occurs if while the scl line is high, there is a low-to-high transition of the sda line. the i 2 c interface serves the function of configuring the MVTX2601Ag at boot time. the master is the MVTX2601Ag, and the slave is the eeprom memory. 2.3 synchronous serial interface the synchronous serial interface serves the function of configuring the MVTX2601Ag not at boot time but via a pc. the pc serves as master and the MVTX2601Ag serves as slave. the protocol for the synchronous serial start slave address r/w ack data 1 (8 bits) ack data 2 ack data m ack stop
MVTX2601Ag data sheet 13 zarlink semiconductor inc. interface is nearly identical to the i 2 c protocol. the main difference is that there is no acknowledgment bit after each byte of data transferred. the unmanaged MVTX2601Ag uses a synchronous serial interface to program the internal registers. to reduce the number of signals required, the register address, command and data are shifted in serially through the d0 pin. strobe- pin is used as the shift clock. autofd- pin is used as data return path. each command consists of four parts. start pulse register address read or write command data to be written or read back any command can be aborted in the middle by sending a abort pulse to the MVTX2601Ag. a start command is detected when d0 is sampled high when strobe- rise and d0 is sampled low when strobe- fall. an abort command is detected when d0 is sampled low when strobe- rise and d0 is sampled high when strobe- fall. 2.3.1 write command 2.3.2 read command all registers in MVTX2601Ag can be modified through this synchronous serial interface. 3.0 MVTX2601Ag data forwarding protocol 3.1 unicast data frame forwarding when a frame arrives, it is assigned a handle in memory by the frame control buffer manager (fcb manager). an fcb handle will always be available, because of advance buffer reservations. the memory (sram) interface consists of a 64-bit bus connected to sram bank. the receive dma (rxdma) is responsible for multiplexing the data and the address. on a port?s ?turn,? the rxdma will move 8 bytes (or up to the end-of-frame) from the port?s associated rxfifo into memory (frame data buffer, or fdb). strobe- d0 start address command data w a0 a1 a2 ... a9 a10 a11 d0 d1 d2 d3 d4 d5 d6 d7 2 extra clock cycles after last transfer strobe- d0 autofd- a0 a1 a2 ... a9 a10 a11 r d0 d1 d2 d3 d4 d5 d6 d7 start address command data a10 a11 a9 a2 d2 d0 d4 d5 d3 a1 a2 a0 d1 d6 d7
MVTX2601Ag data sheet 14 zarlink semiconductor inc. once an entire frame has been moved to the fdb, and a good end-of-frame (eof) has been received, the rx interface makes a switch request. the rxdma arbitrates among multiple switch requests. the switch request consists of the first 64 bytes of a frame, containing among other things, the source and destination mac addresses of the frame. the search engine places a switch response in the switch response queue of the frame engine when done. among other information, the search engine will have resolved the destination port of the frame and will have determined that the frame is unicast. after processing the switch response, the transmission queue manager (txq manager) of the frame engine is responsible for notifying the destination port that it has a frame to forward to it. but first, the txq manager has to decide whether or not to drop the frame, based on global fdb reservations and usage, as well as txq occupancy at the destination. if the frame is not dropped, then the txq manager links the frame?s fcb to the correct per-port-per-class txq. unicast txq?s are linked lists of transmission jobs, represented by their associated frames? fcb?s. there is one linked list for each transmission class for each port. there are 4 transmission classes for each of the 24 10/ 100 ports the txq manager is responsible for scheduling transmission among the queues representing different classes for a port. when the port control module determines that there is room in the mac transmission fifo (txfifo) for another frame, it requests the handle of a new frame from the txq manager. the txq manager chooses among the head-of-line (hol) frames from the per-class queues for that port, using a zarlink semiconductor scheduling algorithm. the transmission dma (txdma) is responsible for multiplexing the data and the address. on a port?s turn, the txdma will move 8 bytes (or up to the eof) from memory into the port?s associated txfifo. after reading the eof, the port control requests a fcb release for that frame. the txdma arbitrates among multiple buffer release requests. the frame is transmitted from the txfifo to the line. 3.2 multicast data frame forwarding after receiving the switch response, the txq manager has to make the dropping decision. a global decision to drop can be made, based on global fdb utilization and reservations. if so, then the fcb is released and the frame is dropped. in addition, a selective decision to drop can be made, based on the txq occupancy at some subset of the multicast packet?s destinations. if so, then the frame is dropped at some destinations but not others, and the fcb is not released. if the frame is not dropped at a particular destination port, then the txq manager formats an entry in the multicast queue for that port and class. multicast queues are physical queues (unlike the linked lists for unicast frames). there are 2 multicast queues for each of the 24 10/100 ports. the queue with higher priority has room for 32 entries and the queue with lower priority has room for 64 entries. there is one multicast queue for every two priority classes. for the 10/100 ports to map the 8 transmit priorities into 2 multicast queues, the 2 lsb are discarded. during scheduling, the txq manager treats the unicast queue and the multicast queue of the same class as one logical queue. the older head of line of the two queues is forwarded first. the port control requests a fcb release only after the eof for the multicast frame has been read by all ports to which the frame is destined.
MVTX2601Ag data sheet 15 zarlink semiconductor inc. 4.0 memory interface 4.1 overview the MVTX2601Ag provides a 64-bit wide sram bank. each dma can read and write from the sram bank. the following figure provides an overview of the MVTX2601Ag sram bank. figure 3 - MVTX2601Ag sram interface block diagram (dmas for 10/1000 ports only) 4.2 detailed memory information because the bus for each bank is 64 bits wide, frames are broken into 8-byte granules, written to and read from memory. 4.3 memory requirements to support 64k mac address, 2 mb memory is required. when vlan support is enabled, 512 entries of the mac address table are used for storing the vlan id at vlan index mapping table. up to 1k ethernet frame buffers are supported and they will use 1.5 mb of memory. each frame uses 1536 bytes. the maximum system memory requirement is 2 mb. if less memory is desired, the configuration can scale down. memory bank frame buffer max mac address 1m 1k 32k 2m 2k 64k table 1 - memory configuration sram tx dma 0-7 tx dma 8-15 tx dma 16-23 rx dma 0-7 rx dma 8-15 rx dma 16-23
MVTX2601Ag data sheet 16 zarlink semiconductor inc. figure 4 - memory map 5.0 search engine 5.1 search engine overview the MVTX2601Ag search engine is optimized for high throughput searching, with enhanced features to support: ? up to 64k mac addresses ? 2 groups of port trunking ? traffic classification into 4 transmission priorities, and 2 drop precedence levels ? flooding, broadcast, multicast storm control ? mac address learning and aging ? port based vlan 5.2 basic flow shortly after a frame enters the MVTX2601Ag and is written to the frame data buffer (fdb), the frame engine generates a switch request, which is sent to the search engine. the switch request consists of the first 64 bytes of the frame, which contain all the necessary information for the search engine to perform its task. when the search engine is done, it writes to the switch response queue, and the frame engine uses the information provided in that queue for scheduling and forwarding. in performing its task, the search engine extracts and compresses the useful information from the 64-byte switch request. among the information extracted are the source and destination mac addresses, the transmission and discard priorities, whether the frame is unicast or multicast. requests are sent to the external sram to locate the associated entries in the external hash table. when all the information has been collected from external sram, the search engine has to compare the mac address on the current entry with the mac address for which it is searching. if it is not a match, the process is repeated on the internal mct table. all mct entries other than the first of each linked list are maintained internal to the chip. if the desired mac address is still not found, then the result is either learning (source mac address unknown) or flooding (destination mac address unknown). in addition, port based vlan information is used to select the correct set of destination ports for the frame (for multicast), or to verify that the frame?s destination port is associated with the vlan (for unicast). if the destination mac address belongs to a port trunk, then the trunk number is retrieved instead of the port number. but on which port of the trunk will the frame be transmitted? this is easily computed using a hash of the source and destination mac addresses. 0.75m 0.25m 1m bank 1.5m 0.5m 2m bank frame data buffer (fdr) area mac address control table (mct) area
MVTX2601Ag data sheet 17 zarlink semiconductor inc. when all the information is compiled, the switch response is generated, as stated earlier. the search engine also interacts with the cpu with regard to learning and aging. 5.3 search, learning and aging 5.3.1 mac search the search block performs source mac address and destination mac address searching. as we indicated earlier, if a match is not found, then the next entry in the linked list must be examined, and so on until a match is found or the end of the list is reached. the port based vlan bitmap is used to determine whether the frame should be forwarded to the outgoing port. when the egress port is not included in the ingress port vlan bitmap, the packet is discarded. the mac search block is also responsible for updating the source mac address timestamp and the vlan port association timestamp, used for aging. 5.3.2 learning the learning module learns new mac addresses and performs port change operations on the mct database. the goal of learning is to update this database as the networking environment changes over time. learning and port change will be performed based on memory slot availability only. 5.3.3 aging aging time is controlled by register 400h and 401h. the aging module scans and ages mct entries based on a programmable ?age out? time interval. as we indicated earlier, the search module updates the source mac address timestamps for each frame it processes. when an entry is ready to be aged, the entry is removed from the table. 5.4 quality of service quality of service (qos) refers to the ability of a network to provide better service to selected network traffic over various technologies. primary goals of qos include dedicated bandwidth, controlled jitter and latency (required by some real-time and interactive traffic), and improved loss characteristics. traditional ethernet networks have had no prioritization of traffic. without a protocol to prioritize or differentiate traffic, a service level known as ?best effort? attempts to get all the packets to their intended destinations with minimum delay; however, there are no guarantees. in a congested network or when a low-performance switch/router is overloaded, ?best effort? becomes unsuitable for delay-sensitive traffic and mission-critical data transmission. the advent of qos for packet-based systems accommodates the integration of delay-sensitive video and multimedia traffic onto any existing ethernet network. it also alleviates the congestion issues that have previously plagued such ?best effort? networking systems. qos provides ethernet networks with the breakthrough technology to prioritize traffic and ensure that a certain transmission will have a guaranteed minimum amount of bandwidth. extensive core qos mechanisms are built into the MVTX2601Ag architecture to ensure policy enforcement and buffering of the ingress port, as well as weighted fair-queue (wfq) scheduling at the egress port. in the MVTX2601Ag, qos-based policies sort traffic into a small number of classes and mark the packets accordingly. the qos identifier provides specific treatment to traffic in different classes, so that different quality of service is provided to each class. frame and packet scheduling and discarding policies are determined by the class to which the frames and packets belong. for example, the overall service given to frames and packets in the premium class will be better than that given to the standard class; the premium class is expected to experience lower loss rate or delay.
MVTX2601Ag data sheet 18 zarlink semiconductor inc. the MVTX2601Ag supports the following qos techniques: ? in a port-based setup, any station connected to the same physical port of the switch will have the same transmit priority ? in a tag-based setup, a 3-bit field in the vlan tag provides the priority of the packet. this priority can be mapped to different queues in the switch to provide qos. ? in a tos/ds-based set up, tos stands for ?type of service? that may include ?minimize delay,? ?maximize throughput,? or ?maximize reliability.? network nodes may select routing paths or forwarding behaviours that are suitably engineered to satisfy the service request. ? in a logical port-based set up, a logical port provides the application information of the packet. certain applications are more sensitive to delays than others; using logical ports to classify packets can help speed up delay sensitive applications, such as voip. 5.5 priority classification rule figure 5 shows the MVTX2601Ag priority classification rule. figure 5 - priority classification rule 5.6 port based vlan an administrator can use the pvmap registers to configure the MVTX2601Ag for port-based vlan. for example, ports 1-3 might be assigned to the marketing vlan, ports 4-6 to the engineering vlan, and ports 7-9 to the administrative vlan. the MVTX2601Ag determines the vlan membership of each packet by noting the port on which it arrives. from there, the MVTX2601Ag determines which outgoing port(s) is/are eligible to transmit each packet, or whether the packet should be discarded. destination port numbers bit map port registers 23 ? 210 register for port #0 pvmap00_0[7:0] to pvmap00_2[7:0] 0 110 fix port priority ? yes yes yes yes yes yes no no no no no use tos use logical port use default port settings use vlan priority use default port settings tos precedence over lan? vlan tag ? ip frame ? ip (fcr regiser, bit 7) no use logical port
MVTX2601Ag data sheet 19 zarlink semiconductor inc. table 2 - pvmap register for example, in the above table, a " 1" denotes that an outgoing port is eligible to receive a packet from an incoming port. a 0 (zero) denotes that an outgoing port is not eligible to receive a packet from an incoming port. in this example: ? data packets received at port #0 are eligible to be sent to outgoing ports 1 and 2. ? data packets received at port #1 are eligible to be sent to outgoing ports 0, and 2. ? data packets received at port #2 are not eligible to be sent to ports 0 and 1. 5.7 memory configurations the MVTX2601Ag supports the following memory configurations. it supports 1m and 2m configurations. register for port #1 pvmap01_0[7:0] to pvmap01_2[7:0] 0 101 register for port #2 pvmap02_0[7:0] to pvmap02_2[7:0] 0 000 ? register for port #23 pvmap23_0[7:0] to pvmap23_2[7:0] 0 000 configuration 1 m (bootstrap pin tstout7 = open) 2 m (bootstrap pin tstout7 = pull down) connections single layer (bootstrap pin tstout13 = open) two 128 k x 32 sram/bank or one 128 k x 64 sram/bank two 256k x 32 sram/bank connect 0e# and we# double layer (bootstrap pin tstout13 = pull down) na four 128 k x 32 sram/bank or two 128 k x 64 sram/bank connect 0e0# and we0# connect 0e1# and we1# table 3 - supported memory configurations (sbram mode) frame data buffer only bank a bank a and bank b bank a and bank b 1m (sram) 2m (sram) 1m/bank (sram) 2m/bank (sram) 1m/bank (zbt sram) 2m/bank (zbt sram) mvtx2601 x x mvtx2602 x x mvtx2603 x x x x table 4 - options for memory configuration destination port numbers bit map
MVTX2601Ag data sheet 20 zarlink semiconductor inc. figure 6 - memory configuration for 2 banks, 1 layer, 2mb total mvtx2603 (gigabit ports in 2giga mode) x (125mhz) x (125mhz) mvtx2604 x x x x mvtx2604 (gigabit ports in 2giga mode) x (125mhz) x (125mhz) table 4 - options for memory configuration memory 128k 32 bits sram memory 128k 32 bits data la_d[63:32] data la_d[31:0] address la_a[19:3] bank a (1m one layer) bootstraps: tstout7 = open, tstout13 = open, tstout4 = open memory 128k 32 bits sram memory 128k 32 bits data lb_d[63:32] data lb_d[31:0] address lb_a[19:3] bank b (1m one layer)
MVTX2601Ag data sheet 21 zarlink semiconductor inc. figure 7 - memory configuration for: 2 banks, 2 layers, 4mb total sram memory 128k 32 bits data la_d[63:32] data la_d[31:0] bank a (2m one layer) sram memory 128k 32 bits address la_a[19:3] sram memory 128k 32 bits data lb_d[63:32] data lb_d[31:0] bank b (2m two layers) sram memory 128k 32 bits address lb_a[19:3] sram memory 128k 32 bits sram memory 128k 32 bits zbt memory 128k 32 bits sram memory 128k 32 bits bootstraps: tstout7 = pull down, tstout13 = pull down, tstout4 = open
MVTX2601Ag data sheet 22 zarlink semiconductor inc. figure 8 - memory configuration for 2 banks, 1 layer, 4mb memory 256k 32 bits sram memory 256k 32 bits data la_d[63:32] data la_d[31:0] address la_a[20:3] bank a (2m one layer) bootstraps: tstout7 = pull down, tstout13 = open, tstout4 = open memory 256k 32 bits sram memory 256k 32 bits data lb_d[63:32] data lb_d[31:0] address lb_a[20:3] bank b (2m one layer)
MVTX2601Ag data sheet 23 zarlink semiconductor inc. figure 9 - memory configuration for: 2 banks, 2 layers 4mb total zbt memory 128k 32 bits data la_d[63:32] data la_d[31:0] bank a (2m two layers) zbt memory 128k 32 bits address la_a[19:3] zbt memory 128k 32 bits data lb_d[63:32] data lb_d[31:0] bank b (2m two layers) zbt memory 128k 32 bits address lb_a[19:3] zbt memory 128k 32 bits zbt memory 128k 32 bits zbt memory 128k 32 bits zbt memory 128k 32 bits
MVTX2601Ag data sheet 24 zarlink semiconductor inc. figure 10 - memory configuration for 2 banks, 1 layer, 4mb 6.0 frame engine 6.1 data forwarding summary when a frame enters the device at the rxmac, the rxdma will move the data from the mac rxfifo to the fdb. data is moved in 8-byte granules in conjunction with the scheme for the sram interface. a switch request is sent to the search engine. the search engine processes the switch request. a switch response is sent back to the frame engine and indicates whether the frame is unicast or multicast, and its destination port or ports. a transmission scheduling request is sent in the form of a signal notifying the txq manager. upon receiving a transmission scheduling request, the device will format an entry in the appropriate transmission scheduling queue (txsch q) or queues. there are 4 txsch q for each 10/100, one for each priority. creation of a queue entry either involves linking a new job to the appropriate linked list if unicast, or adding an entry to a physical queue if multicast. when the port is ready to accept the next frame, the txq manager will get the head-of-line (hol) entry of one of the txsch qs, according to the transmission scheduling algorithm (so as to ensure per-class quality of service). the unicast linked list and the multicast queue for the same port-class pair are treated as one logical queue. the older hol between the two queues goes first. for 10/100 ports multicast queue 0 is associated with unicast queue 0 and multicast queue 1 is associated with unicast queue 2. the txdma will pull frame data from the memory and forward it granule-by-granule to the mac txfifo of the destination port. 6.2 frame engine details this section briefly describes the functions of each of the modules of the MVTX2601Ag frame engine. 6.2.1 fcb manager the fcb manager allocates fcb handles to incoming frames, and releases fcb handles upon frame departure. the fcb manager is also responsible for enforcing buffer reservations and limits. the default values can be determined by referring to chapter 8. in addition, the fcb manager is responsible for buffer aging, and memory 256k 32 bits zbt memory 256k 32 bits data la_d[63:32] data la_d[31:0] address la_a[20:3] bank a (2m one layer) bootstraps: tstout7 = pull down, tstout13 = open, tstout4 = open memory 256k 32 bits zbt memory 256k 32 bits data lb_d[63:32] data lb_d[31:0] address lb_a[20:3] bank b (2m one layer) zbt zbt
MVTX2601Ag data sheet 25 zarlink semiconductor inc. for linking unicast forwarding jobs to their correct txsch q. the buffer aging can be enabled or disabled by the bootstrap pin and the aging time is defined in register fcbat. 6.2.2 rx interface the rx interface is mainly responsible for communicating with the rxmac. it keeps track of the start and end of frame and frame status (good or bad). upon receiving an end of frame that is good, the rx interface makes a switch request. 6.2.3 rxdma the rxdma arbitrates among switch requests from each rx interface. it also buffers the first 64 bytes of each frame for use by the search engine when the switch request has been made. 6.2.4 txq manager first, the txq manager checks the per-class queue status and global reserved resource situation, and using this information, makes the frame dropping decision after receiving a switch response. if the decision is not to drop, the txq manager requests that the fcb manager link the unicast frame?s fcb to the correct per-port-per- class txq. if multicast, the txq manager writes to the multicast queue for that port and class. the txq manager can also trigger source port flow control for the incoming frame?s source if that port is flow control enabled. second, the txq manager handles transmission scheduling; it schedules transmission among the queues representing different classes for a port. once a frame has been scheduled, the txq manager reads the fcb information and writes to the correct port control module. 6.3 port control the port control module calculates the sram read address for the frame currently being transmitted. it also writes start of frame information and an end of frame flag to the mac txfifo. when transmission is done, the port control module requests that the buffer be released. 6.4 txdma the txdma multiplexes data and address from port control, and arbitrates among buffer release requests from the port control modules. 7.0 quality of service and flow control 7.1 model quality of service is an all-encompassing term for which different people have different interpretations. in general, the approach to quality of service described here assumes that we do not know the offered traffic pattern. we also assume that the incoming traffic is not policed or shaped. furthermore, we assume that the network manager knows his applications, such as voice, file transfer, or web browsing, and their relative importance. the manager can then subdivide the applications into classes and set up a service contract with each. the contract may consist of bandwidth or latency assurances per class. sometimes it may even reflect an estimate of the traffic mix offered to the switch. as an added bonus, although we do not assume anything about the arrival pattern, if the incoming traffic is policed or shaped, we may be able to provide additional assurances about our switch?s performance.
MVTX2601Ag data sheet 26 zarlink semiconductor inc. table 5 shows examples of qos applications with three transmission priorities, but best effort (p0) traffic may form a fourth class with no bandwidth or latency assurances. a class is capable of offering traffic that exceeds the contracted bandwidth. a well-behaved class offers traffic at a rate no greater than the agreed-upon rate. by contrast, a misbehaving class offers traffic that exceeds the agreed-upon rate. a misbehaving class is formed from an aggregation of misbehaving microflows. to achieve high link utilization, a misbehaving class is allowed to use any idle bandwidth. however, such leniency must not degrade the quality of service (qos) received by well-behaved classes. as table 6 illustrates, the six traffic types may each have their own distinct properties and applications. as shown, classes may receive bandwidth assurances or latency bounds. in the table, p3, the highest transmission class, requires that all frames be transmitted within 1 ms, and receives 50% of the 100 mbps of bandwidth at that port. best-effort (p0) traffic forms a fourth class that only receives bandwidth when none of the other classes have any traffic to offer. it is also possible to add a fourth class that has strict priority over the other three; if this class has even one frame to transmit, then it goes first. in the MVTX2601Ag, each 10/100 mbps port will support four total classes, and each 1000 mbps port will support eight classes. we will discuss the various modes of scheduling these classes in the next section. in addition, each transmission class has two subclasses, high-drop and low-drop. well-behaved users should rarely lose packets. but poorly behaved users ? users who send frames at too high a rate ? will encounter frame loss, and the first to be discarded will be high-drop. of course, if this is insufficient to resolve the congestion, eventually some low-drop frames are dropped, and then all frames in the worst case. table 6 shows that different types of applications may be placed in different boxes in the traffic table. for example, casual web browsing fits into the category of high-loss, high-latency-tolerant traffic, whereas voip fits into the category of low-loss, low-latency traffic. goals total assured bandwidth (user defined) low drop probability (low-drop) high drop probability (high-drop) highest transmission priority, p3 50 mbps apps: phone calls, circuit emulation. latency: < 1 ms. drop: no drop if p3 not oversubscribed. apps: training video. latency: < 1 ms. drop: no drop if p3 not oversubscribed; first p3 to drop otherwise. middle transmission priority, p2 37.5 mbps apps: interactive apps, web business. latency: < 4-5 ms. drop: no drop if p2 not oversubscribed. apps: non-critical interactive apps. latency: < 4-5 ms. drop: no drop if p2 not oversubscribed; firstp2 to drop otherwise. low transmission priority, p1 12.5 mbps apps: emails, file backups. latency: < 16 ms desired, but not critical. drop: no drop if p1 not oversubscribed. apps: casual web browsing. latency: < 16 ms desired, but not critical. drop: no drop if p1 not oversubscribed; first to drop otherwise. total 100 mbps table 5 - two dimensional world traffic
MVTX2601Ag data sheet 27 zarlink semiconductor inc. 7.2 four qos configurations there are four basic pieces to qos scheduling in the MVTX2601Ag: strict priority (sp), delay bound, weighted fair queuing (wfq), and best effort (be). using these four pieces, there are four different modes of operation, as shown in tables 4 and 5. for 10/100 mbps ports, these modes are selected by the following registers: the default configuration for a 10/100 mbps port is three delay-bounded queues and one best-effort queue. the delay bounds per class are 0.8 ms for p3, 2 ms for p2, and 12.8 ms for p1. best effort traffic is only served when there is no delay-bounded traffic to be served. we have a second configuration for a 10/100 mbps port in which there is one strict priority queue, two delay bounded queues, and one best effort queue. the delay bounds per class are 3.2 ms for p2 and 12.8 ms for p1. if the user is to choose this configuration, it is important that p3 (sp) traffic be either policed or implicitly bounded (e.g. if the incoming p3 traffic is very light and predictably patterned). strict priority traffic, if not admission-controlled at a prior stage to the MVTX2601Ag, can have an adverse effect on all other classes? performance. the third configuration for a 10/100 mbps port contains one strict priority queue and three queues receiving a bandwidth partition via wfq. as in the second configuration, strict priority traffic needs to be carefully controlled. in the fourth configuration, all queues are served using a wfq service discipline. 7.3 delay bound in the absence of a sophisticated qos server and signaling protocol, the MVTX2601Ag may not know the mix of incoming traffic ahead of time. to cope with this uncertainty, our delay assurance algorithm dynamically adjusts its scheduling and dropping criteria, guided by the queue occupancies and the due dates of their head- of-line (hol) frames. as a result, we assure latency bounds for all admitted frames with high confidence, even in the presence of system-wide congestion. our algorithm identifies misbehaving classes and intelligently discards frames at no detriment to well-behaved classes. our algorithm also differentiates between high-drop and low-drop traffic with a weighted random early drop (wred) approach. random early dropping prevents congestion by randomly dropping a percentage of high-drop frames even before the chip?s buffers are completely full, while still largely sparing low-drop frames. this allows high-drop frames to be discarded early, as a sacrifice for future low-drop frames. finally, the delay bound algorithm also achieves bandwidth partitioning among classes. qosc24 [7:6] credit_c00 qosc28 [7:6] credit_c10 qosc32 [7:6] credit_c20 qosc36 [7:6] credit_c30 p3 p2 p1 p0 op1 (default) delay bound be op2 sp delay bound be op3 sp wfq op4 wfq table 6 - four qos configurations for a 10/100mbps port
MVTX2601Ag data sheet 28 zarlink semiconductor inc. 7.4 strict priority and best effort when strict priority is part of the scheduling algorithm, if a queue has even one frame to transmit, it goes first. two of our four qos configurations include strict priority queues. the goal is for strict priority classes to be used for ietf expedited forwarding (ef), where performance guarantees are required. as we have indicated, it is important that strict priority traffic be either policed or implicitly bounded, so as to keep from harming other traffic classes. when best effort is part of the scheduling algorithm, a queue only receives bandwidth when none of the other classes have any traffic to offer. two of our four qos configurations include best effort queues. the goal is for best effort classes to be used for non-essential traffic, because we provide no assurances about best effort performance. however, in a typical network setting, much best effort traffic will indeed be transmitted, and with an adequate degree of expediency. because we do not provide any delay assurances for best effort traffic, we do not enforce latency by dropping best effort traffic. furthermore, because we assume that strict priority traffic is carefully controlled before entering the MVTX2601Ag, we do not enforce a fair bandwidth partition by dropping strict priority traffic. to summarize, dropping to enforce bandwidth or delay does not apply to strict priority or best effort queues. we only drop frames from best effort and strict priority queues when global buffer resources become scarce. 7.5 weighted fair queuing in some environments ? for example, in an environment in which delay assurances are not required, but precise bandwidth partitioning on small time scales is essential, wfq may be preferable to a delay-bounded scheduling discipline. the MVTX2601Ag provides the user with a wfq option with the understanding that delay assurances can not be provided if the incoming traffic pattern is uncontrolled. the user sets four wfq ?weights? such that all weights are whole numbers and sum to 64. this provides per-class bandwidth partitioning with error within 2%. in wfq mode, though we do not assure frame latency, the MVTX2601Ag still retains a set of dropping rules that helps to prevent congestion and trigger higher level protocol end-to-end flow control. as before, when strict priority is combined with wfq, we do not have special dropping rules for the strict priority queues, because the input traffic pattern is assumed to be carefully controlled at a prior stage. however, we do indeed drop frames from sp queues for global buffer management purposes. in addition, queue p0 for a 10/100 port are treated as best effort from a dropping perspective, though they still are assured a percentage of bandwidth from a wfq scheduling perspective. what this means is that these particular queues are only affected by dropping when the global buffer count becomes low. 7.6 wred drop threshold management support to avoid congestion, the weighted random early detection (wred) logic drops packets according to specified parameters. the following table summarizes the behavior of the wred logic. table 7 - wred drop thresholds px is the total byte count, in the priority queue x. the wred logic has three drop levels, depending on the value of n, which is based on the number of bytes in the priority queues. if delay bound scheduling is used, n equals p3*16+p2*4+p1. if using wfq scheduling, n equals p3+p2+p1. each drop level from one to three has defined in kb (kilobytes) p3 p2 p1 high drop low drop level 1 n 120 p3 akb p2 akb p1 akb x% 0% level 2 n 140 y% z% level 3 n 160 100% 100%
MVTX2601Ag data sheet 29 zarlink semiconductor inc. high-drop and low-drop percentages, which indicate the minimum and maximum percentages of the data that can be discarded. the x, y z percent can be programmed by the register rdrc0, rdrc1. in level 3, all packets are dropped if the bytes in each priority queue exceed the threshold. parameters a, b, c are the byte count thresholds for each priority queue. they can be programmed by the qos control register (refer to the register group 5). see programming qos registers application note for more information. 7.7 buffer management because the number of fdb slots is a scarce resource, and because we want to ensure that one misbehaving source port or class cannot harm the performance of a well-behaved source port or class, we introduce the concept of buffer management into the MVTX2601Ag. our buffer management scheme is designed to divide the total buffer space into numerous reserved regions and one shared pool, as shown in figure 11 on page 30. as shown in the figure, the fdb pool is divided into several parts. a reserved region for temporary frames stores frames prior to receiving a switch response. such a temporary region is necessary, because when the frame first enters the MVTX2601Ag, its destination port and class are as yet unknown, and so the decision to drop or not needs to be temporarily postponed. this ensures that every frame can be received first before subjecting them to the frame drop discipline after classifying. six reserved sections, one for each of the first six priority classes, ensure a programmable number of fdb slots per class. the lowest two classes do not receive any buffer reservation. furthermore, even for 10/100 mbps ports, a frame is stored in the region of the fdb corresponding to its class. as we have indicated, the eight classes use only four transmission scheduling queues for 10/100 mbps ports, but as far as buffer usage is concerned, there are still eight distinguishable classes. another segment of the fdb reserves space for each of the 24 ports. one parameters can be set for the source port reservation for 10/100 mbps. these 24 reserved regions make sure that no well-behaved source port can be blocked by another misbehaving source port. in addition, there is a shared pool, which can store any type of frame. the frame engine allocates the frames first in the six priority sections. when the priority section is full or the packet has priority 1 or 0, the frame is allocated in the shared poll. once the shared poll is full the frames are allocated in the section reserved for the source port. the following registers define the size of each section of the frame data buffer: pr100 - port reservation for 10/100 ports sfcb - share fcb size c2rs - class 2 reserve size c3rs - class 3 reserve size c4rs - class 4 reserve size c5rs - class 5 reserve size c6rs - class 6 reserve size c7rs- class 7 reserve size
MVTX2601Ag data sheet 30 zarlink semiconductor inc. figure 11 - buffer partition scheme used to implement MVTX2601Ag buffer management 7.7.1 dropping when buffers are scarce summarizing the two examples of local dropping discussed earlier in this chapter: ? if a queue is a delay-bounded queue, we have a multi level wred drop scheme, designed to control delay and partition bandwidth in case of congestion. ? if a queue is a wfq-scheduled queue, we have a multi level wred drop scheme, designed to prevent congestion. in addition to these reasons for dropping, we also drop frames when global buffer space becomes scarce. the function of buffer management is to make sure that such dropping causes as little blocking as possible. 7.8 MVTX2601Ag flow control basics because frame loss is unacceptable for some applications, the MVTX2601Ag provides a flow control option. when flow control is enabled, scarcity of buffer space in the switch may trigger a flow control signal; this signal tells a source port that is sending a packet to this switch, to temporarily hold off. while flow control offers the clear benefit of no packet loss, it also introduces a problem for quality of service. when a source port receives an ethernet flow control signal, all microflows originating at that port, well-behaved or not, are halted. a single packet destined for a congested output can block other packets destined for uncongested outputs. the resulting head-of-line blocking phenomenon means that quality of service cannot be assured with high confidence when flow control is enabled. in the MVTX2601Ag, each source port can independently have flow control enabled or disabled. for flow control enabled ports, by default all frames are treated as lowest priority during transmission scheduling. this is done so that those frames are not exposed to the wred dropping scheme. frames from flow control enabled ports feed to only one queue at the destination, the queue of lowest priority. what this means is that if flow control is enabled for a given source port, then we can guarantee that no packets originating from that port will be lost, but at the possible expense of minimum bandwidth or maximum delay assurances. in addition, these ?downgraded? frames may only use the shared pool or the per-source reserved pool in the fdb; frames from flow control enabled sources may not use reserved fdb slots for the highest six classes (p2-p7). shared pool s per-source reservations (24 10/100m, cpu) temporary reservation per-class reservation
MVTX2601Ag data sheet 31 zarlink semiconductor inc. the MVTX2601Ag does provide a system-wide option of permitting normal qos scheduling (and buffer use) for frames originating from flow control enabled ports. when this programmable option is active, it is possible that some packets may be dropped, even though flow control is on. the reason is that intelligent packet dropping is a major component of the MVTX2601Ag?s approach to ensuring bounded delay and minimum bandwidth for high priority flows. 7.8.1 unicast flow control for unicast frames, flow control is triggered by source port resource availability. recall that the MVTX2601Ag?s buffer management scheme allocates a reserved number of fdb slots for each source port. if a programmed number of a source port?s reserved fdb slots have been used, then flow control xoff is triggered. xon is triggered when a port is currently being flow controlled, and all of that port?s reserved fdb slots have been released. note that the MVTX2601Ag?s per-source-port fdb reservations assure that a source port that sends a single frame to a congested destination will not be flow controlled. 7.8.2 multicast flow control in unmanaged mode, flow control for multicast frames is triggered by a global buffer counter. when the system exceeds a programmable threshold of multicast packets, xoff is triggered. xon is triggered when the system returns below this threshold. in addition, each source port has a 23-bit port map recording which port or ports of the multicast frame?s fanout were congested at the time xoff was triggered. all ports are continuously monitored for congestion, and a port is identified as uncongested when its queue occupancy falls below a fixed threshold. when all those ports that were originally marked as congested in the port map have become uncongested, then xon is triggered, and the 23-bit vector is reset to zero. 7.9 mapping to ietf diffserv classes for 10/100 mbps ports, the classes of table 6 are merged in pairs?one class corresponding to nm+ef, two af classes, and a single be class. table 8 - mapping between MVTX2601Ag and ietf diffserv classes for 10/100 ports vtx p3 p2 p1 p0 ietf nm+ef af0 af1 be0
MVTX2601Ag data sheet 32 zarlink semiconductor inc. features of the MVTX2601Ag that correspond to the requirements of their associated ietf classes are summarized in the table below. 8.0 port trunking 8.1 features and restrictions a port group (i.e. trunk) can include up to 4 physical ports, but all of the ports in a group must be in the same MVTX2601Ag. load distribution among the ports in a trunk for unicast is performed using hashing based on source mac address and destination mac address. three other options include source mac address only, destination mac address only, and source port (in bidirectional ring mode only). load distribution for multicast is performed similarly. the MVTX2601Ag also provides a safe fail-over mode for port trunking automatically. if one of the ports in the trunking group goes down, the MVTX2601Ag will automatically redistribute the traffic over to the remaining ports in the trunk. 8.2 unicast packet forwarding the search engine finds the destination mct entry, and if the status field says that the destination port found belongs to a trunk, then the group number is retrieved instead of the port number. in addition, if the source address belongs to a trunk, then the source port?s trunk membership register is checked. a hash key, based on some combination of the source and destination mac addresses for the current packet, selects the appropriate forwarding port. 8.3 multicast packet forwarding for multicast packet forwarding, the device must determine the proper set of ports from which to transmit the packet based on the vlan index and hash key. two functions are required in order to distribute multicast packets to the appropriate destination ports in a port trunking environment. determining one forwarding port per group. for multicast packets, all but one port per group, the forwarding port, must be excluded. preventing the multicast packet from looping back to the source trunk. the search engine needs to prevent a multicast packet from sending to a port that is in the same trunk group with the source port. this is because, when we select the primary forwarding port for each group, we do not network management (nm) and expedited forwarding (ef) ? global buffer reservation for nm and ef ? option of strict priority scheduling ? no dropping if admission controlled assured forwarding (af) ? programmable bandwidth partition, with option of wfq service ? option of delay-bounded service keeps delay under fixed levels even if not admission-controlled ? random early discard, with programmable levels ? global buffer reservation for each af class best effort (be) ? service only when other queues are idle means that qos not adversely affected ? random early discard, with programmable levels ? traffic from flow control enabled ports automatically classified as be table 9 - MVTX2601Ag features enabling ietf diffserv standards
MVTX2601Ag data sheet 33 zarlink semiconductor inc. take the source port into account. to prevent this, we simply apply one additional filter, so as to block that forwarding port for this multicast packet. 8.4 trunking 2 trunk groups are supported. groups 0 and 1 can trunk up to 4 10/100 ports. the supported combinations are shown in the following table. select via trunk0_mode register select via trunk1_mode register the trunks are individually enabled/disabled by controlling pin trunk 0,1. 9.0 port mirroring 9.1 port mirroring features the received or transmitted data of any 10/100 port in the MVTX2601Ag chip can be ?mirrored? to any other port. we support two such mirrored source-destination pairs. a mirror port cannot also serve as a data port. please refer to the port mirroring application note for further details. 9.2 setting registers for port mirroring ? mirror1_src: sets the source port for the first port mirroring pair. bits [4:0] select the source port to be mirrored. an illegal port number is used to disable mirroring (which is the default setting). bit [5] is used to select between ingress (rx) or egress (tx) data. ? mirror1_dest: sets the destination port for the first port mirroring pair. bits [4:0] select the destination port to be mirrored. the default is port 23. ? mirror2_src: sets the source port for the second port mirroring pair. bits [4:0] select the source port to be mirrored. an illegal port number is used to disable mirroring (which is the default setting). bit [5] is used to select between ingress (rx) or egress (tx) data. ? mirror2_dest: sets the destination port for the second port mirroring pair. bits [4:0] select the destination port to be mirrored. the default is port 0. group 0 port 0 port 1 port 2 port 3 99 999 9 999 group 1 port 4 port 5 port 6 port 7 99 9 999
MVTX2601Ag data sheet 34 zarlink semiconductor inc. 10.0 gpsi (7ws) interface 10.1 gpsi connection the 10/100 rmii ethernet port can function in gpsi (7ws) mode when the corresponding txen pin is strapped low with a 1k pull down resistor. in this mode, the txd[0], txd[1], rxd[0] and rxd[1] serve as tx data, tx clock, rx data and rx clock respectively. the link status and collision from the phy are multiplexed and shifted into the switch device through external glue logic. the duplex of the port can be controlled by programming the ecr register. the gpsi interface can be operated in port based vlan mode only. figure 12 - gpsi (7ws) mode connection diagram crs_dv rxd[0] rxd[1] txd[1] txd[0] txen port 0 ethernet phy 260x scan_col scan_clk scan_link ethernet port 23 ethernet phy ethernet link serializer (cpld) collision serializer (cpld) crs rxd rx_clk tx_clk txd txen link0 col0 link1 col1 link2 col2 link23 col23
MVTX2601Ag data sheet 35 zarlink semiconductor inc. 10.2 scan link and scan col interface an external cpld logic is required to take the link signals and collision signals from the gpsi phys and shift them into the switch device. the switch device will drive out a signature to indicate the start of the sequence. after that, the cpld should shift in the link and collision status of the phys as shown in the figure. the extra link status indicates the polarity of the link signal. one indicates the polarity of the link signal is active high. figure 13 - scan link and scan collison status diagram 11.0 led interface 11.1 led interface introduction a serial output channel provides port status information from the MVTX2601Ag chips. it requires three additional pins. ? led_clk at 12.5 mhz ? led_syn a sync pulse that defines the boundary between status frames ? led_data a continuous serial stream of data for all status leds that repeats once every frame time a low cost external device (44 pin pal) is used to decode the serial data and to drive an led array for display. this device can be customized for different needs. 11.2 port status in the MVTX2601Ag, each port has 8 status indicators, each represented by a single bit. the 8 led status indicators are: ? bit 0: flow control ? bit 1:transmit data ? bit 2: receive data ? bit 3: activity (where activity includes either transmission or reception of data) ? bit 4: link up ? bit 5: speed (1= 100 mb/s; 0= 10 mb/s) ? bit 6: full-duplex ? bit 7: collision eight clocks are required to cycle through the eight status bits for each port. when the led_syn pulse is asserted, the led interface will present 256 led clock cycles with the clock cycles providing information for the following ports. port 0 (10/100): cycles #0 to cycle #7 port 1 (10/100): cycles#8 to cycle #15 25 cycles for link / 24 cycles for col drived by cpld total 32 cycles period drived by vtx260x scan_clk scan_link/ scan_col
MVTX2601Ag data sheet 36 zarlink semiconductor inc. port 2 (10/100): cycle #16 to cycle #23 ... port 22 (10/100): cycle #176 to cycle #183 port 23 (10/100): cycle #184 to cycle #191 reserved: cycle #192 to cycle #199 reserved: cycle #200 to cycle #207 byte 26 (additional status): cycle #208 to cycle #215 byte 27 (additional status): cycle #216 to cycle #223 cycles #224 to 256 present data with a value of zero. byte 26 and byte 27 provides bist status ? 26[0]: reserved ? 26[1]: reserved ? 26[2]: initialization done ? 26[3]: initialization start ? 26[4]: checksum ok ? 26[5]: link_init_complete ? 26[6]: bist_fail ? 26[7]: ram_error ? 27[0]: bist_in_process ? 27[1]: bist_done 11.3 led interface timing diagram the signal from the MVTX2601Ag to the led decoder is shown in figure 14. figure 14 - timing diagram of led interface
MVTX2601Ag data sheet 37 zarlink semiconductor inc. 12.0 register definition 12.1 MVTX2601Ag register description register description cpu addr (hex) r/w i 2 c addr (hex) default notes ethernet port control registers substitute [n] with port number (0..18) ecr1p?n? port control register 1 for port n 000 + 2 x n r/w 000-018 020 ecr2p?n? port control register 2 for port n 001 + 2 x n r/w 01b-033 000 vlan control registers substitute [n] with port number (0..1a) avtcl vlan type code register low 100 r/w 036 000 avtch vlan type code register high 101 r/w 037 081 pvmap?n?_0 port ?n? configuration register 0 102 + 4n r/w 038-050 0ff pvmap?n?_1 port ?n? configuration register 1 103 + 4n r/w 053-06b 0ff pvmap?n?_2 port ?n? configuration register 2 104 + 4n r/w 06e-086 0ff pvmap?n?_3 port ?n? configuration register 3 105 + 4n r/w 089-0a1 007 pvmode vlan operating mode 170 r/w 0a4 000 pvroute7-0 vlan router group enable 171-178 r/w na 000 trunk control registers trunk0_l trunk group 0 low 200 r/w na 000 trunk0_m trunk group 0 medium 201 r/w na 000 trunk0_h trunk group 0 high 202 r/w na 000 trunk0_ mode trunk group 0 mode 203 r/w 0a5 003 trunk0_ hash0 trunk group 0 hash 0 destination port 204 r/w na 000 trunk0_ hash1 trunk group 0 hash 1 destination port 205 r/w na 001 trunk0_ hash2 trunk group 0 hash 2 destination port 206 r/w na 002 trunk0_ hash3 trunk group 0 hash 3 destination port 207 r/w na 003 trunk1_l trunk group 1 low 208 r/w na 000 trunk1_m trunk group 1 medium 209 r/w na 000 trunk1_h trunk group 1 high 20a r/w na 000 trunk1_ mode trunk group 1 mode 20b r/w 0a6 003 trunk1_ hash0 trunk group 1 hash 0 destination port 20c r/w na 004
MVTX2601Ag data sheet 38 zarlink semiconductor inc. trunk1_ hash1 trunk group 1 hash 1 destination port 20d r/w na 005 trunk1_ hash2 trunk group 1 hash 2 destination port 20e r/w na 006 trunk1_ hash3 trunk group 1 hash 3 destination port 20f r/w na 007 multicast_ hash0-0 multicast hash result 0 mask byte 0 220 r/w na 0ff multicast_ hash0-1 multicast hash result 0 mask byte 1 221 r/w na 0ff multicast_ hash0-2 multicast hash result 0 mask byte 2 222 r/w na 0ff multicast_ hash0-3 multicast hash result 0 mask byte 3 223 r/w na 0ff multicast_ hash1-0 multicast hash result 1 mask byte 0 224 r/w na 0ff multicast_ hash1-1 multicast hash result 1 mask byte 1 225 r/w na 0ff multicast_ hash1-2 multicast hash result 1 mask byte 2 226 r/w na 0ff multicast_ hash1-3 multicast hash result 1 mask byte 3 227 r/w na 0ff multicast_ hash2-0 multicast hash result 2 mask byte 0 228 r/w na 0ff multicast_ hash2-1 multicast hash result 2 mask byte 1 229 r/w na 0ff multicast_ hash2-2 multicast hash result 2 mask byte 2 22a r/w na 0ff multicast_ hash2-3 multicast hash result 2 mask byte 3 22b r/w na 0ff multicast_ hash3-0 multicast hash result 3 mask byte 0 22c r/w na 0ff multicast_ hash3-1 multicast hash result 3 mask byte 1 22d r/w na 0ff multicast_ hash3-2 multicast hash result 3 mask byte 2 22e r/w na 0ff multicast_ hash3-3 multicast hash result 3 mask byte 3 22f r/w na 0ff register description cpu addr (hex) r/w i 2 c addr (hex) default notes
MVTX2601Ag data sheet 39 zarlink semiconductor inc. cpu port configuration mac0 cpu mac address byte 0 300 r/w na 000 mac1 cpu mac address byte 1 301 r/w na 000 mac2 cpu mac address byte 2 302 r/w na 000 mac3 cpu mac address byte 3 303 r/w na 000 mac4 cpu mac address byte 4 304 r/w na 000 mac5 cpu mac address byte 5 305 r/w na 000 int_mask0 interrupt mask 0 306 r/w na 000 intp_mask?n? interrupt mask for mac port 2n, 2n+1 310+n (310 -313) r/w na 000 rqs receive queue select 323 r/w na 000 rqss receive queue status 324 ro na n/a tx_age transmission queue aging time 325 r/w 0a7 008 search engine configurations agetime_low mac address aging time low 400 r/w 0a8 2m:05c / 4m:02e agetime_ high mac address aging time high 401 r/w 0a9 000 v_agetime vlan to port aging time 402 r/w na off se_opmode search engine operating mode 403 r/w na 000 scan scan control register 404 r/w na 000 buffer control and qos control fcbat fcb aging timer 500 r/w 0aa 0ff qosc qos control 501 r/w 0ab 000 fcr flooding control register 502 r/w 0ac 008 avpml vlan priority map low 503 r/w 0ad 000 avpmm vlan priority map middle 504 r/w 0ae 000 avpmh vlan priority map high 505 r/w 0af 000 tospml tos priority map low 506 r/w 0b0 000 tospmm tos priority map middle 507 r/w 0b1 000 tospmh tos priority map high 508 r/w 0b2 000 avdm vlan discard map 509 r/w 0b3 000 register description cpu addr (hex) r/w i 2 c addr (hex) default notes
MVTX2601Ag data sheet 40 zarlink semiconductor inc. tosdml tos discard map 50a r/w 0b4 000 bmrc broadcast/multicast rate control 50b r/w 0b5 000 ucc unicast congestion control 50c r/w 0b6 1m:008 / 2m:010 mcc multicast congestion control 50d r/w 0b7 050 pr100 port reservation for 10/100 ports 50e r/w 0b8 1m:035 / 2m:058 sfcb share fcb size 510 r/w 0ba 1m:046 / 2m:0e6 c2rs class 2 reserve size 511 r/w 0bb 000 c3rs class 3 reserve size 512 r/w 0bc 000 c4rs class 4 reserve size 513 r/w 0bd 000 c5rs class 5 reserve size 514 r/w 0be 000 c6rs class 6 reserve size 515 r/w 0bf 000 c7rs class 7 reserve size 516 r/w 0c0 000 qosc?n? qos control (n=0 - 5) 517- 51c r/w 0c1-0c6 000 qos control (n=6 - 11) 51d- 522 r/w na 000 qos control (n=12 - 23) 523- 52e r/w 0c7-0d2 000 qos control (n=24 - 59) 52f- 552 r/w na 000 qosc?n? qos control (n=0 59) 517 512 r/w 0c1-0d2 000 rdrc0 wred drop rate control 0 553 r/w 0fb 08f rdrc1 wred drop rate control 1 554 r/w 0fc 088 user_ port?n?_low user define logical port ?n? low (n=0-7) 580 + 2n r/w 0d6-0dd 000 user_ port?n?_high user define logical port ?n? high 581 + 2n r/w 0de-0e5 000 user_ port1:0_ priority user define logic port 1 and 0 priority 590 r/w 0e6 000 user_ port3:2_ priority user define logic port 3 and 2 priority 591 r/w 0e7 000 user_ port5:4_ priority user define logic port 5 and 4 priority 592 r/w 0e8 000 register description cpu addr (hex) r/w i 2 c addr (hex) default notes
MVTX2601Ag data sheet 41 zarlink semiconductor inc. user_ port7:6_priorit y user define logic port 7 and 6 priority 593 r/w 0e9 000 user_port_ enable user define logic port enable 594 r/w 0ea 000 wlpp10 well known logic port priority for 1 and 0 595 r/w 0eb 000 wlpp32 well known logic port priority for 3 and 2 596 r/w 0ec 000 wlpp54 well known logic port priority for 5 and 4 597 r/w 0ed 000 wlpp76 well-known logic port priority for 7 & 6 598 r/w 0ee 000 wlpe well known logic port enable 599 r/w 0ef 000 rlowl user define range low bit7:0 59a r/w 0f4 000 rlowh user define range low bit 15:8 59b r/w 0f5 000 rhighl user define range high bit 7:0 59c r/w 0d3 000 rhighh user define range high bit 15:8 59d r/w 0d4 000 rpriority user define range priority 59e r/w 0d5 000 cpuqosc1~3 byte limit for txq on cpu port 5a0-5a2 r/w na 000 misc configuration registers mii_op0 mii register option 0 600 r/w 0f0 000 mii_op1 mii register option 1 601 r/w 0f1 000 fen feature registers 602 r/w 0f2 010 miic0 mii command register 0 603 r/w n/a 000 miic1 mii command register 1 604 r/w n/a 000 miic2 mii command register 2 605 r/w n/a 000 miic3 mii command register 3 606 r/w n/a 000 miid0 mii data register 0 607 ro n/a n/a miid1 mii data register 1 608 ro n/a n/a led led control register 609 r/w 0f3 000 device device id and test 60a r/w n/a 000 sum eeprom checksum register 60b r/w 0ff 000 port mirroring controls register description cpu addr (hex) r/w i 2 c addr (hex) default notes
MVTX2601Ag data sheet 42 zarlink semiconductor inc. 12.2 group 0 address mac ports group 12.2.1 ecr1pn: port n control register ?i 2 c address 000-018; cpu address:0000+2xn (n = port number) ? accessed by serial interface and i 2 c (r/w) mirror1_src port mirror 1 source port 700 r/w n/a 07f mirror1_ dest port mirror 1 destination port 701 r/w n/a 017 mirror2_src port mirror 2 source port 702 r/w n/a 0ff mirror2_ dest port mirror 2 destination port 703 r/w n/a 000 device configuration register gcr global control register f00 r/w n/a 000 dcr device status and signature register f01 ro n/a n/a dcr1 chip status f02 ro n/a n/a dpst device port status register f03 r/w n/a 000 dtst data read back register f04 ro n/a n/a da da register fff ro n/a da 76 5 4 3 21 0 sp state a-fc port mode bit [0] 1 - flow control off 0 - flow control on ? when flow control on: ? in half duplex mode, the mac transmitter applies back pressure for flow control. in full duplex mode, the mac transmitter sends flow control frames when necessary. the mac receiver interprets and processes incoming flow control frames. the flow control frame received counter is incremented whenever a flow control is received. ? when flow control off: in half duplex mode, the mac transmitter does not assert flow control by sending flow control frames or jamming collision. in full duplex mode, the mac transmitter does not send flow control frames. the mac receiver does not interpret or process the flow control frames. the flow control frame received counter is not incremented. register description cpu addr (hex) r/w i 2 c addr (hex) default notes
MVTX2601Ag data sheet 43 zarlink semiconductor inc. 12.2.2 ecr2pn: port n control register ?i 2 c address: 01b-035; cpu address:0001+2xn ? accessed by and serial interface and i 2 c (r/w) bit [1] 1 - half duplex - only 10/100 mode 0 - full duplex bit [2] 1 - 10mbps 0 - 100mbps bit [4:3] ? 00 - automatic enable auto neg. this enables hardware state machine for auto-negotiation. ? 01 - limited disable auto neg. this disables hardware for speed auto- negotiation. poll mii for link status. ? 10 - link down. disable auto neg. state machine and force link down (disable the port) ? 11 - link up. user erc1 [2:0] for config. bit [5] ? asymmetric flow control enable ? 0 - disable asymmetric flow control ? 1 - enable asymmetric flow control ? asymmetric flow control enable. when this bit is set and flow control is on (bit[0] = 0, don't send out a flow control frame. but mac receiver interprets and process flow control frames. default is 0 bit [7:6] ss - spanning tree state default is 11 00 ? blocking: frame is dropped 01 - listening: frame is dropped 10 - learning: frame is dropped. source mac address is learned. 11 - forwarding: frame is forwarded. source mac address is learned. 765 4 2 1 0 qos sel reserve disl ftf futf bit[0]: ? filter untagged frame (default 0) ?0: disable ? 1: all untagged frames from this port are discarded bit[1]: ? filter tag frame (default 0) ?0: disable ? 1: all tagged frames from this port are discarded bit[2]: ? learning disable (default 0) ? 1 learning is disabled on this port ? 0 learning is enabled on this port bit[3]: ? must be set to ?1?
MVTX2601Ag data sheet 44 zarlink semiconductor inc. 12.3 group 1 address vlan group 12.3.1 avtcl ? vlan type code register low ? i 2 c address 036; cpu address:h100 ? accessed by serial interface and i 2 c (r/w) 12.3.2 avtch ? vlan type code register high ?i 2 c address 037; cpu address:h101 ? accessed by serial interface and i 2 c (r/w) 12.3.3 pvmap00_0 ? port 00 configuration register 0 ?i 2 c address 038, cpu address:h102) ? accessed by serial interface and i 2 c (r/w) this register indicates the legal egress ports. a ?1? on bit 7 means that the packet can be sent to port 7. a ?0? on bit 7 means that any packet destined to port 7 will be discarded. this register works with registers 1 and 2 to form a 24 bit mask to all egress ports. 12.3.4 pvmap00_1 ? port 00 configuration register 1 ?i 2 c address h39, cpu address:h103 ? accessed by serial interface and i 2 c (r/w) 12.3.5 pvmap00_2 ? port 00 configuration register 2 ?i 2 c address h3a, cpu address:h104 ? accessed by serial interface and i 2 c (r/w) bit [5:4:] ? qos mode selection (default 00) ? determines which of the 4 sets of qos settings is used for 10/100 ports. ? note that there are 4 sets of per-queue byte thresholds, and 4 sets of wfq ratios programmed. these bits select among the 4 choices for each 10/100 port. refer to qos application note. ? 00: select class byte limit set 0 and classes wfq credit set 0 ? 01: select class byte limit set 1 and classes wfq credit set 1 ? 10: select class byte limit set 2 and classes wfq credit set 2 ? 11: select class byte limit set 3 and classes wfq credit set 3 bit[7:6] reserved bit[7:0]: ? lantype_low: lower 8 bits of the vlan type code (default 00) bit[7:0]: ? vlantype_high: upper 8 bits of the vlan type code (default is 81) bit[7:0]: ? vlan mask for ports 7 to 0 (default ff) bit[7:0]: ? vlan mask for ports 15 to 8 (default is ff) bit [7:0]: ? vlan mask for ports 23 to 16 (default ff)
MVTX2601Ag data sheet 45 zarlink semiconductor inc. 12.3.6 pvmap00_3 ? port 00 configuration register 3 ?i 2 c address h3b, cpu address:h105) ? accessed by serial interface and i 2 c (r/w) 12.4 port configuration register ? pvmap01_0,1,2,3 i 2 c address h3c,3d,3e,3f; cpu address:h106,107,108,109) ? pvmap02_0,1,2,3 i 2 c address h40,41,42,43; cpu address:h10a, 10b, 10c, 10d) ? pvmap03_0,1,2,3 i 2 c address h44,45,46,47; cpu address:h10e, 10f, 110, 111) ? pvmap04_0,1,2,3 i 2 c address h48,49,4a,4b; cpu address:h112, 113, 114, 115) ? pvmap05_0,1,2,3 i 2 c address h4c,4d,4e,4f; cpu address:h116, 117, 118, 119) ? pvmap06_0,1,2,3 i 2 c address h50,51,52,53; cpu address:h11a, 11b, 11c, 11d) ? pvmap07_0,1,2,3 i 2 c address h54,55,56,57; cpu address:h11e, 11f, 120, 121) ? pvmap08_0,1,2,3 i 2 c address h58,59,5a,5b; cpu address:h122, 123, 124, 125) ? pvmap09_0,1,2,3 i 2 c address h5c,5d,5e,5f; cpu address:h126, 127, 128, 129) ? pvmap10_0,1,2,3 i 2 c address h60,61,62,63; cpu address:h12a, 12b, 12c, 12d) ? pvmap11_0,1,2,3 i 2 c address h64,65,66,67; cpu address:h12e, 12f, 130, 131) ? pvmap12_0,1,2,3 i 2 c address h68,69,6a,6b; cpu address:h132, 133, 134, 135) ? pvmap13_0,1,2,3 i 2 c address h6c,6d,6e,6f; cpu address:h136, 137, 138, 139) ? pvmap14_0,1,2,3 i 2 c address h70,71,72,73; cpu address:h13a, h13b, 13c, 13d) ? pvmap15_0,1,2,3 i 2 c address h74,75,76,77; cpu address:h13e, 13f, 140, 141) ? pvmap16_0,1,2,3 i 2 c address h78,79,7a,7b; cpu address:h142, 143, 144, 145) ? pvmap17_0,1,2,3 i 2 c address h7c,7d,7e,7f; cpu address:h146, 147, 148, 149) ? pvmap18_0,1,2,3 i 2 c address h80,81,82,83; cpu address:h14a, 14b, 14c, 14d) 765 32 0 fp en drop default tx priority bit [2:0]: reserved (default 7) bit [5:3]: default transmit priority. used when bit[7] = 1 (default 0) ? 000 transmit priority level 0 (lowest) ? 001 transmit priority level 1 ? 010 transmit priority level 2 ? 011 transmit priority level 3 ? 100 transmit priority level 4 ? 101 transmit priority level 5 ? 110 transmit priority level 6 ? 111 transmit priority level 7 (highest) bit [6]: default discard priority (default 0) ? 0 ? discard priority level 0 (lowest) ? 1 ? discard priority level 7(highest) bit [7]: enable fix priority (default 0) ? 0 disable fix priority. all frames are analyzed. transmit priority and discard priority are based on vlan tag, tos field or logical port. ? 1 transmit priority and discard priority are based on values programmed in bit [6:3]
MVTX2601Ag data sheet 46 zarlink semiconductor inc. ? pvmap19_0,1,2,3 i 2 c address h84,85,86,87; cpu address:h14e, 14f, 150, 151) ? pvmap20_0,1,2,3 i 2 c address h88,89,8a,8b; cpu address:h152, 153, 154, 155) ? pvmap21_0,1,2,3 i 2 c address h8c,8d,8e,8f; cpu address:h156, 157, 158, 159) ? pvmap22_0,1,2,3 i 2 c address h90,91,92,93; cpu address:h15a, 15b, 15c, 15d) ? pvmap23_0,1,2,3 i 2 c address h94,95,96,97; cpu address:h15e, 15f, 160, 161) 12.4.1 pvmode ?i 2 c address: h0a4, cpu address:h170 ? accessed by serial interface, and i 2 c (r/w) 12.5 group 2 address port trunking group 12.5.1 trunk0_mode? trunk group 0 mode ?i 2 c address h0a5; cpu address:203 ? accessed by serial interface and i 2 c (r/w) 70 df sl bit [0]: ? reserved ? must be ?0? bit [1]: ? slow learning ? same function as se_op mode bit 7. either bit can enable the function; both need to be turned off to disable the feature. bit [2]: ? disable dropping frames with destination mac addresses 0180c2000001 to 0180c200000f ? 0: drop all frames in the range ? 1: treats frames as multicast bit [3]: ? reserved bit [4]: ? support mac address 0 ? 0: mac address 0 is not learned. ? 1: mac address 0 is learned. bit [7:5]: ? reserved 73210 hash select port select bit [1:0]: ? port selection in unmanaged mode. input pin trunk0 enable/disable trunk group 0. ? 00 reserved ? 01 port 0 and 1 are used for trunk0 ? 10 port 0,1 and 2 are used for trunk0 ? 11 port 0,1,2 and 3 are used for trunk0
MVTX2601Ag data sheet 47 zarlink semiconductor inc. 12.5.2 trunk1_mode ? trunk group 1 mode ?i 2 c address h0a6; cpu address:20b ? accessed by serial interface and i 2 c (r/w) 12.5.3 trunk1_hash0 ? trunk group 1 hash result 0 destination port number ? cpu address:h20c ? accessed by serial interface (r/w) ? bit [4:0] hash result 0 destination port number (default 04) 12.5.4 tx_age ? tx queue aging timer ?i 2 c address: h07;cpu address:h325 ? accessed by serial interface (rw) ? bit[5:0]: unit of 100ms (default 8) ? disable transmission queue aging if value is zero. aging timer for all ports and queues. ? for no packet loss flow control, this register must be set to 0. 12.6 group 4 address search engine group 12.6.1 agetime_low ? mac address aging time low ?i 2 c address h0a8; cpu address:h400 ? accessed by serial interface and i 2 c (r/w) ? bit [7:0] low byte of the mac address aging timer. ? mac address aging is enable/disable by boot strap tstout9 bit [3:2] ? hash select. the hash selected is valid for trunk 0, 1 and 2. (default 00) ? 00 use source and destination mac address for hashing ? 01 use source mac address for hashing ? 10 use destination mac address for hashing ? 11 use source destination mac address and ingress physical port number for hashing 73210 port select bit [1:0]: ? port selection in unmanaged mode. input pin trunk1 enable/disable trunk group 1. ? 00 reserved ? 01 port 4 and 5 are used for trunk1 ? 10 reserved ? 11 port 4,5,6 and 7 are used for trunk1 75 0 tx queue agent
MVTX2601Ag data sheet 48 zarlink semiconductor inc. 12.6.2 e_high ?mac address aging time high ?i 2 c address h0a9; cpu address h401 ? accessed by serial interface and i 2 c (r/w) ? bit [7:0]: high byte of the mac address aging timer. ? the default setting provide 300 seconds aging time. aging time is based on the following equation: ? {agetime_time,agetime_low} x (# of mac address entries in the memory x 100 sec). number of mac entries = 32k when 1mb is used. number of mac entries = 64k when 2mb is used. 12.6.3 v_agetime ? vlan to port aging time ? cpu address h402 ? accessed by serial interface (r/w) ? bit [7:0] (default ff) reserved 12.6.4 se_opmode ? search engine operation mode ? cpu address:h403 ? accessed by serial interface (r/w) ? {se_opmode} x(# of entries 100 u sec) 76 543 2 1 0 sl dms bit [0]: ? reserved bit [1]: ? reserved bit [2]: ? reserved bit [3]: ? reserved bit [4]: ? reserved bit [5]: ? reserved bit [6]: ? disable mct speedup aging ? 1 ? disable speedup aging when mct resource is low. ? 0 ? enable speedup aging when mct resource is low. bit [7]: ? slow learning ? 1? enable slow learning. learning is temporary disabled when search demand is high ? 0 ? learning is performed independent of search deman
data sheet MVTX2601Ag 49 zarlink semiconductor inc. 12.8 group 5 address buffer control/qos group 12.8.1 fcbat ? fcb aging timer ?i 2 c address h0aa; cpu address:h500 12.8.2 qosc ? qos control ? i2c address h0ab; cpu address:h501 ? accessed by serial interface and i 2 c (r/w) 12.8.3 fcr ? flooding control register ?i 2 c address h0ac; cpu address:h502 ? accessed by serial interface and i 2 c (r/w) 70 fcbat bit [7:0]: ? fcb aging time. unit of 1ms. ( default ff ) ? this function is for buffer aging control. it is used to configure the aging time, and can be enabled/ disabled through bootstrap pin. it is not recommended to use this function for normal operation. 76 5 4 0 tos-d tos-p vf1c l bit [0]: ? qos frame lost is ok. priority will be available for flow control enabled source only when this bit is set (default 0) bit [4]: ? per vlan multicast flow control (default 0) ?0 ? disable ?1 ? enable bit [5]: ? reserved bit [6]: ? select tos bits for priority (default 0) ? 0 - use tos [4:2] bits to map the transmit priority ? 1 - use tos [7:5] bits to map the transmit priority bit [7]: ? select tos bits for drop priority (default 0) ?0 - use tos[4:2] bits to map the drop priority ? 1 - use tos[7:5] bits to map the drop priority 76 43 0 tos timebase u2mr
MVTX2601Ag data sheet 50 zarlink semiconductor inc. 12.8.4 avpml ? vlan priority map ?i 2 c address h0ad; cpu address:h503 ? accessed by serial interface and i 2 c (r/w) registers avpml, avpmm, and avpmh allow the eight vlan priorities to map into eight internal level transmit priorities. under the internal transmit priority, seven is highest priority where as zero is the lowest. this feature allows the user the flexibility of redefining the vlan priority field. for example, programming a value of 7 into bit 2:0 of the avpml register would map vlan priority 0 into internal transmit priority 7. the new priority is used inside the 2601. when the packet goes out it carries the original priority. 12.8.5 avpmm ? vlan priority map ?i 2 c address h0ae, cpu address:h504 ? accessed by serial interface and i 2 c (r/w) bit [3:0]: ? u2mr: unicast to multicast rate. units in terms of time base defined in bits [6:4]. this is used to limit the amount of flooding traffic. the value in u2mr specifies how many packets are allowed to flood within the time specified by bit [6:4]. to disable this function, program u2mr to 0. ( default = 8 ) bit [6:4]: ? timebase: 000 = 100us 001 = 200us 010 = 400us 011 = 800us 100 = 1.6ms 101 = 3.2ms 110 = 6.4ms 111 = 100us (same as 000) ? (default = 000) bit [7]: ? select vlan tag or tos (ip packets) to be preferentially picked to map transmit priority and drop priority ( default = 0 ). ? 0 ? select vlan tag priority field over tos ? 1 ? select tos over vlan tag priority field 76 5 32 0 bit [2:0]: ? priority when the vlan tag priority field is 0 (default 0) bit [5:3]: ? priority when the vlan tag priority field is 1 (default 0) bit [7:6]: ? priority when the vlan tag priority field is 2 (default 0)
data sheet MVTX2601Ag 51 zarlink semiconductor inc. map vlan priority into eight level transmit priorities: 12.8.6 avpmh ? vlan priority map ?i 2 c address h0af, cpu address:h505 ? accessed by serial interface and i 2 c (r/w) map vlan priority into eight level transmit priorities: 12.8.7 tospml ? tos priority map ?i 2 c address h0b0, cpu address:h506 ? accessed by serial interface and i 2 c (r/w) map tos field in ip packet into eight level transmit priorities 12.8.8 tospmm ? tos priority map ?i 2 c address h0b1, cpu address:h507 ? accessed by serial interface and i 2 c (r/w) 7 6 43 10 bit [0]: ? priority when the vlan tag priority field is 2 (default 0) bit [3:1]: ? priority when the vlan tag priority field is 3 (default 0) bit [6:4]: ? priority when the vlan tag priority field is 4 (default 0) bit [7]: ? priority when the vlan tag priority field is 5 (default 0) 7 6 43 10 bit [1:0]: ? priority when the vlan tag priority field is 5 (default 0) bit [4:2]: ? priority when the vlan tag priority field is 6 (default 0) bit [7:5]: ? priority when the vlan tag priority field is 7 (default 0) 70 bit [2:0]: ? priority when the tos field is 0 (default 0) bit [5:3]: ? priority when the tos field is 1 (default 0) bit [7:6]: ? priority when the tos field is 2 (default 0) 70
MVTX2601Ag data sheet 52 zarlink semiconductor inc. map tos field in ip packet into four level transmit priorities 12.8.9 tospmh ? tos priority map ?i 2 c address h0b2, cpu address:h508 ? accessed by serial interface and i 2 c (r/w) map tos field in ip packet into four level transmit priorities: 12.8.10 avdm ? vlan discard map ?i 2 c address h0b3, cpu address:h509 ? accessed by serial interface and i 2 c (r/w) map vlan priority into frame discard when low priority buffer usage is above threshold bit [0]: ? priority when the tos field is 2 (default 0) bit [3:1]: ? priority when the tos field is 3 (default 0) bit [6:4]: ? priority when the tos field is 4 (default 0) bit [7]: ? priority when the tos field is 5 (default 0) 70 bit [1:0]: ? priority when the tos field is 5 (default 0) bit [4:2]: ? priority when the tos field is 6 (default 0) bit [7:5]: ? priority when the tos field is 7 (default 0) 70 bit [0]: ? frame drop priority when vlan tag priority field is 0 (default 0) bit [1]: ? frame drop priority when vlan tag priority field is 1 (default 0) bit [2]: ? frame drop priority when vlan tag priority field is 2 (default 0) bit [3]: ? frame drop priority when vlan tag priority field is 3 (default 0) bit [4]: ? frame drop priority when vlan tag priority field is 4 (default 0) bit [5]: ? frame drop priority when vlan tag priority field is 5 (default 0) bit [6]: ? frame drop priority when vlan tag priority field is 6 (default 0) bit [7]: ? frame drop priority when vlan tag priority field is 7 (default 0)
data sheet MVTX2601Ag 53 zarlink semiconductor inc. 12.8.11 tosdml ? tos discard map ?i 2 c address h0b4, cpu address:h50a ? accessed by serial interface and i 2 c (r/w) map tos into frame discard when low priority buffer usage is above threshold 12.8.12 bmrc - broadcast/multicast rate control ?i 2 c address h0b5, cpu address:h50b) ? accessed by serial interface and i 2 c (r/w) ? this broadcast and multicast rate defines for each port the number of packet allowed to be forwarded within a specified time. once the packet rate is reached, packets will be dropped. to turn off the rate limit, program the field to 0. timebase is based on register 502 [6:4]. 12.8.13 ucc ? unicast congestion control ?i 2 c address h0b6, cpu address: 50c ? accessed by serial interface and i 2 c (r/w) 70 bit [0]: ? frame drop priority when tos field is 0 (default 0) bit [1]: ? frame drop priority when tos field is 1 (default 0) bit [2]: ? frame drop priority when tos field is 2 (default 0) bit [3]: ? frame drop priority when tos field is 3 (default 0) bit [4]: ? frame drop priority when tos field is 4 (default 0) bit [5]: ? frame drop priority when tos field is 5 (default 0) bit [6]: ? frame drop priority when tos field is 6 (default 0) bit [7]: ? frame drop priority when tos field is 7 (default 0) 70 broadcast rate multicast rate bit [3:0] : ? multicast rate control number of multicast packets allowed within the time defined in bits 6 to 4 of the flooding control register (fcr). (default 0) . bit [7:4] : ? broadcast rate control number of broadcast packets allowed within the time defined in bits 6 to 4 of the flooding control register (fcr). (default 0) 70 unicast congest threshold
MVTX2601Ag data sheet 54 zarlink semiconductor inc. 12.8.14 mcc ? multicast congestion control ?i 2 c address h0b7, cpu address: 50d ? accessed by serial interface and i 2 c (r/w) 12.8.15 pr100 ? port reservation for 10/100 ports ?i 2 c address h0b8, cpu address 50e ? accessed by serial interface and i 2 c (r/w) 12.8.16 sfcb ? share fcb size ?i 2 c address h0ba), cpu address 510 ? accessed by serial interface and i 2 c (r/w) bit [7:0] : ? number of frame count. used for best effort dropping at b% when destination port?s best effort queue reaches ucc threshold and shared pool is all in use. granularity 1 frame. (default: h10 for 2 mb or h08 for 1 mb) 754 0 fc reaction prd multicast congest threshold bit [4:0]: ? in multiples of two. used for triggering mc flow control when destination multicast port?s best effort queue reaches mcc threshold.(default 0x10) bit [7:5]: ? flow control reaction period (default 2) granularity 4usec. 7430 buffer low thd sp buffer reservation bit [3:0]: ? per port buffer reservation. ? define the space in the fdb reserved for each 10/100 port. expressed in multiples of 4 packets. for each packet 1536 bytes are reserved in the memory. bits [7:4]: ? expressed in multiples of 4 packets. threshold for dropping all best effort frames when destination port best efforts queues reach ucc threshold and shared pool all used and source port reservation is at or below the pr100[7:4] level. also the threshold for initiating uc flow control. ? default: ? h58 for configuration with 2mb; ? h35 for configuration with 1mb; 70 shared buffer size
data sheet MVTX2601Ag 55 zarlink semiconductor inc. 12.8.17 c2rs ? class 2 reserve size ?i 2 c address h0bb, cpu address 511 ? accessed by serial interface and i 2 c (r/w) ? buffer reservation for class 2 (third lowest priority). granularity 1. (default 0) 12.8.18 c3rs ? class 3 reserve size ? i 2 c address h0bc, cpu address 512 ? accessed by serial interface and i 2 c (r/w) ? buffer reservation for class 3. granularity 1. (default 0) 12.8.19 c4rs ? class 4 reserve size ?i 2 c address h0bd, cpu address 513 ? accessed by serial interface and i 2 c (r/w) ? buffer reservation for class 4. granularity 1. (default 0) 12.8.20 c5rs ? class 5 reserve size ?i 2 c address h0be; cpu address 514 ? accessed by serial interface and i 2 c (r/w) ? buffer reservation for class 5. granularity 1. (default 0) 12.8.21 c6rs ? class 6 reserve size ?i 2 c address h0bf; cpu address 515 ? accessed by serial interface and i 2 c (r/w) bits [7:0]: ? expressed in multiples of 4 packets. buffer reservation for shared pool. ? default: ? he6 for configuration with memory of 2mb; ? h46 for configuration with memory of 1mb; 70 class 2 fcb reservation 70 class 3 fcb reservation 70 class 4 fcb reservation 70 class 5 fcb reservation 70 class 6 fcb reservation
MVTX2601Ag data sheet 56 zarlink semiconductor inc. ? buffer reservation for class 6 (second highest priority). granularity 1. (default 0) 12.8.22 c7rs ? class 7 reserve size ?i 2 c address h0c0; cpu address 516 ? accessed by serial interface and i 2 c (r/w) ? buffer reservation for class 7 (highest priority). granularity 1. (default 0) 12.8.23 classes byte limit set 0 ? accessed by serial interface and i 2 c (r/w): c ? qosc00 ? byte_c01 (i 2 c address h0c1, cpu address 517) b ? qosc01 ? byte_c02 (i 2 c address h0c2, cpu address 518) a ? qosc02 ? byte_c03 (i 2 c address h0c3, cpu address 519) qosc00 through qosc02 represents one set of values a-c for a 10/100 port when using the weighted random early drop (wred) scheme described in chapter 7.7. there are four such sets of values a-c specified in classes byte limit set 0, 1, 2, and 3. each 10/ 100 port can choose one of the four byte limit sets as specified by the qos select field located in bits 5 to 4 of the ecr2n register. the values a-c are per-queue byte thresholds for random early drop. qosc02 represents a, and qosc00 represents c. granularity when delay bound is used: qosc02: 128 bytes, qosc01: 256 bytes. qosc00: 512 bytes. granularity when wfq is used: qosc02: 512 bytes, qosc01: 512 bytes, qosc00: 512 bytes. 12.8.24 classes byte limit set 1 ? accessed by serial interface and i 2 c (r/w): c - qosc03 ? byte_c11 (i 2 c address h0c4, cpu address 51a) b - qosc04 ? byte_c12 (i 2 c address h0c5, cpu address 51b) a - qosc05 ? byte_c13 (i 2 c address h0c6, cpu address 51c) qosc03 through qosc05 represents one set of values a-c for a 10/100 port when using the weighted random early detect (wred) scheme. granularity when delay bound is used: qosc05: 128 bytes, qosc04: 256 bytes. qosc03: 512 bytes. granularity when wfq is used: qosc05: 512 bytes, qosc04: 512 bytes, qosc03: 512 bytes. 12.8.25 classes byte limit set 2 ? accessed by serial interface and i 2 c (r/w): c - qosc06 ? byte_c21 (cpu address 51d) b - qosc07 ? byte_c22 (cpu address 51e) a - qosc08 ? byte_c23 (cpu address 51f) qosc06 through qosc08 represents one set of values a-c for a 10/100 port when using the weighted random early detect (wred) scheme. granularity when delay bound is used: qosc08: 128 bytes, qosc07: 256 bytes. qosc06: 512 bytes. granularity when wfq is used: qosc08: 512 bytes, qosc07: 512 bytes, qosc06: 512 bytes. 70 class 7 fcb reservation
data sheet MVTX2601Ag 57 zarlink semiconductor inc. 12.8.26 classes byte limit set 3 ? accessed by serial interface and i 2 c (r/w): c - qosc09 ? byte_c31 (cpu address 520) b - qosc10 ? byte_c32 (cpu address 521) a - qosc11 ? byte_c33 (cpu address 522) qosc09 through qosc011 represents one set of values a-c for a 10/100 port when using the weighted random early detect (wred) scheme. granularity when delay bound is used: qosc11: 128 bytes, qosc10: 256 bytes. qosc09: 512 bytes. granularity when wfq is used: qosc11: 512 bytes, qosc10: 512 bytes, qosc09: 512 bytes. 12.8.27 classes wfq credit set 0 ? accessed by serial interface (r/w) w3 - qosc24[5:0] ? credit_c00 (cpu address 52f) w2 - qosc25[5:0] ? credit_c01 (cpu address 530) w1 - qosc26[5:0] ? credit_c02 (cpu address 531) w0 - qosc27[5:0] ? credit_c03 (cpu address 532) qosc24 through qosc27 represents one set of wfq parameters for a 10/100 port. there are four such sets of values. the granularity of the numbers is 1, and their sum must be 64. qosc27 corresponds to w0, and qosc24 corresponds to w3. qosc24[7:6]: priority service type for the ports select this parameter set. option 1 to 4. qosc25[7]: priority service allow flow control for the ports select this parameter set. qosc25[6]: flow control pause best effort traffic only both flow control allow and flow control best effort only can take effect only the priority type is wfq. 12.8.28 classes wfq credit set 1 ? accessed by serial interface (r/w) w3 - qosc28[5:0] ? credit_c10 (cpu address 533) w2 - qosc29[5:0] ? credit_c11 (cpu address 534) w1 - qosc30[5:0] ? credit_c12 (cpu address 535) w0 - qosc31[5:0] ? credit_c13 (cpu address 536) qosc28 through qosc31 represents one set of wfq parameters for a 10/100 port. there are four such sets of values. the granularity of the numbers is 1, and their sum must be 64. qosc31 corresponds to w0, and qosc28 corresponds to w3. qosc28[7:6]: priority service type for the ports select this parameter set. option 1 to 4. qosc29[7]: priority service allow flow control for the ports select this parameter set. qosc29[6]: flow control pause best effort traffic only 12.8.29 classes wfq credit set 2 ? accessed by serial interface (r/w) w3 - qosc32[5:0] ? credit_c20 (cpu address 537) w2 - qosc33[5:0] ? credit_c21 (cpu address 538) w1 - qosc34[5:0] ? credit_c22 (cpu address 539)
MVTX2601Ag data sheet 58 zarlink semiconductor inc. w0 - qosc35[5:0] ? credit_c23 (cpu address 53a) qosc35 through qosc32 represents one set of wfq parameters for a 10/100 port. there are four such sets of values. the granularity of the numbers is 1, and their sum must be 64. qosc35 corresponds to w0, and qosc32 corresponds to w3. qosc32[7:6]: priority service type for the ports select this parameter set. option 1 to option 4. qosc33[7]: priority service allow flow control for the ports select this parameter set. qosc33[6]: flow control pause best effort traffic only 12.8.30 classes wfq credit set 3 ? accessed by serial interface (r/w) w3 - qosc36[5;0] ? credit_c30 (cpu address 53b) w2 - qosc37[5:0] ? credit_c31 (cpu address 53c) w1 - qosc38[5:0] ? credit_c32 (cpu address 53d) w0 - qosc39[5:0] ? credit_c33 (cpu address 53e) qosc39 through qosc36 represents one set of wfq parameters for a 10/100 port. there are four such sets of values. the granularity of the numbers is 1, and their sum must be 64. qosc39 corresponds to w0, and qosc36 corresponds to w3. qosc36[7:6]: priority service type for the ports select this parameter set. option 1 to option 4. qosc37[7]: priority service allow flow control for the ports select this parameter set. qosc37[6]: flow control pause best effort traffic only 12.8.31 rdrc0 ? wred rate control 0 ?i 2 c address 0fb, cpu address 553 ? accessed by serial interface and i c c (r/w) 12.8.32 rdrc1 ? wred rate control 1 ?i 2 c address 0fc, cpu address 554 ? accessed by serial interface and i 2 c (r/w) 70 x rate y rate bits [7:4]: ? corresponds to the frame drop percentage x% for wred. granularity 6.25%. bits[3:0]: ? corresponds to the frame drop percentage y% for wred. granularity 6.25%. see programming qos registers application note for more information. 70 z rate b rate
data sheet MVTX2601Ag 59 zarlink semiconductor inc. 12.8.33 user defined logical ports and well known ports the mvtx2600ag supports classifying packet priority through layer 4 logical port information. it can be setup by 8 well known ports, 8 user defined logical ports, and 1 user defined range. the 8 well known ports supported are: ?0:23 ?1:512 ?2:6000 ?3:443 ?4:111 ? 5:22555 ?6:22 ? 7:554 their respective priority can be programmed via well_known_port [7:0] priority register. well_known_port_ enable can individually turn on/off each well known port if desired. similarly, the user defined logical port provides the user programmability to the priority, plus the flexibility to select specific logical ports to fit the applications. the 8 user logical ports can be programmed via user_port 0-7 registers. two registers are required to be programmed for the logical port number. the respective priority can be programmed to the user_port [7:0] priority register. the port priority can be individually enabled/disabled via user_port_enable register. the user defined range provides a range of logical port numbers with the same priority level. programming is similar to the user defined logical port. instead of programming a fixed port number, an upper and lower limit need to be programmed, they are: {rhighh, rhighl} and {rlowh, rlowl} respectively. if the value in the upper limit is smaller or equal to the lower limit, the function is disabled. any ip packet with a logical port that is less than the upper limit and more than the lower limit will use the priority specified in rpriority. 12.8.33.1 user_port0_(0~7) ? user define logical port (0~7) ? user_port_0 - i 2 c address h0d6 + 0de; cpu address 580(low) + 581(high) ? user_port_1 - i 2 c address h0d7 + 0df; cpu address 582 + 583 ? user_port_2 - i 2 c address h0d8 + 0e0; cpu address 584 + 585 ? user_port_3 - i 2 c address h0d9 + 0e1; cpu address 586 + 587 ? user_port_4 - i 2 c address h0da + 0e2; cpu address 588 + 589 ? user_port_5 - i 2 c address h0db + 0e3; cpu address 58a + 58b ? user_port_6 - i 2 c address h0dc + 0e4; cpu address 58c + 58d ? user_port_7 - i 2 c address h0dd + 0e5; cpu address 58e + 58f ? accessed by serial interface and i 2 c (r/w) bits [7:4]: ? corresponds to the frame drop percentage z% for wred. granularity 6.25%. bits[3:0]: ? corresponds to the best effort frame drop percentage b%, when shared pool is all in use and destination port best effort queue reaches ucc. granularity 6.25%. see programming qos register application note for more information. 70 tcp/udp logic port low
MVTX2601Ag data sheet 60 zarlink semiconductor inc. ? (default 00) this register is duplicated eight times from port 0 through port 7 and allows the definition of eight separate ports. 12.8.33.2 user_port_[1:0]_priority - user define logic port 1 and 0 priority ?i 2 c address h0e6, cpu address 590 ? accessed by serial interface and i 2 c (r/w) ? the chip allows the definition of the priority 12.8.33.3 user_port_[3:2]_priority - user define logic port 3 and 2 priority ?i 2 c address h0e7, cpu address 591 ? accessed by serial interface and i 2 c (r/w) 12.8.33.4 user_port_[5:4]_priority - user define logic port 5 and 4 priority ?i 2 c address h0e8, cpu address 592 ? accessed by serial interface and i 2 c (r/w) ? (default 00) 12.8.33.5 user_port_[7:6]_priority - u ser d efine l ogic p ort 7 and 6 p riority ?i 2 c address h0e9, cpu address 593 ? accessed by serial interface and i 2 c (r/w) ? (default 00) 70 tcp/udp logic port high 7543 10 priority 1 drop priority 0 drop bits[3:0]: ? priority setting, transmission + dropping, for logic port 0 bits [7:4]: ? priority setting, transmission + dropping, for logic port 1 (default 00) 754310 priority 3 drop priority 2 drop 754310 priority 5 drop priority 4 drop 754310 priority 7 drop priority 6 drop
data sheet MVTX2601Ag 61 zarlink semiconductor inc. 12.8.33.6 user_port_enable [7:0] ? user define logic 7 to 0 port enables ?i 2 c address h0ea, cpu address 594 ? accessed by serial interface and i 2 c (r/w) ? (default 00) 12.8.33.7 well_known_port [1:0] priority- well known logic port 1 and 0 priority ?i 2 c address h0eb, cpu address 595 ? accessed by serial interface and i 2 c (r/w) ? priority 0 - well known port 23 for telnet applications. ? priority 1 - well known port 512 for tcp/udp ? (default 00) 12.8.33.8 well_known_port [3:2] priority- well known logic port 3 and 2 priority ?i 2 c address h0ec, cpu address 596 ? accessed by serial interface and i 2 c (r/w) ? priority 2 - well known port 6000 for xwin. ? priority 3 - well known port 443 for http. sec ? (default 00) 12.8.33.9 well_known_port [5:4] priority- well known logic port 5 and 4 priority ?i 2 c address h0ed, cpu address 597 ? accessed by serial interface and i 2 c (r/w) ? priority 4 - well known port 111 for sun rpe. ? priority 5 - well known port 22555 for ip phone call setup. ? (default 00) 7654 3 2 10 p7 p6 p5 p4 p3 p2 p1 p0 754310 priority 1 drop priority 0 drop 754310 priority 3 drop priority 2 drop 754310 priority 5 drop priority 4 drop
MVTX2601Ag data sheet 62 zarlink semiconductor inc. 12.8.33.10 well_known_port [7:6] priority- well known logic port 7 and 6 priority ?i 2 c address h0ee, cpu address 598 ? accessed by serial interface and i 2 c (r/w) ? priority 6 - well known port 22 for ssh. ? priority 7 - well known port 554 for rtsp. ? (default 00) 12.8.33.11 well known_port_enable [7:0] ? well known logic 7 to 0 port enables ?i 2 c address h0ef, cpu address 599 ? accessed by serial interface and i 2 c (r/w) ?1 - enable ? 0 - disable ? default 00) 12.8.33.12 rlowl ? user define range low bit 7:0 ?i 2 c address h0f4, cpu address: 59a ? accessed by serial interface and i 2 c (r/w) ? (default 00) 12.8.33.13 rlowh ? user define range low bit 15:8 ?i 2 c address h0f5, cpu address: 59b ? accessed by serial interface and i 2 c (r/w) ? (default 00) 12.8.33.14 rhighl ? user define range high bit 7:0 ?i 2 c address h0d3, cpu address: 59c ? accessed by serial interface and i 2 c (r/w) ? (default 00) 12.8.33.15 rhighh ? user define range high bit 15:8 ?i 2 c address h0d4, cpu address: 59d ? accessed by serial interface and i 2 c (r/w) ? (default 00) 12.8.33.16 rpriority ? user define range priority ?i 2 c address h0d5, cpu address: 59e ? accessed by serial interface and i 2 c (r/w) ? rlow and rhigh form a range for logical ports to be classified with priority specified in rpriority. 754310 priority 7 drop priority 6 drop 7654 3 2 10 p7 p6 p5 p4 p3 p2 p1 p0 73 0 range transmit priority drop
data sheet MVTX2601Ag 63 zarlink semiconductor inc. 12.9 group 6 address misc group 12.9.1 mii_op0 ? mii register option 0 ?i 2 c address f0, cpu address:h600 ? accessed by serial interface and i 2 c (r/w) 12.9.2 mii_op1 ? mii register option 1 ?i 2 c address f1, cpu address:h601 ? accessed by serial interface and i 2 c (r/w) bit[3:1] ? transmit priority bits[0]: ? drop priority 76 5 4 0 hfc 1prst vendor spc. reg addr bits [7]: ? half duplex flow control feature ? 0 = half duplex flow control always enable ? 1 = half duplex flow control by negotiation bits[6]: ? link partner reset auto-negotiate disable bits[5]: ? disable jabber detection. this is for homepna application or any serial operation slower than 10mbps. ? 1 = disable ? 0 = enable bit[4:0]: ? vendor specified link status register address (null value means don?t use it) (default 00); used when the linkup bit position in the phy is non-standard. 743 0 speed bit location duplex bit location bits[3:0]: ? duplex bit location in vendor specified register bits [7:4]: ? speed bit location in vendor specified register (default 00)
MVTX2601Ag data sheet 64 zarlink semiconductor inc. 12.9.3 fen ? feature register ?i 2 c address f2, cpu address:h602) ? accessed by serial interface and i 2 c (r/w) 12.9.4 miic0 ? mii command register 0 ? cpu address:h603 ? accessed by serial interface only (r/w) ? bit [7:0] mii data [7:0] note : before programming mii command: set fen[6], check miic3, making sure no rdy, and no valid; then program mii command. 12.9.5 miic1 ? mii command register 1 ? cpu address:h604 ? accessed by serial interface only (r/w) ? bit [7:0] mii data [15:8] note : before programming mii command: set fen[6], check miic3, making sure no rdy and no valid; then program mii command. 12.9.6 miic2 ? mii command register 2 ? cpu address:h605 ? accessed by serial interface only (r/w) 70 dml mii ds bits [0]: ? reserved (default 0) bits[1]: ? reserved (default 0) bit [2]: ? support ds ef code. (default 0) ? when 101110 is detected in ds field (tos [7:2]), the frame priority is set for 110 and drop is set for 0. bit [3]: ? reserved (default 0) bit [4]: ? reserved (default 1) bit [5]: ? reserved (default 0) bit [6]: ? disable mii management state machine ? 0: enable mii management state machine (default 0) ? 1: disable mii management state machine bit [7]: ? disable using mct link list structure ? 0: enable using mct link list structure (default 0) ? 1: disable using mct link list structure 70 mii op register address
data sheet MVTX2601Ag 65 zarlink semiconductor inc. note : before programming mii command: set fen[6], check miic3, making sure no rdy and no valid; then program mii command. writing to this register will initiate a serial management cycle to the mii management interface. for detail information, please refer to the phy control application note. 12.9.7 miic3 ? mii command register 3 ? cpu address:h606 ? accessed by serial interface only (r/w) note : before programming mii command: set fen[6], check miic3, making sure no rdy and no valid; then program mii command. 12.9.8 miid0 ? mii data register 0 ? cpu address:h607 ? accessed by serial interface only (ro) ? bit [7:0] mii data [7:0] 12.9.9 miid1 ? mii data register 1 ? cpu address:h608 ? accessed by serial interface only (ro) ? bit [7:0] mii data [15:8] 12.9.10 led mode ? led control ? cpu address:h609 ? accessed by serial interface and i 2 c (r/w) bits [4:0]: ? reg_ad ? register phy address bit [6:5] ? op ? operation code ?10? for read command and ?01? for write command 70 rd y valid phy address bits [4:0]: ? phy_ad ? 5 bit phy address bit [6] ? valid ? data valid from phy (read only) bit [7] ? rdy ? data is returned from phy (ready only) 70 clock rate hold time bit [0] ? reserved (default 0) bit[2:1]: ? hold time for led signal (default= 00) 00=8msec 01=16msec 10=32msec11=64msec
MVTX2601Ag data sheet 66 zarlink semiconductor inc. 12.9.11 device mode ? cpu address:h60a ? accessed by serial interface (r/w) 12.9.12 checksum - eeprom checksum ?i 2 c address ff, cpu address:h60b ? accessed by serial interface and i 2 c (r/w) before requesting that the MVTX2601Ag updates the eeprom device, the correct checksum needs to be calculated and written into this checksum register. when the mvtx2604ag boots from the eeprom the checksum is calculated and the value must be zero. if the checksum is not zeroed the mvtx2604ag does not start and pin checksum_ok is set to zero. the checksum formula is: ff i 2 c register = 0 i=0 12.10 group 7 address port mirroring group 12.10.1 mirror1_src ? port mirror source port ? cpu address 700 ? accessed by serial interface (r/w) (default 7f) bit[4:3]: ? led clock frequency (default 0) for 100 mhz sclk, 00=100m/8=12.5 mhz01=100m/16= 6.25 mhz 10=100m/32= 3.125 mhz11=100m/64=1.5625 mhz for 125 mhz sclk 00=125m/64=1953 khz 01=125m/128= 977 khz 10=125m/512= 244 khz11=125m/1024=122 khz bit[6]: ? reserved. must be 0. (default 0) bit[7]: ? reserved. must be 0. (default 0) 74 0 bit[1:0]: ? reserved. must be 0. (default 0) bit [7:4]: ? reserved bit [7:0]: ? (default 0) 70 ov i/o src port select
data sheet MVTX2601Ag 67 zarlink semiconductor inc. 12.10.2 mirror1_dest ? port mirror destination ? cpu address 701 ? accessed by serial interface (r/w) (default 17) 12.10.3 mirror2_src ? port mirror source port ? cpu address 702 ? accessed by serial interface (r/w) (default ff) 12.10.4 mirror2_dest ? port mirror destination ? cpu address 703 ? accessed by serial interface (r/w) (default 00) 12.11 group f address cpu access group 12.11.1 gcr-global control register ? cpu address: hf00 ? accessed by serial interface. (r/w) bit [4:0]: ? source port to be mirrored. use illegal port number to disable mirroring bit [5]: ? 1 ? select ingress data ? 0 ? select egress data bit [7]: ? must be ?1? 70 dest port select bit [4:0]: ? port mirror destination 70 i/o src port select bit [4:0]: ? source port to be mirrored. use illegal port number to disable mirroring bit [5]: ? 1 ? select ingress data ? 0 ? select egress data bit [7] ? must be 1 70 dest port select bit [4:0]: ? port mirror destination 70
MVTX2601Ag data sheet 68 zarlink semiconductor inc. 12.11.2 dcr-device status and signature register ? cpu address: hf01 ? accessed by serial interface. (ro) reset bist sr sc bit [0]: ? store configuration (default = 0) ? write ?1? followed by ?0? to store configuration into external eeprom bit[1]: ? store configuration and reset (default = 0) ? write ?1? to store configuration into external eeprom and reset chip bit[2]: ? start bist (default = 0) ? write ?1? followed by ?0? to start the device?s built-in self-test. the result is found in the dcr register. bit[3]: ? soft reset (default = 0) ? write ?1? to reset chip bit[4]: ? reserved. 70 revision signature re binp br bw bit [0]: ? 1: busy writing configuration to i 2 c ? 0: not busy writing configuration to i 2 c bit[1]: ? 1: busy reading configuration from i 2 c ? 0: not busy reading configuration from i 2 c bit[2]: ? 1: bist in progress ? 0: bist not running bit[3]: ? 1: ram error ?0: ram ok bit[5:4]: ? device signature ? 01: MVTX2601Ag device bit [7:6]: ? revision ? 00: initial silicon ? 01: xa1 silicon
data sheet MVTX2601Ag 69 zarlink semiconductor inc. 12.11.3 dcr1-chip status ? cpu address: hf02 ? accessed by serial interface (ro) 12.11.4 dpst ? device port status register ? cpu address:hf03 ? accessed by serial interface (r/w) 7 3210 cic bit [7] ? chip initialization completed bit[4:0]: ? read back index register. this is used for selecting what to read back from dtst. (default 00) - 5?b00000 - port 0 operating mode and negotiation status - 5?b00001 - port 1 operating mode/neg status - 5?b00010 - port 2 operating mode/neg status - 5?b00011 - port 3 operating mode/neg status - 5?b00100 - port 4 operating mode/neg status - 5?b00101 - port 5 operating mode/neg status - 5?b00110 - port 6 operating mode/neg status - 5?b00111 - port 7 operating mode/neg status - 5?b01000 - port 8 operating mode/neg status - 5?b01001 - port 9 operating mode/neg status - 5?b01010 - port 10 operating mode/neg status - 5?b01011 - port 11 operating mode/neg status - 5?b01100 - port 12 operating mode/neg status - 5?b01101 - port 13 operating mode/neg status - 5?b01110 - port 14 operating mode/neg status - 5?b01111 - port 15 operating mode/neg status - 5?b10000 - port 16 operating mode/neg status - 5?b10001 - port 17 operating mode/neg status - 5?b10010 - port 18 operating mode/neg status - 5?b00011 - port 19 operating mode/neg status - 5?b10100 - port 20 operating mode/neg status - 5?b10101 - port 21 operating mode/neg status - 5?b10110 - port 22 operating mode/neg status - 5?b10111 - port 23 operating mode/neg status
MVTX2601Ag data sheet 70 zarlink semiconductor inc. 12.11.5 dtst ? data read back register ? cpu address: hf04 ? accessed by serial interface (ro) ? this register provides various internal information as selected in dpst bit[4:0]. refer to the phy control application note. when bit is 1: ? bit[0] ? flow control enable ? bit[1] ? full duplex port ? bit[2] ? fast ethernet port ? bit[3] ? link is down ? bit[7:4] ? reserved 12.11.6 da ? da register ? cpu address: hfff ? accessed by cpu and serial interface (ro) ? always return 8?h da . indicate the serial port connection is good. inkdn fe fdpx fcen
data sheet MVTX2601Ag 71 zarlink semiconductor inc. 13.0 bga and ball signal descriptions 13.1 bga views 13.1.1 encapsulated view 123456789101112131415161718192021222324252627 28 29 a la_ d 4 la_ d 7 la_ d 10 la_ d 13 la_ d 15 la_ a 4 la_ o e0 la_ a 8 la_ a 13 la_ a 16 la_ a 19 la_d 33 la_d 36 la_d 39 la_d 42 la_d 45 rese rved rese rved tr un k1 rese rved rese rved scl sda stro be tsto ut7 b la_ d 1 la_ d 3 la_ d 6 la_ d 9 la_ d 12 la_ d 14 la_ a dsc la_ o e1 la_ a 7 la_ a 12 la_ a 15 la_ a 18 la_d 32 la_d 35 la_d 38 la_d 41 la_d 44 rese rved rese rved la_ d 62 rese rved rese rved rese rved rese rved d0 tsto ut8 tsto ut3 c la_ c lk la_ d 0 la_ d 2 la_ d 5 la_ d 8 la_ d 11 la_ a 3 la_ o e_ la w e_ t_ mo de1 la_ a 11 la_ a 14 la_ a 17 la_a 20 la_d 34 la_d 37 la_d 40 la_d 43 rese rved rese rved rese rved tr un k0 rese rved rese rved auto fd tsto ut11 tsto ut9 tsto ut4 tsto ut0 d agn d la_d 17 la_ d 19 la_ d 21 la_ d 23 la_ d 25 la_ d 27 la_ d 29 la_ d 31 la_ a 6 la_ a 10 la w e0 la_ d 49 la_d 51 la_d 53 la_d 55 la_d 57 la_d 59 la_ d 61 la_ d 63 la_ d 47 scan col scan clk tsto ut14 tsto ut13 tsto ut12 tsto ut10 tsto ut5 tsto ut1 e sclk la_ d 16 la_ d 18 la_ d 20 la_ d 22 la_ d 24 la_ d 26 la_ d 28 la_ d 30 la_ a 5 la_ a 9 la w e1 la_ d 48 la_d 50 la_d 52 la_d 54 la_d 56 la_d 58 la_ d 60 rese rved la_ d 46 scan link tsto ut15 rese rved rese rved scan mod e tsto ut6 tsto ut2 f avc c resi n_ scan en rese rved rese rved vdd 33 vdd 33 vdd 33 vdd 33 vdd 33 rese rved rese rved rese rved rese rved rese rved g rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved h rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved j rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved k rese rved rese rved rese rved rese rved rese rved vdd vdd vdd vdd rese rved rese rved rese rved rese rved rese rved l rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved m rese rved rese rved rese rved rese rved rese rved vdd vss vss vss vss vss vss vss vdd rese rved rese rved rese rved rese rved rese rved n rese rved rese rved rese rved rese rved rese rve d vdd 33 vdd vss vss vss vss vss vss vss vdd vdd 33 rese rve d rese rved rese rved p rese rved rese rved rese rved rese rved rese rve d vdd 33 vss vss vss vss vss vss vss vdd 33 rese rve d rese rved mdio rese rved r rese rved rese rved rese rved rese rved rese rve d vdd 33 vss vss vss vss vss vss vss vdd 33 rese rve d rese rved mdc m_ cl k t rese rved rese rved rese rved rese rved rese rve d vdd 33 vss vss vss vss vss vss vss vdd 33 rese rve d rese rved rese rved rese rved rese rved u rese rved rese rved rese rved rese rved rese rve d vdd 33 vdd vss vss vss vss vss vss vss vdd vdd 33 rese rve d rese rved rese rved rese rved rese rved v rese rved rese rved rese rved rese rved rese rved vdd vss vss vss vss vss vss vss vdd rese rved rese rved rese rved rese rved rese rved w rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved y rese rved rese rved rese rved rese rved rese rved vdd vdd vdd vdd rese rved rese rved rese rved rese rved rese rved a a rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved a b rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved a c rese rved rese rved rese rved rese rved rese rved rese rved rese rved m2 3 _ crs m2 3 _ rxd0 m2 3 _ rxd1 a d rese rved rese rved rese rved rese rved rese rved vdd 33 vdd 33 vdd 33 vdd 33 vdd 33 rese rved rese rved m2 3 _ txd1 m2 3 _ txd0 m2 3 _ txen a e m0_t xen m0_t xd0 m0_t xd1 m3_t xd1 m3_t xen m3_r xd0 m5_t xd1 m5_t xen m5_r xd0 m8 _ t xd1 m8 _ t xen m8 _ r xd0 m1 0 _ txd1 m10 _ txen m10 _ rxd0 m13 _ txd1 m16_ txd0 m15_ txd1 m16_ rxd1 m15_ txen m15_ rxd0 m18_ txd1 m18_ txen m18_ rxd0 m20_ txd1 m20_ txen m2 0 _ rxd0 m2 2 _ rxd1 af m0_r xd1 m0_r xd0 m0_c rs m3_t xd0 m3_c rs m3_r xd1 m5_t xd0 m5_c rs m5_r xd1 m8 _ t xd0 m8 _ c rs m8 _ r xd1 m1 0 _ txd0 m10 _ crs m10 _ rxd1 m13 _ txd0 m13_ crs m13_ rxd1 m14_ crs m16r xd0 m15_ rxd1 m17_ rxd0 m17_ crs m18_ rxd1 m20_ txd0 m20_ crs m2 0 _ rxd1 m2 2 _ rxd0 m2 2 _ crs a g m1_t xen m1_t xd0 m1_t xd1 m2_t xd1 m2_c rs m4_t xd1 m4_c rs m6_t xd1 m6_c rs m7 _ t xd1 m7 _ c rs m9 _ t xd1 m9 _ c rs m11 _ txd1 m11 _ crs m12 _ txd1 m12_ crs m14_ txd1 m15_ txd0 m16_ txd1 m16_ crs m18_ txd0 m18_ crs m19_ txd1 m19_ crs m21_ txd1 m2 1 _ crs m2 2 _ txen m2 2 _ txd0 a h m1_r xd0 m1_c rs m2_t xd0 m2_r xd0 m4_t xd0 m4_r xd0 m6_t xd0 m6_r xd0 m7 _ t xd0 m7 _ r xd0 m9 _ t xd0 m9 _ r xd0 m11 _ txd0 m11 _ rxd0 m12 _ txd0 m12_ rxd0 m14_ txd0 m14_ rxd0 m13_ rxd0 m15_ crs m17_ txd0 m17_ rxd1 m19_ txd0 m19_ rxd0 m21_ txd0 m2 1 _ rxd0 m2 2 _ txd1 aj m1_r xd1 m2_t xen m2_r xd1 m4_t xen m4_r xd1 m6_t xen m6_r xd1 m7 _ t xen m7 _ r xd1 m9 _ t xen m9 _ r xd1 m11 _ txen m11 _ rxd1 m12 _ txen m12_ rxd1 m14_ txen m14_ rxd1 m16_ txen m13_ txen m17_ txen m17_ txd1 m19_ txen m19_ rxd1 m21_ txen m2 1 _ rxd1 1234567891011121314151617181920212223242526272829
MVTX2601Ag data sheet 72 zarlink semiconductor inc. 13.1.2 power and ground distribution the following figure provides an encapsulated view of the power and ground distribution 123456789101112131415161718192021222324252627 28 29 a la_ d 4 la_ d 7 la_ d 10 la_ d 13 la_ d 15 la_ a 4 la_o e0 la_a 8 la_a 13 la_ a 16 la_ a 19 la_ d 33 la_ d 36 la_ d 39 la_ d 42 la_ d 45 rese rved rese rved trun k1 mirr or4 mirr or1 scl sda stro be tsto ut7 b la_ d 1 la_ d 3 la_ d 6 la_ d 9 la_ d 12 la_ d 14 la_ a dsc la_o e1 la_a 7 la_a 12 la_ a 15 la_ a 18 la_ d 32 la_ d 35 la_ d 38 la_ d 41 la_ d 44 rese rved rese rved la_d 62 mirr or5 mirr or2 tr un k2 rese rved d0 tsto ut8 tsto ut3 c la_ c lk la_ d 0 la_ d 2 la_ d 5 la_ d 8 la_ d 11 la_ a 3 la_ o e_ la w e_ t_mo de1 la_a 11 la_ a 14 la_ a 17 la_ a 20 la_ d 34 la_ d 37 la_ d 40 la_ d 43 rese rved rese rved rese rved trun k0 mirr or3 mirr or0 auto fd tsto ut11 tsto ut9 tsto ut4 tsto ut0 d agn d la_d 17 la_ d 19 la_ d 21 la_ d 23 la_ d 25 la_ d 27 la_ d 29 la_d 31 la_a 6 la_a 10 la w e0 la_ d 49 la_ d 51 la_ d 53 la_ d 55 la_ d 57 la_ d 59 la_ d 61 la_d 63 la_d 47 scan col scan clk tsto ut14 tsto ut13 tsto ut12 tsto ut10 tsto ut5 tsto ut1 e sclk la_ d 16 la_ d 18 la_ d 20 la_ d 22 la_ d 24 la_ d 26 la_ d 28 la_d 30 la_a 5 la_a 9 la w e1 la_ d 48 la_ d 50 la_ d 52 la_ d 54 la_ d 56 la_ d 58 la_ d 60 rese rved la_d 46 scan link tsto ut15 m26_ crs m26_ txer scan mod e tsto ut6 tsto ut2 f avc c resi n_ scan en lb _ d 63 lb _ d 62 vdd 33 vdd 33 vdd 33 vdd 33 vdd 33 m26_ txcl k m26_ txen m26_ mtx clk m26_ rxd v m2 6 _ rxcl k g lb _ c lk rese tout _ lb _ d 47 lb _ d 61 lb _ d 60 m26_ txd1 4 m26_ txd1 5 m26_ rxd1 5 m26_ rxer m2 6 _ col h lb _ d 46 lb _ d 45 lb _ d 44 lb _ d 59 lb _ d 58 m26_ txd1 2 m26_ txd1 3 m26_ rxd1 2 m26_ rxd1 3 m2 6 _ rxd1 4 j lb _ d 43 lb _ d 42 lb _ d 41 lb _ d 57 lb _ d 56 m26_ txd1 0 m26_ txd1 1 m26_ rxd9 m26_ rxd1 0 m2 6 _ rxd1 1 k lb _ d 40 lb _ d 39 lb _ d 38 lb _ d 55 lb _ d 54 vdd vdd vdd vdd m26_ txd9 m26_ txd8 m26_ rxd6 m26_ rxd7 m2 6 _ rxd8 l lb _ d 37 lb _ d 36 lb _ d 35 lb _ d 53 lb _ d 52 m26_ txd4 m26_ txd6 m26_ rxd3 m26_ rxd4 m2 6 _ rxd5 m lb _ d 34 lb _ d 33 lb _ d 32 lb _ d 51 lb _ d 50 vdd vss vss vss vss vss vss vss vdd m26_ txd7 m26_ txd5 m26_ rxd0 m26_ rxd1 m2 6 _ rxd2 n lb _ a 18 lb _ a 19 lb _ a 20 lb _ d 49 lb _ d 48 vdd 33 vdd vss vss vss vss vss vss vss vdd vdd 33 m26_ txd2 m26_ txd3 d_ co nfig 1 d_co nfig 0 gref _clk 1 p lb _ a 15 lb _ a 16 lb _ a 17 lb w e0 lb _ we1 vdd 33 vss vss vss vss vss vss vss vdd 33 m26_ txd0 m26_ txd1 mdio gref _clk 0 r lb _ a 10 lb _ a 11 lb _ a 12 lb _ a 13 lb _ a 14 vdd 33 vss vss vss vss vss vss vss vdd 33 m25_ crs m25_ txer mdc m_ cl k t lb _ a 5 lb _ a 6 lb _ a 7 lb _ a 8 lb _ a 9 vdd 33 vss vss vss vss vss vss vss vdd 33 m25_ txcl k m25_ txen m25_ mtx clk m25_ rxd v m2 5 _ rxcl k u lb _ o e0 lb _ o e1 t_ mo de0 lb _ d 31 lb _ d 30 vdd 33 vdd vss vss vss vss vss vss vss vdd vdd 33 m25_ txd1 4 m25_ txd1 5 m25_ rxd1 5 m25_ rxer m2 5 _ col v lb _ a dsc lb _ o e_ lb w e_ lb _ d 29 lb _ d 28 vdd vss vss vss vss vss vss vss vdd m25_ txd1 2 m25_ txd1 3 m25_ rxd1 2 m25_ rxd1 3 m2 5 _ rxd1 4 w lb _ d 15 lb _ a 3 lb _ a 4 lb _ d 27 lb _ d 26 m25_ txd1 0 m25_ txd1 1 m25_ rxd9 m25_ rxd1 0 m2 5 _ rxd1 1 y lb _ d 14 lb _ d 13 lb _ d 12 lb _ d 25 lb _ d 24 vdd vdd vdd vdd m25_ rxd6 m25_ txd8 m25_ txd9 m25_ rxd7 m2 5 _ rxd8 a a lb _ d 11 lb _ d 10 lb _ d 9 lb _ d 23 lb _ d 22 m25_ txd6 m25_ txd7 m25_ rxd3 m25_ rxd4 m2 5 _ rxd5 a b lb _ d 8 lb _ d 7 lb _ d 6 lb _ d 21 lb _ d 20 m25_ txd4 m25_ txd5 m25_ rxd0 m25_ rxd1 m2 5 _ rxd2 a c lb _ d 5 lb _ d 4 lb _ d 3 lb _ d 19 lb _ d 18 m25_ txd2 m25_ txd3 m23_ crs m23_ rxd0 m2 3 _ rxd1 a d lb _ d 2 lb _ d 1 lb _ d 0 lb _ d 17 lb _ d 16 vdd 33 vdd 33 vdd 33 vdd 33 vdd 33 m25_ txd0 m25_ txd1 m23_ txd1 m23_ txd0 m2 3 _ txen a e m0_t xen m0_t xd0 m0_t xd1 m3_t xd1 m3_t xen m3 _ r xd0 m5 _ t xd1 m5 _ t xen m5_ r xd0 m8_ t xd1 m8_t xen m8_r xd0 m10_ txd1 m10_ txen m10_ rxd0 m13_ txd1 m16_ txd0 m1 5 _ txd1 m1 6 _ rxd1 m15 _ txen m15 _ rxd0 m18_ txd1 m18_ txen m18_ rxd0 m20_ txd1 m20_ txen m20_ rxd0 m22_ rxd1 af m0_r xd1 m0_r xd0 m0_c rs m3_t xd0 m3_c rs m3 _ r xd1 m5 _ t xd0 m5 _ c rs m5_ r xd1 m8_ t xd0 m8_c rs m8_r xd1 m10_ txd0 m10_ crs m10_ rxd1 m13_ txd0 m13_ crs m1 3 _ rxd1 m1 4 _ crs m16 r xd0 m15 _ rxd1 m17_ rxd0 m17_ crs m18_ rxd1 m20_ txd0 m20_ crs m20_ rxd1 m22_ rxd0 m2 2 _ crs a g m1_t xen m1_t xd0 m1_t xd1 m2_t xd1 m2_c rs m4 _ t xd1 m4 _ c rs m6 _ t xd1 m6_ c rs m7_ t xd1 m7_c rs m9_t xd1 m9_c rs m11_ txd1 m11_ crs m12_ txd1 m12_ crs m1 4 _ txd1 m1 5 _ txd0 m16 _ txd1 m16 _ crs m18_ txd0 m18_ crs m19_ txd1 m19_ crs m21_ txd1 m21_ crs m22_ txen m2 2 _ txd0 a h m1_r xd0 m1_c rs m2_t xd0 m2_r xd0 m4 _ t xd0 m4 _ r xd0 m6 _ t xd0 m6_ r xd0 m7_ t xd0 m7_r xd0 m9_t xd0 m9_r xd0 m11_ txd0 m11_ rxd0 m12_ txd0 m12_ rxd0 m1 4 _ txd0 m1 4 _ rxd0 m13 _ rxd0 m15 _ crs m17_ txd0 m17_ rxd1 m19_ txd0 m19_ rxd0 m21_ txd0 m21_ rxd0 m22_ txd1 aj m1_r xd1 m2_t xen m2_r xd1 m4 _ t xen m4 _ r xd1 m6 _ t xen m6_ r xd1 m7_ t xen m7_r xd1 m9_t xen m9_r xd1 m11_ txen m11_ rxd1 m12_ txen m12_ rxd1 m1 4 _ txen m1 4 _ rxd1 m16 _ txen m13 _ txen m17_ txen m17_ txd1 m19_ txen m19_ rxd1 m21_ txen m21_ rxd1 1234567891011121314151617181920212223242526272829
data sheet MVTX2601Ag 73 zarlink semiconductor inc. 13.2 ball ? signal descriptions all pins are cmos type; all input pins are 5 volt tolerance; and all output pins are 3.3 cmos drive. 13.2.1 ball signal descriptions ball no(s) symbol i/o description c19, b19, a19, c20, b20, a20, c21, e20, b22, a22, c23, b23, a23, c24 b25 p_data[15:8][5:0] p_int# i/o with pull up output not used. leave unconnected not used i 2 c interface (0) note: in unmanaged mode, use i 2 c and serial control interface to configure the system a24 scl output i 2 c data clock a25 sda i/o-ts with pull up i 2 c data i/o serial control interface a26 strobe input with weak internal pull up serial strobe pin b26 d0 input serial data input c25 autofd output with pull up serial data output (autofd) frame buffer interface d20, b21, d19, e19,d18, e18, d17, e17, d16, e16, d15, e15, d14, e14, d13, e13, d21, e21, a18, b18, c18, a17, b17, c17, a16, b16, c16, a15, b15, c15, a14, b14, d9, e9, d8, e8, d7, e7, d6, e6, d5, e5, d4, e4, d3, e3, d2, e2, a7, b7, a6, b6, c6, a5, b5, c5, a4, b4, c4, a3, b3, c3, b2, c2 la_d[63:0] i/o-ts with pull up frame bank a? data bit [63:0] c14, a13, b13, c13, a12, b12, c12, a11, b11, c11, d11, e11, a10, b10, d10, e10, a8, c7 la_a[20:3] output frame bank a ? address bit [20:3] b8 la_adsc# output with pull up frame bank a address status control c1 la_clk output frame bank a clock input c9 la_we# output with pull up frame bank a write chip select for one layer sram application
MVTX2601Ag data sheet 74 zarlink semiconductor inc. d12 la_we0# output with pull up frame bank a write chip select for lower layer of two layers sram application e12 la_we1# output with pull up frame bank a write chip select for upper layer of two layers sram application c8 la_oe# output with pull up frame bank a read chip select for one layer sram application a9 la_oe0# output with pull up frame bank a read chip select for lower layer of two layers sram application b9 la_oe1# output with pull up frame bank a read chip select for upper layer of two layers sram application fast ethernet access ports [23:0] rmii r28 m_mdc output mii management data clock ? (common for all mii ports [23:0]) p28 m_mdio i/o-ts with pull up mii management data i/o ? (common for all mii ports ? [23:0])) r29 m_clki input reference input clock ac29, ae28, aj27, af27, aj25, af24, ah23, ae19, af21, aj19, af18, aj17, aj15, af15, aj13, af12, aj11, aj9, af9, aj7, af6, aj5, aj3, af1 m[23:0]_rxd[1] input with weak internal pull up resistors. ports [23:0] ? receive data bit [1] ac28, af28, ah27, ae27, ah25, ae24, af22, af20, ae21, ah19, ah20, ah17, ah15, ae15, ah13, ae12, ah11, ah9, ae9, ah7, ae6, ah5, ah2, af2 m[23:0]_rxd[0] input with weak internal pull up resistors ports [23:0] ? receive data bit [0] ac27, af29, ag27, af26, ag25, ag23, af23, ag21, ah21, af19, af17, ag17, ag15, af14, ag13, af11, ag11, ag9, af8, ag7, af5, ag5, ah3, af3 m[23:0]_crs_dv input with weak internal pull down resistors. ports [23:0] ? carrier sense and receive data valid ball no(s) symbol i/o description
data sheet MVTX2601Ag 75 zarlink semiconductor inc. ad29, ag28, aj26, ae26, aj24, ae23, aj22, aj20, ae20, aj18, aj21, aj16, aj14, ae14, aj12, ae11, aj10, aj8, ae8, aj6, ae5, aj4, ag1, ae1 m[23:0]_txen i/o- ts with pull up, slew ports [23:0] ? transmit enable strap option for rmii/gpsi ad27, ah28, ag26, ae25, ag24, ae22, aj23, ag20, ae18, ag18, ae16, ag16, ag14, ae13, ag12, ae10, ag10, ag8, ae7, ag6, ae4, ag4, ag3, ae3 m[23:0]_txd[1] output, slew ports [23:0] ? transmit data bit [1] ad28, ag29, ah26, af25, ah24, ag22, ah22, ae17, ag19, ah18, af16, ah16, ah14, af13, ah12, af10, ah10, ah8, af7, ah6, af4, ah4, ag2, ae2 m[23:0]_txd[0] output, slew ports [23:0] ? transmit data bit [0] led interface c29 led_clk/tstout0 i/o- ts with pull up led serial interface output clock d29 led_syn/tstout1 i/o- ts with pull up led output data stream envelope e29 led_bit/tstout2 i/o- ts with pull up led serial data output stream b28 tstout3 i/o- ts with pull up (reserved) c28 tstout4 i/o- ts with pull up (reserved) d28 tstout5 i/o- ts with pull up (reserved) e28 tstout6 i/o- ts with pull up (reserved) a27 tstout7 i/o- ts with pull up (reserved) b27 tstout8 i/o- ts with pull up (reserved) c27 init_done/tstout 9 i/o- ts with pull up system start operation d27 init_start/tstou t10 i/o- ts with pull up start initialization c26 checksum_ok/ts tout11 i/o- ts with pull up eeprom read ok ball no(s) symbol i/o description
MVTX2601Ag data sheet 76 zarlink semiconductor inc. d26 fcb_err/tstout1 2 i/o- ts with pull up fcb memory self test fail d25 mct_err/tstout1 3 i/o- ts with pull up mct memory self test fail d24 bist_in_prc/tsto ut14 i/o- ts with pull up processing memory self test e24 bist_done/tstou t15 i/o- ts with pull up memory self test done trunk enable c22 trunk0 input w/ weak internal pull down resistors trunk port enable a21 trunk1 input w/ weak internal pull down resistors trunk port enable test facility u3 t_mode0 i/o-ts test pin ? set mode upon reset, and provides nand tree test output during test mode (pull up) c10 t_mode1 i/o-ts test pin ? set mode upon reset, and provides nand tree test output during test mode (pull up) t_mode1 t_mode0 0 0 nandtree 0 1 reserved 1 0 reserved 1 1 regular operation t_mode0 and t_mode1 are used for manufacturing tests. the signals should both be set to 1 for regular operation. f3 scan_en input with pull down scan enable 0 - normal mode (unconnected) e27 scanmode input with pull down 1 - enables test mode. 0 - normal mode (unconnected) system clock, power and ground pins ball no(s) symbol i/o description
data sheet MVTX2601Ag 77 zarlink semiconductor inc. e1 sclk input system clock at 100 mhz k12, k13, k17,k18 m10, n10, m20, n20, u10, v10, u20, v20, y12, y13, y17, y18 vdd power +2.5 volt dc supply f13, f14, f15, f16, f17, n6, p6, r6, t6, u6, n24, p24, r24, t24, u24, ad13, ad14, ad15, ad16, ad17 vdd33 power +3.3 volt dc supply m12, m13, m14, m15, m16, m17, m18, n12, n13, n14, n15, n16, n17, n18, p12, p13, p14, p15, p16, p17, p18, r12, r13, r14, r15, r16, r17, r18, t12, t13, t14, t15, t16, t17, t18, u12, u13, u14, u15, u16, u17, u18, v12, v13, v14, v15, v16, v17, v18, vss power ground ground f1 avcc analog power used for the pll d1 agnd analog ground used for the pll misc d22 scancol input scans the collision signal of home phy d23 scanclk input/ output clock for scanning home phy collision and link e23 scanlink input link up signal from home phy f2 resin# input reset input g2 resetout_ output reset phy ball no(s) symbol i/o description
MVTX2601Ag data sheet 78 zarlink semiconductor inc. b22, f4, f5, g4, g5, h4, h5, j4, j5, k4, k5, l4, l5, m4, m5, n4, n5, g3, h1, h2, h3, j1, j2, j3, k1, k2, k3, l1, l2, l3, m1, m2, m3, u4, u5, v4, v5, w4, w5, y4, y5, aa4, aa5, ab4, ab5, ac4, ac5, ad4, ad5, w1, y1, y2, y3, aa1, aa2, aa3, ab1, ab2, ab3, ac1, ac2, ac3, ad1, ad2, ad3, n3, n2, n1, p3, p2, p1, r5, r4, r3, r2, r1, t5, t4, t3, t2, t1, w3, w2, v1, g1, v3, p4, p5, v2, u1, u2, u26, u25, v26, v25, w26, w25, y27, y26, aa26, aa25, ab26, ab25, ac26, ac25, ad26, ad25, t28, u28, r25, u29, t29, u27, v29, v28, v27, w29, w28, w27, y29, y28, y25, aa29, aa28, aa27, ab29, ab28, ab27, t26, r26, t27, t25, p29, g26, g25, h26, h25, j26, j25, k25, k26, m25, l26, m26, l25, n26, n25, p26, p25, f28, g28, e25, g29, f29, g27,h29, h28, h27, j29, j28, j27, k29, k28, k27, l29, l28, l27, m29, m28, m27, f26, e26, f27, f25, n29,b24 reserved i/o-ts reserved pin bootstrap pins (default= pull up, 1= pull up 0= pull down) after reset tstout0 to tstout15 are used by the led interface. c29 tstout0 default: 1 reserved d29 tstout1 default: enable (1) rmii mac power saving enable 0 - no power saving 1 - power saving e29 tstout2 default: (1) reserved b28 tstout3 default: (1) reserved c28 tstout4 default: (1) reserved ball no(s) symbol i/o description
data sheet MVTX2601Ag 79 zarlink semiconductor inc. d28 tstout5 default: sclk (1) scan speed 0 - ? sclk(hpna) 1 - sclk e28 tstout6 default: (1) reserved a27 tstout7 default: 128k x 32 or 128k x 64 (1) memory size 0 - 256k x 32 or 256k x 64 (4m total) 1 - 128k x 32 or 128k x 64 (2m total) b27 tstout8 default: not installed (1) eeprom installed 0 - eeprom installed 1 - eeprom not installed c27 tstout9 default: mct aging enable (1) mct aging 0 - mct aging disable 1 - mct aging enable d27 tstout10 default: fcb aging enable (1) fcb aging 0 - fcb aging disable 1 - fcb aging enable c26 tstout11 default: timeout reset enable (1) timeout reset 0 - time out reset disable 1 - time out reset enable. issue reset if any state machine did not go back to idle for 5 sec. d26 tstout12 default: normal (1) test speed up 0 - enable test speed up. do not use. 1 - disable test speed up d25 tstout13 default: single depth (1) fdb ram depth (1 or 2 layers) 0 - two layers 1 - one layer d24 tstout14 default: (1) reserved. leave unconnected e24 tstout15 default: normal operation sram test mode 0 - enable test mode 1 - normal operation ad29, ag28, aj26, ae26, aj24, ae23, aj22, aj20, ae20, aj18, aj21, aj16, aj14, ae14, aj12, ae11, aj10, aj8, ae8, aj6, ae5, aj4, ag1, ae1, m[23:0]_txen default: rmii 0 ? gpsi 1 - rmii ball no(s) symbol i/o description
MVTX2601Ag data sheet 80 zarlink semiconductor inc. notes: c21 p_d[9] default: pll enable pll enable for la_clk. 0 ? disable pll, use delay specified by p_d[15:10] strap option 1 ? enable pll c19, b19, a19 p_d[15:13] default: 111 programmable delay for internal oe_clk from sclk input when pll is disabled. the oe_clk is used for generating the oe0 and oe1 signals suggested value is 001. c20, b20, a20 p_d[12:10] default: 111 programmable delay for la_clk from internal oe_clk when pll is diabled. the la_clk delay from sclk is the sum of the delay programmed in here and the delay in p_d[15:13]. suggested value is 011. # = active low signal input = input signal in-st = input signal with schmitt-trigger output = output signal (tri-state driver) out-od= output signal with open-drain driver i/o-ts = input & output signal with tri-state driver i/o-od = input & output signal with open-drain driver ball no(s) symbol i/o description
data sheet MVTX2601Ag 81 zarlink semiconductor inc. 13.3 ball ? signal name ball no. signal name ball no. signal name ball no. signal name d20 la_d[63] d3 la_d[19] a9 la_oe0# b21 la_d[62] e3 la_d[18] b9 la_oe1# d19 la_d[61] d2 la_d[17] f4 reserved e19 la_d[60] e2 la_d[16] f5 reserved d18 la_d[59] a7 la_d[15] g4 reserved e18 la_d[58] b7 la_d[14] g5 reserved d17 la_d[57] a6 la_d[13] h4 reserved e17 la_d[56] b6 la_d[12] h5 reserved d16 la_d[55] c6 la_d[11] j4 reserved e16 la_d[54] a5 la_d[10] j5 reserved d15 la_d[53] b5 la_d[9] k4 reserved e15 la_d[52] c5 la_d[8] k5 reserved d14 la_d[51] a4 la_d[7] l4 reserved e14 la_d[50] b4 la_d[6] l5 reserved d13 la_d[49] c4 la_d[5] m4 reserved e13 la_d[48] a3 la_d[4] m5 reserved d21 la_d[47] b3 la_d[3] n4 reserved e21 la_d[46] c3 la_d[2] n5 reserved a18 la_d[45] b2 la_d[1] g3 reserved b18 la_d[44] c2 la_d[0] h1 reserved c18 la_d[43] c14 la_a[20] h2 reserved a17 la_d[42] a13 la_a[19] h3 reserved b17 la_d[41] b13 la_a[18] j1 reserved c17 la_d[40] c13 la_a[17] j2 reserved a16 la_d[39] a12 la_a[16] j3 reserved b16 la_d[38] b12 la_a[15] k1 reserved c16 la_d[37] c12 la_a[14] k2 reserved a15 la_d[36] a11 la_a[13] k3 reserved b15 la_d[35] b11 la_a[12] l1 reserved
MVTX2601Ag data sheet 82 zarlink semiconductor inc. c15 la_d[34] c11 la_a[11] l2 reserved a14 la_d[33] d11 la_a[10] l3 reserved b14 la_d[32] e11 la_a[9] m1 reserved d9 la_d[31] a10 la_a[8] m2 reserved e9 la_d[30] b10 la_a[7] m3 reserved d8 la_d[29] d10 la_a[6] u4 reserved e8 la_d[28] e10 la_a[5] u5 reserved d7 la_d[27] a8 la_a[4] v4 reserved e7 la_d[26] c7 la_a[3] v5 reserved d6 la_d[25] b8 la_dsc# w4 reserved e6 la_d[24] c1 la_clk w5 reserved d5 la_d[23] c9 la_we# y4 reserved e5 la_d[22] d12 la_we0# y5 reserved d4 la_d[21] e12 la_we1# aa4 reserved e4 la_d[20] c8 la_oe# aa5 reserved ab4 reserved u2 reserved ah7 m[4]_rxd[0] ab5 reserved r28 mdc ae6 m[3]_rxd[0] ac4 reserved p28 mdio ah5 m[2]_rxd[0] ac5 reserved r29 m_clk ah2 m[1]_rxd[0] ad4 reserved ac29 m[23]_rxd[1] af2 m[0]_rxd[0] ad5 reserved ae28 m[22]_rxd[1] ac27 m[23]_crs_dv w1 reserved aj27 m[21]_rxd[1] af29 m[22]_crs_dv y1 reserved af27 m[20]_rxd[1] ag27 m[21]_crs_dv y2 reserved aj25 m[19]_rxd[1] af26 m[20]_crs_dv y3 reserved af24 m[18]_rxd[1] ag25 m[19]_crs_dv aa1 reserved ah23 m[17]_rxd[1] ag23 m[18]_crs_dv aa2 reserved ae19 m[16]_rxd[1] af23 m[17]_crs_dv aa3 reserved af21 m[15]_rxd[1] ag21 m[16]_crs_dv ab1 reserved aj19 m[14]_rxd[1] ah21 m[15]_crs_dv ab2 reserved af18 m[13]_rxd[1] af19 m[14]_crs_dv ab3 reserved aj17 m[12]_rxd[1] af17 m[13]_crs_dv ball no. signal name ball no. signal name ball no. signal name
data sheet MVTX2601Ag 83 zarlink semiconductor inc. ac1 reserved aj15 m[11]_rxd[1] ag17 m[12]_crs_dv ac2 reserved af15 m[10]_rxd[1] ag15 m[11]_crs_dv ac3 reserved aj13 m[9]_rxd[1] af14 m[10]_crs_dv ad1 reserved af12 m[8]_rxd[1] ag13 m[9]_crs_dv ad2 reserved aj11 m[7]_rxd[1] af11 m[8]_crs_dv ad3 reserved aj9 m[6]_rxd[1] ag11 m[7]_crs_dv n3 reserved af9 m[5]_rxd[1] ag9 m[6]_crs_dv n2 reserved aj7 m[4]_rxd[1] af8 m[5]_crs_dv n1 reserved af6 m[3]_rxd[1] ag7 m[4]_crs_dv p3 reserved aj5 m[2]_rxd[1] af5 m[3]_crs_dv p2 reserved aj3 m[1]_rxd[1] ag5 m[2]_crs_dv p1 reserved af1 m[0]_rxd[1] ah3 m[1]_crs_dv r5 reserved ac28 m[23]_rxd[0] af3 m[0]_crs_dv r4 reserved af28 m[22]_rxd[0] ad29 m[23]_txen r3 reserved ah27 m[21]_rxd[0] ag28 m[22]_txen r2 reserved ae27 m[20]_rxd[0] aj26 m[21]_txen r1 reserved ah25 m[19]_rxd[0] ae26 m[20]_txen t5 reserved ae24 m[18]_rxd[0] aj24 m[19]_txen t4 reserved af22 m[17]_rxd[0] ae23 m[18]_txen t3 reserved af20 m[16]_rxd[0] aj22 m[17]_txen t2 reserved ae21 m[15]_rxd[0] aj20 m[16]_txen t1 reserved ah19 m[14]_rxd[0] ae20 m[15]_txen w3 reserved ah20 m[13]_rxd[0] aj18 m[14]_txen w2 reserved ah17 m[12]_rxd[0] aj21 m[13]_txen v1 reserved ah15 m[11]_rxd[0] aj16 m[12]_txen g1 reserved ae15 m[10]_rxd[0] aj14 m[11]_txen v3 reserved ah13 m[9]_rxd[0] ae14 m[10]_txen p4 reserved ae12 m[8]_rxd[0] aj12 m[9]_txen p5 reserved ah11 m[7]_rxd[0] ae11 m[8]_txen v2 reserved ah9 m[6]_rxd[0] aj10 m[7]_txen u1 reserved ae9 m[5]_rxd[0] aj8 m[6]_txen ball no. signal name ball no. signal name ball no. signal name
MVTX2601Ag data sheet 84 zarlink semiconductor inc. ae8 m[5]_txen ah8 m[6]_txd[0] g27 reserved aj6 m[4]_txen af7 m[5]_txd[0] h29 reserved ae5 m[3]_txen ah6 m[4]_txd[0] h28 reserved aj4 m[2]_txen af4 m[3]_txd[0] h27 reserved ag1 m[1]_txen ah4 m[2]_txd[0] j29 reserved ae1 m[0]_txen ag2 m[1]_txd[0] j28 reserved ad27 m[23]_txd[1] ae2 m[0]_txd[0] j27 reserved ah28 m[22]_txd[1] u26 reserved k29 reserved ag26 m[21]_txd[1] u25 reserved k28 reserved ae25 m[20]_txd[1] v26 reserved k27 reserved ag24 m[19]_txd[1] v25 reserved l29 reserved ae22 m[18]_txd[1] w26 reserved l28 reserved aj23 m[17]_txd[1] w25 reserved l27 reserved ag20 m[16]_txd[1] y27 reserved m29 reserved ae18 m[15]_txd[1] y26 reserved m28 reserved ag18 m[14]_txd[1] aa26 reserved m27 reserved ae16 m[13]_txd[1] aa25 reserved g26 reserved ag16 m[12]_txd[1] ab26 reserved g25 reserved ag14 m[11]_txd[1] ab25 reserved h26 reserved ae13 m[10]_txd[1] ac26 reserved h25 reserved ag12 m[9]_txd[1] ac25 reserved j26 reserved ae10 m[8]_txd[1] ad26 reserved j25 reserved ag10 m[7]_txd[1] ad25 reserved k25 reserved ag8 m[6]_txd[1] u27 reserved k26 reserved ae7 m[5]_txd[1] v29 reserved m25 reserved ag6 m[4]_txd[1] v28 reserved l26 reserved ae4 m[3]_txd[1] v27 reserved m26 reserved ag4 m[2]_txd[1] w29 reserved l25 reserved ag3 m[1]_txd[1] w28 reserved n26 reserved ae3 m[0]_txd[1] w27 reserved n25 reserved ad28 m[23]_txd[0] y29 reserved p26 reserved ball no. signal name ball no. signal name ball no. signal name
data sheet MVTX2601Ag 85 zarlink semiconductor inc. ag29 m[22]_txd[0] y28 reserved p25 reserved ah26 m[21]_txd[0] y25 reserved f28 reserved af25 m[20]_txd[0] aa29 reserved g28 reserved ah24 m[19]_txd[0] aa28 reserved e25 reserved ag22 m[18]_txd[0] aa27 reserved g29 reserved ah22 m[17]_txd[0] ab29 reserved f29 reserved ae17 m[16]_txd[0] ab28 reserved f26 reserved ag19 m[15]_txd[0] ab27 reserved e26 reserved ah18 m[14]_txd[0] r26 reserved f25 reserved af16 m[13]_txd[0] t25 reserved e24 bist_done/tstout[15] ah16 m[12]_txd[0] t26 reserved d24 bist_in_prc/tst0ut[14] ah14 m[11]_txd[0] t28 reserved d25 mct_err/tstout[13] af13 m[10]_txd[0] u28 reserved d26 fcb_err/tstout[12] ah12 m[9]_txd[0] r25 reserved c26 checksum_ok/tstout[ 11] af10 m[8]_txd[0] u29 reserved d27 init_start/tstout[10] ah10 m[7]_txd[0] t29 reserved c27 init_done/tstout[9] b27 tstout[8] u18 vss n12 vss a27 tstout[7] v12 vss n13 vss e28 tstout[6] v13 vss k17 vdd d28 tstout[5] v14 vss k18 vdd c28 tstout[4] v15 vss m10 vdd b28 tstout[3] v16 vss n10 vdd e29 led_bit/tstout[2] v17 vss m20 vdd d29 led_syn/tstout[1] v18 vss n20 vdd c29 led_clk/tstout[0] n14 vss u10 vdd n29 reserved n15 vss v10 vdd p29 reserved n16 vss u20 vdd f3 scan_en n17 vss v20 vdd e1 sclk n18 vss y12 vdd u3 t_mode0 p12 vss y13 vdd ball no. signal name ball no. signal name ball no. signal name
MVTX2601Ag data sheet 86 zarlink semiconductor inc. c10 t_mode1 p13 vss y17 vdd b24 reserved p14 vss y18 vdd a21 trunk1 p15 vss k12 vdd c22 trunk0 p16 vss k13 vdd a26 strobe c19 reserved m16 vss b26 d0 b19 reserved m17 vss c25 autofd a19 reserved m18 vss a24 scl r13 vss f16 vdd33 a25 sda r14 vss f17 vdd33 f1 avcc r15 vss n6 vdd33 d1 agnd r16 vss p6 vdd33 d22 scancol r17 vss r6 vdd33 e23 scanlink r18 vss t6 vdd33 e27 scanmode t12 vss u6 vdd33 n28 t13 vss n24 vdd33 n27 t14 vss p24 vdd33 f2 resin# t15 vss r24 vdd33 g2 resetout_ t16 vss t24 vdd33 b22 reserved t17 vss u24 vdd33 a22 reserved t18 vss ad13 vdd33 c23 reserved u12 vss ad14 vdd33 b23 reserved u13 vss ad15 vdd33 a23 reserved u14 vss ad16 vdd33 c24 reserved u15 vss ad17 vdd33 d23 scanclk u16 vss f13 vdd33 t27 reserved u17 vss f14 vdd33 f27 reserved m12 vss f15 vdd33 c20 reserved m13 vss b20 reserved m14 vss a20 reserved m15 vss c21 reserved p17 vss ball no. signal name ball no. signal name ball no. signal name
data sheet MVTX2601Ag 87 zarlink semiconductor inc. 13.4 ac/dc timing 13.4.1 absolute maximum ratings storage temperature-65 c to +150 c operating temperature-40 c to +85 c supply voltage vdd33 with respect to vss+3.0 v to +3.6 v supply voltage vdd with respect to vss +2.38 v to +2.75 v voltage on input pins-0.5 v to (vdd33 + 3.3 v) caution: stress above those listed may damage the device. exposure to the absolute maximum ratings for extended periods may affect device reliability. functionality at or above these limits is not implied. 13.4.2 dc electrical characteristics vdd33 = 3.0 v to 3.6 v (3.3v +/- 10%)t ambient = -40 c to +85 c vdd = 2.5v +10% - 5% e20 reserved p18 vss b25 reserved r12 vss ball no. signal name ball no. signal name ball no. signal name
MVTX2601Ag data sheet 88 zarlink semiconductor inc. 13.4.3 recommended operation conditions symbol parameter description preliminary unit min typ max f osc frequency of operation 100 mhz i dd1 supply current ? @ 100 mhz (vdd33=3.3 v) 450 ma i dd2 supply current ? @ 100 mhz (vdd=2.5 v) 1500 ma v oh output high voltage (cmos) vdd33 - 0.5 v v ol output low voltage (cmos) 0.5 v v ih-ttl input high voltage (ttl 5v tolerant) vdd33 x 70% vdd33 + 2.0 v v il-ttl input low voltage (ttl 5v tolerant) vdd33 x 30% v i ih-5vt input leakage current (0.1 v < v in < vdd33)(all pins except those with internal pull-up/pull-down resistors) 10 a c in input capacitance 5 pf c out output capacitance 5 pf c i/o i/o capacitance 7 pf ja thermal resistance with 0 air flow 11.2 c/w ja thermal resistance with 1 m/s air flow 10.2 c/w ja thermal resistance with 2m/s air flow 8.9 c/w
data sheet MVTX2601Ag 89 zarlink semiconductor inc. 13.5 local frame buffer sbram memory interface 13.5.1 local sbram memory interface: figure 15 - local memory interface ? input setup and hold timing figure 16 - local memory interface - output valid delay timing ac characteristics ? local frame buffer sbram memory interface symbol parameter -100mhz note: min (ns) max (ns) l1 la_d[63:0] input set-up time 4 l2 la_d[63:0] input hold time 1.5 l3 la_d[63:0] output valid delay 1.5 7 c l = 25pf l4 la_a[20:3] output valid delay 2 7 c l = 30pf l6 la_adsc# output valid delay 1 7 c l = 30pf la_clk la_d[63:0] l1 l2 l3-max l3-min la_d[63:0] la_clk l4-max l4-min la_a[20:3] l6-max l6-min la_adsc#] l3-max l3-min la_we[1:0]# l3-max l3-min la_oe[1:0]# l3-max l3-min la_we# l3-max l3-min la_oe# ####
MVTX2601Ag data sheet 90 zarlink semiconductor inc. figure 17 - ac characteristics ? reduced media independent interface figure 18 - ac characteristics ? reduced media independent interface 13.6 ac characteristics 13.6.1 reduced media independent interface l7 la_we[1:0]#output valid delay 1 7 c l = 25pf l8 la_oe[1:0]# output valid delay -1 1 c l = 25pf l9 la_we# output valid delay 1 7 c l = 25pf l10 la_oe# output valid delay 1 5 c l = 25pf symbol parameter -50mhz note: min (ns) max (ns) m2 m[23:0]_rxd[1:0] input setup time 4 m3 m[23:0]_rxd[1:0] input hold time 1 m4 m[23:0]_crs_dv input setup time 4 m5 m[23:0]_crs_dv input hold time 1 m6 m[23:0]_txen output delay time 2 11 c l = 20 pf m7 m[23:0]_txd[1:0] output delay time 2 11 c l = 20 pf table 10 - ac characteristics ? reduced media independent interface ac characteristics ? local frame buffer sbram memory interface m_clki m[23:0]_txen m[23:0]_txd[1:0] m6-max m6-min m7-max m7-min m_clki m[23:0]_rxd m[23:0]_crs_dv m2 m4 m3 m5
data sheet MVTX2601Ag 91 zarlink semiconductor inc. 13.6.2 led interface figure 19 - ac characteristics ? led interface 13.6.3 scanlink scancol output delay timing figure 20 - scanlink scancol output delay timing figure 21 - scanlink, scancol setup timing symbol parameter variable freq. note: min (ns) max (ns) le5 led_syn output valid delay -1 7 c l = 30pf le6 led_bit output valid delay -1 7 c l = 30pf table 10 - ac characteristics ? led interface led_clk led_syn led_bit le5-max le5-min le6-max le6-min scanclk scanlink scancol c5-max c5-min c7-max c7-min scanclk scanlink scancol c1 c3 c2 c4
MVTX2601Ag data sheet 92 zarlink semiconductor inc. 13.6.4 mdio input setup and hold timing figure 22 - mdio input setup and hold timing figure 23 - mdio output delay timing symbol parameter -25mhz note: min (ns) max (ns) c1 scanlink input set-up time 20 c2 scanlink input hold time 2 c3 scancol input setup time 20 c4 scancol input hold time 1 c5 scanlink output valid delay 0 10 c l = 30pf c7 scancol output valid delay 0 10 c l = 30pf table 10 - scanlink, scancol timing 1mhz symbol parameter min (ns) max (ns) note: d1 mdio input setup time 10 d2 mdio input hold time 2 d3 mdio output delay time 1 20 c l = 50pf table 10 - mdio timing mdc mdio d1 d3 mdc mdio d3-max d3-min
data sheet MVTX2601Ag 93 zarlink semiconductor inc. 13.6.5 i 2 c input setup timing figure 24 - i 2 c input setup timing figure 25 - i 2 c output delay timing 50khz symbol parameter min (ns) max (ns) note: s1 sda input setup time 20 s2 sda input hold time 1 s3* sda output delay time 4 usec 6 usec c l = 30pf * open drain output. low to high transistor is controlled by external pullup resistor. table 10 - i 2 c timing scl sda s1 s2 scl sda s3-max s3-min
MVTX2601Ag data sheet 94 zarlink semiconductor inc. 13.6.6 serial interface setup timing figure 26 - serial interface setup timing figure 27 - serial interface output delay timing symbol parameter note: min (ns) max (ns) d1 d0 setup time 20 d2 d0 hold time 3 s d3 autofd output delay time 1 50 c l = 100pf d4 strobe low time 5 s d5 strobe high time 5 s table 10 - serial interface timing d4 d5 d2 d1 d2 d1 strobe d0 autofd d3-max d3-min strobe
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