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1 idt7381 16-bit cascadable alu commercial temperature range april 2001 2001 integrated device technology, inc. dsc-2525/- c idt7381 commercial temperature range 16-bit cmos cascadable alu functional block diagram description: the idt7381 is a high-speed cascadable arithmetic logic unit (alu). these three-bus devices have two input registers, an ultra-fast 16-bit alu and 16-bit output register. with idts high-performance cmos technology, the idt7381 can do arithmetic or logic operations in 25ns. the idt7381 functionally replaces four 54/74s381 four-bit alus in a 68-pin package. the two input operands, a and b, can be clocked or fed through for flexible pipelining. the f output can also be set into clocked or flow-through mode. an output enable is provided for three-state control of the output port on a bus. the idt7381 has three function pins to select 1 of 8 arithmetic or logic operations. the two r and s selection pins determine whether a, b, f or 0 are fed into the alu. this alu has carry-out, propagate and generate outputs for cascading using carry look-ahead. a 0 - 1 5 b 0 - 1 5 16 a reg b reg a mux b mux r mux s mux f reg f mux power supply clk enb ftab ftf gnd v cc 16 2 3 16 rs 0 - 1 i 0 - 2 ena enf p g oe c 16 ovf z f 0 - 15 c 0 16-bit alu 0000h 0000h features: - high-performance 16-bit arithmetic logic unit (alu) - 25ns to 55ns clocked alu operations - ideal for radar, sonar or image processing applications - 74s381 instruction set (8 functions) - replaces gould s614381 or logic devices l4c381 - cascadable with or without carry look-ahead - pipeline or flow-through modes - internal feedback path for accumulation - three-state outputs - ttl-compatible - produced with advanced submicron cmos technology - available in plcc - speeds available: l/25/30/40/55
2 commercial temperature range idt7381 16-bit cascadable alu pin configuration 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 98765432 16867666564636261 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ena enb ftab rs 1 rs 0 i 2 i 1 i 0 c 0 a 9 a 10 a 11 a 12 a 13 a 14 a 15 clk v cc gnd c 16 p g z ovf enf ftf a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 b 1 5 b 1 4 b 1 3 b 1 2 b 1 1 b 1 0 b 9 b 8 j68 - 1 oe f 15 f 14 f 13 f 12 f 11 f 10 f 9 f 8 f 7 f 6 f 5 f 4 f 3 f 2 f 1 f 0 pin 1 designator plcc top view
3 idt7381 16-bit cascadable alu commercial temperature range pin description pin name i/o description a 0 - a 15 i sixteenCbit data input port. b 0 - b 15 i sixteenCbit data input port. ena i register enable for the a input port; active low pin. enb i register enable for the b input port; active low pin. ftab i flowCthrough control pin. when this pin is high, both register a and b are transparent. f 0 C f 15 o sixteenCbit data output port. enf i register enable for the f output port; active low pin. ftf i flowCthrough control pin. when this pin is high, the f register is transparent. clk i clock input. oe i output enable control pin. when this pin is high, the output port f is in a high impedance state. when low, the output port f is active. c 0 i carry input. this pin receives arithmetic carries from less significant alu components in a cascade configuration. c 16 o carry output. this pin produces arithmetic carries to more significant alu components in a cascaded configuration. ovf o this pin indicates a twos complement arithmetic overflow, when high. z o this pin indicates a zero output result, when high. rs 0 C rs 1 i two control pins used to select input operands for the r and s multiplexers. i 0 - i 2 i three control pins to select the alu function performed. p o indicates the carry propagate output state to the alu. g o indicates the carry generate output state to the alu. v cc power supply pin, 5v. gnd ground pin, 0v. r and s mux table rs 1 rs 0 r mux s mux 00af 01a0 100b 11ab alu function table i 2 i 1 i 0 function 0 0 0 f = 0 0 0 1 f = r + s + c 0 0 1 0 f = r + s + c 0 0 1 1 f = r + s + c 0 1 0 0 f = r xor s 1 0 1 f = r or s 1 1 0 f = r and s 1 1 1 f = all 1s
4 commercial temperature range idt7381 16-bit cascadable alu absolute maximum ratings (1) symbol description max. unit v term terminal voltage with C0.5 to v respect to ground v cc + 0.5 v cc power supply voltage C0.5 to +7.0 v t stg storage temperature C55 to +125 c i out dc output current 50 ma note: 1. stresses greater than those listed under absolute maximum rat- ings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. under no circumstances should an input of an i/o pin be greater than v cc + 0.5v. capacitance (t a = +25c, f = 1.0mhz) symbol parameter (1) conditions pkg. typ. unit c in input capacitance v in = 0v pga 10 pf plcc 5 c out output capacitance v out = 0v pga 12 pf plcc 7 note: 1. this parameter is sampled at initial characterization and is not production tested. dc electrical characteristics commercial: t a = 0c to +70c, v cc = 5.0v 5% symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level guaranteed logic high level 2 v v il input low level guaranteed logic low level 0.8 v i ih input high current v cc = max., v in = 2.7v 10 a i il input low current v cc = max., v in = 0.5v C10 a i os (3) short circuit current v cc = max., v out = gnd C20 C100 ma i oz off state (high impedance) v cc = max. v o = 0.5v C0.1 C20 a output current v o = 2.7v C0.1 20 v oh output high voltage v cc = min. i oh = C4ma 2.4 v v in = v ih or v il v ol output low voltage v cc = min. i ol = 8ma 0.5 v v in = v ih or v il notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient and maximum loading. 3. not more than one output should be shorted at one time. duration of the short circuit test should not exceed one second.
5 idt7381 16-bit cascadable alu commercial temperature range power supply characteristics commercial: t a = 0c to +70c, v cc = 5.0v 5% symbol parameter test conditions (1) min. typ. (2) max. unit i cc quiescent power supply current v cc = max. 2 6 ma v in =gnd or v cc d i cc (3) quiescent power supply current v cc = max. 0.5 1 ma/ ttl input high v in = 3.4v input i ccd (4) dynamic power supply current v cc = max. 15 48 a/ outputs disabled mhz v in = gnd or v cc mode: ftab = ftf = 1 i ccd1 dynamic power supply current v cc = max. 20 33 ma outputs disabled all data inputs disabled f i = 10mhz, f cp = 10mhz 50% duty cycle v il = gnd, v ih = v cc mode: ftab = ftf = 1 i ccd2 (6) dynamic power supply current v cc = max. 40 60 ma outputs enabled. (cl = 50pf) all data inputs sw itching f i = 10mhz, f cp = 10mhz 50% duty cycle v il = gnd, v ih = v cc mode: ftab = ftf = 1 i c (7) total power supply current v cc = max. outputs disabled 22 39 ma v in = gnd or v cc all data inputs switching f i = 10mhz, f cp = 10mhz outputs enabled 42 76 ma 50% duty cycle notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. per ttl driven input (v in = 3.4v); all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived from i ccd1 for use in total power supply calculations. 5. total power supply current is calculated as follows: i c = i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f cp + f i n i ) i cc = quiescent current d i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an output transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) f i = input frequency n i = number of inputs at f i all currents are in milliamps and all frequencies are in megahertz. 6. this parameter is not production tested but is an indicator of the power dissipated with outputs loaded. 7. values for these conditions are examples of the i c formula in note 5 above. these are guaranteed but not tested.
6 commercial temperature range idt7381 16-bit cascadable alu ac electrical characteristics (v cc = 5v 5%, t a = 0c to +70c) notes: 1. only for ftf = 0. 2. minimum propagation delays are not production tested but guaranteed to be greater than or equal to 3ns. maximum combinational propagation delays idt7381l25 idt7381l30 from input f 0C15 p, g, n z,ovf c 16 f 0C15 p, g, n z,ovf c 16 unit ftab = 0, ftf = 0 clk 1322262220283028 ns c 0 16 16 20 20 ns i 0C2 , rs 0 , rs 1 22 22 22 28 28 28 ns ftab = 0, ftf = 1 clk 2722262233283028 ns c 0 22 16 16 28 20 20 ns i 0C2 , rs 0 , rs 1 22 22 22 22 28 28 28 28 ns ftab = 1, ftf = 0 a 0 Ca 15 , b 0 Cb 15 18 25 22 24 30 28 ns clk 1319 ns c 0 16 16 20 20 ns i 0C2 , rs 0 , rs 1 22 22 22 28 28 28 ns ftab = 1, ftf = 1 a 0 Ca 15 , b 0 Cb 15 26 18 25 22 32 24 30 28 ns c 0 22 16 16 28 20 20 ns i 0C2 , rs 0 , rs 1 22 22 22 22 28 28 28 28 ns maximum combinational propagation delays idt7381l40 idt7381l55 from input f 0C15 p, g, n z,ovf c 16 f 0C15 p, g, n z,ovf c 16 unit ftab = 0, ftf = 0 clk 2630443232385336 ns c 0 28 20 34 22 ns i 0C2 , rs 0 , rs 1 32 34 35 42 42 42 ns ftab = 0, ftf = 1 clk 4630443256385336 ns c 0 30 28 20 37 34 22 ns i 0C2 , rs 0 , rs 1 40 32 34 35 55 42 42 42 ns ftab = 1, ftf = 0 a 0 Ca 15 , b 0 Cb 15 30 40 32 36 46 37 ns clk 2632 ns c 0 28 20 34 22 ns i 0C2 , rs 0 , rs 1 32 34 35 42 42 42 ns ftab = 1, ftf = 1 a 0 Ca 15 , b 0 Cb 15 40 30 40 32 55 36 46 37 ns c 0 30 28 20 37 34 22 ns i 0C2 , rs 0 , rs 1 40 32 34 35 55 42 42 42 ns
7 idt7381 16-bit cascadable alu commercial temperature range ac electrical characteristics (v cc = 5v 5%, t a = 0c to +70c) - (cont'd.) notes: 1. only for ftf = 0. 2. minimum propagation delays are not production tested but guaranteed to be greater than or equal to 3ns. minimum set-up and hold times relative to clock (clk) idt7381l25 idt7381l30 idt7381l40 idt7381l55 input set-up hold set-up hold set-up hold set-up hold unit ftab = 0, ftf = x a 0 Ca 15 , b 0 Cb 15 60606080 ns c 0 (1) 16 0 16 0 16 0 21 0 ns i 0C2 , rs 0 , rs 1 (1) 24 0 29 0 32 0 44 0 ns ena , enb , enf 60606080 ns ftab = 1, ftf = 0 a 0 Ca 15 , b 0 Cb 15 16 0 25 0 28 0 35 0 ns c 0 16 0 16 0 16 0 21 0 ns i 0C2 , rs 0 , rs 1 24 0 29 0 32 0 44 0 ns enf 60606080 ns minimum clock cycle times and pulse widths parameter idt7381l25 idt7381l30 idt7381l40 idt7381l55 unit clock low time 6 8 10 14 ns clock high time 6 8 10 14 ns clock period 20 25 34 43 ns maximum output enable/disable times parameter idt7381l25 idt7381l30 idt7381l40 idt7381l55 unit enable time 10 15 18 20 ns disable time 10 15 18 20 ns
8 commercial temperature range idt7381 16-bit cascadable alu waveforms for ftab = 0, ftf = x prop. 1 prop. 1 prop. 1 prop. 1 prop. 2 prop. 2 prop. 2 prop. 2 prop. 3 prop. 3 prop. 3 prop. 1 enable enable disable disable result result result result result hold set-up hold set-up hold set-up hold set-up clk a 0- 15 b 0- 15 c 0 i 0- 2 , ena, enb enf oe f 0- 15 (ftf = 0) f 0- 15 (ftf = 1) prop. 1: propagation delay with respect to the clk. prop. 2: propagation delay with respect to i 0- 2 , rs 0- 2. prop. 3: propagation delay with respect to c0. data 2 data 3 t1 t2 data 3 data 2 data 3 data 2 data 2 data 3 data 1 data 1 data 1 data 1 rs 0- 1 p , g z, ovf c 16
9 idt7381 16-bit cascadable alu commercial temperature range waveforms for ftab = 1, ftf = x prop. 4 (for ftf = 1 only) prop. 4 (for ftf = 1 only) prop. 2 prop. 2 prop. 2 prop. 2 prop. 3 prop. 3 prop. 3 prop. 1 enable enable disable disable result result result result result hold set-up hold set-up hold set-up hold set-up prop. 4 data 2 data 3 t1 t2 data 3 data 2 data 3 data 2 data 2 data 3 data 1 data 1 data 1 data 1 prop. 4 (for ftf = 1 only) prop. 1: propagation delay with respect to the clk. prop. 2: propagation delay with respect to i 0- 2 , rs 0- 2. prop. 3: propagation delay with respect to c0. prop. 4: propagation delay with respect to a, b. clk (ftf = 0) a 0- 15 b 0- 15 c 0 i 0- 2 , enf oe f 0- 15 (ftf = 0) f 0- 15 (ftf = 1) rs 0- 1 p , g z, ovf c 16
10 commercial temperature range idt7381 16-bit cascadable alu propagation delay calculations for two idt7381s note: 1. flags are p , g , ovf, z and c 16 . to output to set put time from input f 0 C 15 flags (1) relative to clock (clk) ftab = 0, ftf = 0 clk as in 16-bit case (clk ? c 16 ) + (c 0 ? flag) . . . . c 0 . . . . (c 0 ? c16) + (c 0 ? flag) (c 0 ? c 16 ) + (c 0 setCup time) i 0 C 2 , rs 0 C 1 . . . . (i 0C2, rs 0C1 ? c 16 ) + (c 0 ? flag) (i 0C2 , rs 0C1 ? c 16 ) + (c 0 setCup time) a 0 C 15 , b 0 C 15 . . . . . . . . as in 16-bit case ena, enb,enf . . . . . . . . as in 16-bit case ftab = 0, ftf = 1 clk (clk ? c 16 ) + (c 0 ? f 0C15 )(clk ? c 16 ) + (c 0 ? flag) . . . . c 0 (c 0 ? c 16 ) + (c 0 ? f 0C15 )(c 0 ? c 16 ) + (c 0 ? flag) (c 0 ? c 16 ) + (c 0 setCup time) i 0 C 2 , rs 0 C 1 (i 0C2 , rs 0C1 ? c 16 ) + (c 0 ? f 0C15 )(i 0C2 , rs 0C1 ? c 16 ) + (c 0 ? flag) (i 0C2 , rs 0C1 ? c 16 ) + (c 0 setCup time) a 0 C 15 , b 0 C 15 . . . . . . . . as in 16-bit case ena, enb,enf . . . . . . . . as in 16-bit case ftab = 1, ftf = 0 clk as in 16-bit case . . . . . . . . c 0 . . . . (c 0 ? c 16 ) + (c 0 ? flag) (c 0 ? c 16 ) + (c 0 setCup time) i 0 C 2 , rs 0 C 1 . . . . (i 0C2 , rs 0C1 ? c 16 ) + (c 0 ? flag) (i 0C2 , rs 0C1 ? c 16 ) + (c 0 setCup time) a 0 C 15 , b 0 C 15 . . . . (a 0C15 , b 0C15 ? c 16 ) + (c 0 ? flag) as in 16-bit case ena, enb,enf . . . . . . . . as in 16-bit case ftab = 0, ftf = 1 clk don't care condition don't care condition . . . . c 0 (c 0 ? c 16 ) + (c 0 ? f 0C15 )(c 0 ? c 16 ) + (c 0 ? flag) . . . . i 0 C 2 , rs 0 C 1 (i 0C2 , rs 0C1 ? c 16 ) + (c 0 ? f 0C15 )(i 0C2 , rs 0C1 ? c 16 ) + (c 0 ? flag) . . . . a 0 C 15 , b 0 C 15 (a 0C15 , b 0C15 ? c 16 ) + (c 0 ? f 0C15 )(a 0C15 , b 0C15 ? c 16 ) + (c 0 ? flag) . . . . ena, enb,enf . . . . . . . . . . . .
11 idt7381 16-bit cascadable alu commercial temperature range cascading the idt7381 some applications require 32-bit or wider input operands. cascading is the hardware solution. it provides a high speed alternative in handling more than 16-bit wide operands. 1. cascading the idt7381 cascading to 32-bit wide operands takes only two idt7381s and no external hardware. however, cascading to data widths greater than 32- bit can be done in two ways: without external hardware (slow method) or by using a carry look ahead generator. a) cascading the idt7381 without a carry-look-ahead generator: (figures 1 and 2) 1. connect the c 16 output of the least significant device into the c 0 input of the next most significant device. 2. common lines to all devices are: rs 0C1 , i 0C2 , clk, ftf, ftab, ena , enb , enf . 3. take ovf, c 16 , p , g of the most significant device as valid. 4. the systems zero flag (z) is obtained by anding all zero flag results. b) cascading three or more idt7381s with carry-look-ahead (cla) generator: (figure 3) 1. connect the p and g outputs of each device to the cla generators corresponding inputs. 2. take the cla generator outputs into the c 0 inputs of each device (except for the least significant one). 3. common lines to all devices are: rs 0C1 , i 0C2 , clk, ftf, ftab, ena , enb , enf . 4. take ovf, c 16 , p , g of the most significant device as valid. 5. carry-in to the system should be connected to the c 0 input of the least significant device and also to the cla generator. 2. time delay considerations once cascading has taken place, time delays may become critical in high performance systems. our main interest here is focused on propagation delays, i.e. calculating the time required for an input signal to propagate through several cascaded devices up to a specific output in another device within the cascaded system. propagation delay the propagation delay for two devices between the input and output of interest (input to output delay) is done as follows: 1. calculate delay between the input and c 16 in the first device. 2. calculate delay between c 0 and the output in the second device. 3. add both results. the following table is an example on how to build a propagation delay table for all inputs in a 32-bit idt7381 cascaded system. propagation delay calculations can be extended to nCcascaded devices as the sum of the delays in all devices between the input and output of interest. that is: (input) 1 ? (c16) 1 = t 1 ... (c 0 ) i ? (c 16 ) i = t i (c 0 ) i + 1 ? (c 16 ) i + 1 = t i + 1 ... (c 0 ) n ? (output) n = t n where the subscript i denotes the device number and the arrow ( ? ) represents the delay in between. notice that i + 1 is the immediate upper device from device i. adding the delays t i we get: propagation delay = t 1 + t 2 + ... + t i + t i + 1 + ... + t n total delay as seen from figure 8, the propagation delay is within the idt7381 devices only. a complete analysis should also include the delay associated with the transmission line li (which depends on the line length and its impedance). this line delay should then be added to the propagation delay to obtain the total delay for the cascaded system: total delay = propagation delay + transmission line delay
12 commercial temperature range idt7381 16-bit cascadable alu figure 1. cascading two idt7381s to 32 bits figure 3. cascading three idt7381s to 48 bits wide with a carry-lookahead generator figure 2. cascading three idt7381s to 48 bits wide without a carry-lookahead generator g p c 16 ovf z z z c 16 c 0 c 0 c in a 16 - 31 b 16 - 31 a 0 - 15 b 0 - 15 rs 0 - 1 clk, i 0 - 2 , ena, enb enf, ftf, ftab idt7381 idt7381 msd lsd 11 f 16 - 3 1 f 0 - 15 z c 16 c 0 a 0 - 15 b 0 - 15 idt7381 lsd f 0 - 15 cin clk, i 0 - 2 , ena, enb enf, ftf, ftab 11 p c 16 ovf z z c 0 a 32 - 47 b 32 - 47 idt7381 msd f 32 - 4 7 z c 16 c 0 a 16 - 31 b 16 - 31 idt7381 f 16 - 3 1 g rs 0 - 1 z c 0 a 0 - 15 b 0 - 15 idt7381 lsd f 0 - 15 cin clk, i 0 - 2 , ena, enb enf, ftf, ftab 11 p c 16 ovf z z c 0 a 32 - 47 b 32 - 47 idt7381 msd f 32 - 4 7 z c 0 a 16 - 31 b 16 - 31 idt7381 f 16 - 3 1 g rs 0 - 1 p g p g fct182/a lookahead generator cn g 0 g 1 p 0 p 1 cn+x cn+y
13 idt7381 16-bit cascadable alu commercial temperature range figure 4. 32-bit configuration for ftab = 0, ftf = 0 figure 5. 32-bit configuration for ftab = 0, ftf = 1 a 16 - 31 b 16 - 31 a mux r mux b mux s mux 16-bit alu c 0 msd f mux 16 16 16 f 16 - 3 1 clk a 0 - 15 b 0 - 15 a mux r mux b mux s mux 16-bit alu c 16 lsd f mux 16 16 16 f 0 - 15 b reg a reg b reg a reg f reg f reg a 16 - 31 b 16 - 31 a mux r mux b mux s mux 16-bit alu c 0 msd f mux 16 16 16 f 16 - 3 1 clk a 0 - 15 b 0 - 15 a mux r mux b mux s mux 16-bit alu c 16 lsd f mux 16 16 16 f 0 - 15 b reg a reg b reg a reg
14 commercial temperature range idt7381 16-bit cascadable alu figure 6. 32-bit configuration for ftab = 1, ftf = 0 figure 7. 32-bit configuration for ftab = 1, ftf = 1 a 16 - 31 b 16 - 31 a mux r mux b mux s mux 16-bit alu c 0 msd f reg f mux 16 16 16 f 16 - 3 1 clk a 0 - 15 b 0 - 15 a mux r mux b mux s mux 16-bit alu c 16 lsd f reg f mux 16 16 16 f 0 - 15 a 16 - 31 b 16 - 31 a mux r mux b mux s mux 16-bit alu c 0 msd f mux 16 16 16 f 16 - 3 1 a 0 - 15 b 0 - 15 a mux r mux b mux s mux 16-bit alu c 16 lsd f mux 16 16 16 f 0 - 15
15 idt7381 16-bit cascadable alu commercial temperature range figure 8. propagation delay = t1 + t2 + . . . + tn n-cascaded devices output input d 0 d 1 d n l 1 l 2 i n t n t 2 t 1 ac test conditions input rise levels gnd to 3v input rise/fall times 3ns input timing reference levels 1.5v output reference levels 1.5v output load figure 1
16 commercial temperature range idt7381 16-bit cascadable alu pulse generator r t d.u.t. v cc v in c l v out 50pf 500 w 500 w 7.0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h preset clear clock enable etc. high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable v oh test w a veforms propagation delay test circuits for all outputs enable and disable times set-up, hold, and release times pulse width notes: 1. diagram shown for input control enable-low and input control disable-high 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns switch position test switch open drain disable low closed enable low all other tests open definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator.
17 idt7381 16-bit cascadable alu commercial temperature range corporate headquarters for sales: 2975 stender way 800-345-7015 or 408-727-6116 santa clara, ca 95054 fax: 408-492-8674 www.idt.com* *to search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. the idt logo is a registered trademark of integrated device technology, inc. ordering information 25 30 40 55 idt xxxx device type xx speed x package j 7381l plastic leaded chip carrier (j68-1) speed grade 16-bit alu

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