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confidential VP77 vi deo decoder for por table lcd display (preliminary) version: 0.96 date : apr. 7, 2005 VP77 data sheet
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 2 1. features the VP77, is an one-chip video decoder with integrated scalar, osd function, tcon, and dac, which can drives small size 4, 5.6, 7-inch tft-lcd panel with analog interlace. for analog panels, VP77 can support the display resolutions of 1440x234, 1200x234, or 960x234. support inputs: - composite video (cvbs) input - s-video input - component video input - analog rgb input - digital ccir-656 input video decoder - supporting ntsc/pal/secam standard - 2d comb filter - 2d noise reduction - closed-caption/font-rendering - macro-vision copy protection - selectable ccir-656 output video scaling - horizontal scaling - vertical scaling - 4:3 to/from 16:9 conversion osd - the normal font size of 12x16 - 127-downloadable fonts and one space code - alpha blending, blinking - maximum display dimension is 16(row) by 31(column) - flexible memory partition to allocated normal character fonts (with 16 foreground colors and 8 background colors) and graphic character fonts (with 8 colors per dot) - programmable character height, width, row space, column space built-in rgb-to-yuv matrix for rgb input signal brightness, contrast, tint, and color adjustment auto-adjustment for phase, frequency, h/v position, and white balance programmable gamma correction h-peaking and cti hardware mode detection support rgb-yuv and yuv-rgb matrix conversion support free-run mode if the sync signal is missing programmable tcon three pwm?s dc-dc control signals on-chip triple video dac?s 128-pin lqfp package
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 3 2. block diagram adc cvbs s-video yc b c r rgb adc adc 2d-yc separation vbi & closed-ca p tion decoder n o i se reduction external osd tcon dac dac_r rac_g dac_b ccir-656 c_d[7:0] dc - dc dcpwm1/2/3 dcfbk1/2/3 nstc/pal/secam decoder video scalin g color adjustment cti/h-peaking gamma correction internal osd t con si g nals vou t i2s sda sc l VP77
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 4 3. pinning diagram fig.3.1 VP77 pinning diagram for 128-lead lqfp nc c_d0 vcca25_pll sogin vcca33_adc nc vssa_adc nc nc vss25 dhs VP77 35 vssa25_pll gmidbypass cb comp_y rin c filt c_vs c_d3 c_d4 c_fid vdd33 pwm3 pwm2 c_clk vss33 c_d5 c_d7 vout nc scl sda rstn vdd33 vss33 vcca33_adc y cvbs1 tpad vssap_adc vccdp33_adc vssdp_adc testa tests vss25 intn vss33 nc nc p_hme nc dac_rext vssa_dac1 vssa_dac3 vcca_dac3 vdd25 nc vdd33 pwm1 c_hs c_d2 c_d6 nc nc dvs nc nc nc nc nc nc vdd33 nc nc nc vss33 dac_b dac_g vssa_dac2 vcca_dac2 dac_r vssa_adc rmidbypass iicadrsel gin cvbs2 vdd25 dcpwm3 dcpwm2 dcpwm1 dcfbk3 dcfbk2 dcfbk1 vcca_dac1 dac_comp nc vdd25 c_d1 25 20 15 10 5 1 40 45 50 55 65 75 80 85 125 120 115 110 128lqfp 30 60 70 90 95 100 105 vcca33_adc cr bin bmidbypass refbypass vssa_adc p_pol p_lp p_stvd p_stvu p_clkv p_sthr p_sthl vdd25 xtal1 p_gp3 xtal2 p_gp2 p_gp1 vss25 nc nc nc nc cph2 cph3 cph1 vss25 vccap33_adc
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 5 4. pin assignment pin name pin type pin# description comp_y a 13 y of component video y a 14 luma of s-video input cvbs1 a 15 composite video input 1 rain a 16 red channel analog input rmidbypass a 18 r channel internal midscale voltage bypass (default to be ground) cb a 20 c b of component video c a 21 chroma of s-video input cvbs2 a 22 composite video input 2 gain a 23 green channel analog input gmidbypass a 26 g channel internal midscale voltage bypass (default to be ground) cr a 28 c r of component video bain a 29 blue channel analog input bmidbypass a 30 b channel internal midscale voltage bypass (default to be ground) sogin a 24 sync-on-green slicer input refbypass a 31 internal reference bypass filt a 34 external filter connection for pll dhs i(smt, pd) 127 vga input h sync dvs i(smt, pd) 126 vga input v sync vout a 12 buffered composite video output tpad a 35 te s t m o d e o u t p u t c_vs/ovr io(pd4) 44 vertical sync of video port / overlay color select r input of external osd c_hs/ovg io(pd4) 45 horizontal sync of video port / overlay color select g input of external osd c_fid/ovb io(pd4) 43 field id/ overlay color select b input of external osd c_clk/ovclk io(pd4) 46 clock for video port/ overlay clock of external osd c_d[7:4], c_d3/ovs, c_d2/ohs, c_d1/ovi, c_d0/ovfb io(pd4) 54~51, 50, 49, 48, 47 yuv data of video port bit 7~0/ yuv bit-3 alternative to overlay vsync of ext-osd/ yuv bit-2 alternative to overlay hsync of ext-osd/ yuv bit-1 alternative to overlay intensity of ext- osd/ yuv bit-0alternative to overlay fast blanking of ext-osd sda io(smt, pu4) 4 serial i/f data in/out scl io(smt, pu4) 3 serial i/f clock iicadrsel i(pd) 8 serial i/f sub-address setting testa i(pd) 39 te s t p i n a tests i(pd) 40 te s t p i n s xtal1 i 66 input external free-run clock of 20 mhz xtal2 o 65 output external free-run clock of 20 mhz rstn i(smt) 5 reset signal (active low) pwm1 o(pd4) 77 pwm output 1 pwm2 o(pd4) 78 pwm output 2
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 6 pwm3 o(pd4) 79 pwm output 3 dcpwm1 o(pd4) 80 dc-dc control pwm output 1 dcpwm2 o(pd4) 81 dc-dc control pwm output 2 dcpwm3 o(pd4) 82 dc-dc control pwm output 3 dcfbk1 a 83 dc-dc feedback input 1 dcfbk2 a 84 dc-dc feedback input 2 dcfbk3 a 85 dc-dc feedback input 3 intn o(pu8) 72 interrupt to host (active low) cph1 o(pd4) 97 clock phase 1 output for sourced river ic p_sthl o(pd4) 64 start pulse for source driver ic; active when scan from l to r, and tri-state when scan from r to l p_sthr o(pd4) 63 start pulse for source driver ic; active when scan from r to l, and tri-state when scan from l to r p_clkv o(pd4) 62 clock for gate driver ic p_stvu o(pd4) 61 start pulse for gate driver; active when scan from u to d, and tri-state when scan from d to u p_stvd o(pd4) 60 start pulse for gate driver; active when scan from d to u, and tri-state when scan from u to d p_lp/oeh o(pd4) 59 latch pulse for source driver ic p_pol/pfrp i(pd4) 58 polarity for source driver ic p_hme o(pd4) 57 data inversion control for source driver ic p_gp1/oev o(pd4) 69 tcon gpo1 p_gp2/q1h o(pd4) 68 tcon gpo2 p_gp3 o(pd4) 67 tcon gpo3 nc o(pd4) 1 no connection nc o(pd4) 2 no connection nc o(pd4) 128 no connection cph2 o(pd4) 99 clock phase 2 for source driver ic cph3 o(pd4) 98 clock phase 3 for source driver ic nc 105~100 no connection nc 115~108 no connection nc 125~118 no connection dac_r a 90 red channel dac output dac_g a 93 green channel dac output dac_b a 94 blue channel dac output dac_rext a 88 external resistor input for dac dac_comp a 89 compensation pin of dac vcca_dac1 p 86 dedicated analog vcc (3.3v) for dac vssa_dac1 p 87 dedicated analog ground for dac vcca_dac2 p 91 dedicated analog vcc (3.3v) for dac vssa_dac2 p 92 dedicated analog ground for dac vcca_dac3 p 95 dedicated analog vcc (3.3v) for dac vssa_dac3 p 96 dedicated analog ground for dac vcca25_pll p 73 analog vdd (2.5v) for pll clock generator vssa25_pll p 74 analog ground for pll clock generator vccdp33_adc p 37 adc/pll digital core (3.3v) vssdp_adc p 38 adc/pll digital core ground vccap33_adc p 33 adc/pll analog core (3.3v) vssap_adc p 36 adc/pll analog core ground vcca33_adc p 11,19,27 avdd (3.3v) for adc analog core
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 7 vssa_adc p 17,25,32 ground for adc analog core vdd33 p 6,55,76,117 vdd (3.3v) for io vss33 p 5,56,75,116 ground for io vdd25 p 9,42,71,107 vdd (2.5v) for digital core vss25 p 10,41,70,106 ground for digital core - smt: schmitt trigger in input - i: input - o: output - io: in/out - od: open-drain - pu: pull-up in input (not valid for chip external) - pd: pull-down in input (not valid for chip external) - pd4: pull-down with 4 ma driving capability in output - pu4: pull-up with 4 ma driving capability in output - pu8: pull-up with 8 ma driving capability in output - p: power - a: analog io
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 8 5. system description 5.1 2-wire serial bus interface this chip supports the industrial standard 2-wire serial bus interface, which consists of sda bi-directional data line and scl clock line. the 2-wire serial bus slave addresses(also known as device address) of this chip are described in the below table. the definition of the basic 2-wire serial bus interface protocol is illustrated as follows. for detailed timing and operation protocol, please refer to the standard 2-wire serial bus specification. VP77 has four slave serial-bus devices. the slave addresses table is shown as belows: device name iicadrsel slave address (hex) [6:0],0 0 40 video decoder (vdec) 1 48 0 42 adc 1 4a 0 f4 scalar system 1 fc 0 f6 tcon 1 fe 5.2 panel pll (ppll) setup VP77 has one pll for pclk generation. pclk is used for display panel clocking. the pll output frequency, ppll xosc adc _ llc adc _ datack pll_xi_sel[1:0] xi clk_ou t t o clock system m[7:0] n[6:0] k pd clk _ off t st
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 9 clk_out, is determined by the ratio set between the value set in the input divider and the feedback divider. pll output frequency clk_out is calculated from the following equations: clk_out = xi * (m/n) * [1/(1+k)] where: m = 2~255 (feedback divider value) n = 2~127 (input divider value) k = 0,1 (post divider for output clock) xi= 20mhz in default (2~50mhz can be valid), and the following conditions must be satisfied to have a qualified clk_out: 1. 1mhz ?? (xi/n) ?? 15mhz 2. 100mhz ?? [clk_out * (1+k)] ?? 450mhz ppll0 (ppll control register 0, bah) default 7:0 m feedback divider value 63h ppll1 (ppll control register 1, bbh) default 7 k post divider for output clock 1 6:0 n input divider value 11h ppll2 (ppll control register 2, beh) default 7~6 - reserved 00 5 tst ppll test mode 0 4 pll_prediv4 ppll pre-divide 4 0 3~2 pll_xi[1:0] 00: select xosc as ppll source clock 01: select adc?s datack as ppll source clock 10: select adc?s llc as ppll source clock 11: reserved 00 1 pll_div6 ppll output divide by 6 after ?pre-divide 4? 1 0 pll_div4 ppll output divide by 4 0 5.3 reset system a reset is accomplished by holding the rstn pin low (low active) for at least 1us while the crystal oscillator is running in xtal1 and xtal2. an automatic reset can be obtained by switching on vcc, if the rstn pin is connected to ground via a capacitor and to the vdd via a resistor. the vdd rise time must not exceed 10 ms and the capacitor should be at least 10 uf. the increase of the rstn pin voltage depends on the capacitor and the external resistor.
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 10 5.4 adc front end the 10bit ad converter is shown in fig.5.3. it employs three 10-bit adcs and a pll timing generator. the adc sampling clock can be derived from either an external source or incoming horizontal signal using internal, pll. output data are 30-bit rgb and 1-channel video_out. input amplitude range is 500~1000mv at rgb mode, 650~1300mv at video mode, and programmable through the 8-bit gain control. input offset voltage of each converter is programmable through the 7-bit offset control. fig. 5.4.1 adc block diagram 00h pll divider msb register bit access symbol description [7:0] r/w plldiv[11:4] this register is used for bits 11-4 of pll divider. the pll divider has total of 12 bits value ( default at 1693 ) . lar g er value means that the pll will o p erate at a hi g her rate. this re g ister should be loaded in the beginning before any change is needed. (plldiv[11:4] is default to 69h) 01h pll divider lsb register vinbuffer comp_y y cvbs1 rain gain/offset a/d converter ra[9:0] vinbuffer gain/offset a/d converter ga[9:0] vinbuffer gain/offset a/d converter ba[9:0] i2c sda scl a0 c b c cvbs2 gain c r bain vssa vssa vinselbr[7:4] vinselg[4:1] vinselbr[3:0] video_out dack ext_clk 1 0 sogin sogout pll
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 11 bit access symbol description [7:4] r/w plldiv[3:0] this register is used for bits 3-0 of pll divider. the pll divider has total of 12 bits value (default at 1693). (plldiv[3:0] is default to 0dh) [3:0] r/w reserved 02h red gain control register bit access symbol description [7:0] r/w rgain t his re g ister controls the red color adc in p ut ran g e ( i.e. contrast). smaller values give more contrast. (deafult to 80h) 03h green gain control register bit access symbol description [7:0] r/w ggain t his re g ister controls the green color adc in p ut ran g e ( i.e. contrast). smaller values give more contrast. (deafult to 80h) 04h blue gain control register bit access symbol description [7:0] r/w bgain this register controls the blue color adc in p ut ran g e ( i.e. contrast). smaller values give more contrast. (deafult to 80h) 05h red offset control register bit access symbol description [7:1] r/w roff this register controls the red color dc offset (i.e. brightness ) . smaller values give a brighter image (default to 1000000b) [0] r/w reserved 06h green offset control register bit access symbol description [7:1] r/w goff t his re g ister controls the green color dc offset ( i.e. brightness). smaller values give a brighter image. (default to 1000000b) [0] r/w reserved 07h blue offset control register bit access symbol description [7:1] r/w boff t his re g ister controls the blue color dc offset ( i.e. bri g htness ) . smaller values give a brighter image. (default to 1000000b) [0] r/w reserved 08h clamp placement register bit access symbol description
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 12 [7:0] r/w clpl t his re g ister is used to p lace the clamp si g nal an inte g er number of clock p eriods after the railin g ed g e of the hsync signal. this register can be p ro g rammed to an y value between 1 and 255. (default to 80h) 09h clamp duration register bit access symbol description [7:0] r/w cldu t his re g ister is used to control the number of clock p eriods that the clamp signal is active clamping. (default to 80h) 0ah control register bit access symbol description [7:6] r/w ctrl[7:6] default: 2?b11 5 r/w ctrl[5] hsync polarity changes the polarity of the incoming hsync signal. 0b: active low (hsync is negative-going pulse) 1b: active high (hsync is positive-going pulse) (default) 4 r/w ctrl[4] coast polarity changes the polarity of external coast signal. 0b: active low 1b: active high (default) 3 r/w ctrl[3] clamp source selects hsync for g eneratin g internal clam p si g nal or selects external clamp signal for clamping. 0b: uses hsync as clamping signal (default) 1b: select external clamping signal 2 r/w ctrl[2] clamp polarity chan g es the p olarit y of external clamp si g nal. onl y valid with external clamp signal. 0b: active low 1b: active high (default) 1 r/w ctrl[1] pll bypass @ rgb mode selects the internal pll or the external clock input. 0b: use internal pll (default) 1b: use external clock input & shut down the internal pll 0 r/w reserved 0bh phase adjust register bit access symbol description [7:3] r/w phase t his re g ister is used to ad j ust the clock p hase for adc. lar g er values mean more delay (1 lsb = t/32). (deafult to 11110b) [2:0] r/w reserved 0ch vco/cpmp register bit access symbol description
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 13 [7] r/w reserved vco range selects vco frequency range. [6:5] r/w vcocp[4:3] 00b: 20 ~ 60 mhz 01b: 50 ~ 90 mhz (default) 10b: 80 ~ 120 mhz 11b: 110 ~ 140 mhz charge pump current changes the driving current to the low pass filter. [4:2] r/w vcocp[2:0] 000b: 50 ua 001b: 100 ua (default) 010b: 150 ua 011b: 250 ua 100b: 350 ua 101b: 500 ua 110b: 750 ua 111b: 1500 ua [1:0] r/w reserved 0dh red midscale voltage level control register bit access symbol description [7:1] r/w rboff this register controls the red channel midscale volta g e level for mid-level clamping use. (default to 1000000b) [0] r/w reserved 0eh green midscale voltage level control register bit access symbol description [7:1] r/w gboff this register controls the green channel midscale volta g e level for mid-level clamping use. (default to 1000000b) [0] r/w reserved 0fh blue midscale voltage level control register bit access symbol description [7:1] r/w bboff t his re g ister controls the blue channel midscale volta g e level for mid-level clamping use. (default to 1000000b) [0] r/w reserved 10h sync routing select & output control register bit access symbol description [7:4] r/w reserved [3] r/w hrefsel t he reference clock for pll can be external hsync/com p osite sync or sog input. 0: external hsync/composite sync (default) 1: sog [2] r/w cstsel t wo t yp es of in p ut can be a pp lied into coast for pll to lock on current frequency. 0: coast input pin (default) 1: using vsync [1:0] r/w reserved 11h yuv clamping & sog threshold control register bit access symbol description
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 14 clamp to xclampsel xclp256 gnd mid 256 0 x 1 0 1 1 [7:6] r/w hsy default: 10b [5:4] r/w sog default: 01b [3] r/w comp mid-level clamping op-amp compensation enable signal. default: 1 (enabled) [2] r/w rclampsel [1] r/w gclampsel [0] r/w bclapmsel when rain / gain / bain is connected to analo g video si g nal, rclampsel / gclampsel / bclapmsel can be used to clam p video to 00h or 10h (midscale). 0: clamp to groud (default) 1: clamp to midscale 16h video input select register bit access symbol description [7:6] r/w - reserved default:00 5 r/w clp_pumpb video dc restore method selects the dc restore method for video input. 0b: charge pump (default) 1b: clamping 4 r/w vinselg[4] gain input selection on green channel default: 0 3 r/w vinselg[3] cvbs2 input selection on green channel default: 0 2 r/w vinselg[2] c input selection on green channel default: 0 1 r/w vinselg[1] cb input selection on green channel default: 1 0 r/w vmode adc video mode selection select between rgb mode and video mode input. 0b: rgb mode (default) 1b: video mode 17h video power down register bit access symbol description [7] r/w vtst[7] 0: reference clock and feedback clock are the same fre q uenc y 1: reference clock is twice the feedback clock frequence (default = 0) [6] vtst[6] reserved [5] r/w cbpd power down blue channel (default = 0) [4] r/w crpd power down red channel (default = 0) [3] r/w ypd power down green channel (default = 0) [2] r/w sogpd power down sog function (default = 0) [1] r/w gclp256 (default = 0) [0] r/w rclp256 (default = 0) 18h hsync pulse width counter register bit access symbol description [7:0] r/w hscount counter for ad j ustin g the p ulse width of the internally-generated hsout signal (default = 80h)
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 15 19h hsync test mode register bit access symbol description [7:2] r/w hstest[7:2] reserved [1:0] r/w hstest[1:0] keep hsout frequency during coast period (default = 00h) 1ah speed register bit access symbol description [7] r/w reserved [6] r/w pll_vmode adc clock source selection select between rgb mode and video mode clock function. 0b: rgb mode, adc clock uses pll clock (default) 1b: video mode, adc clock uses external clock [5:0] r/w reserved 1bh speed register bit access symbol description [7:4] r/w bc[3:0] adc bias current, default: 1000b [3:0] r/w test 20h video sync tip control 1 register bit access symbol description charge pump current for y (green channel) changes the dc restore current for video mode. [7:0] r/w ypumpctrl[7:0] 01h: 25 ua 02h: 50 ua 04h: 100 ua 08h: 200 ua 10h: 250 ua 20h: 300 ua 40h: 350 ua 80h: 400 ua (default = 00h) 21h video sync tip control 2 register bit access symbol description charge pump current for cr (red channel) changes the dc restore current for video mode. [7:0] r/w crpumpctrl[7:0] 01h: 25 ua 02h: 50 ua 04h: 100 ua 08h: 200 ua 10h: 250 ua 20h: 300 ua 80h: 400 ua 40h: 350 ua (default = 00h) 22h video sync tip control 3 register bit access symbol description charge pump current for cb (blue channel) changes the dc restore current for video mode. [7:0] r/w cbpumpctrl[7:0] 01h: 25 ua 02h: 50 ua 04h: 100 ua 08h: 200 ua 10h: 250 ua 20h: 300 ua 40h: 350 ua 80h: 400 ua (default = 00h)
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 16 23h input select register (default = 00h) bit access symbol description [7] r/w vinselbr[7] vssa input switch on b channel [6] r/w vinselbr[6] vssa input switch on b channel [5] r/w vinselbr[5] bain input switch on b channel [4] r/w vinselbr[4] cr input switch on b channel [3] r/w vinselbr[3] rain input switch on r channel [2] r/w vinselbr[2] cvbs1 input switch on r channel [1] r/w vinselbr[1] y input switch on r channel [0] r/w vinselbr[0] comp_y input switch on r channel 25h power management register bit access symbol description [7:1] r/w reserved [0] r/w pdadc_b power down adc, low-active signal. default:0
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 17 5.5 video decoder (vdec) VP77?s vdec is a high quality ntsc, pal, and secam video decoder plus ypbpr component inputs designed for video applications. minimum external components ar e required due to its integrated analog front-end containing agc, clamping, and three high speed adcs. fo r composite inputs, an adaptive 2d comb filter and luma/chroma processing produce exceptionally high quality pictures for y/c separation. furthermore, 2d noise reduction which provide good video quality especially when the source is from a noisy vcr tape are included. 5.5.1 vdec control register 00h vdec control0 7 6 5 4 3 2 1 0 ifmt dfmt v625 cmode rsvd mnemonic type description ifmt r/w this bit selects input video format. 0 = composite (default) 1 = s-video (separated y/c) cmode r/w these bits select video colour standard. 000 = ntsc (default) 001 = pal (i,b,g,h,d,n) 010 = pal (m) 011 = pal (cn) 100 = secam v625 r/w this bit selects the number of scan lines per frame. 0 = 525 (default) 1 = 625 dfmt r/w these bits select the output display format. standard pixels/line bit-setting ntsc, pal(m) 858 00 (default) pal(b,d,g,h,i,n,cn),secam 864 01 ntsc square pixel, pal(m) square pixel 780 10 pal(b,d,g,h,i,n) square pixel 944 11 bit 0 r/w reserved (default to 0) 01h vdec control1 7 6 5 4 3 2 1 0 compvi compv lnowd chromalpf burstwdh ped mnemonic type description ped r/w this bit enables black level correction for 7.5 blank-to-black setup (pedestal). 0 = no pedestal subtraction 1 = pedestal subtraction (default) burstwdh r/w this bit selects the burst gate width 0 = 5 subcarrier clock cycles (default) 1 = 10 subcarrier clock cycles chromalpf r/w this bit set the chroma low pass filter to wide or narrow 0 = narrow (default) 1 = wide 2 = extra wide
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 18 lnowdh r/w these bits select luma notch width 00 = none (default) 01 = narrow 10 = medium 11 = wide compv r/w this bit enables the component video input format. 0 = disable the component video input (default) 1 = component-video (y,pb,pr) compvi r/w this bit inverts the select si g nal for the analo g in p ut multi p lexer durin g component video mode. 0 = not inverted (default) 1 = inverted 02h vdec control2 7 6 5 4 3 2 1 0 lagcfld mvagc clampmd rsvd rsvd cagcen lagcen mnemonic type description lagcen r/w this bit when set enables the luma/com p osite agc. if disabled, then the agc target (register 04h) is used to drive directly the agc gain. 0 = off 1 = on (default) cagcen r/w this bit when set enables the chroma agc. if disabled, then the agc tar g et is used to drive directly the agc gain. 0 = off 1 = on (default) bit 2 r/w reserved (default to 1) bit 3 r/w reserved (default to 1) clampmd r/w this bit sets the mode for the analog front end dc clamping 00 = auto (default) 01 = backporch only 10 = synctip only 11 = off mvagc r/w this bit, when set, automaticall y reduces the g ain ( set in re g ister 4 ) b y 25% when macro-vision encoded signals are detected 0 = off 1 = on (default) lagcfld r/w when this bit is ?0? ( the default ) , then the g ain is u p dated once p er line, after dc clam p in g . when this bit is set, then the g ain is onl y u p dated once p er field, at the start of vertical blank. 0 = off (default) 1 = on 03h yc-separation control 7 6 5 4 3 2 1 0 n443 rsvd ctrap adapmd mnemonic type description adapmd r/w for ntsc mode set to 000b for ntsc443 mode set to 110b for pal 60 mode set to 011b for other pal modes set to 110b (default = 000b)
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 19 ctrap r/w this bit enables the notch-filter at the luma path after the comb filter. this filter can be turned on or off irrespective of the adaptive mode setting. 0 = disabled (default) 1 = enabled n443 r/w this bit enable the ntsc443 input mode (default=0) 04h luma agc value 7 6 5 4 3 2 1 0 lagc mnemonic type description lagc r/w set luma agc control level : standard programming value ntsc m ddh (221d) (default) ntsc j cdh (205d) pal b,d,g,h,i, comb n, secam dch (220d) pal m,n ddh (221d) ntsc m (macrovisioin) a6h (166d) pal b,d,g,h,i, comb n (macrovision) aeh (174d) lagc is used when lagcen bit is 0 (reg 02h/bit-0) 06h adc_swap 7 6 5 4 3 2 1 0 rsvd rsvd rsvd agcg_thd mnemonic type description agcg_thd r/w this specifies the threshold at which the rough gate generator creates a sync gate. default = 10 bit 7 r/w reserved bit 6 r/w reserved bit 5 r/w reserved 08h luma contrast adjustment 7 6 5 4 3 2 1 0 contrast mnemonic type description contrast r/w these bits control the adjustable gain to the luma output path (default = 128). 09h luma brightness adjustment 7 6 5 4 3 2 1 0 brightness mnemonic type description brightness r/w this 2?s complement number control the adjustable brightness level to the luma output path. (default = 32) 0ah chroma saturation adjustment 7 6 5 4 3 2 1 0 saturation
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 20 mnemonic type description saturation r/w these bits adjust the colour saturation (default = 128). 0bh chroma hue phase adjustment 7 6 5 4 3 2 1 0 hue mnemonic type description hue r/w this 2?s complement number adjusts the hue phase offset (default = 0). 0ch chroma agc 7 6 5 4 3 2 1 0 cagc mnemonic type description cagc r/w these bits set the chroma agc target (default = 138) 12h agc control 1 7 6 5 4 3 2 1 0 mnemonic type description agc_control_1 r/w default to 0c6h, and set to 34h for the xtal clock of 20mhz 13h agc control 2 7 6 5 4 3 2 1 0 mnemonic type description agc_control_2 r/w default to 82h, and set to 0d2h for the xtal clock of 20mhz 14h agc control 3 7 6 5 4 3 2 1 0 mnemonic type description agc_control_3 r/w default to 64, and set to 2fh for the xtal clock of 20mhz 15h agc control 4 7 6 5 4 3 2 1 0 mnemonic type description agc_control_4 r/w default = 64h, and set to 4ah for the xtal clock of 20mhz 17h h loop maxstate 7 6 5 4 3 2 1 0 hlock_vsync_mode hstate_fixed disable_hfine hstate_unloc ked hstate_max mnemonic type description hstate_max r/w these bits set the maximum state for the horizontal pll state machine. if ?hstate_fixed? is set, then this register is used to force the state. (default = 3). hstate_unlocked r/w this bit sets the state when unlocked (default = 1)
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 21 disable_hfine r/w this bit, when set, disables the fine mode of the hpll p hase com p arator. ( default = 0) hstate_fixed r/w this bit when set forces the state machine to remain in the state set in ?hstate_max? (default = 0) hlock_vsync_mo de r/w these bits control hsync locking during vsync: 00 = disabled 01 = enabled 10 = enabled except for noisy signals 11 = enabled only for vcr signals (default) 18h chroma dto increment 31 30 29 28 27 26 25 24 cdto_fixed reserved cdto_inc[29:24] mnemonic type description cdto_fixed r/w this bit, when set, fixes the chroma dto at its centre frequency (default = 0) cdto_inc[29:24] r/w these bits contain bits 29:24 of the 30-bit-wide chroma dto increment. 19h chroma dto increment 23 22 21 20 19 18 17 16 cdto_inc[23:16] mnemonic type description cdto_inc[23:16] r/w these bits contain bits 23:16 of the 30-bit-wide chroma dto increment. 1ah chroma dto increment 15 14 13 12 11 10 9 8 cdto_inc[15:8] mnemonic type description cdto_inc[15:8] r/w these bits contain bits 15:8 of the 30-bit-wide chroma dto increment. 1bh chroma dto increment 7 6 5 4 3 2 1 0 cdto_inc[7:0] mnemonic type description cdto_inc[7:0] r/w these bits contain bits 7:0 of the 30-bit-wide chroma dto increment. 1ch horizontal sync dto increment 31 30 29 28 27 26 25 24 hdto_fixed reserved hdto_inc[29:24] mnemonic type description hdto_fixed r/w this bit, when set, fixes the horizontal s y nc dto at its centre fre q uenc y ( default = 0) hdto_inc[29:24] r/w these bits contain bits 29:24 value of the 30-bit-wide horizontal sync dto increment.
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 22 1dh horizontal sync dto increment 23 22 21 20 19 18 17 16 hdto_inc[23:16] mnemonic type description hdto_inc[23:16] r/w these bits contain bits 23:16 value of the 30-bit-wide horizontal sync dto increment. 1eh horizontal sync dto increment 15 14 13 12 11 10 9 8 hdto_inc[15:8] mnemonic type description hdto_inc[15:8] r/w these bits contain bits 15:8 value of the 30-bit-wide horizontal sync dto increment. 1fh horizontal sync dto increment 7 6 5 4 3 2 1 0 hdto_inc[7:0] mnemonic type description hdto_inc[7:0] r/w these bits contain bits 7:0 value of the 30-bit-wide horizontal sync dto increment. 28h backporch interval start time 7 6 5 4 3 2 1 0 backporch_start mnemonic type description backporch_start r/w these bits control the backporch detect window. this specifies the beginning of the window. (default = 34) 29h backporch interval end time 7 6 5 4 3 2 1 0 backporch_end mnemonic type description backporch_end r/w these bits control the backporch detect window. this specifies the end of the window (default = 78) 2ch chroma burst gate start time 7 6 5 4 3 2 1 0 burst_gate_start mnemonic type description burst_gate_start r/w this specifies the beginning of the burst g ate window. note that this window is set to be bi gg er than the burst. the automatic burst p osition tracker finds the burst within this window. (default = 50)
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 23 2dh chroma burst gate end time 7 6 5 4 3 2 1 0 burst_gate_end mnemonic type description burst_gate_end r/w these bits specifies the end of the burst gate window (default = 70) 2eh active video horizontal start_time 7 6 5 4 3 2 1 0 hactive_start mnemonic type description hactive_start r/w these bits control the active video line time interval. this s p ecifies the be g innin g of active line. this register is used to centre the horizontal position, and should not be used to crop the image to a smaller size. (default = 130) 2fh active video horizontal width 7 6 5 4 3 2 1 0 hactive_width mnemonic type description hactive_width r/w these bits control the active video line time interval. this register specifies the width of the active line, and should not be used to cr o p the ima g e to a smaller size. the value 640 is added to this register. (default = 80, and so the total width is 640+80=720) 30h active video vertical start 7 6 5 4 3 2 1 0 vactive_start mnemonic type description vactive_start r/w these bits control the first active video line in a field. this s p ecifies the number of half lines from the start of a field. (default = 34). 31h active video vertical height 7 6 5 4 3 2 1 0 vactive_height mnemonic type description vactive_height r/w these bits control the active video hei g ht. this s p ecifies the hei g ht b y the number of half lines. the value 384 is added to this register. (default = 97 , and 394+97=481 half lines) 34h vsync agc lockout start 7 6 5 4 3 2 1 0 reserved vsync_agc_min mnemonic type description vsync_agc_min r/w this register defines the number of half-lines before the vsync that the agc, synctip, and backporch gates are disabled. (default = -20)
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 24 35h vsync agc lockout end 7 6 5 4 3 2 1 0 vsync_clamp_mode vsync_agc_max mnemonic type description vsync_agc_max r/w this register defines the number of half-lines after the vsync that the agc, synctip, and backporch gates are re-enabled. (default = 16) vsync_clamp_m ode r/w these bits control dc clamping during the vertical blanking interval. 00 = disabled 01 = enabled 10 = enabled except for noisy signals (default) 11 = enabled except for noisy signals and vcrs 38h vsync_cntl 7 6 5 4 3 2 1 0 vsync_cntl vsync_thresh mnemonic type description vsync_thresh r/w this re g ister s p ecifies a relative threshold to add to the slice level for the p ur p ose of vsync detection. (default = 0 with 2?s complement value) vsync_cntl r/w these bits set the vsync output mode 00 = output the vertical pll vsync when the signal is noisy; otherwise use directly derived vsync (default) 01 = output the directly detected vsync 10 = output the vertical pll derived vsync 11 = output the pll vsync in alternate mode 39h vsync_time_constant 7 6 5 4 3 2 1 0 field_pol flip_field veven_dly vodd_dly field_detect_mode vloop_tc mnemonic type description vloop_tc r/w these bits set the vertical pll time constant 0 = fast. only useful if the vloop_cntl register is not 11. internal values are 2 and 1. 1 = moderate. internal values are 1 and 1/4. 2 = slow. internal values are 1/2 and 1/16 (default) 3 = very slow. most useful for noisy signals. internal values are 1/4 and 1/2 field_detect_mo de r/w these bits control the field detection logic. (default = 2) vodd_dly r/w this bit delays detection of odd fields by 1 vertical line (default = 0) veven_dly r/w this bit delays detection of even fields by 1 vertical line (default = 0) flip_field r/w this bit flips even/odd fields field_polarity r/w this bit sets the output field polarity. 0 ?@?@ field=1 for odd fields, field=0 for even fields (default) 1 ?@?@ field=0 for odd fields, field=1 for even fields 3ah vdec status register 1 7 6 5 4 3 2 1 0 mv_cstripes mv_vbi_det chromalock vlock hlock no_signal
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 25 mnemonic type description no_signal r no signal detection 1 = no signal detected 0 = signal detected hlock r horizontal line locked 1 = locked 0 = unlocked vlock r vertical lock 1 = locked 0 = unlocked chromalock r chroma pll locked to colour burst 1 = locked 0 = unlocked mv_vbi_det r macrovision vbi pseudo-sync pulses detection 1 = detected 0 = undetected mv_colourstripes r macrovision colour stripes detected. the number indicates the number of colour stripe lines in each group 3bh vdec status register 2 7 6 5 4 3 2 1 0 reserved - no_colorburs t vnon_stan dard hnon_stan dard proscan_de tected mnemonic type description proscan_detected r progressive scan detected hnon_standard r horizontal frequency non-standard input signal detected vnon_standard r vertical frequency non-standard input signal detected no_colorburst r no colorburst detect 3ch vdec status register 3 7 6 5 4 3 2 1 0 vcr_rew vcr_ff vcr_trick vcr noisy 625_det secam_det pal_det mnemonic type description pal_det r pal mode detected secam_det r secam mode detected 625_det r 625 scan lines detected noisy r noisy signal detected. vcr r vcr detected vcr_trick r vcr trick-mode detected vcr_ff r vcr fast-forward detected vcr_rew r vcr rewind detected 3fh vdec reset register 7 6 5 4 3 2 1 0 reserved soft_rst mnemonic type description soft_rst w soft reset
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 26 5.5.2 vbi decoder registers 40h vdec teletext vbi frame code register 7 6 5 4 3 2 1 0 reserved slvl_en st_err vbi_en mnemonic type description vbi_en r/w this bit enable the vbi decoder 0 = off (default) 1 = on st_err r/w when this is 1, it will allow one bit error in the stat code detection. when this bit is 0, all the start-code-bits must be correct during vbi line detection. 0 = off (default) 1 = on slvl_en r/w when it is enable, the slicer level is auto determined. when is disable, the slicer level is specified by the vbi_data_hlvl register. 0 = off 1 = on (default) 42h vdec data high level register 7 6 5 4 3 2 1 0 vbi_data_hlvl mnemonic type description vbi_data_hlvl r/w these bits specified the vbi data high level 51h vdec vbi data type configuration register for line 21 7 6 5 4 3 2 1 0 vbil21e vbil21o mnemonic type description vbil21o r/w set vbi data type for odd field vbil21e r/w set vbi data t yp e for even field ( line 284 for 525 s y stem, line 334 for 625 system) vbi data type programming value closed caption (us) 0001b reserved others 5.5.3 status registers 2 70h horizontal sync dto increment status 31 30 29 28 27 26 25 24 reserved status_hdto_inc[29:24] mnemonic type description status hdto_inc[29:24] r these bits contain status bits 29:24 of the 30-bit-wide horizontal sync dto increment. 71h horizontal sync dto increment status 23 22 21 20 19 18 17 16
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 27 status_hdto_inc[23:16] mnemonic type description status_ hdto_inc[23:16] r these bits contain status bits 23:16 of the 30-bit-wide horizontal sync dto increment. 72h horizontal sync dto increment status 15 14 13 12 11 10 9 8 status_hdto_inc[15:8] mnemonic type description status_ hdto_inc[15:8] r these bits contain status bits 15:8 of the 30-bit-wide horizontal sync dto increment. 73h sync-tip level data 7 6 5 4 3 2 1 0 synctip_level[9:2] mnemonic type description synctip_level[9:2] r these bits contain status bits [9:2] of the 10-bit sync-tip level data 77h blank level data 7 6 5 4 3 2 1 0 blank_level[9:1] mnemonic type description blank_level[9:2] r these bits contain status bits [9:2] of the 10-bit blank level data 7dh blank/sync-tip data 7 6 5 4 3 2 1 0 reserved synctip_level[1:0] blank_level[1:0] mnemonic type description blank_level[1:0] r these bits contain status bits [1:0] of the 10-bit blank level data synctip_level[1:0] r these bits contain status bits [1:0] of the 10-bit sync-tip level data 80h vdec luma peaking register 7 6 5 4 3 2 1 0 reserved secam_ybw peak_range peak_gain peak_en mnemonic type description peak_en r/w this bit enables the luma horizontal peaking control around the colour subcarrier 0 = disabled (default) 1 = enabled peak_gain r/w these bits set the gain for the luma horizontal peaking control. this allows adjustable gain to the luma around the colour subcarrier frequency (default = 2). peak_range r/w these bits set the range of peak_gain setting peak_range value 00 1 (default) 01 2 10 4 11 8
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 28 secam_ybw r/w these bit set the secam luma notch filter bandwidth 0 = narraw (default) 1 = wide 83h vdec chroma_lock_config 7 6 5 4 3 2 1 0 lose_chromalock_count lose_chromalock_level lose_chroma lock_ckill mnemonic type description lose_chromalock_ckill rw when set, chroma is killed whenever chromlock is lost (default = 1). lose_chromalock_level rw set the level for chromakill (default = 7). lose_chromalock_count rw this register is used to tune the chromakill, smaller values are more sensitive to losing lock (default = 6). 5.5.4 vdec input and adc/vdec output control register a0h output_control 7 6 5 4 3 2 1 0 ccir656_en cbcr_swap blue_mode yc_delay mnemonic type description yc_delay r/w this 2?s complement number controls the output delay between luma and chroma. negative values shift luma outputs to the left while positive values shift luma values to the right. the range is [-5,7]., and the default = 0 blue_mode r/w this bit controls the blue screen mode. 00 = disabled 01 = enabled 10 = auto (default) 11 = reserved cbcr_swap r/w this bit swaps cb/cr outputs. 0 = don?t swap cb/cr (default) 1 = swap cb/cr ccir656_en r/w this bit enable the ccir656 output a1h output_control 7 6 5 4 3 2 1 0 reserved din_mux flip_yuv output_format ofid_pol blank_mask_en 000 0 0 0 0 mnemonic type description blank_mask_ en r/w force the output data during blanking interval to be zeros 0: non-mask the output data 1: mask the output data ofid_pol r/w vdec output fid pin polarity output_format r/w select the output data format 0: 8 bits data output 1: 16 bit data ouput flip_yuv r/w swap the output data of y and u/v
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 29 din_mux r/w the digital switches for the mapping of adc output to ycbcr digital input. y cb cr 000 : g b r 001 : g r b 010 : r g b 011 : r b g 100 : b r g 101 : b g r
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 30 1 2 4 8 1 2 4 8 c omp_y y cvbs1 rain cb c cr vssa vinselbr[7:4] vinselg[4:1] vinselbr[3:0] r channel g channel b channel 1 2 4 8 cvbs2 gain bain adc core adc core adc core video decoder cr[8:0] y[8:0] cb[8:0] [9:1] [9:1] [9:1] don't care don't care y[7:0] [8:1] [8:1] [8:1] din_mux[2:0] 000 001 010 011 100 101 000 101 011 100 001 010 000 011 001 100 010 101 1 0 1 0 1 0 cvd_byp rout[7:0] gout[7:0] bout[7:0] (to scaler system or ext. chip) ( to scaler s y stem ) ( to scaler s y stem ) adc/video-decoder output multiplexing
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 31 5.5.5 y/c separation register afh y/c separation control 1 7 6 5 4 3 2 1 0 mnemonic type description y/c control 1 r/w default is 0ah, and set to 05h for ntsc mode, and 0ah for pal mode b0h y/c separation control 2 7 6 5 4 3 2 1 0 mnemonic type description y/c control 2 r/w default is 0fah, and set to 0fah for ntsc mode, and 0fh for pal mode b5h vdec chroma edge enhancement register 7 6 5 4 3 2 1 0 chroma_peak_ en chroma_co ring_en reserved chroma_peak mnemonic type description chroma_peak r/w these register bits specified the peak gain for the chroma edge enhancement. increase this value will increase the sharpness of the chroma edge. default = 3 chroma_coring_ en r/w this register bit enables the coring function circuit which is used to eliminate the low level chroma noise such that the low amplitude noise will not be amplified. default = 1 chroma_peak_en r/w this register bit enable the chroma edge enhancement circuit. default = 0 b7h y/c control 3 7 6 5 4 3 2 1 0 mnemonic type description y/c control 3 r/w default is 0h, and set to 04h for ntsc mode, and 34h for pal mode bbh vdec misc controller register 1 7 6 5 4 3 2 1 0 reserved byp_adc byp_vd 0 0 mnemonic type description byp_vd r/w bypass the digital part of vdec and use adc only. byp_adc r/w bypass internal adc. (debug test use only) beh vdec misc controller register 2
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 32 7 6 5 4 3 2 1 0 mnemonic type description misc 2 r/w default is 00h, and set to 08h 5.5.6 noise reduction registers cfh vdec nr control register 1 7 6 5 4 3 2 1 0 reserved nr_demo_mode nr_mode 00 00 mnemonic type description nr_mode r/w for noise reduction, 00 = none(default) 01 = processed with 2d noise reduction others reserved nr_demo_mode r/w for noise reduction, 0x = normal(default) 10 = demo by horizontal 11 = demo by vertical e0h vdec nr control register 2 7 6 5 4 3 2 1 0 reserved nr_ outcode nr_incode 0 0 mnemonic type description nr_incode r/w this bit shows the input yuv format for noise reduction. 0 = unsigned(default) 1 = signed nr_outcode r/w set the desired the yuv output format from noise reduction. 0 = unsigned(default) 1 = signed e1h vdec nr control register 3 7 6 5 4 3 2 1 0 nr2d_thrd 0000-0100 mnemonic type description nr2d_thrd r/w threshold for 2d noise reduction ebh vdec nr control register 4 7 6 5 4 3 2 1 0 reserved cr_sel nr_demo_ch reserved 0 0 mnemonic type description nr_demo_ch r/w 0 = left/up part is processed 1 = right/down part is processed
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 33 cr_sel r/w for component video, select pb_valid at the chip ech vdec nr control register 5 7 6 5 4 3 2 1 0 reserved weight_met hod nr2d_yc 0 11 mnemonic type description nr2d_yc r/w whether processed by 2d noise reduction 00 = none(default) 10 = luma only 01 = chroma only 11 = both weight_method r/w 5.5.7 closed caption registers f0h vdec cc control register 1 7 6 5 4 3 2 1 0 reserved cc_timer_erase cc_mode 000 0000 mnemonic type description cc_mode r/w data display mode. 0000 = cc1{odd field, channel 1}(default) 0001 = cc2{odd field, channel 2} 0010 = cc3{even field, channel 1} 0011 = cc4{even field, channel 2} 0100 = t1{odd field, channel 1} 0101 = t2{odd field, channel 2} 0110 = t3{even field, channel 1} 0111 = t4{even field, channel 2} 1xxx = xds data and odd field mode can work at the same time cc_timer_erase r/w timer erase select 000 = disable 110 = enable f1h vdec cc control register 2 7 6 5 4 3 2 1 0 reserved cc_ external uv_swap bypass_ cc erase_ memory underline osd_ flipfield 1 0 0 0 0 0 mnemonic type description osd_flipfield r/w flip osd field 0: don?t flip(default) 1: flip field underline r/w force display underline 0: don?t force(default) 1: force display underline
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 34 erase_memory r/w erase display memory 0: don?t erase(default) 1: erase memory bypass_cc r/w bypass cc display 0: don?t bypass(default) 1: bypass uv_swap r/w swap u v 0: don?t swap(default) 1: swap cc_external r/w decide cc display data from internal decoder or insertion port 0: internal decoder 1: insertion port(default) f2h vdec cc control register 3 7 6 5 4 3 2 1 0 roll_up_speed roll_up roll_up_setting 00 0 0-0000 mnemonic type description roll_up_setting r/w roll-up method select (suggest 01) roll_up r/w force roll up 0: don?t set(default) 1: roll up one row roll_up_speed r/w adjust roll up speed 00:roll up one line every field(default) 01:roll up one line every two fields 10:roll up one line every three fields 11:roll up one line every four fields f3h vdec cc control register 4 7 6 5 4 3 2 1 0 debug_fifo disable_transparent erase_sc ereen_en backspace user_input cc_test_mode delay_fb 0 0 0 0 0 0 00 mnemonic type description delay_fb r/w adjust the position of fast_blanking 00: original(default) 01: delay 1 clk 10: delay 2 clk 11: delay 3 clk cc_test_mode r/w cc test mode, when set ,it will automaticall y fill dis p la y memory. 0: don?t set(default) 1: set user_input r/w user can input 2 bytes cc data from i2c. 0: don?t set(default) 1: user input mode backspace r/w force backspace 0: don?t work(default) 1: erase one character
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 35 erase_scereen_en r/w when this bit is set, the dis p la y data will be erase durin g pause, forward and backward. 0: don?t set(default) 1: set disable_transparent r/w disable transparent char 0: don?t disable transparent 1: disable transparent debug_fifo r/w store cc data into xds_fifo for debug 0: don?t store cc data into xds_fifo 1: store cc data into xds_fifo f4h vdec cc control register 5 7 6 5 4 3 2 1 0 background color 0000 0000 mnemonic type description color r/w force foreground color. 0xxx = define by cc control code 1000 = black 1001 = blue 1010 = green 1011 = cyan 1100 = red 1101 = magenta 1110 = yellow 1111 = white background r/w force background color. 0000 = define by cc control code 0000 = black 0001 = blue 0010 = green 0011 = cyan 0100 = red 0101 = magenta 0110 = yellow 0111 = white 1xxx = opaque f5h vdec erase time register 7 6 5 4 3 2 1 0 reserved zero_time erase_time reserved 0 00 mnemonic type description erase_time r/w if no cc signal during erase_time ,screen will be erase 00: 2sec(default) 01: 4sec 10: 6sec 11: 8sec zero_time r/w get zero data during 8sec, screen will be erase 0: disable 1: enable
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 36 f6h vdec xds_fifo_status register 7 6 5 4 3 2 1 0 reserved xds_fifo_rdy xds_ fifo_empty xds_ fifo_full 0 0 0 mnemonic type description xds_fifo_full r xds fifo status 0: fifo is not full 1: fifo is full xds_fifo_empty r xds fifo status 0: fifo is not empty 1: fifo is empty xds_fifo_rdy r xds fifo can be read 0: fifo is not ready, it can?t be read 1: fifo is ready f7h vdec xds_data register 7 6 5 4 3 2 1 0 xds_data 0000-0000 mnemonic type description xds_data r xds data read from i2c f8h vdec user input register 1 7 6 5 4 3 2 1 0 user_ccdata1 0000-0000 mnemonic type description user_ccdata1 r/w user can in put cc data from i2c (byte1) f9h vdec user input register 2 7 6 5 4 3 2 1 0 user_ccdata2 0000-0000 mnemonic type description user_ccdata2 r/w user can in put cc data from i2c (byte2) fah vdec cc horizontal position register 7 6 5 4 3 2 1 0 cc_h_start 0000-0000 mnemonic type description cc_h_start r/w cc display horizontal position
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 37 fbh vdec cc vertical position register 7 6 5 4 3 2 1 0 reserved xds_wr_en cc_v_start 0 0-0000 mnemonic type description cc_v_start r/w cc display vertical position xds_wr_en r/w xds fifo enable 0: xds data can?t write to fifo 1: xds data can write to fifo ffh vdec version number register 7 6 5 4 3 2 1 0 version_number 0000-0001 mnemonic type description version_number r
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 38 5.6 scalar system (sc) the VP77 scalar system receives the ccir656/yuv444/rgb signals and performs image scaling on the digitized rgb data. an auto adjustment function provides automatic frequency, phase, h&v position, saturation, and white balance tuning in graphics mode. it also contains display mode auto detection circuitry that provides accurate h and v timing detection for all display modes (including sync-on-green signals). VP77 contains an on chip osd (on screen display) logic together with an overlay port for external osd signals interface. 5.6.1 color adjust VP77 supports the contrast control useng a 8-bit signal to set a multiply value from 2 to 0 (in fact, the 256 choices are 255/128, 254/128, ..., 128/128, .., 1/128, 0). the brightness correction uses a 8-bit signal to set an offset value from 127 to -128 (the 256 choices are 127, 126, ..., 1, 0, -1, ..., -127, -128). the control signals brightness[7:0] and contrast[7:0] are programmable via serial interface. the formula to set contrast[7:0] value is ((contrast+128) mod 256)/128 where con-trast is in the range of [255,0]. for brightness control, the signal brightness[7:0] is interpreted as a 2s complement value. table 5.5.3. contrast & brightness definition contrast correction for msb=0 contrast[7:0] 7f(hex) 7e ...... 02 01 00 multiply value 255/128 254/128 ...... 130/128 129/128 128/128 contrast correction for msb=1 contrast[7:0] ff(hex) fe ...... 82 81 80 multiply value 127/128 126/128 ...... 2/128 1/128 0/128 brightness correction for msb=0 brightness[7:0] 7f(hex) 7e 7d ....... 02 01 00 offset value 127 126 125 . ...... 2 1 0 brightness correction for msb=1 brightness[7:0] ff(hex) fe fd ....... 82 81 80 offset value -1 -2 -3 ....... -126 -127 -128 limiter scaled r/g/b contrast[7:0] bri g htness[7:0] ad j usted r/g/b
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 39 5.6.2 gamma correction ram tables gamma correction ram tables are implemented after the brightness/contrast block to provide the color-mapping of the rgb data. the tables can be activated by setting gammause (msb of outctr1 or 04 hex) bit = 1. we can also by-pass the gamma correction function by resetting the gammause bit = 0. through three gamma table registers (grwaddr, ggwaddr and gbwaddr) the data representing gamma curves can be put into the rams sequentially. 5.6.3 osd, clut this VP77 embeds an on screen display function for human interfacing. it is designed to display colored patterns, icons or characters onto the screen. a 127 character fonts (downloadable from mcu) are provided for the application of multi-language tv/monitor. the graphic character fonts can produce the effect of the pixel based graphic display, which allows the impressive display of the customized pattern or logos. the osd provides plentiful features to enhance the appearance of the displayed character fonts. each character can have its own colors (up to 16 colors) and blinking option. up to 10 shadowing modes (including bordering, boxing etc.) are provided together with 16 background colors. the versatile choice for display font color, background/shadow/window color, and shadow modes (including bordering and graphic character mode) leads to a unique osd style. some dynamic features, such as built-in see-through curtain effect, two-direction wipe in/out, character basis blinking, hardware overlapping windows etc. also enhance the image of osd menu. there is a 16x16 clut (color look-up table) which provides a programmable color palette for internal/external osd and background color. the color index bus, namely r/g/b/i, is used as the address to the clut which defines the 16 colors for osd and background color. the content and the index selection of clut are programming via serial interface. the mapping of the 16-bit rgb565 color to 24-bit true color is depicted as the following figure. 8-bit gamma correction ta b l e mux 16x16 clut format converter for panel (with alpha blending) 0 16-bit 24-bit 24-bit 24-bit 24-bit 24-bit 24-bit 4-bit r/g/b/i r/g/b/i 4-bit external osd internal osd back g roud colo r r7 r6 r5 r4 r3 g7 g6 g5 g4 g3 g2 b7 b6 b5 b4 b3 r7 r6 r5 r4 r3 0 0 0 g7 g6 g5 g4 g3 g2 0 0 b7 b6 b5 b4 b3 0 0 0 note: if clut_alpha[4]=1, then the lsb of g readout = 0: means alpha blending off 1: means alpha blending on
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 40 scalar?s 2-wire serial bus registers table addr (hex) h\l 0 1 2 3 4 5 6 7 0 id_ver inctr0 inctr1 outctr0 outctr1 outctr2 inctr2 inctr3 1 ih_astart ih_awidth ih_total iv_astart 2 awivsta ih_awidth ih_total iv_astart 3 ph_astart ph_awidth pv_awidth 4 bh_astart bh_end reset_reg 5 pbv_aoffset_even pbv_aoffset_odd pbv_awidth osd_font_adr osd_font_lsb 6 offset_no sync_distance line_margin ihsc_awdith 7 vdeno sdnhdx sdhdy sdnhhinc fread_r fread_g fread_b 8 rgb_ov rgb_min aw2vsta aw2vend 9 hend hsr hsg hsb her heg heb a iclk_meas pclk_meas ih_total_meas pwg_outsc1 pwg_outsc2 b gcontrsast gbrightness grwaddr ggwaddr gbwaddr lutwaddr clut_alpha bcontrast c osd_sys_ctrl ph_total ph_delay d hwdcnt intsrc sync_status hperiod vperiod pulcnt e peak_ctrl1 peak_ctrl2 peak_ctrl3 peak_ctrl4 peak_ctrl5 peak_ctrl6 f osd_font_adr2 osd_disp_op1 osdlut aw2hsta addr (hex) h\l 8 9 a b c d e f 0 misctr2 misctr3 misctr0 misctr1 misctr4 status1 intctr misctr5 1 iv_awidth iv_total ih_pulw ivs_delay vs_fporch 2 asum asod 3 pv_total ph_pulw pv_pulw olhnv graphics_str (osd) graphics_end (osd) 4 cti_ctrl1 cti_ctrl2 cti_ctrl3 cti_ctrl4 sinhue coshue black 5 osd_font_msb osd_font_attr osd_font_code osd_dram_adr0 osd_dram_adr1 pwm0_pulh pwm0_period 6 vdx vdy vhinc algo_sd vnume 7 sod_mask pwm0_pulh clamp_start clamp_width iv_wrap ih_wrap 8 mlnum vstart vend hstart 9 lnum pdfvaddr pdfhstart lb_margin a pwg_outsc3 px_as_aline aml_overflow rcontrast rbrightness b bbrightness gcstart pllctrl0 pllctrl1 auxidl auxidh pllctrl2 c iv_sfdl osd_spdef osd_disp_opt0 osd_hpos osd_vpos osdctr0 osdctr1 d hvpwth poutpolpos hmdmisc hfphigh hvfploe vfphigh vsepproglo vsepproghi e fread (freeze line) fvaddr (freeze line) fhstart (freeze line) vspd_with_hs f aw2hend pwg_outctr1 pwg_outctr2 pwg_outctr3 pwm1pulh pwm2pulh
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 41 sc?s i/o and misc. registers descriptions: register function addr (hex) d7 d6 d5 d4 d3 d2 d1 d0 chip id and version (id_ver) 00h id_ver[7:0] input control register 0 (inctr0) 01h (r/w) dis_ihspol ihs_pol ivs_select ivs2pvs avref_use ahref_use rgb_order input control register 1 (inctr1) 02h (r/w) iclk_inv iaclk_delay[2:0] llck_delay[1:0] osd_clk_en irgben output control register 0 (outctr0) 03h (r/w) dither_on chp1_ctr1 pclkin_ext pclk_inv pclk_op[2:0] output control register 1 (outctr1) 04h (r/w) gamma_use rst_gt_adr cph1_ctr2 bkfrc bkcol[3:0] output control register 2 (outctr2) 05h (r/w) ovclk_delay[2:0] pvs_pol phs_pol pde_pol pout_off input control register 2 (inctr2) 06h (r/w) swap_rb matrix_on ry_sel rgb_invm ext_video uti_yuv656 en_freeze re_fhaddr input control register 3 (inctr3) 07h (r/w) yuv444 odd_pol incode interlace _sen iv_inv ih_inv fid_msel fid_esel misc. control register 2 (misctr2) 08h (r/w) vclko_mode[3:0] cph_mode[3:0] misc. control register 3 (misctr3) 09h (r/w) pll_54m_en usb_datck 27m_sel xosc2adc_ div2_en adc_iclk_mode[3:0] misc. control register 0 (misctr0) 0ah (r/w) adc_tst pwd_en xtal_pulse_sel[1:0] vhsyn_sel dactst freerun_n rgb_out_ dis misc. control register 1 (misctr1) 0bh (r/w) osdlut_reload ovs_vactive eosd_en eosdfr eosd_synsel clamp_off aclk_sel iic_act_direct misc. control register 4 (misctr4) 0ch (r/w) video_pin_in_ en video_pin_out _en sc_out2d_en sc_out2a_en adc_pll_clk_ off pwg_clk_off byp_cvd cph_off status register (status1) 0dh (r) apxl_resort asod_rdy aml_rdy interrupt control register (intctr) 0eh (w) inten misc. control register 5 (misctr5) 0fh (r/w) dac_clkx3_ en cph_out_en dcpwmout_ off dac_en dac_invert
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 42 id_ver (chip id and version, 00h) default 7-0 id_ver for VP77 01100010 62 inctr0(input control register 0, 01h) default 7 dis_ihspol 0: auto detecting function of the p olarit y of hs of in p ut video will be checked automatically 1: auto detectin g function of the p olarit y of hs of in p ut video will be disabled note: the polarity of vs of input video will be checked automatically 0 6 ihs_pol 0: the rising edge of input hs will be used as the start of the s y nc pulse 1: the falling edge of input hs will be used as the start of the sync pulse 0 5 ivs_select input vs source selection. 0: from external ivs, 1: from internal mode detection circuit. 0 4 ivs2pvs pvs generation usin g the risin g /fallin g ed g e of ivs ( for the case pvs is generated by free-running, this control bit is invalid) 0: falling edge. 1: rising edge. 0 3 - reserved 0 2 avref_use 1: scalar use vref from external scalar 0: scalar use vref from internal scalar 0 1 ahref_use 1: scalar use href from external scalar 0: scalar use href from internal scalar 0 0 rgb_order 1: rgb[7:0] output changed to rgb[1,0,7~2]; 0: no change, [7:0] 0 inctr1(input control register 1, 02h) default default 7 inclk_inv inclk invert enable 0: normal input clock 1: invert input clock 0 6:4 iaclk_delay[2:0] programmable delay for iaclk 000 ~ 111: 0 to 7 unit delay 000 3:2 llck_delay[1:0] programmable delay for llck 00 ~ 11: 0 to 3 unit delay 0 1 osd_clk_en 0: internal osd clock inactive 1: internal osd clock active 1 0 irgben 0: video input 1: rgb input 1 outctr0(output control register 0, 03h) (this register can be read and write) default 7 dither_on 0: no dithering (for the panel with 8 bit color depth per r/g/b) 1: 2 bit dithering (for the panel with 6 bit color depth per r/g/b) 0 6 chp1_ctr1 0: chp1 source is from pclki 1: chp1 source is from pclk6i (pclki div6) 0 5 pclkin_ext the way pclk, panel clock, is generated. 0: pclk is generated by internal pll. 1: pclk is fed from pclkin pin (by external source). 0 4 phclk_inv 0: normal phclk clock output to panel 1: inverted phclk clock output to panel (the relationship of phclk and pclk is also defined by phclk_op(1:0)) 1 3:1 phclk_op (2:0) phase deviation of phclk with respect to pclk 000: no delay 001: delay 1 unit 000
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 43 010: delay 2 units 011: delay 3 units 100: delay 4 units 101: delay 5 units 110: delay 6 units 111: delay 7 units (the relationship of phclk and pclk is also defined by phclk_inv.) outctr1 (output control register 1, 04h) 7 gamma_use use gamma correction table for each r,g, and b. 0: bypass the gamma table 1: use the gamma look-up table 0 6 rst_gt_adr reload gamma table starting address control bit the gamma table starting address is reloaded to the value defined b y reg gcstart ( b9h )while there is a low to high transition 0 5 chp1_ctr2 0: chp1 use original source as cph2/3 1: chp1 use new source sync. with scalar clock phase 0 4 bkfrc panel output force to background color 0: normal panel output 1: output panel is forced to background color, the color is selected by bkcol[3:0] 0 3:0 bkcol[3:0] panel output background color select signals. these signals share the look-up table with osd to generate colors. 000 outctr2 (output control register 2, 05h) 7:5 ovclk_delay[2:0] ovclk phase deviation for the nominal clock reference phase. ovclk_delay[2]: 0: ovclk for osd output is not inverted, 1: ovclk for osd output is inverted. besides, there are delays defined by ovclk_delay[1:0] as follows: ovclk_delay[1:0]: 00: 0 unit delay, 01: 1 unit delay, 10: 2 units delay, 11: 3 units delay. 000 3 pvs_pol pvs output polarity (inside use active high) 0: negative polarity (active low) 1: positive polarity (active high) 0 2 phs_pol phs output polarity (inside use active high) 0: negative polarity (active low) 1: positive polarity (active high) 0 1 pde_pol 0: active high for display data enable output to panel 1: active low for display data enable output to panel 0 0 pout_off panel output control & data disable 0: phs, pvs, pde, pared/pagrn/pablu, and pbred/pbgrn/pbblu output are enabled. 1: phs, pvs, pde, pared/pagrn/pablu, and pbred/pbgrn/pbblu output are set to weak pull low. 0 inctr2(input control register 2, 06h) default 7 swap_rb input r channel and b channel can be swapped by setting this bit 0 6 matrix_on 0: yuv2rgb matrix disable 1: yuv2rgb matrix enable 0 5 ry_sel 0: color adjust based on rgb 1: color adjust based on yuv 0 4 rgb_invm 0: rgb2yuv matrix disable 1: rgb2yuv matrix enable 0 3 ext_video 0: scalar?s video signal comes from internal video decoder 0
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 44 1: scalar?s video signal comes from external chip 2 uti_yuv656 0: scalar?s video input is not ccir656 encoded 1: scalar?s video input is ccir656 encoded 0 1 en_freeze 0: disable freeze 1: enable freeze 0 0 re_fhaddr reload freeze h start address 0 inctr3 (input control register 3, 07h) 7 yuv444 0: scalar?s video input format is not yuv444 1: scalar?s video input format is yuv444 0 6 odd_pol 0: scalar selects 1 st field is odd and odd is active high 1: scalar selects 1 st field is odd and odd is active low 0 5 incode 0: scalar?s video input format is binary 1: scalar?s video input format is 2?s complement 0 4 interlace_sen 1: interlace shift enable; 0: disable 0 3 iv_inv 0: normal 1: scalar selects inverse input video vs 0 2 ih_inv 0: normal 1: scalar selects inverse input video hs 0 1 fid_msel 1: scalar selects from hmd fid 0: scalar selects from internal fid 0 0 fid_esel 1: scalar selects from external fid_odd 0: scalar selects internal fid 0 misctr2(misc. control register 2, 08 hex) default 7:4 vclko_mode[3:0] programmable delay(vclk_delay) for vclko (video clock output from vdec) vclko_mode[2:0]: 000 ~ 111: 0 ~ 7 unit delay vclko_mode[3]: 0: no delay after vclk_delay 1: more half of vclk delay after vclk_delay 0000 3:0 cph_mode[3:0] programmable delay(cph_delay) for cph1/2/3 (analog panel clock) cph_mode[2:0]: 000 ~ 111: 0 to 7 unit delay cph_mode[3]: 0: no delay after cph_delay 1: more half of cph delay after cph_delay 0000 misctr3(misc. control register 3, 09 hex) default 7 pll_54m_en see clock system 0 6 use_datck see clock system 0 5 27m_sel see clock system 0 4 xosc2adc_div2_en see clock system 0 3:0 adc_iclk_mode[3:0] programmable delay(adc_iclk_delay) for adc input clock adc_iclk_mode[2:0]: 000 ~ 111: 0 to 7 unit delay adc_iclk_mode[3]: 0: no delay after adc_iclk_delay 1: more half of adc_iclk delay after adc_iclk_delay 0000
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 45 misctr0(misc. control register 0, 0ah) (this register can be read and write) default 7 adctst 0: adc test mode inactive 1: adc test mode active 0 6 pwd_en 0: VP77 is alive (clk_off=0) 1: VP77 is in power down mode (clk_off=1) 0 5:4 xtal_pulse_sel crystal clock pulse selection. this clock pulse will then be counted by iclk and pclk. 00: 1024 crystal clocks. 01: 2048 crystal clocks. 10: 3072 crystal clocks. 11: 4096 crystal clocks. 0 3 vhsyn_sel port a vs & hs synchronization edge 0: use aclk rising edge 1: use aclk falling edge 0 2 dactst 0: dac test mode inactive 1: dac test mode active 0 1 bypass(output free-run mode) 0: (default) panel vs and hs (pvs & phs) free-runs and acts as a s y nc master. 1: in this mode, the input and output frames are synchronized. in a sense, ivs & ihs are the sync master that generate pvs & phs. note: in order to activate free-run mode, micro-controller should choose bypass = 0. to this, the in p ut data can be i g nored, if necessar y , b y settin g bkfrc= 1 so back g round colors are sent to p anel. 0 0 rgb_out_dis 0:rgb 24 bits output pins active 1:rgb 24 bits output pins inactive 0 misctr1(misc. control register 1, 0b hex) default 7 osdlut_reload reload osd lut from address f3h 0: inactive. 1: active. 0 6 ovs_vactive the osd vs output is generated using 0: overlay vs as in zurac1. 1: vertical display active signal. 0 5 eosd_en 0: external osd will be disabled 1: external osd will be enabled (the internal osd can be enabled by iosd_en in bit 0 of osdctr1 register) 0 3 eosd_synsel 0: eosd data latch uses ovclk 1: eosd data latch uses the inverse of ovclk 0 2 clamp_off clamp pulse will be generated according to the register 7a and 7b (hex) 0: clamp pulse is sent out. 1: clamp pin is in tri-state 0 1 aclk_sel aclk_sel is for iaclk selection. 0: iclk = iaclk/2 (for llc2) 1: iclk = iaclk 1 0 iic_act_direct 0: 2-wire serial bus parameters are activated until next vs retrace period. 1: 2-wire serial bus parameters are activated upon data received 1 misctr4(misc. control register 4, 0c hex) default 7 video_pin_in_en 0: video signal input from pins disable 1: video signal input from pins enable 0 6 video_pin_out_en 0: video signal output to pins disable 0
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 46 1: video signal output to pins enable 5 sc_out2d_en 0: scalar output for digital lcd panel disable 1: scalar output for digital lcd panel enable 0 4 sc_out2a_en 0: scalar output for analog lcd panel disable 1: scalar output for analog lcd panel enable 0 3 adc_pll_clk_off see clock system 0 2 pwg_clk_off see clock system 0 1 byp_cvd see clock system 0 0 cph_off see clock system 0 status1 (status register 0, 0dh) (read only) default r/w 7:3 reserved 2 apxl_report for auto adjustment, by setting to 0, the pxl_report function will be performed. this status bit will be set to 1 as the function is completed. this is a rd/wr bit. the pxl_report function can read the pixel value via pxl_value (x74 ~ x76) of specified position via pxl_address ( x9a ~ 9d ). r/w 1 asod_rdy for auto adjustment, by setting to 0, the sod (sum or sum of difference ) function will be p erformed. this status bit will be set to 1 as the function is completed. this is a rd/wr bit. 1 r/w 0 aml_rdy for auto adjustment, by setting to 0, the mth line function will be performed. this status bit will be set to 1 as the function is completed. 1 r/w intctr (interrupt control register, 0eh) default 7 inten 0: disable all interrupt 1: enable all interrupt 1 6:0 reserved misctr5(misc. control register 5, 0f hex) default 7 dac_clkx3_en 0: internal dac clock frequence x1 (dac_clk f * 1) 1: internal dac clock frequence x3 (dac_clk f * 3) 0 6 cph_out_en 0: analog panel clock output to pins disable 1: analog panel clock output to pins enable 0 5 dcpwmout_off 0: dcdc pwm output to pins disable 1: dcdc pwm output to pins enable 0 4:1 dac_en dac_en[1]: (dac global power control) 0: dac enable 1: dac disable dac_en[4:2]: (dac sub-channel power control) 001: r channel disable 010: g channel disable 100: b channel disable 000: no disable 0000 0 dac_invert 0: dac input clock no invert 1: dac input clock invert 0 register function addr(hex ) msb:odd lsb:even reset value (hex) r/w description
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 47 register function addr(hex ) msb:odd lsb:even reset value (hex) r/w description input window parameter input horizontal active start(ih_astart[10:0]) 11,10 01,28 w this value should be at least larger than six. input horizontal active width (ih_awidth[10:0]) 13,12 04,00 w all default values are setting for test purpose input hsync total (ih_total[10:0]) 15,14 05,40 w input hsync total input vertical active start (iv_astart[10:0]) 17,16 00,23 w input vertical active start input vertical active width (iv_awidth[10:0]) 19,18 03,00 w input vertical active width input vsync total (iv_total[10:0]) 1b,1a 03,26 w input vsync total input hsync pulse width (ih_pulw[7:0]) 1c 44 w this register specifies the pulse width of the input hsync. within this region the input video data are forced to zero by the internal circuit. the max. allowed value is 255 (in the unit of iclk). input vs delay (vs_eq_vref, ivs_delay[3:0]) 1e 00 w the input vs delay. the lsb 4-bit is used. by programming these bits, the input vs signal will be delayed by ivs_delay*16 or ivs_delay*32 pixels (depends on irgb24=1 or 0, see inctr1 at register 02h). ivs_delay=00 (default) means no delay. the bit higher than ivs_delay[3:0] is used for vs_eq_vref. or the generation of internal vs signal for video display. 0: (default) internal vs is different from vref input. 1: internal vs is equal to vref input. vs_fporch[7:0] 1f 00 w define the vertical front p orch width when scalar?s input video is encoded ccir656 format input vsync delay for wrap around (iv_delay4wrap[10:0]) 7d,7c 00,02 w the v delay for vga input. the value 2 (default) means no delay and 3 means one h line delay, and so on (0 and 1 are not allowed.) input hsync delay for wrap around (ih_delay4wrap[10:0]) 7f,7e 00,01 w the h delay for vga input. the value 1 (default) means no dela y and 2 means one pixel delay, and so on (0 is not allowed.) output window parameter panel horizontal active start(ph_astart[10:0]) 31,30 01,28 w please refer to the figure of output window panel horizontal active width(ph_awidth[10:0]) 33,32 04,00 w panel horizontal active panel vertical active width (pv_awidth[10:0]) 37,36 03,00 w panel vertical active width panel vsync even total (pv_total_even[10:0]) 39,38 03,26 w this 10-bit register defines the panel vertical active total lines for non- interlaced video or the even field active total lines for interlaced video. panel hsync pulse width (ph_pulw[7:0]) 3a 88 w panel hsync pulse width panel vsync pulse width (pv_pulw[7:0]) 3b 06 panel vsync pulse width
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 48 register function addr(hex ) msb:odd lsb:even reset value (hex) r/w description olhnvl[10:0] 3d,3c r report the offset between the last phs to next pvs; msb:x3d[2:0]; lsb:x3c[7:0] background window parameter background horizontal start (bh_start[10:0]) 41,40 01,28 w background horizontal end (bh_end[10:0]) 43,42 05,28 w please refer to the figure of output window all default values are setting for 1024*768@60hz reserved 44 w reset_pwm[6:1] 45 02 w reset_pwm [1] : reset_scalar reset the rest of blocks (except i2c, pwm, hmd) reset_pwm [2] : pwm0_out_en 0 : pwm0 output is enable 1 : pwm0 output is disable reset_pwm [3] : pwm1_out_en 0 : pwm1 output is enable 1 : pwm1 output is disable reset_pwm [5] : pwm2_out_en 0 : pwm2 output is enable 1 : pwm2 out p ut is disable reset_pwm [6] : output_swap 1 : swap the a/b port output cti control parameter cti_ctrl1 48 06 w cti_ctrl1[7]: 0: disable cti 1: enable cti cti_ctrl1[3]: 0: disable the pre-filter 1: enable the pre-filter cti_ctrl1[2:0]: cti filter type cti_ctrl2 49 42 w cti_ctrl2[6:4]: 000: filter_out x1 001: filter_out x2 010: filter_out x3 011: filter_out x4 100: filter_out x5 101: filter_out x6 110: filter_out x7 111: filter_out x8 cti_ctrl2[1:0]: 00: divided by one 01: divided by two others: divided by four
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 49 register function addr(hex ) msb:odd lsb:even reset value (hex) r/w description cti_ctrl3 4a c1 w cti_ctrl3[7]: 0: discontinues coring 1: continuous coring cti_ctrl3[6:4]: 000: no coring others: 2*cti_ctrl3 cti_ctrl3[1:0]: 00: one 01: two 10: three 11: four cti_ctrl4 4b 78 w cti_ctrl4[7]: 0: disable pre-dcti 1: enable pre-dcti cti_ctrl4[6]: 0: disable pre-dcti filter1 1: enable pre-dcti filter1 cti_ctrl4[5]: 0: disable pre-dcti filter2 1: enable pre-dcti filter2 cti_ctrl4[4]: 0: disable pre-dcti filter3 1: enable pre-dcti filter3 cti_ctrl4[3]: 0: type 1 of filter1 1: type 2 of filter1 hue saturation control sinhue 4d 00 w the register defines the sat_sinhue setting for yuv domain color adjustment. coshue 4e 80 w t he re g ister defines the sat_coshue settin g for yuv domain color adjustment. black 4f 00 w t he re g ister defines the black settin g for yuv domain luminance adjustment. note: during the yuv-domain color setting, the contrast and brightness of r, g and b should be set to the same values. panel background parameter panel background active offset for even field (pb_lead_lag_en, pbv_aoffset_even[9:0]) 51, 50 00,00 w the lsb 10-bit defines the offset of p anel background active region for even field. the value is counted from the pv_astart. the msb, pb_lead_lag_en, defines lead or la g to pv_astart.pb_lead_lag_en = 1 is la g , otherwise (default) lead. panel background active offset for odd field (pb_lead_lag_od, pbv_aoffset_odd[9:0]) 53, 52 00,00 w the lsb 10-bit defines the offset of p anel background active region for odd field. the value is counted from the pv_astart. the msb, pb_lead_lag_od, defines lead or la g to pv_astart.pb_lead_lag_od = 1 is la g , otherwise (default) lead. panel background active width 55, 54 00,00 w the lsb 11-bit defines the width of p anel
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 50 register function addr(hex ) msb:odd lsb:even reset value (hex) r/w description (pbv_awidth[10:0]) background active region. osd control register graphic_start(osd) 3e ff w graphic font starting graphic_end(osd) 3f ff w graphic font ending osd font address [6:0] 56 00 w font ram write address (auto increment ) . there are 127 (0x00 ~ 0x7e) address for the downloadable fonts. address 0x7f is the s p ace code. osd font lsb [7:0] 57 00 w font lsb, each font is composed of 20x12 bits osd font msb [11:8] 58 00 w font msb osd attribute for font code(osd_at[7:0]) 59 00 w font code attribute osd font code address (osd_dt[6:0]) 5a 00 w font code address osd display ram address 0~255 (osd_ad0[7:0]) 5b 00 w display ram address, range (0-255) osd display ram address 256-511 (osd_ad1[7:0]) 5c 00 w display ram address, range (256-511) osd display ram address 512-639 (osd_ad2[7:0]) f0 00 w display ram address, range (512-639) osd system control c2 00 w bit0~bit1:bits for dot rate selection 00,01: divided by 1 02: divided by 2 03: divided by 3 bit2:vint enable interrupt signal to mcu bit3:winfb_n drive pin fb 0 or 1 bit5:vintorendl selection between the leadin g ed g e of vs y nc and the last scanning line bit6:faderate determine the fade rate 0:0.5 sec / 1:0.25 sec bit7:winmask determine whether the outer of osd window is displayed (winmask=0) or not(winmsk=1). osd default setting for s p ace code color (osd_spdef]) ca 00 w bit0:intensity color of space code bit1:blue color of space code bit2:green color of space code bit3:red color of space code bit5~bit4:veritical position step bit7~bit6:horziontal position step osd display option0 (display_option0) cb 00 w bit7~5:column space 000:no space 001 ~ 111:1 to 7 dot bit4~0:point to the first display row in the display ram osd horizontal start in cc ff w the horizontal starting position
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 51 register function addr(hex ) msb:odd lsb:even reset value (hex) r/w description window(osd_hpos[7:0]) osd vertical start in window(osd_vpos[7:0]) cd ff w the vertical starting position osd control register2 (osd_ctrl2) ce 01 w bit0:intensity color of monitor mode bit1:blue color of monitor mode bit2:green color of monitor mode bit3:red color of monitor mode bit4:not used bit5:wipe enable bit bit6:wipe in/out bit7:wipe direction osd control register (osd_ctrl) cf 1c w bit0:osd enable bit bit1:select blinking rarte bit2:the polarity of r,g,b,i,fb bit3:vsync polarity bit4:hysnc polarity bit5: character font downloadable 0: disable 1: enable bit6:half-tone/see through-effect enable bit bit7:determine if background color can be spilt osd display option (display_option1[2:0]) f1 00 w bit0: horizontal mirror font bit1: vertical mirror font bit2: rotate font address port to address osd window registers osdwindow_addr[6:0] f4 00 w bit4~0:osd window registers address port bit5: vertical position bit 8 bit6: horizontal position bit 8 data port to write osd window registers osdwindow_data[7:0] f5 00 w osd window registers data port *those registers are used to define 4 osd windows. they are programmed through address port (osdwindow_addr[6:0], f4h) and data port (osdwindow_data[7:0], f5h) using indirect addressing mode win1vs win2vs win3vs win4vs ind(00)* ind(05)* ind(0a)* ind(0f)* 00 w bit4-bit0:the display starting row of window 1,2,3,4 win1ve win2ve win3ve win4ve ind(01)* ind(06)* ind(0b)* ind(10)* 00 w bit4-bit0:the display ending row of window 1,2,3,4 win1hs win2hs win3hs win4hs ind(02)* ind(07)* ind(0c)* ind(11)* 00 w bit0: the intensity color of window color index bit1: window 1 halftone enable bit bit2: window 1 enable bit bit7-bit3: the display starting column of window 1,2,3,4 win1he win2he win3he ind(03)* ind(08)* ind(0d)* 00 w bit0: the blue color of window color index bit1: the green color of window color index bit2: the red color of window color index
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 52 register function addr(hex ) msb:odd lsb:even reset value (hex) r/w description win4he ind(12)* bit7-bit3:the display ending column of window 1,2,3,4 win1sh win2sh win3sh win4sh ind(04)* ind(09)* ind(0e)* ind(13)* 00 w bit1-bit0: the height of the window shadow bit3-bit2: the width of the window shadow bit4: if set, enable the window shadow if cleared, disable the window shadow bit7-bit5: the color index of the window shadow the actual color is defined by clut. pwm pwm1_high_period[15:0] 79,5d 00 w define the duty ratio of pwm. duty ratio = pwm_high_period / pwm_period note: msb should be programed first. lsb is located at x79[7:0]. the smallest value of pwm_high_period is 1. pwm0_period[15:0] 5f,5e 00,ff w define the freqnency of pwm. pwm frequency = 14.318mhz/ 4 /pwm_preiod note: msb should be programed first. pwm_period should be g reater than pwm _high_period. so this pwm can be programed from 55hz to 1.7mhz. pwm1[7:0] fd 00 w t he default value 00 means a low out p ut while the value ff(hex) can be integrated by a capacitor for an almost high signal pwm2[7:0] fe 00 w t he default value 00 means a low out p ut while the value ff(hex) can be integrated by a capacitor for an almost high signal scaling parameter offset_no 60 00 w s p ecif y the number of m lines amon g n lines from which ph_total is com p ensated b y value 2 ( works to g ether with re g . line_margin) sync_distance 63,62 r report the distance between last ihs to next phs from where the output starts to display line_margin 65,64 r report the offset pixel number for last synchronized phs ih_active_sc 67,66 w for scalin g factor calculation, to have a fixed scaling factor svdx[7:0], svdy[7:0], svhinc[6:0] 69,6b,6d 01,00, 80 w svhinc= floor(32/vsf), vdy/vdx= 32/vsf - svhinc. these parameters are used for both scaling up and down algo_sd[7:4] 6e 80 w the msb 2-bit of algo_sd is defined as algorithm for scaling algorithm selection, where salgo = 0 chooses linear interpolation, salgo = 1 selects bell shape interpolation,
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 53 register function addr(hex ) msb:odd lsb:even reset value (hex) r/w description salgo = 2 selects sinc (default), salgo = 3 chooses pixel replicate. the bit 5 v_sd_on, is used for enabling v scaledown operations, i.e. vsd_on=0 (default) for scaling up, vsd_on=1 for scaling down the bit 4 h_sd_on, is used for enablin g h scaledown operations, i.e. hsd_on=0 (default) for scaling up, hsd_on=1 for scaling down vnemu(6:0) 6f 01 w vdeno(6:0) 70 01 w vnume/vdeno = vsf sdnhdx[6:0], sdnhdy[6:0], sdnhhinc[5:0] 71,72,73 01,00, 08 w for scaling down, sdnhhinc= floor ( 8/hsf ) , sdnhdy/sdnhdx= 8/hsf - sdnhhinc. note that we should set shdx[6:0]=01, shdy[6:0]=00, and shhinc[5:0]=20 for scaling down operation. also note that sdnhdx[6:0]=01, sdnhdy[6:0]=00, and sdnhhinc[5:0] =08 should be set for scaling up operation. fread e9 00 r read out the freezed data fvaddr eb,ea 00 w freeze vertical start address fhaddr ed,ec 00 w freeze horizontal start address registers 74-78 are for auto adjustments misc clamp pulse starting setting register (clamp_sta) 7a 8a w the starting point of clamp pulse setting. counted from the falling edge of s y nc p ulse b y iaclk. clamp pulse width setting register (clamp_width) 7b 80 w the width of clamp pulse by iaclk (1.2us is suggested) auto adjust register the 1st line of the window for sod calculation (awv1start[10:0]) 21,20 00,00 w the last line of the window for sod calculation (awv1end[10:0]) 23,22 00,00 w the 1st pixel of the window for sod calculation (awh1start[10:0]) 25,24 00,00 w the last pixel of the window for sod calculation (awh1end [10:0]) 27,26 00,00 w define the range of intra-frame sod operation. note that awvstart and awhstart are counted from the starting ed g e of in p ut vsync/hsync pulse. awvstart should be larger than 3 and awhstart should be lar g er than 6. the 1st line of the window for sod calculation (awv2start[10:0]) 83,82 00,00 w the last line of the window for sod calculation (awv2end[10:0]) 85,84 00,00 w the 1st pixel of the window for sod calculation (awh2start[10:0]) f7,f6 00,00 w define the range of intra-frame sod operation. note that awvstart and awhstart are counted from the starting ed g e of in p ut vsync/hsync pulse. awvstart should be larger than 3 and awhstart should be lar g er
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 54 register function addr(hex ) msb:odd lsb:even reset value (hex) r/w description the last pixel of the window for sod calculation (awh2end [10:0]) f9,f8 00,00 w than 6. the resulting value of the sum of the sod calculation (asum[31:0]) 28,29, 2a,2b 00,00 r the resulting value of sum of difference of the sod calculation (asod[31:0]) 2c,2d 2e,2f 00,00 r the resulting value of the sum of the sod calculation. pxl value 76,75,74 00,00 r report the data value of specified position in pxl_address (x9a~9d) 74 : r 75 : g 76 : b reserved 77 00 w sod mask register (sodmask[7:0]) 78 00 w the msb 3 bit of sodmask[7:0], sod_mask_bit[2:0], is used to select the number of msb bits for sod operation. the default state is all channels are calculated. registers 79-7b (pwm and clamp) are described at misc, and registers 7c-7f (ihv_delay4wrap) are described at input window. maximum threshold (argb_max[7:0]) 80 7f w designate the threshold value for r, g, and b. the result will be available at aml_overflow (reg. 0xac) minimum threshold (argb_min[7:0]) 81 00 w designate the threshold value for either r, g, or b the mth line chosen to check the horizontal start & end (amlnum[ 10:0]) 89,88 00,00 r/ w designated by host, the auto adjust function searches (horizontally) the startin g and endin g pixels along the mth line. if 00 are programmed, the entire screen is covered for h_start and h_end points searching. the 1st line exceeds argb_min (avstart[10:0]) 8b,8a 00,00 r the 1st line exceeds argb_min. the last line exceeds argb_min (avend[10:0]) 8d,8c 00,00 r the last line exceeds argb_min. the 1st pixel exceeds argb_min position at mth line (amlhsta[10:0]) 8f,8e 00,00 r the 1st pixel exceeds argb_min p osition at mth line the last pixel of the mth line exceeds argb_min position (amlhend[10:0]) 91,90 00,00 r if sod_intra = 1 (sod, sum of difference), the number read should minus one. the rgb value of the 1st pixel of the mth line that exceeds argb_min (amlhstar[7:0],amlhstag[7:0] ,amlhstab[7:0]) 92,93,94 00,00,0 0 r if sod_intra = 1 (sod, sum of difference), the values are not available. the rgb value of the last pixel of the mth line that exceeds argb_min(amlhendr[7:0],aml hendg[7:0], amlhendb[7:0]) 95,96,97 00,00,0 0 r if sod_intra = 1 (sod, sum of difference), the values are not available
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 55 register function addr(hex ) msb:odd lsb:even reset value (hex) r/w description reserved 98 w vhperlow_16bit 99 00 the msb 4-bit of reg 99 is vperiod[3:0] and the lsb 4-bit is hperiod[3:0] pxl address 9b,9a 9d,9c w t he pxl_report function (xod[2]) can read the pixel value via pxl_value (x74 ~ x76) of specified postion via pxl_address ( x9a ~ 9d ). note: 9a 9b v position (y) 9c 9d h position (x) t he p osition are counted and ali g ned to v/hsync. vsep_spt 9f,9e 00,60 r programmable sampling point, this is a 12-bits register for csync separation registers a0-a7 are for iclk/pclk measurement reserved a8 r px_as_aline[3:0] a9 02 w the threshold of number of pixels that will be treated as an active line. the lsb 4-bit will be used. the default number is at least 2 p ixels will be treated as an active line. - ab, aa 00,10 r reserved an overflow had been detected on the m-th line (aml_overflow) (0: b channel, 1: g channel, 2: r channel, other bits are reserved) ac 00 r an overflow (a value larger or equal to argb_max[7:0] at reg 0x80) of color value in r, g, or b has been detected on mth line iclk/pclk measure parameter iclk measure (xpulse_by_iclk[15:0]) a1,a0 00,00 r the number the xtal pulse (programmable at the len g th of 1k, 2k, 3k,and 4k ) counted b y the iclk. pclk measure (xpulse_by_pclk[15:0]) a3,a2 00,00 r the number the xtal pulse (programmable at the len g th of 1k, 2k, 3k,and 4k ) counted b y the pclk. - a5,a4 00,00 r reserved brightness, contrast, gamma, clut, and alpha blending rcontrast[7:0] ae 00 w 256 level contrast control for r rbrightness[7:0] af 00 w 256 level brightness control for r gcontrast[7:0] b0 00 w 256 level contrast control for g gbrightness[7:0] b1 00 w 256 level brightness control for g gamma table r write address (grwaddr[7:0]) b2 00 w each gamma-correction table is a 256x8 lut (look-up table) which can be u p dated b y writing to these ports. b y p ro g rammin g this p ort 256 times the 256x8 lut is u p dated completely. gamma table g write address (ggwaddr[7:0]) b3 00 w same as r channel. gamma table b write address (gbwaddr[7:0]) (the table write address will be auto increased upon each writing) b4 00 w same as r channel.
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 56 register function addr(hex ) msb:odd lsb:even reset value (hex) r/w description clut write address (clutwaddr[7:0]) b5 00 w the 16x16 color lut can be written b y host from this port. first the lower byte data are sent to an entity, then followed b y the hi g her byte data, color index 0 is filled followed b y color index 1 until color index 15, the final one. the 16-bit output of this color lut will be interpreted as the rgb565 format, i.e. the msb 5 bits are for r, the middle 6 bits for g, and the lsb 5 bits for b. starting address of osd look up table osd_lut_addr[3:0] f3 00 w t he startin g address for osd look u p table to be updated clut alpha blending (clut_alpha[4:0]) b6 00 w the msb of clut_alpha is used indirectl y for the interpretation of the i signal of osd, while clut_alpha[3:0] is used to select the blending factor between the output of the clut and the output of the dithered video. clut_alpha[4]= 0: the content of clut is rgb565. 1: the content of clut is rgb555. and the lsb of g will be interpreted as lsb of g of clut read out =0: means alpha blending off. =1: means alpha blending on. if alpha blending is on and any one of the internal/external osd/background color is activated, the final video of p anel out will be equal to video*clut_alpha[3:0]/16+clut* (1-clut_alpha[3:0]/16). for the case that clut_alpha[3:0]=0, the final video of p anel is directly from the output of clut. and for clut_alpha[3:0]=6, the final video is video*6/16+clut*12/16. bcontrast[7:0] b7 00 w 256 level contrast control for b the in p ut si g nal is multiplied by a value (( contrast+128 ) mod 256)/128 where contrast is in the range of [255,0]. bbrightness[7:0] b8 00 w 256 level brightness control for b 7f ->127,..., 01 -> 1, 00 -> 0, ff -> -1,..., 80 -> -128 i.e. the input data is added by a 2,s complement value gcstart[7:0] b9 00 define gamma table starting address ppll program parameter registers 0xba,0xbb,oxbe, please refer to the section of clock system for ppll setting. in/out hs/vs parameter
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 57 register function addr(hex ) msb:odd lsb:even reset value (hex) r/w description panel hsync total (ph_total[10:0]) c5,c4 00,00 w the lsb 11-bit defines the total value of lcd panel hs. the value is counted b y pclk. usin g the results of iclk/pclk measurement ( see reg. a0-a3), this parameter can be calculated via ih_total * iclk_period = vsf * ph_total * pclk_period. panel hsync delay (ph_delay[10:0]) c7,c6 00,00 w the lsb 11-bit defines the delay of dis p la y output hs from ivs. the value is counted b y pclk. input sfdl delay (iv_sfdl[5:0]) c9 01 w the register defines the value of line dela y of an internal signal sfdl . the value is counted from the falling edge of in p ut vs b y ihs. this delayed signal is used to s y nchronize the p anel vs. registers ca-cf are described in osd parameters registers d0-df are described in ha rdware mode detection parameters peaking control peak_ctrl1 e0 1a w peak_ctrl1[7]: 0: disable peaking function 1: enable peaking function peak_ctrl1[6]: 0: normal hactive output 1: delay hactive 1 clock than normal peak_ctrl1[5:4]: gain of bpf1 00: divided by four 01: divided by two others: divided by one peak_ctrl1[3:2]: gain of bpf2 00: divided by four 01: divided by two others: divided by one peak_ctrl1[1:0]: gain of hpf 00: divided by four 01: divided by two others: divided by one
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 58 register function addr(hex ) msb:odd lsb:even reset value (hex) r/w description peak_ctrl2 e1 44 w {peak_ctrl2[7], peak_ctrl2[3], peak_ctrl3[7]} : 000: all frame are processed by peaking 001: not processed at frame edge within 4 pixels 010: not processed at frame edge within 5 pixels 011: not processed at frame edge within 6 pixels 100: not processed at frame edge within 7 pixels 101: not processed at frame edge within 8 pixels 110: not processed at frame edge within 9 pixels 111: not processed at frame edge within 10 pixels peak_ctrl2[6:4]/peak_ctrl[2:0]: gain of filter1 and filter2 000: zero 001: filter_out / 4 010: filter_out / 2 011: filter_out *3 / 4 100: filter_out 101: filter_out *5 /4 110: filter_out *6 /4 111: filter_out *2 peak_ctrl3 e2 44 w peak_ctrl3[7]: described in e1h peak_ctrl3[6:4]: gain of filter3 000: zero 001: filter_out / 4 010: filter_out / 2 011: filter_out *3 / 4 100: filter_out 101: filter_out *5 /4 110: filter_out *6 /4 111: filter_out *2 peak_ctrl3[3:0]: coring value 0000: zero 1000: 64 0001: 8 1001: 72 0010: 16 1010: 80 0011: 24 1011: 88 0100: 32 1100: 96 0101: 40 1101: 104 0110: 48 1110: 112 0111: 56 1111: 120 peak_ctrl4 e3 a0 w peak_ctrl4[7]: reg_dec_en 0: without mapping 1: with mapping peak_ctrl4[6:0]: curve1 of mapping range1 peak_ctrl5 e4 40 w peak_ctrl5[7]: reserved peak_ctrl5[6:0]: curve2 of mapping range1 peak_ctrl6 e5 60 w peak_ctrl6[7]: reserved peak_ctrl6[6:0]: curve3 of mapping range1
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 59 the register map of hardware mode detector: name: (bit) 7 6 5 4 3 2 1 0 hwdcnt(d0h) enhwd selde hwd_inten vint_ren vint_fen vcnt-sel hvsep1 hvsep0 83h r/w r/w r/w r/w r/w r/w r/w r/w intsrc(d1h) - - vint_r vint_f vfchanged vpolcha hfchanged hpolcha 00h - - r r r r r r syncstatus(d2h) - falt fwhalf odd_even vpresence hpresence vpolarity hpolarity 00h - r r r r r r r hperhigh(d3h) hper15 hper14 hper13 hper12 hper11 hper10 hper9 hper8 00h r r r r r r r r hperlow(d4h) hper7 hper6 hper5 hper4 hper3 hper2 hper1 hper0 00h r r r r r r r r vperhigh(d5h) vper15 vper14 vper13 vper12 vper11 vper10 vper9 vper8 00h r r r r r r r r vperlow(d6h) vper7 vper6 vper5 vper4 vper3 vper2 vper1 vper0 00h r r r r r r r r pulcnt(d7h) envout enhout voutmode1 voutmode0 houtmode1 houtmode0 htolerance1 htolerance0 c0h r/w r/w r/w r/w r/w r/w r/w r/w hvpwth(d8h) vpw4 vpw3 vpw2 vpw1 vpw0 hpw2 hpw1 hpw0 43h r/w r/w r/w r/w r/w r/w r/w r/w poutpolpos(d9h) vshift5 vshift4 vshift3 vshift2 vshift1 vshift0 voutpol houtpol 00h r/w r/w r/w r/w r/w r/w r/w r/w hmdmisc(dah) - macvis_on vfrmcnt1 vfrmcnt0 vcdelay1 vcdelay0 fidpol eoenable 60h - r/w r/w r/w r/w r/w r/w r/w hfphigh(dbh) hfp9 hfp8 hfp7 hfp6 hfp5 hfp4 hfp3 hfp2 4ah r/w r/w r/w r/w r/w r/w r/w r/w hvfplow(dch) vtolerance1 vtolerance0 vfp3 vfp2 vfp1 vfp0 hfp1 hfp0 18h r/w r/w r/w r/w r/w r/w r/w r/w vfphigh(ddh) vfp11 vfp10 vfp9 vfp8 vfp7 vfp6 vfp5 vfp4 32h r/w r/w r/w r/w r/w r/w r/w r/w vsepproglo(deh) vsep_spt7 vsep_spt6 vsep_spt5 vsep_spt4 vsep_spt3 vsep_spt2 vsep_spt1 vsep_spt0 32h r/w r/w r/w r/w r/w r/w r/w r/w vsepproghi(dfh) vsync_dly3 vsync_dly2 vsync_dly1 vsync_dly0 vsep_spt11 vsep_spt10 vsep_spt9 vsep_spt8 32h r/w r/w r/w r/w r/w r/w r/w r/w ia-hardware mode detector control register, 0xd0 ~ 0xdf hwdcnt (hardware mode detector control register, 0xd0 ) default 7 enhwd enable hardware mode detectorenable 0: disabled; (clock is sleeping also to save power) 1: enabled 1 6 selde selection between de and csync input (de and csync are mutually exclusive) (if selde = 1, hvsep is automatically set as 00) 0: csync is selected 1: de is selected 0 5 hwd_inten enable interrupt from one of sync signal changes: h/v frequency or polarity change 0: disabled 1: enabled 0 4 vint_ren enable interrupt at vsync leading edge 0: disabled 1: enabled 0
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 60 3 vint_fen enable interrupt at vsync trailing edge 0: disabled 1: enabled 0 2 vcnt_sel select vperiod count by time or by line number 0: by time; i.e. vclk (hclk/11) 1: by h line 0 1~0 hvsep1-hvsep 0 multiplexer to select vsync source: 00: csync/de + vsyncsep 01: hsync + vsyncsep 10: hsync + vsyncsep xor vsync 11: hsync + vsync (if selde = 1, 00 is chosen, i.e. de is treated as one kind of csync) 11 intsrc (interrupt source, 0xd1) default 5 vint_r interrupt is caused by vsync leading edge 0: vsync leading edge not happened 1: vsync leading edge happened 0 4 vint_f interrupt is caused by vsync trailing edge 0: vsync trailing edge not happened 1: vsync trailing edge happened 0 3 vfchanged interrupt is caused by v frequency change 0: v frequency not changed 1: v frequency changed 0 2 vpolcha interrupt is caused by v polarity change 0: v polarity not changed 1: v polarity changed 0 1 hfchanged interrupt is caused by h frequency change 0: h frequency not changed 1: h frequency changed 0 0 hpolcha interrupt is caused by h polarity change 0: h polarity not changed 1: h polarity changed 0 syncstatus (h/v sync signals status, 0xd2) default 6 falt indicate whether field contains alternating n / n+1 lines 0: not this format 1: yes 0 5 fwhalf indicate whether field contains n+1/2 lines (half line) 0: not this format 1: yes 0 4 odd_even indicate current field is odd field or even field 0: odd field/1st field; with earlier h sync 1: even field/2nd field; with lagged h sync 0 3 vpresence the presence status of vsync 0: not present 1: present 0 2 hpresence the presence status of hsync/csync 0: not present 1: present 0 1 vpolarity the polarity of vsync 0: positive polarity (pulse width smaller than 1/4 of vperiod) 1: negative polarity (pulse width larger than 3/4 of vperiod) 0 0 hpolarity the polarity of hsync 0: positive polarity (pulse width smaller than 1/4 of hperiod) 1: negative polarity (pulse width larger than 3/4 of hperiod) 0 hperiod (0xd3, 0xd4) default 15~0 hperiod 64 hsync line periods hx0000 vperiod (0xd5, 0xd6) default
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 61 15~0 vperiod vsync period ( the period of one frame ) hx2000 pulcnt (h/v output pulse control register, 0xd7) default 7 envout enable vsyncout pulse 0: disabled; vsyncout is kept low 1: enabled 1 6 enhout enable hsyncout pulse 0: disabled; hsyncout is kept low 1: enabled 1 5~4 voutmode1 - voutmode0 00 (freerun) : the period of vsyncout is programmed by 12-bit counter, vfper. 01 (loopth_st) : the leading edge of vsyncout will be roughly close to the incoming vsync, however, snapped to the leading edge of incoming hsyncout. 10 (r_aligned) : the leadin g ed g e of vs y ncout will be shifted ahead o r after the leading edge of vsync based on the programmed value, however, snapped to the leading edge of incoming hsyncout. 11 (loopth) : completely copy the shape of the incoming vsync 00 3~2 houtmode1 - houtmode0 00 ( freerun) : the period of hsyncout is programmed by 10-bit counter, hfper. the pulse width is programmed by 3-bit register, hpw. 01 (loopth_st) : the hsyncout will be snapped to the rising/falling edge of incoming hsync; if the pulse of incoming hsync is missing, an artificial pulse will be inserted with pulse width defined by hpw. 10 (r_aligned) : the leading edge of the output hsync is aligned with the incoming hsync. however, the pulse width is defined by hpw. 11 (loopth) : completely copy the shape of the incoming hsync 00 1~0 htolerance1 - htolerance0 the definition of h frequency/count deviation is programmable: 00: +/- 4 counts 01: +/- 8 counts 10: +/- 16 counts 00 hvpwth (the pulse width of h/v sync output, 0xd8) default 7~3 vpw4 -vpw0 there are 16 programmable values to set the pulse width of vsyncout 2 * ( vpw + 1 ) => 2, 4, 6, .... 30, 32 h lines. 01000 2~0 hpw2 - hpw0 the pulse width of hsync output: 000: 4(0.28us) 001: 8(0.59us) 010: 16(1.12us) 011: 20(1.40us) 100: 24(1.68us) 101: 28(1.96us) 110: 32(2.23us) 111: 36(2.51us) 011 poutpolpos (the polarity of h/v sync ou tput and the position of vsyncout, 0xd9) default 7~2 vshift5 - vshift0 vshift(5) = 1 (leading edge of vsyncout ahead the incoming vsync): vshift4 - vshift0= 00000 ~ 11111 : ahead 1 ~ 32 h lines vshift(5) = 0 (leading edge of vsyncout lag the incoming vsync): vshift4 - vshift0= 00000: kept at the same position as incoming vsync 00001 ~ 11111 : after 1 ~ 31 h lines 000000 1 voutpol the polarity of vsyncout 0: positive polarity (pulse width smaller than 1/4 of vsyncout) 1: negative polarity (pulse width larger than 3/4 of vsyncout) 0 0 houtpol the polarity of hsyncout 0: positive polarity (pulse width smaller than 1/4 of hsyncout) 1: negative polarity (pulse width larger than 3/4 of hsyncout) 0 hmdmisc (hmd misc register, 0xda) default 6 macvis_on macro vision on 0: turn off 1: turn on 0 5~4 vfrmcnt vertical frame counter set (iteration check value if have any change) 11 3~2 vcdelay delay counter set of vsyncout (delay output is vcdelayout) 00
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 62 1 fid_pol field polarity 0: (default) keep the original field polarity 1: inverse the current field polarity 0 0 eoenable the selection of even/odd flag. 0: (default) even/odd flag will be disabled. 1: even/odd flag will be readable and used 0 hfphigh (0xdb) default 7~0 hfperiod9 - hfperiod2 the high nibble of h free run period (9 - 0) 01001010 hvfplow (0xdc) default 7~6 vtolerance1 - vtolerance0 the definition of v frequency/count deviation is programmable: 00: +/- 4 counts 01: +/- 8 counts 10: +/- 16 counts 11: +/- 88 counts 00 5~2 vfperiod3 - vfperiod0 the low nibble of v free run period (11 - 0) 0110 1~0 hfperiod1 - hfperiod0 the low nibble of h free run period (9 - 0) 00 vfphigh (0xdd) default 7~0 vfperiod11 - vfperiod4 the high nibble of v free run period (11 - 0) 00110010 vsepproglo (0xde) default 7~0 vsep_spt_l the low nibble of vsync separation position (7 - 0) from csync 01100000 vsepproghi (0xdf) default 7~4 vsync_dly process vsync with clock delay 0000 3~0 vsep_spt_m the high nibble of vsync separation position (11 - 8) from csync 0000
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 63 5.7 tcon 5.7.1 the tcon example timing for gpo[0,1,2] *for the mode of no logical operation : *for the mode with latched pol?s value : 5.7.2 tcon timing - the tcon horizontal timing relationship of data, starting and other related signals dac _ r/g/b pfrp sth ( l/r ) oeh clkv oev blank blank blank gpo_hstart gpo_hactive gpo_vstart gpo_vend gpo_vstart+1 ? gpon gpo_hstart gpo_vstart gpo_vend gpo_vstart+1 gpon gpo_vstart+2 ? gpo_hstart gpo_hstart pol
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 64 5.7.2.1 register definition for tcon the 2-wire serial bus slave address of this chip is 1111011b or 1111111b. the table is listed: low nibble of subaddress addr (hex) 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 reserved tc_ maj or1 tc_ maj or2 tc_ maj or4 tc_ maj or5 1 gpo0 programming registers reserved lp programming registers 2 gpo1 programming registers reserved clkv programming registers 3 sth programming pol programming clkh programming registers 4 stv programming and clkv_vstart ahead_de sth width reserved 5 gpo2 programming registers reserved 6 reserved high nibble 7~f reserved tc_major1 (tcon major control register 1, 02h) default 7 lp_phase the phase selection of the edges of lp pulse signal with respect to the internal pixel clock. 0: (default) aligned with the rising edge of clkh. 1: aligned with the falling edge of clkh. note: internal pixel clock, clkh, will send to pin 63 which can be inverted with programmable delay. please refer to phclk_inv and phclk_op in register outctr0 or 03hex. 0 6 ti_mode stv start position (this bit also defines the clkv start position) 0: (default) normal start. 1: late start. 0 5 pol_mode the toggle duration of pol (polarity output signal) pin 0: (default) toggle per h line. 1: toggle per 2h lines 0 4 clkh_off the clkh signal can be turned off during the non-active display period. 0: (default) clkh output signal is always available. 1: clkh signal will be turned off during the non-active display period. the duration is defined by the tc_clkh_vstart, tc_clkh_vactive, tc_clkh_hstart, and tc_clkh_hactive registers. 0 tc_major1 (tcon major control register 1, 02h) default 3 rgb_bus_skew data bus group delay for emi reduction. 0: (default) the data bus of rgb signals are distributed as 0.0/1.0/2.0ns. 1: the data bus of rgb signals are distributed as 0.0/2.0/4.0ns. 0 2 dir_scmd the driver ic r/l direction control. 0: start pulse for gate driver(active l to r), sthl output , sthr high impedance. 1: start pulse for gate driver(active r to l), sthl high impedance , sthr output. 0 1 inverse_hms the inversion of hmso and hmse signals. 0
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 65 0: (default) no inversion. 1: the hmso and hmse signals will be inversed 0 enable_hms the operation of hmso and hmse signals. 0: the hmso and hmse signals will be kept at high or low (in a word, hmso=hmse=inverse_hms). 1: (default ) the o p eration of hmso and hmse is enabled. ( note: hmso and hmse will be calculated separately) 1 tc_major2 (tcon major control register 2, 03h) default 7 inverse_clkv the inversion of clkv clock. 0: (default) no inversion. 1: inversed clkv. 0 6 tcon_8bit tcon can be configured for 8-bit or 6-bit (for each rgb) tft-lcd panel 0: (default) tcon is configured for 8-bit (for each rgb) panel. 1: tcon is configured for 6-bit (for each rgb) panel 0 5 single_hms this register defines the operation of hms is based on two single port (24/18 bits) or one dual port (48/36 bits) 0 : even/odd is calculated separately 1 : even/odd is calculated together 0 1 phsi_pol this bit control the phs in 0: (default) phs in 1: invert phs in 0 0 tcon_en this bit control the tcon function. 0: disable tcon 1: enable tcon 0 tc_major4 (tcon major control register4, 05h) default 7 dir_scmd2 the gate ic u/d direction control. 0: start pulse for gate driver(active u to d), stvu output , stvd high impedance. 1: start pulse for gate driver(active d to u), stvu high impedance , stvd output. 0 6 phso_pol panel h sync output pol 0: (default) phs 1: invert phs 0 5 pvso_pol panel h sync output pol 0: (default) pvs 1: invert pvs 0 4 lp_pol latch pulse pol 0: (default) lp 1: invert lp 0 3 frn_fid_pol frn field id pol 0: field = 0 1: field = 1 0 2 ext_fid_pol ext field id pol 0: (default) fid in 1: invert fid in 0 1 fid_sel field id select 0: free-run. 1: external 0 0 pixc_fhsredge pixel count from hs rising edge 0: falling 1: rising 0 tc_major5 (tcon major control register5, 06h) default 7 lkill_en line drop enable 0
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 66 0: (default) disable 1: enable 6,5 lk_mode line drop mode 00: (default) ?1 line number 01: same line number 10: +1 line number 11: reserved 0 2 r_b_swap r/b channel swap 0: (default) original rgb channel 1: swap r/b channel 0 1 frn_gradient free run gradient pattern select 0: normal (no free run gradient pattern 1: free run gradient pattern enable 0 0 pol_inv_rgb rgb inverted by pol 0: (default) disable 1: enable (invert rgb) 0 register function addr (hex) msb:odd lsb:even reset value r/w description timing control parameter hex reserved 00-01 00 w major feature control register tc_major1[7:0] 02 00 w major programming features of the timing controller 1 major feature control register tc_major2[7:0] 03 00 w major programming features of the timing controller 2 major feature control register tc_major3[7:0] 04 00 w major programming features of the timing controller 3 major feature control register tc_major4[7:0] 05 00 w major programming features of the timing controller 4 major feature control register tc_major5[7:0] 06 00 w major programming features of the timing controller 5 reserved 07-0c 00 w lk_count 0d 00 w line drop counter lk_vstart 0f,0e 00,00 w line drop start gpo0 horizontal start tc_gpo0_hstart[10:0] 11, 10 00,94 w define the gpo0 horizontal start counter value. gpo0 horizontal active tc_gpo0_hactive[10:0] 13, 12 02,94 w define the gpo0 horizontal active duration counter value. gpo0 vertical start tc_gpo0_vstart[10:0] 15, 14 00,01 w define the gpo0 vertical start counter value. gpo0 vertical end tc_gpo0_vend[10:0] 17, 16 03,00 w define the gpo0 vertical end duration counter value. gpo0 control register tc_gpo0_control[7:0] 18 00 w define the gpo0 control value. tc_gpo0_control[1:0] defines = 00 : no logical operation = 01 : inverted = 10 : latch pol?s value = 11 : latch pol?s value, and then inverted reserved 19 00 w lp horizontal start tc_lp_hstart[10:0] 1b, 1a 01,28 w define the lp signal horizontal start counter value. lp horizontal active tc_lp_hactive[10:0] 1d, 1c 00,1f w define the lp signal horizontal active duration counter value.
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 67 register function addr (hex) msb:odd lsb:even reset value r/w description lp vertical end tc_lp_vend[10:0] 1f, 1e 03,00 w define the lp signal vertical end counter value. gpo1 horizontal start tc_gpo1_hstart[10:0] 21, 20 00,94 w define the gpo1 horizontal start counter value. gpo1 horizontal active tc_gpo1_hactive[10:0] 23, 22 02,94 w define the gpo1 horizontal active duration counter value. gpo1 vertical start tc_gpo1_vstart[10:0] 25, 24 00,01 w define the gpo1 vertical start counter value gpo1 vertical end tc_gpo1_vend[10:0] 27, 26 03,00 w define the gpo1 vertical end duration counter value. gpo1 control register tc_gpo1_control[7:0] 28 00 w define the gpo1 control value tc_gpo1_control[3:0] = 0000 : no logical operation = 0001 : inverted = 0010 : latched pol?s value = 0011 : latched pol?s value, and then inverted reserved 29 00 w clkv horizontal start tc_clkv_hstart[10:0] 2b, 2a 02,00 w define the clkv signal horizontal start counter value. clkv horizontal active tc_clkv_hactive[10:0] 2d, 2c 01,00 w define the clkv signal horizontal active duration counter value. clkv vertical end tc_clkv_vend[10:0] 2f, 2e 03,01 w define the clkv signal vertical end counter value. note: the vertical start of the clkv signal is defined by the position of stv pulse (so called ti_mode ). also the v start value of clkv is defined at tc_stvclkv_vstrat[3:0]. sth horizontal start tc_sth_hstart[10:0] 31, 30 00,93 w define the sth signal horizontal start counter value. sth vertical end tc_sth_vend[10:0] 33, 32 03,00 w define the sth signal vertical end counter value pol horizontal start tc_pol_hstart[10:0] 35, 34 02,00 w define the pol signal horizontal start counter value. note: the pol si g nal can be to gg led ever y h line or every 2h lines. pol vertical end tc_pol_vend[10:0] 37, 36 03,01 w define the pol signal vertical end counter value. clkh horizontal start tc_clkh_hstart[10:0] 39, 38 00,94 w define the clkh horizontal start counter value. note: to save power consumption, clkh can be deactivated during the non-active display period. r. clkh horizontal end tc_clkh_hend[10:0] 3b, 3a 02,94 w define the clkh horizontal end duration counter value. clkh vertical start tc_clkh_vstart[10:0] 3d, 3c 00,01 w define the clkh vertical start counter value. clkh vertical end tc_clkh_vend[10:0] 3f, 3e 03,00 w define the clkh vertical end duration counter value. stv horizontal start tc_stv_hstart[10:0] 41, 40 00,94 w define the stv signal horizontal start counter value. stv horizontal active tc_stv_hactive[11:0] 43, 42 00,14 w define the stv signal horizontal active counter value stv and clkv vertical start tc_stvclkv_vstrat[7:0] 44 11 w define the vertical start counter value of stv and clkv. tc_stvclkv_vstrat[3:0] is for the v start value of clkv and tc_stvclkv_vstrat[7:4] is for the v start value of stv
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 68 register function addr (hex) msb:odd lsb:even reset value r/w description tc_lnum_ahead_de[10:0] 46,45 00,01 w define the number of lines that is ahead dena; the vertical value is calculated from this point tc_sth_width[7:0] 47 00 w define the width of sth pulse reserved 48-4f 00 w gpo2 horizontal start tc_gpo2_hstart[10:0] 51, 50 00,94 w define the gpo2 horizontal start counter value. gpo2 horizontal active tc_gpo2_hactive[10:0] 53, 52 02,94 w define the gpo2 horizontal active duration counter value gpo2 vertical start tc_gpo2_vstart[10:0] 55, 54 00,01 w define the gpo2 vertical start counter value. gpo2 vertical end tc_gpo2_vend[10:0] 57, 56 03,00 w define the gpo2 vertical end duration counter value gpo2 control register tc_gpo2_control[7:0] 58 00 w define the gpo2 control value. tc_gpo2_control[1:0] = 0000 : no logical operation = 0001 : inverted = 0010 : latch pol?s value = 0011 : latch pol?s value, and then inverted reserved 59-ff 00 w 5.8 dc-dc and pwg 3 pairs of pwg and feedback signals are provided to control the dc-dc converter for high voltage generation. the basic structure is: dc-dc (analog) dcpwm1/3 dcfbk1/3 dcpwm2 dcfbk2 xosc pwg2 pwg3 pwg1 clk_en (clock divider) osc_div[2:0] ck_en ck_en ck_en pwm_in1 pwm_in2 pwm_in3 cken_on fc[3:0] vset_en mode[1:0] inv en dcdc_en
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 69 pwg_outosc1 (pwg clock input control register 1, a6h) default 5:4 mode[1:0] the dc-dc force the pwg1?s pulse width increment or decrement (recommended to use 11b) 00 3 dcdc_dis 1: dcdc disable (low power consumption) 0: enable dcdc 1 2:0 pwg1_osc_div pwg1 clock divide ratio 011 pwg_outosc2 (pwg clock input control register 2, a7h) default 5:4 mode[1:0] the dc-dc force the pwg2?s pulse width increment or decrement (recommended to use 11b) 01 3 - reserved 0 2:0 pwg2_osc_div pwg2 clock divide ratio 000 pwg_outosc3 (pwg clock input control register 3, a8h) default 5:4 mode[1:0] the dc-dc force the pwg3?s pulse width increment or decrement (recommended to use 11b) 01 3 - reserved 0 2:0 pwg3_osc_div pwg3 clock divide ratio 001 pwg_outctr1 (pwg pulse output control register 1, fah) default 7:4 fc[3:0] 16 pwg1 pulse modulation parameters 1000 3 pwg_rstn 0: pwg1 reset 1: pwg1 no reset 0 2 cken_on 0: pwg1?s xosc is disabled 1: pwg1?s xosc will be controlled by ck_en 1 1 vset_en 0: pwg1?s vset from dc-dc is disabled 1: pwg1?s vset from dc-dc is enabled 0 0 inv 0: pwg1?s output no invert 1: pwg1?s output invert 0 pwg_outctr2 (pwg pulse output control register 2, fbh) default 7:4 fc[3:0] 16 pwg2 pulse modulation parameters 1000 3 pwg_rstn 0: pwg2 reset 1: pwg2 no reset 0 2 cken_on 0: pwg2?s xosc is disabled 1: pwg2?s xosc will be controlled by ck_en 1 1 vset_en 0: pwg2?s vset from dc-dc is disabled 1: pwg2?s vset from dc-dc is enabled 0 0 inv 0: pwg2?s output no invert 1: pwg2?s output invert 1 pwg_outctr3 (pwg pulse output control register 3, fch) default 7:4 fc[3:0] 16 pwg3 pulse modulation parameters 1001 3 pwg_rstn 0: pwg3 reset 1: pwg3 no reset 0 2 cken_on 0: pwg3?s xosc is disabled 1: pwg3?s xosc will be controlled by ck_en 1 1 vset_en 0: pwg3?s vset from dc-dc is disabled 1: pwg3?s vset from dc-dc is enabled 0 0 inv 0: pwg3?s output no invert 1: pwg3?s output invert 0
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 70 6 electrical specifications 6.1 absolute maximum ratings symbol parameter rating unit v dd3 io power supply -0.3 to 3.6 v v dd2 core power supply -0.25 to 2.75 v v in input voltage -0.3 to v cc3 +0.3 v v out output voltage -0.3 to v cc3 +0.3 v t stg storage temperature -40 to 125 o c *stress beyond the absolute maximum ratings may cause permanent damage to the devices. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under dc characteristics is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 recommended operating condition symbol parameter min. typ. max. unit v dd3 io dc power supply 3.0 3.3 3.6 v v dd2 core dc power supply 2.25 2.5 2.75 v v in dc input voltage 0 v cc3 v t oc operating classic temperature 0 25 70 o c 6.3 dc characteristics v dd3 =3.0~3.6v; v dd2 =2.25~2.75v, v ss =0v; t oc =0~+70 o c symbol parameter condition min. typ. max. unit i run supply current in run state v cc3 =3.3v, v cc2 =2.5v, t.b.f. ma i pd power saving supply current power down mode t.b.f. a v ih low-level input voltage 0.7* v cc v v il high-level input voltage 0.3* v cc3 v i il input leakage current -1.0 1.0 a v oh low-level output voltage 2.4 v v ol high-level output voltage 0.4 v 6.4 adc?s dc characteristics item min. typ. max. unit supply voltage (vdda/vdd) 3.0 3.3 3.6 v resolution 10 bit dnl 0.5 lsb inl 1 lsb offset error 0.5 lsb input range 0 1(rgb) 1.3(video) v clock 20 mhz 6.5 dac?s dc characteristics vcca33_dac1=vcca33_dac2=vcca33_dac3=3.3v; rl=37.5ohm, cl=10pf; temp=25oc parameter symbol min typ max unit operating range vcca33_dac1 vcca33_dac2 vcca33_dac3 3.0 3.3 3.6 v max per channel output current 18.6 ma
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 71 max output voltage 0.7 v integral non-linearity error inl -1 lsb 0.5 lsb +1 lsb lsb differential non-linearity error dnl -1 lsb 0.5 lsb +1 lsb lsb
vi deo decoder for por table lcd display VP77 (ver. 0.96) confidential 72 7 package outline lqfp128 (14mm x 14mm x 1.4mm)

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