1 EDI8F321024C rev. 7 3/98 eco #9798 EDI8F321024C 1024kx32 sram module features pin configurations and block diagram 1024kx32 bit cmos static random access memory ? access times: 15, 17, 20, 25, and 35ns ? individual byte selects ? fully static, no clocks ? ttl compatible i/o high density package ? 72 pin zip, no. 175 ? 72 lead simm, no. 176 (angle) ? 72 lead simm, no. 356 (straight) ? common data inputs and outputs single +5v (10%) supply operation the EDI8F321024C is a high speed 32 megabit static ram module organized as 1024k words by 32 bits. this module is constructed from eight 1024kx4 static rams in soj packages on an epoxy laminate (fr4) board. four chip enables (e?-e3) are used to independently enable the four bytes. reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. the EDI8F321024C is offered in 72 pin zip and 72 lead simm packages, which enable 32 megabits of memory to be placed in less than 1.3 square inches of board space. all inputs and outputs are ttl compatible and operate from a single 5v supply. fully asynchronous circuitry requires no clocks or refreshing for operation and provides equal access and cycle times for ease of use. pins pd1- pd4, are used to identify module memory density in applications where alternate modules can be interchanged. nc pd3 vss pd2 dq8 dq9 dq10 dq11 a? a1 a2 dq12 dq13 dq14 dq15 vss a15 e1 e3 a17 g dq24 dq25 dq26 dq27 a3 a4 a5 vcc a6 dq28 dq29 dq30 dq31 a18 nc nc pd4 pd1 dq? dq1 dq2 dq3 vcc a7 a8 a9 dq4 dq5 dq6 dq7 w a14 e? e2 a16 vss dq16 dq17 dq18 dq19 a10 a11 a12 a13 dq20 dq21 dq22 dq23 vss a19 nc 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 a?-a19 w g e? e1 e2 e3 dq?-dq3 dq8-dq11 dq16-dq19 dq24-dq27 20 4 dq4-dq7 dq12-dq15 dq20-dq23 dq28-dq31 4 4 4 4 4 4 4 electronic designs incorporated ? one research drive ? westborough, ma 01581 usa ? 508-366-5151 ? fax 508-836-4850 ? http://www.electronic-designs.com pd1 & pd3 = vss pd2 & pd4 = open pin names a?-a19 address inputs e?-e3 chip enables w write enable g output enable dq?-dq31 common data input/output vcc power (+5v10%) vss ground nc no connection 1024kx32 static ram cmos, high speed module
2 EDI8F321024C rev. 7 3/98 eco #9798 EDI8F321024C 1024kx32 sram module absolute maximum ratings* recommended dc operating conditions dc electrical characteristics parameter sym conditions min typ max units operating power supply current icc1 w, e = vil, ii/o = 0ma, min cycle 1880 ma standby (ttl) power supply current icc2 e 3 vih, vin vil or vin 3 vih 480 ma full standby power supply current icc3 e 3 vcc-0.2v 80 ma cmos vin 3 vcc-0.2v or vin 0.2v input leakage current ili vin = 0v to vcc -- -- 80 a output leakage current ilo v i/o = 0v to vcc -- -- 20 a output high voltage voh ioh = -4.0ma 2.4 -- -- v output low voltage vol iol = 8.0ma -- -- 0.4 v capacitance truth table (f=1.0mhz, vin=vcc or vss) parameter sym max unit address lines ci 60 pf data lines cd/q 20 pf chip enable line cc 20 pf write line cn 60 pf ac test conditions *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter sym min typ max units supply voltage vcc 4.5 5.0 5.5 v supply voltage vss 0 0 0 v input high voltage vih 2.2 -- 6.0 v input low voltage vil -0.3 -- 0.8 v (note: for tehqz,tghqz and twlqz, cl = 5pf) voltage on any pin relative to vss -0.5v to 7.0v operating temperature ta (ambient) commercial. 0c to +70c industrial -40c to +85c storage temperature, plastic -55c to +125c power dissipation 7.0 watts output current. 20 ma input pulse levels vss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load 1ttl, cl = 30pf *typical: ta = 25c, vcc = 5.0v e w g mode output power h x x standby high z icc2/icc3 l h l read dout icc1 l l x write din icc1 output l h h deselect high z icc1 these parameters are sampled, not 100% tested.
3 EDI8F321024C rev. 7 3/98 eco #9798 EDI8F321024C 1024kx32 sram module ac characteristics read cycle read cycle 2 - w high note 1: parameter guaranteed, but not tested. symbol 15ns 17ns 20ns 25ns 35ns parameter jedec alt. min max min max min max min max min max units read cycle time tavav trc 15 17 20 25 35 ns address access time tavqv taa 15 17 20 25 35 ns chip enable access telqv tacs 15 17 20 25 35 ns chip enable to output in low z (1) telqx tclz 3 3 3 3 3 ns chip disable to output in high z (1) tehqz tchz 7 7 10 12 15 ns output hold from address change tavqx toh 3 3 3 3 3 ns output enable to output valid tglqv toe 7 8 8 10 12 ns output enable to output in low z (1) tglqx tolz 0 0 0 0 0 ns output disable to output in high z(1) tghqz tohz 7 7 8 10 12 ns read cycle 1 - w high, g, e low tavav tavqv tavqx data 2 a q address 1 address 2 data 1 tghqz telqv telqx e g q tehqz a tavav tglqv tglqx tavqv
4 EDI8F321024C rev. 7 3/98 eco #9798 EDI8F321024C 1024kx32 sram module note 1: parameter guaranteed, but not tested. write cycle 1 - w controlled symbol 15ns 17ns 20ns 25ns 35ns parameter jedec alt. min max min max min max min max min max units write cycle time t avav twc 15 17 20 25 35 ns chip enable to end of write telwh tcw 10 15 15 20 25 ns twleh tcw 10 15 15 20 25 ns address setup time tavwl tas 0 0000 ns tavel tas 0 0000 ns address valid to end of write tavwh taw 10 15 15 20 25 ns taveh taw 10 15 15 20 25 ns write pulse width twlwh twp 12 12 15 20 25 ns teleh twp 12 12 15 20 25 ns write recovery time twhax twr 0 0000 ns tehax twr 0 0000 ns data hold time twhdx tdh 3 3300 ns tehdx tdh 3 3300 ns write to output in high z (1) twlqz twhz 0 70808012015 ns data to write time tdvwh tdw 7 10 12 15 20 ns tdveh tdw 7 10 12 15 20 ns output active from end of write (1) twhqx twlz 3 3333 ns a e w d q tavav telwh tavwh twlwh tavwl tdvwh twhdx twhqx high z twlqz data valid twhax ac characteristics write cycle
5 EDI8F321024C rev. 7 3/98 eco #9798 EDI8F321024C 1024kx32 sram module a w e d q tavav tavel tehax tdveh tehdx teleh taveh data valid high z twleh write cycle 2 - e controlled
6 EDI8F321024C rev. 7 3/98 eco #9798 EDI8F321024C 1024kx32 sram module 2.045 1.992 .062 r. .125 min. max. .360 .225 min. .250 .062 r. .680 max. p1 .050 typ. 4.255 max. .250 typ. 3.750 3.984 .400 electronic designs incorporated ? one research drive ? westborough, ma 01581 usa ? 508-366-5151 ? fax 508-836-4850 ? http://www.electronic-designs.com electronic designs inc. reserves the right to change specifications without notice. cage no. 66301 part number speed (ns) package no. EDI8F321024C15mnc 15 176 EDI8F321024C17mnc 17 176 EDI8F321024C20mnc 20 176 EDI8F321024C25mnc 25 176 EDI8F321024C35mnc 35 176 edi8g321024c15mnc 15 176 edi8g321024c17mnc 17 176 edi8g321024c20mnc 20 176 edi8g321024c25mnc 25 176 edi8g321024c35mnc 35 176 ordering information note: to order gold simm option refer to "edi8g321024cxxmnc"; to order tin plated contacts option refer to "EDI8F321024Cxxmnc". package descriptions part number speed (ns) package no. EDI8F321024C17mzc 17 175 EDI8F321024C20mzc 20 175 EDI8F321024C25mzc 25 175 EDI8F321024C35mzc 35 175 EDI8F321024C15mzc 15 175 EDI8F321024C17mmc 17 356 EDI8F321024C20mmc 20 356 EDI8F321024C25mmc 25 356 EDI8F321024C35mmc 35 356 edi8g321024c15mmc 15 356 edi8g321024c17mmc 17 356 edi8g321024c20mmc 20 356 edi8g321024c25mmc 25 356 edi8g321024c35mmc 35 356 j2 j1 j4 r.# p1 .250 .600 max. .250 typ. .050 typ. 2.045 .062 r. (2x) .125 dia (2x) .125 min. .360 max. 4.255 max 3.750 164 3.984 1.992 .400 .360 max. .100 typ. p1 .050 .050 3.865 max. .020 .100 typ. .052 typ. .250 typ. .175 .125 .590 max. package no.175 72 pin zip package no. 176 72 lead angled simm package no. 356 72 pin simm
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