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general description the BW1244X is a cmos 10bit d/a converter for general application. this digital to analog converter has a r-2r ladder structure. its maximum conversion rate is 0.5msps. typical applications hard disk drive (hdd) battery operated instruments motor control systems general applications functional block diagram features resolution : 10bit differential linearity error : 1.0 lsb integral linearity error : 2.0 lsb maximum conversion rate : 0.5msps low power consumption : 9.9mw power down mode operation temperature range : 0o c ~ 70o c power supply : 3.3v single 3.3v 10bit 0.5msps dac BW1244X samsung electronics co. ltd ver 1.8 (april 2002) no responsibility is assumed by sec for its use nor for any infringements of patents or other rights of third parties that may result from its use. the content of this datasheet is subject to change without any notice. d[9:0] r-2r ladder vrb vrt vout pwrdn vddd vssd vdda vssa vbba op amp _ +
sec asic BW1244X 3.3v 10bit 0.5msps dac analog core pin description name i/o type i/o pad pin description d[9:0] di picc_bb digital input data (10bit) d[9] : msb , d[0] : lsb pwrdn di picc_bb power down (active low) vrt ab pia_bb voltage reference top vrb ab pia_bb voltage reference bottom vout ao poa_bb analog voltage output vddd dp vddd digital power (+3.3v) vssa dg vssd digital ground (0.0v) vdda ap vdda analog power (+3.3v) vssa ag vssa analog ground (0.0v) vbba ag vbba analog sub bias (0.0v) core configuration i/o type abbr. ai : analog input di : digital input ao : analog output do : digital output ab : analog bidirectional db : digital bidirectional ap : analog power dp : digital power ag : analog ground dg : digital ground 2/11 vrt vrb d[9:0] vout vddd vssd vdda vssa vbba pwrdn BW1244X
sec asic BW1244X 3.3v 10bit 0.5msps dac analog absolute maximum ratings characteristics symbol value unit supply voltage vdd (vdda,vddd) 4.5 v analog output voltage vout vss to vdd v digital input voltage d[9:0] vss to vdd v reference voltage vrt vrb vdd vss v operating temperature range topr 0to70 c notes : 1. absolute maximum rating specifies the values beyond which the device may be damaged permanently. exposure to absolute maximum rating conditions for extended periods may affect reliability. each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. all voltages are measured with respect to vss(vssa or vssd or vbba) unless otherwise specified. 3. 100pf capacitor is discharged through a 1.5k ? resistor (human body model) recommended operating conditions characteristics symbol min typ max unit supply voltage vdda - vssa vddd - vssd 3.15 3.3 3.45 v supply voltage difference vdda - vddd -0.1 0.0 0.1 v reference voltage vrt vrb - 0.0 - - 3.3 - v digital input 'low' voltage digital input 'high' voltage vil vih - 0.7 vdd - - 0.3 vdd - v operating temperature topr 0 - 70 c note : it is strongly recommended that to avoid power latch-up all the supply pins(vdda,vddd) be driven from the same source. 3/11
sec asic BW1244X 3.3v 10bit 0.5msps dac analog dc electrical characteristics (converter specifications : vdda=vddd=3.3v, vssa=vssd=vbba=0v, pwrdn=high, top=25 c, vrt=3.3v, vrb=0.0v unless otherwise specified.) characteristics symbol min typ max unit conditions resolution bit - - 10 bits - differential linearity error dle - 0.3 0.5 lsb - integral linearity error ile - 1.5 2.0 lsb - zero scale error 1 v zse - 3 6 mv vrt=3.3v , vrb=0.0v full scale voltage error 2 v fse - 4 11 mv maximum output voltage vo max 3.280 3.290 3.297 v vo max = vout(d[9:0]=high) v lsb =vo max / 1023 lsb size v lsb 3.206 3.220 3.223 mv note 1 : v zse =vout(d[9:0]=low) - vrb 2:v fse =vout(d[9:0]=high) - {(vrt-vrb) 1023/1024 + vrb} ac electrical characteristics (converter specifications : vdda=vddd=3.3v, vssa=vssd=vbba=0v, load cap=25pf top=25c, vrt=3.3v, vrb=0.0v unless otherwise specified.) characteristics symbol min typ max unit conditions maximum conversion rate f c - - 0.5 msps data rate = 0.5mhz dynamic supply current ivdd1 - 3 - ma ivdd1 = i vdda +i vrt +i vddd data rate = 0.5mhz dynamic supply current (power down mode) ivdd2 - - 10 ua ivdd2 = i vdda +i vddd data rate = 0.5mhz pwrdn=low analog output delay td 90 100 105 ns data rate = 0.5mhz data : all low all high analog output rise time tr 100 107 115 ns data rate = 0.5mhz data : all low all high analog output fall time tf 94 100 107 ns data rate = 0.5mhz data : all high all low analog output settling time ts 160 240 350 ns data rate = 0.5mhz data : all low all high vrt = vdd/2 powerdownontime ton 50 53 60 ns pwrdn : high low power down off time toff 155 165 180 ns pwrdn : low high 4/11
sec asic BW1244X 3.3v 10bit 0.5msps dac analog timing diagram 1. output delay measured from the 50% point of the rising edge of input data to the full scale transition. 2. settling time measured from the 50% point of full scale transition to the output remaining within 1/2 lsb. 3. output rise/fall time measured between the 10% and 90% points of full scale transition. functional description 1. the BW1244X has a r-2r ladder block for 10bit and an op amp block for driving output. 2. the r-2r ladder block generates binary weighted voltage (vrt/2 1 ,vrt/2 2 ,vrt/2 3 ,?vrt/2 10 ) corresponding to digital input data for n-bit dac and output total voltage is summing of each values. 3. in output voltage, v msb =vrt/2 1 v lsb =vrt/2 10 vout vrt vrb ( d[n]) vrb 10 n n0 9 2 2 = ? + = 4. output of the r-2r ladder block is driven by op amp. 5. in power down mode, only analog current (i vdda ) is reduced. data vout td 0000000000 1111111111 50% 50% vout 0000000000 1111111111 0000000000 10% 90% data tr tf vout 0000000000 1111111111 0000000000 50% 0.5lsb data ts pwrdn vout ton 50% toff 50% 0.5lsb 0.5lsb 0.0v 5/11
sec asic BW1244X 3.3v 10bit 0.5msps dac analog core evaluation guide testability whether you use mux or the internal logic for testability, it is required to be able to select the values of digital inputs ( d[9:0] ). see above figure. only if it is, you can check the main function. ( linearity ) normal test condition : vrt=3.3v , vrb=0.0v , pwrdn=high location description ct 10uf tantalum capacitor cc 0.1uf ceramic capacitor 6/11 host dsp core mux test path 10 10 10 cc ct vddd vssd vdda vssa vbba 3.3v gnd 3.3v gnd cc ct ct cc ct cc 3.3v gnd 0.0v gnd d[9:0] pwrdn vrt vrb vout BW1244X vout
sec asic BW1244X 3.3v 10bit 0.5msps dac analog phantom cell information BW1244X pwrdn vddd vssd d[9] d[8] d[7] d[6] d[5] d[0] d[1] d[2] d[3] d[4] vrt vrb vout vbba vssa vdda BW1244X pwrdn vddd vssd d[9] d[8] d[7] d[6] d[5] d[0] d[1] d[2] d[3] d[4] vrt vrb vout vbba vssa vdda pin name property pin usage pin layout guide d[9:0] di internal / external 1. digital input signal lines must have same length to reduce propagation delay. pwrdn di internal / external vrt ab external 1. voltage reference lines (vrt and vrb) must be wide metal to reduce voltage drop of metal lines. 2. vout signal should not be crossed by any signals and should not run next to digital signals to minimize capacitive coupling between the two signals. vrb ab external vout ao internal / external vdda ap external 1. it is recommended that you use thick analog power metal. when connected to pad, the path should be kept as short as possible. 2. digital power and analog power are separately used. vssa ag external vddd dp external vssd dg external vbba ag external 1. when the core block is connected to other blocks, it must be double guard-ring using n-well and p+ active to remove the substrate and coupling noise. in that case, the power metal should be connected to pad directly. 2. the bulk power is used to reduce the influence of substrate noise. 7/11
sec asic BW1244X 3.3v 10bit 0.5msps dac analog package configuration vrb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 vddd vddd vssd vssd nc nc nc d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] nc nc nc nc nc vrb vrb vbba vbba nc nc vssz vssz vddz vddz nc vssa vssa vdda vdda nc nc nc nc pwrdn vout vout nc nc vrt vrt cc ct l1 l2 cc ct + + 0.0v 3.3v (vss) (vdd) + ct cc pwrdn vout vrt (3.3v typ.) (3.3v in normal operation) ct + cc (0.0v typ.) d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] l3 l5 l4 BW1244X d[9] d[8] vrb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 vddd vddd vssd vssd nc nc nc d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] nc nc nc nc nc vrb vrb vbba vbba nc nc vssz vssz vddz vddz nc vssa vssa vdda vdda nc nc nc nc pwrdn vout vout nc nc vrt vrt 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 vddd vddd vssd vssd nc nc nc d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] nc nc nc nc nc vrb vrb vbba vbba nc nc vssz vssz vddz vddz nc vssa vssa vdda vdda nc nc nc nc pwrdn vout vout nc nc vrt vrt cc ct l1 l2 cc ct + + 0.0v 3.3v (vss) (vdd) + ct cc pwrdn vout vrt (3.3v typ.) (3.3v in normal operation) ct + cc (0.0v typ.) d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] l3 l5 l4 BW1244X d[9] d[8] location description ct 10uf tantalum capacitor cc 0.1uf ceramic capacitor l1~l5 ferrite bead ( 0.1mh ) 8/11
sec asic BW1244X 3.3v 10bit 0.5msps dac analog package pin description name pin no i/o type pin description vddd 1,2 dp digital power (3.3v) vssd 3,4 dg digital ground (0.0v) d[9:0] 8~17 di digital input data vrb 23,24 ab voltage reference bottom (0.0v) vrt 25,26 ab voltage reference top (3.3v) vout 29,30 ao analog voltage output pwrdn 31 di power down mode (low active) vdda 36,37 ap analog power (3.3v) vssa 38,39 ag analog ground (0.0v) vddz 41,42 ap pad power (3.3v) vssz 43,44 ag pad ground (0.0v) vbba 47,48 ag analog sub bias (0.0v) nc 5,6,7,18,19 20,21,22,27 28,32,33,34 35,40,45,46 do no connection i/o type abbr. ai : analog input di : digital input ao : analog output do : digital output ab : analog bidirectional db : digital bidirectional ap : analog power dp : digital power ag : analog ground dg : digital ground 9/11
sec asic BW1244X 3.3v 10bit 0.5msps dac analog pc board layout consideration 1. pc board considerations to minimize noise on the power lines and the ground lines, the digital inputs need to be shielded and decoupled. this trace length between groups of vdd (vdda,vddd) and vss (vssa,vssd) pins should be as short as possible so as to minimize inductive ringing. 2. supply decoupling and planes for the decoupling capacitor between the power line and the ground line, 0.1uf ceramic capacitor is used in parallel with a 10uf tantalum capacitor. the digital power plane(vddd) and analog power plane(vdda) are connected through a ferrite bead, and also the digital ground plane(vssd) and the analog ground plane(vssa). this ferrite bead should be located within 3inches of the BW1244X. the analog power plane supplies power to the BW1244X of the analog output pin and related devices. 10 / 11
sec asic BW1244X 3.3v 10bit 0.5msps dac analog feedback request we appreciate your interest in out products. if you have further questions, please specify in the attached form. thank you very much. dc / ac electrical characteristic characteristics min typ max unit remarks supply voltage v power dissipation mw resolution bits analog output voltage v operating temperature c output load capacitor pf output load resistor k ? integral non-linearity error lsb differential non-linearity error lsb maximum conversion rate mhz voltage output dac reference voltage top bottom v analog output voltage range v digital input format binary code or 2's complement code current output dac analog output maximum current ma analog output maximum signal frequency khz reference voltage v external resistor for current setting(rset) ? pipeline delay sec - do you want to power down mode? - do you want to internal reference voltage(bgr)? - which do you want to serial input data type or parallel input data type? - do you need 5v power supply in your system? 11 / 11
sec asic BW1244X 3.3v 10bit 0.5msps dac analog history card version date modified items comments ver 1.6 00.02.22 version updates all pictures and texts are modified with dac1236x's datasheet. the format ant fonts of datasheet are same with dac1236x's datasheet. reference datasheet dac1236x ver 1.7 01.03.28 version updated page 4 : power down mode current ( 10ua) page 11 : c k ?( output load resistor) ver 1.8 02.04.23 version updated page 5 : functional description is modified. page 6 : functon function page 7 : phantom cell is modified and table is added. page 8 : vrt pin number is modified (18 25) page 11 : w ?

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