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xcr5032c 32 macrocell cpld with enhanced clocking product specification supersedes data of 1998 jun 24 ic27 data handbook 1998 jul 23 integra ted circuits
philips semiconductors xcr5032c 32 macrocell cpld with enhanced clocking product specification 2 1998 jul 23 8532080 19774 features ? industry's first totalcmos ? pld both cmos design and process technologies ? fast zero power (fzp ? ) design technique provides ultra-low power and very high speed ? high speed pin-to-pin delays of 6ns ? ultra-low static power of less than 75 m a ? dynamic power that is 70% lower at 50mhz than competing devices ? 100% routable with 100% utilization while all pins and all macrocells are fixed ? deterministic timing model that is extremely simple to use ? up to 6 clocks with programmable polarity at every macrocell ? 5 volt, in-system programmable (isp) using a jtag interface on-chip supervoltage generation isp commands include: enable, erase, program, verify supported by multiple isp programming platforms 4 pin jtag interface (tck, tms, tdi, tdo) jtag commands include: bypass, idcode ? support for complex asynchronous clocking ? innovative xpla ? architecture combines high speed with extreme flexibility ? 1000 erase/program cycles guaranteed ? 20 years data retention guaranteed ? logic expandable to 37 product terms ? pci compliant ? advanced 0.5 m e 2 cmos process ? security bit prevents unauthorized access ? design entry and verification using industry standard and philips cae tools ? reprogrammable using industry standard device programmers ? innovative control term structure provides either sum terms or product terms in each logic block for: programmable 3-state buffer asynchronous macrocell register preset/reset up to 2 asynchronous clocks ? programmable global 3-state pin facilitates `bed of nails' testing without using logic resources ? available in both plcc and tqfp packages table 1. pz5032c features pz5032c usable gates 1000 maximum inputs 36 maximum i/os 32 number of macrocells 32 i/o macrocells 32 buried macrocells 0 propagation delay (ns) 6.0 packages 44-pin plcc, 44-pin tqfp description the pz5032c cpld (complex programmable logic device) is a member of the fast zero power (fzp ? ) family of cplds from philips semiconductors. these devices combine high speed and zero power in a 32 macrocell cpld. with the fzp ? design technique, the pz5032c offers true pin-to-pin speeds of 6ns, while simultaneously delivering power that is less than 75 m a at standby without the need for `turbo bits' or other power down schemes. by replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in plds since the bipolar era) with a cascaded chain of pure cmos gates, the dynamic power is also substantially lower than any competing cplde70% lower at 50mhz. these devices are the first totalcmos ? plds, as they use both a cmos process technology and the patented full cmos fzp ? design technique. for 3v applications, philips also offers the high speed pz3032c cpld that offers pin-to-pin speeds of 8ns. the philips fzp ? cplds introduce the new patent-pending xpla ? (extended programmable logic array) architecture. the xpla ? architecture combines the best features of both pla and pal ? type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. the xpla ? structure in each logic block provides a fast 6ns pal ? path with 5 dedicated product terms per output. this pal ? path is joined by an additional pla structure that deploys a pool of 32 product terms to a fully programmable or array that can allocate the pla product terms to any output in the logic block. this combination allows logic to be allocated efficiently throughout the logic block and supports as many as 37 product terms on an output. the speed with which logic is allocated from the pla array to an output is only 2ns, regardless of the number of pla product terms used, which results in worst case t pd 's of only 8ns from any pin to any other pin. in addition, logic that is common to multiple outputs can be placed on a single pla product term and shared across multiple outputs via the or array, effectively increasing design density. the pz5032c cplds are supported by industry standard cae tools (cadence, exemplar logic, minc, mentor, synopsys, synario, viewlogic, orcad), using text (abel, vhdl, verilog) and/or schematic entry. design verification uses industry standard simulators for functional and timing simulation. development is supported on personal computer, sparc, and hp platforms. device fitting uses either minc or philips semiconductors-developed tools. the pz5032c cpld is reprogrammable using industry standard device programmers from vendors such as data i/o, bp microsystems, sms, and others. the pz5032c also includes an industry-standard, ieee 1149.1, jtag interface through which in-system programming (isp) and reprogramming of the device are supported. pal is a registered trademark of advanced micro devices, inc.
philips semiconductors product specification pz5032c 32 macrocell cpld with enhanced clocking 1998 jul 23 3 ordering information order code description description drawing number pz5032cs6a44 44-pin plcc, 6ns t pd commercial temp range, 5 volt power supply, 5% sot187-2 pz5032cs7a44 44-pin plcc, 7.5ns t pd commercial temp range, 5 volt power supply, 5% sot187-2 pz5032cs10a44 44-pin plcc, 10ns t pd commercial temp range, 5 volt power supply, 5% sot187-2 pz5032cs6bc 44-pin tqfp, 6ns t pd , commercial temp range, 5 volt power supply, 5% sot376-1 pz5032cs7bc 44-pin tqfp, 7.5ns t pd commercial temp range, 5 volt power supply, 5% sot376-1 pz5032cs10bc 44-pin tqfp, 10ns t pd commercial temp range, 5 volt power supply, 5% sot376-1 xpla ? architecture figure 1 shows a high level block diagram of a 32 macrocell device implementing the xpla ? architecture. the xpla ? architecture consists of logic blocks that are interconnected by a zero-power interconnect array (zia). the zia is a virtual crosspoint switch. each logic block is essentially a 36v16 device with 36 inputs from the zia and 16 macrocells. each logic block also provides 32 zia feedback paths from the macrocells and i/o pins. from this point of view, this architecture looks like many other cpld architectures. what makes the coolrunner ? family unique is what is inside each logic block and the design technique used to implement these logic blocks. the contents of the logic block will be described next. logic block architecture figure 2 illustrates the logic block architecture. each logic block contains control terms, a pal array, a pla array, and 16 macrocells. the 6 control terms can individually be configured as either sum or product terms, and are used to control the preset/reset and output enables of the 16 macrocells' flip-flops. in addition, two of the control terms can be used as clock signals (see macrocell architecture section for details). the pal array consists of a programmable and array with a fixed or array, while the pla array consists of a programmable and array with a programmable or array. the pal array provides a high speed path through the array, while the pla array provides increased product term density. each macrocell has 5 dedicated product terms from the pal array. the pin-to-pin t pd of the pz5032c device through the pal array is 6ns. this performance is equivalent to the fastest 5 volt cpld available today. if a macrocell needs more than 5 product terms, it simply gets the additional product terms from the pla array. the pla array consists of 32 product terms, which are available for use by all 16 macrocells. the additional propagation delay incurred by a macrocell using 1 or all 32 pla product terms is just 2ns. so the total pin-to-pin t pd for the pz5032c using 6 to 37 product terms is 8ns (6ns for the pal + 2ns for the pla). sp00550 logic block i/o 36 16 16 36 16 16 mc0 mc1 mc15 i/o mc0 mc1 mc15 zia logic block figure 1. philips xpla cpld architecture
philips semiconductors product specification pz5032c 32 macrocell cpld with enhanced clocking 1998 jul 23 4 to 16 macrocells 6 5 control pal array 36 zia inputs pla array (32) sp00435a figure 2. philips xpla logic block architecture
philips semiconductors product specification pz5032c 32 macrocell cpld with enhanced clocking 1998 jul 23 5 macrocell architecture figure 3 shows the architecture of the macrocell used in the coolrunner ? pz5032c. the macrocell can be configured as either a d or t type flip-flop or a combinatorial logic function. a d-type flip-flop is generally more useful for implementing state machines and data buffering while a t-type flip-flop is generally more useful in implementing counters. each of these flip-flops can be clocked from any one of four sources. two of the clock sources (clk0 and clk1) are connected to low-skew, device-wide clock networks designed to preserve the integrity of the clock signal by reducing skew between rising and falling edges. clock 0 (clk0) is designated as a asynchronouso clock and must be driven by an external source. clock 1 (clk1) can be used as a asynchronouso clock that is driven by an external source, or as an aasynchronouso clock that is driven by a macrocell equation. both clk0 and clk1 can clock the macrocell flip-flops on either the rising edge or the falling edge of the clock signal. the other clock sources are two of the six control terms (ct2 and ct3) provided in each logic block. these clocks can be individually configured as either a product term or sum term equation created from the 36 signals available inside the logic block. the timing for asynchronous and control term clocks is different in that the tco time is extended by the amount of time that it takes for the signal to propagate through the array and reach the clock network, and the tsu time is reduced. please see the app note titled aunderstanding coolrunner clocking optionso for more detail. the six control terms of each logic block are used to control the asynchronous preset/reset of the flip-flops and the enable/disable of the output buffers in each macrocell. control terms ct0 and ct1 are used to control the asynchronous preset/reset of the macrocell's flip-flop. note that the power-on reset leaves all macrocells in the azeroo state when power is properly applied, and that the preset/reset feature for each macrocell can also be disabled. control terms ct2 and ct3 can be used as a clock signal to the flip-flops of the macrocells, and as the output enable of the macrocell's output buffer. control terms ct4 and ct5 can be used to control the output enable of the macrocell's output buffer. having four dedicated output enable control terms ensures that the coolrunner ? devices are pci compliant. the output buffers can also be always enabled or always disabled. all coolrunner ? devices also provide a global tri-state (gts) pin, which, when enabled and pulled low, will 3-state all the outputs of the device. this pin is provided to support ain-circuit testingo or abed-of-nailso testing. there are two feedback paths to the zia: one from the macrocell, and one from the i/o pin. the zia feedback path before the output buffer is the macrocell feedback path, while the zia feedback path after the output buffer is the i/o pin feedback path. when the macrocell is used as an output, the output buffer is enabled, and the macrocell feedback path can be used to feedback the logic implemented in the macrocell. when the i/o pin is used as an input, the output buffer will be 3-stated and the input signal will be fed into the zia via the i/o feedback path, and the logic implemented in the buried macrocell can be fed back to the zia via the macrocell feedback path. it should be noted that unused inputs or i/os should be properly terminated (see the section on terminations in this data sheet and the app note terminating unused coolrunner ? i/o pins ). init (p or r) d/t q sp00551 clk0 clk0 clk1 clk1 to zia gnd ct0 ct1 gts ct2 ct3 ct4 ct5 v gnd cc gnd pal pla figure 3. pz5032c macrocell architecture
philips semiconductors product specification pz5032c 32 macrocell cpld with enhanced clocking 1998 jul 23 6 simple timing model figure 4 shows the coolrunner ? timing model. the coolrunner ? timing model looks very much like a 22v10 timing model in that there are three main timing parameters, including t pd , t su , and t co . in other competing architectures, the user may be able to fit the design into the cpld, but is not sure whether system timing requirements can be met until after the design has been fit into the device. this is because the timing models of competing architectures are very complex and include such things as timing dependencies on the number of parallel expanders borrowed, sharable expanders, varying number of x and y routing channels used, etc. in the xpla ? architecture, the user knows up front whether the design will meet system timing requirements. this is due to the simplicity of the timing model. for example, in the pz5032c device, the user knows up front that if a given output uses 5 product terms or less, the t pd = 6ns, the t su = 4.5ns, and the t co = 5ns. if an output is using 6 to 37 product terms, an additional 2.5ns must be added to the t pd and t su timing parameters to account for the time to propagate through the pla array. totalcmos ? design technique for fast zero power philips is the first to offer a totalcmos ? cpld, both in process technology and design technique. philips employs a cascade of cmos gates to implement its sum of products instead of the traditional sense amp approach. this cmos gate implementation allows philips to offer cplds which are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. refer to figure 5 and table 2 showing the i dd vs. frequency of our pz5032c totalcmos ? cpld. output pin input pin sp00552 t pd_pal = combinatorial pal only t pd_pla = combinatorial pal + pla output pin input pin dq registered t su_pal = pal only t su_pla = pal + pla registered t co global clock pin figure 4. coolrunner ? timing model typical i dd (ma) frequency (mhz) sp00635 figure 5. i dd vs. frequency @ v dd = 5.0v table 2. i dd vs frequency v dd = 5.00v freq (mhz) 0 1 20 40 60 80 100 120 140 160 180 typical i dd (ma) 0.04 0.20 3.14 6.25 9.32 12.5 15.5 18.7 21.7 24.7 27.8
philips semiconductors product specification pz5032c 32 macrocell cpld with enhanced clocking 1998 jul 23 7 jtag testing capability jtag is the commonly-used acronym for the boundary scan test (bst) feature defined for integrated circuits by ieee standard 1149.1. this standard defines input/output pins, logic control functions, and commands which facilitate both board and device level testing without the use of specialized test equipment. the philips pz5032c devices use the jtag interface for insystem programming/reprogramming. although only a subset of the full jtag command set is implemented (see table 5), the devices are fully capable of sitting in a jtag scan chain. the philips pz5032c's jtag interface includes a tap port defined by the ieee 1149.1 jtag specification. as implemented in the philips pz5032c, the tap port includes four of the five pins (refer to table 3) described in the jtag specification: tck, tms, tdi, and tdo. the fifth signal defined by the jtag specification is trst* (test reset). trst* is considered an optional signal, since it is not actually required to perform bst or isp. the philips pz5032c saves an i/o pin for general purpose use by not implementing the optional trst* signal in the jtag interface. instead, the philips pz5032c supports the test reset functionality through the use of its power up reset circuit, which is included in all philips cplds. the pins associated with the tap port should connect to an external pullup resistor to keep the jtag pins from floating when they are not being used (see section on terminations). in the philips pz5032c, the four mandatory jtag pins each require a unique, dedicated pin on the device. the devices come from the factory with these i/o pins set to perform jtag functions, but through the software, the final function of these pins can be controlled. if the end application will require the device to be reprogrammed at some future time with isp, then the pins can be left as dedicated jtag functions, which means they are not available for use as general purpose i/o pins. however, unlike competing cplds, the philips pz5032c allow the macrocells associated with these pins to be used as buried logic when the jtag/isp function is enabled. this is the default state for the software, and no action is required to leave these pins enabled for the jtag/isp functions. if, however, jtag/isp is not required in the end application, the software can specify that this function be turned off and that these pins be used as general purpose i/o. because the devices initially have the jtag/isp functions enabled, the jedec file can be down loaded into the device once, after which the jtag/isp pins will become general purpose i/o. this feature is good for manufacturing because the devices can be programmed during test and assembly of the end product and yet still use all of the i/o pins after the programming is done. it eliminates the need for a costly, separate programming step in the manufacturing process. of course, if the jtag/isp function is never required, this feature can be turned off in the software and the device can be programmed with an industry-standard programmer, leaving the pins available for i/o functions. table 4 defines the dedicated pins used by the four mandatory jtag signals for each of the pz5032c package types. table 3. jtag pin description pin name description tck test clock output clock pin to shift the serial data and instructions in and out of the tdi and tdo pins, respectively. tms test mode select serial input pin selects the jtag instruction mode. tms should be driven high during user mode operation. tdi test data input serial input pin for instructions and test data. data is shifted in on the rising edge of tck. tdo test data output serial output pin for instructions and test data. data is shifted out on the falling edge of tck. the signal is tri-stated if data is not being shifted out of the device. table 4. pz5032c jtag pinout by package type device (pin number / macrocell #) device tck tms tdi tdo pz5032c 44-pin plcc 32/b8 13/a8 7/a3 38/b3 44-pin tqfp 26/b8 7/a8 1/a3 32/b3 table 5. pz5032c low-level jtag boundary-scan commands instruction (instruction code) register used description bypass (1111) bypass register places the 1 bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through the selected device to adjacent devices during normal device operation. the bypass instruction can be entered by holding tdi at a constant high value and completing an instruction-scan cycle. idcode (0001) boundary-scan register selects the idcode register and places it between tdi and tdo, allowing the idcode to be serially shifted out of tdo. the idcode instruction permits blind interrogation of the components assembled onto a printed circuit board. thus, in circumstances where the component population may vary, it is possible to determine what components exist in a product.
philips semiconductors product specification pz5032c 32 macrocell cpld with enhanced clocking 1998 jul 23 8 5-volt, in-system programming (isp) isp is the ability to reconfigure the logic and functionality of a device, printed circuit board, or complete electronic system before, during, and after its manufacture and shipment to the end customer. isp provides substantial benefits in each of the following areas: ? design faster time-to-market debug partitioning and simplified prototyping printed circuit board reconfiguration during debug better device and board level testing ? manufacturing multi-functional hardware reconfigurability for test eliminates handling of afine lead-pitcho components for programming reduced inventory and manufacturing costs improved quality and reliability ? field support easy remote upgrades and repair support for field configuration, re-configuration, and customization the philips pz5032c allows for 5-volt, in-system programming/reprogramming of its eeprom cells via its jtag interface. an on-chip charge pump eliminates the need for externally-provided supervoltages, so that the pz5032c may be easily programmed on the circuit board using only the 5-volt supply required by the device for normal operation. a set of low-level isp basic commands implemented in the pz5032c enable this feature. the isp commands implemented in the philips pz5032c are specified in table 6. please note that an enable command must precede all isp commands unless an enable command has already been given for a preceding isp command. terminations the coolrunner ? pz5032c cplds are totalcmos ? devices. as with other cmos devices, it is important to consider how to properly terminate unused inputs and i/o pins when fabricating a pc board. the pz5032c devices do not have on-chip termination circuits, so it is recommended that unused inputs and i/o pins be properly terminated. allowing unused inputs and i/o pins to float can cause the voltage to be in the linear region of the cmos input structures, which can increase the power consumption of the device. philips recommends the use of 10k w pull-up resistors for the termination. using pull-up resistors allows the flexibility of using these pins should late design changes require additional i/o. these unused pins may also be tied directly to v dd , but this will make it more difficult to reclaim the use of the pin, should this be needed by a subsequent design revision. when using the jtag/isp functions, it is also recommended that 10k w pull-up resistors be used on each of the four mandatory signals. letting these signals float can cause the voltage on tms to come close to ground, which could cause the device to enter jtag/isp mode at unspecified times. see the application notes jtag and isp in philips devices and terminating unused coolrunner ? i/o pins for more information. table 6. low level isp commands instruction (register used) instruction code description enable (isp shift register) 1001 enables the erase, program, and verify commands. erase (isp shift register) 1010 erases the entire eeprom array. program (isp shift register) 1011 programs the data in the isp shift register into the addressed eeprom row. verify (isp shift register) 1100 transfers the data from the addressed row to the isp shift register. the data can then be shifted out and compared with the jedec file. the outputs during this operation can be defined by the user.
philips semiconductors product specification pz5032c 32 macrocell cpld with enhanced clocking 1998 jul 23 9 jtag and isp interfacing a number of industry-established methods exist for jtag/isp interfacing with cpld's and other integrated circuits. the philips pz5032c supports the following methods: ? pc parallel port ? workstation or pc serial port ? embedded processor ? automated test equipment ? third party programmers ? high-end isp tools for more details on jtag and isp for the pz5032c, refer to the related application note: jtag and isp in philips cplds . programming specifications symbol parameter min. max. unit dc parameters v ccp v cc supply program/verify 4.5 5.5 v i ccp i cc limit program/verify 200 ma v ih input voltage (high) 2.0 v v il input voltage (low) 0.8 v v sol output voltage (low) 0.5 v v soh output voltage (high) 2.4 v tdo_i ol output current (low) 8 ma tdo_i oh output current (high) 8 ma ac parameters f max tck maximum frequency 10 mhz pwe pulse width erase 100 ms pwp pulse width program 10 ms pwv pulse width verify 10 m s init initialization time 100 m s tms_su tms setup time before tck 10 ns tdi_su tdi setup time before tck 10 ns tms_h tms hold time after tck 25 ns tdi_h tdi hold time after tck 25 ns tdo_co tdo valid after tck 40 ns
philips semiconductors product specification pz5032c 32 macrocell cpld with enhanced clocking 1998 jul 23 10 absolute maximum ratings 1 symbol parameter min. max. unit v dd supply voltage 2 0.5 7.0 v v i input voltage 1.2 v dd +0.5 v v out output voltage 0.5 v dd +0.5 v i in input current 30 30 ma i out output current 100 100 ma t j maximum junction temperature 40 150 c t str storage temperature 65 150 c notes: 1. stresses above those listed may cause malfunction or permanent damage to the device. this is a stress rating only. functional operation at these or any other condition above those indicated in the operational and programming specification is not implied. 2. the chip supply voltage must rise monotonically. operating range product grade temperature voltage commercial 0 to +70 c 5 5% v
philips semiconductors product specification pz5032c 32 macrocell cpld with enhanced clocking 1998 jul 23 11 dc electrical characteristics for commercial grade devices commercial: 0 c t amb +70 c; 4.75v v dd 5.25v symbol parameter test conditions min. max. unit v il input voltage low v dd = 4.75v 0.8 v v ih input voltage high v dd = 5.25v 2.0 v v i input clamp voltage 2 v dd = 4.75v, i in = 18ma 1.2 v v ol output voltage low v dd = 4.75v, i ol = 12ma 0.5 v v oh output voltage high v dd = 4.75v, i oh = 12ma 2.4 v i il input leakage current low v dd = 5.25v (except cko), v in = 0.4v 10 10 m a i ih input leakage current high v dd = 5.25v, v in = 3.0v 10 10 m a i il clock input leakage current v dd = 5.25v, v in = 0.4v 10 10 m a i ozl 3-stated output leakage current low v dd = 5.25v, v in = 0.4v 10 10 m a i ozh 3-stated output leakage current high v dd = 5.25v, v in = 3.0v 10 10 m a i ddq standby current v dd = 5.25v, t amb = 0 c 75 m a i ddd 1 dynamic current v dd = 5.25v, t amb = 0 c @ 1mhz 1 ma i ddd 1 dynamic current v dd = 5.25v, t amb = 0 c @ 50mhz 15 ma i os short circuit output current 2 1 pin at a time for no longer than 1 second 50 200 ma c in input pin capacitance t amb = 25 c, f = 1mhz 8 pf c clk clock input capacitance t amb = 25 c, f = 1mhz 5 12 pf c i/o i/o pin capacitance t amb = 25 c, f = 1mhz 10 pf note: 1. this parameter measured with a 16bit, loadable up/down counter loaded into every logic block, with all outputs disabled and unloaded. inputs are tied to v dd or ground. this parameter guaranteed by design and characterization, not testing. 2. this parameter guaranteed by design and characterization, not by test. ac electrical characteristics 1 for commercial grade devices commercial: 0 c t amb +70 c; 4.75v v dd 5.25v symbol parameter 6 7 10 unit symbol parameter min. max. min. max. min. max. unit t pd_pal propagation delay time, input (or feedback node) to output through pal 2 6 2 7.5 2 10 ns t pd_pla propagation delay time, input (or feedback node) to output through pal & pla 3 8 3 10 3 12.5 ns t co clock to out delay time 2 5.5 2 7 2 9 ns t su_pal setup time (from input or feedback node) through pal 3.5 5.5 8 ns t su_pla setup time (from input or feedback node) through pal + pla 5.5 8 10.5 ns t h hold time 0 0 0 ns t ch clock high time 3 4 5 ns t cl clock low time 3 4 5 ns t r input rise time 20 20 20 ns t f input fall time 20 20 20 ns f max1 maximum ff toggle rate 2 (1/t ch + t cl ) 167 125 100 mhz f max2 maximum internal frequency 2 (1/t supal + t cf ) 133 91 64 mhz f max3 maximum external frequency 2 (1/t supal + t co ) 111 80 59 mhz t buf output buffer delay time 1.5 1.5 1.5 ns t pdf_pal input (or feedback node) to internal feedback node delay time through pal 4.5 6 8.5 ns t pdf_pla input (or feedback node) to internal feedback node delay time through pal + pla 6.5 8.5 11 ns t cf clock to internal feedback node delay time 4 5.5 7.5 ns t init delay from valid v dd to valid reset 50 50 50 m s t er input to output disable 2, 3 11 12.5 15 ns t ea input to output valid 2 11 12.5 15 ns t rp input to register preset 2 11 12.5 15 ns t rr input to register reset 2 14 15.5 18 ns notes: 1. specifications measured with one output switching. see figure 6 and table 7 for derating. 2. this parameter guaranteed by design and characterization, not by test. 3. output c l = 5pf.
philips semiconductors product specification pz5032c 32 macrocell cpld with enhanced clocking 1998 jul 23 12 switching characteristics the test load circuit and load values for the ac electrical characteristics are illustrated below. v dd v in v out c1 r1 r2 s1 s2 component values r1 470 w r2 250 w c1 35pf measurement s1 s2 t pzh open closed t pzl closed closed t p closed closed note: for t phz and t plz c = 5pf, and 3-state levels are measured 0.5v from steady state active level. sp00476 sp00636 v dd = 5v, 25 c ns 6.00 5.60 5.20 4.80 4.40 4.00 12 4 8 12 16 typical figure 6. t pd_pal vs. outputs switching table 7. t pd_pal vs # of outputs switching v dd = 5.00v # of outputs 1 2 4 8 12 16 typical (ns) 4.2 4.4 4.6 4.9 5.0 5.2 voltage waveform 90% 10% 1.5ns 1.5ns +3.0v 0v t r t f measurements: all circuit delays are measured at the +1.5v level of inputs and outputs, unless otherwise specified. input pulses sp00368
philips semiconductors product specification pz5032c 32 macrocell cpld with enhanced clocking 1998 jul 23 13 pin descriptions pz5032c 44-pin plastic leaded chip carrier 1 6 7 17 18 28 29 39 40 pin function 1 in1 2 in3 3v dd 4 i/oa0ck1 5 i/oa1 6 i/oa2 7 i/oa3 (tdi) 8 i/oa4 9 i/oa5 10 gnd 11 i/oa6 12 i/oa7 13 i/oa8 (tms) 14 i/oa9 15 v dd pin function 16 i/oa10 17 i/oa11 18 i/oa12 19 i/oa13 20 i/oa14 21 i/oa15 22 gnd 23 v dd 24 i/ob15 25 i/ob14 26 i/ob13 27 i/ob12 28 i/ob11 29 i/ob10 30 gnd pin function 31 i/ob9 32 i/ob8 (tck) 33 i/ob7 34 i/ob6 35 v dd 36 i/ob5 37 i/ob4 38 i/ob3 (tdo) 39 i/ob2 40 i/ob1 41 i/ob0 42 gnd 43 in0ck0 44 in2gtsn plcc sp00546 pz5032c 44-pin thin quad flat package 44 1 11 12 22 23 33 34 pin function 1 i/oa3 (tdi) 2 i/oa4 3 i/oa5 4 gnd 5 i/oa6 6 i/oa7 7 i/oa8 (tms) 8 i/oa9 9v dd 10 i/oa10 11 i/oa11 12 i/oa12 13 i/oa13 14 i/oa14 15 i/oa15 pin function 16 gnd 17 v dd 18 i/ob15 19 i/ob14 20 i/ob13 21 i/ob12 22 i/ob11 23 i/ob10 24 gnd 25 i/ob9 26 i/ob8 (tck) 27 i/ob7 28 i/ob6 29 v dd 30 i/ob5 pin function 31 i/ob4 32 i/ob3 (tdo) 33 i/ob2 34 i/ob1 35 i/ob0 36 gnd 37 in0ck0 38 in2gtsn 39 in1 40 in3 41 v dd 42 i/oa0ck1 43 i/oa1 44 i/oa2 tqfp sp00547 package thermal characteristics philips semiconductors uses the temperature sensitive parameter (tsp) method to test thermal resistance. this method meets mil-std-883c method 1012.1 and is described in philips 1995 ic package databook . thermal resistance varies slightly as a function of input power. as input power increases, thermal resistance changes approximately 5% for a 100% change in power. figure 7 is a derating curve for the change in q ja with airflow based on wind tunnel measurements. it should be noted that the wind flow dynamics are more complex and turbulent in actual applications than in a wind tunnel. also, the test boards used in the wind tunnel contribute significantly to forced convection heat transfer, and may not be similar to the actual circuit board, especially in size. package q ja 44-pin plcc 49.8 c/w 44-pin tqfp 66.3 c/w 0 10 20 30 40 50 01234 5 percentage reduction in q ja (%) air flow (m/s) plcc/ qfp sp00419a figure 7. average effect of airflow on q ja
philips semiconductors product specification pz5032c 32 macrocell cpld with enhanced clocking 1998 jul 23 14 plcc44: plastic leaded chip carrier; 44 leads sot187-2
philips semiconductors product specification pz5032c 32 macrocell cpld with enhanced clocking 1998 jul 23 15 tqfp44: plastic thin quad flat package; 44 leads; body 10 x 10 x 1.0 mm sot376-1
philips semiconductors product specification pz5032c 32 macrocell cpld with enhanced clocking 1998 jul 23 16 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1998 all rights reserved. printed in u.s.a. date of release: 07-98 document order number: 9397 750 04176
data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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