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IXF440 multiport 10/100 mbps ethernet controller datasheet product features the IXF440 multiport 10/100 mbps ethernet controller (also called the IXF440) provides eight 10/100 mbps intelligent, high-performance mac ports. it includes network management support and is optimized for switch applications. integration ? eight ethernet 10/100 mbps mac ports ? onchip scrambler, descrambler, and pcs functions for 100base-x connection ? handles snmp and rmon counters ix bus ? supports a 4 gbps high bus bandwidth ? variable bus speed of 25 to 66 mhz operational, and from 16 mhz for testing ? interfaces a 64-bit bus with a 32-bit optional mode ? supports concurrent unidirectional 32-bit buses for transmit and receive in split ix bus mode ? provides transmit- and receive-independent 256-byte fifos for each of the eight ports ? offers a generic slave fifo interface ? supports little or big endian byte ordering ? supports transmit and receive byte alignment ? supports receive packet fragmentation on byte boundaries (replay feature) ? provides programmable transmit and receive bus thresholds ? appends packet status to received packet performance ? allows status register access without interrupting packet transfer ? enables early address filtering ability, with packet header preprocessing and vlan detection ability ? offers retry or ignore options following packet transmission errors ? supports automatic retransmission following excessive collisions ? provides programmable automatic discard of badly received packets such as runts, crc errors, and too long packets operational ? enables independent 10 or 100 mbps port operation ? provides full-duplex support ? enables standard flow-control functionality in full-duplex mode ? offers backpressure logic capability in half-duplex mode ? interfaces to standard mii connections ? supports 10base-t, 100base-tx, 100base-t4, and 100base-fx connections ? provides programmable crc generation and removal ? allows backoff limit programming ? provides full collision support, including jamming, backoff, and automatic retransmission ? complies with ieee 802.3 standard cpu interface ? supports fully programmable independent ports through a dedicated generic cpu port ? enables interrupt programming device ? optimized for switch, bridge, and router applications ? includes internal and external loopback capabilities ? provides software reset support ? supports jtag boundary scan ? low-power 3.3 v and 5 v tolerant cmos device ? 352-bga package pa rt nu m ber: 278 1 60-005 september, 2000
datasheet revision history date revision description 11/98 001 first intel version. 3/3/00 002 first update. 4/24/00 003 device name change to IXF440. describe operation in various ix bus modes. 5/25/00 004 changed to intel branding. 9/26/00 005 updates for v1.1 release of ixp1200 software. information in this document is provided in connection with intel products. no license, express or implied, by estoppel or othe rwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the ixp1200 network processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel?s website at http://www.intel.com. copyright ? intel corporation, 2000 *third-party brands and names are the property of their respective owners.
datasheet iii IXF440 multiport 10/100 mbps ethernet controller contents 1.0 introduction................................................................................................................ ......... 9 1.1 general description............................................................................................... 9 1.2 IXF440 block diagram .......................................................................................... 9 2.0 pinout ...................................................................................................................... .........11 2.1 signal descriptions..............................................................................................11 2.2 pin count.............................................................................................................16 2.3 connection rules ................................................................................................16 2.4 pin list.................................................................................................................17 3.0 register descriptions ....................................................................................................... 21 3.1 register conventions ..........................................................................................21 3.1.1 access rules..........................................................................................21 3.2 csr register ......................................................................................................22 3.2.1 register mapping ...................................................................................22 3.2.2 base registers .......................................................................................23 3.2.2.1 chip interrupt summary register ..............................................23 3.2.2.2 interrupt status register ...........................................................24 3.2.2.3 interrupt enable register ..........................................................25 3.2.2.4 transmit status register ...........................................................26 3.2.2.5 receive status register ............................................................27 3.2.2.6 port control register .................................................................28 3.2.2.7 device id register ....................................................................29 3.2.2.8 revision id register..................................................................29 3.2.2.9 serial command register .........................................................30 3.2.3 configuration registers..........................................................................31 3.2.3.1 fifo threshold register ...........................................................31 3.2.3.2 ix bus mode register ...............................................................32 3.2.3.3 transmit parameters register ..................................................33 3.2.3.4 transmit error mode register ...................................................34 3.2.3.5 transmit threshold and backoff register .................................35 3.2.3.6 receive parameters register ...................................................36 3.2.3.7 receive filtering mode register ...............................................37 3.2.3.8 transmit pause time register ..................................................38 3.2.3.9 maximum packet size register ................................................38 3.2.3.10interpacket gap register ..........................................................39 3.2.4 serial registers ......................................................................................40 3.2.4.1 serial mode register .................................................................40 3.2.4.2 link status register ..................................................................41 3.2.4.3 physical address register ........................................................41 3.3 network statistic counter mapping .....................................................................42 3.3.1 register mapping ...................................................................................42 3.3.2 network statistic counters access rules ..............................................44 3.4 access sequences..............................................................................................44 3.4.1 initialization sequence ...........................................................................44 3.4.2 mode change sequence........................................................................44 3.4.3 interrupt handling sequence..................................................................45
IXF440 multiport 10/100 mbps ethernet controller iv datasheet 4.0 fifo interface operation ................................................................................................. 47 4.1 fifo interface ..................................................................................................... 47 4.1.1 byte ordering on ix bus ....................................................................... 47 4.1.2 fifo status signaling ............................................................................ 48 4.2 packet transmission........................................................................................... 48 4.2.1 packet loading ...................................................................................... 48 4.2.2 network transmission............................................................................ 49 4.2.3 excessive collisions............................................................................... 49 4.2.4 late collision.......................................................................................... 49 4.2.5 fifo underflow ...................................................................................... 49 4.2.6 stopping mode on transmission errors ................................................. 50 4.2.7 transmit flow diagram .......................................................................... 51 4.3 packet reception ................................................................................................ 51 4.3.1 packet storing........................................................................................ 52 4.3.2 header preprocessing ........................................................................... 53 4.3.3 packet segmentation ............................................................................. 53 4.3.4 packet abortion ...................................................................................... 53 4.3.5 network reception................................................................................. 54 4.3.6 rejecting mode on reception errors ..................................................... 54 4.3.7 accepting mode on reception errors..................................................... 54 4.3.8 receive flow diagram ........................................................................... 55 5.0 cpu interface operation.................................................................................................. 57 5.1 cpu interface...................................................................................................... 57 5.2 network management ......................................................................................... 57 5.2.1 snmp mib support................................................................................ 58 5.2.2 rmon statistic group support .............................................................. 59 5.2.3 rmon host group support ................................................................... 60 6.0 network interface operation ............................................................................................ 61 6.1 operating modes................................................................................................. 61 6.2 mii port interface................................................................................................. 62 6.3 mac frame format ............................................................................................ 63 6.4 mac transmit operation .................................................................................... 64 6.4.1 transmit initiation ................................................................................... 64 6.4.2 initial deferral ......................................................................................... 64 6.4.3 frame encapsulation ............................................................................. 64 6.4.4 collision.................................................................................................. 65 6.4.5 terminating transmission ...................................................................... 65 6.4.6 backpressure ......................................................................................... 66 6.4.7 flow control ........................................................................................... 66 6.5 mac receive operation ..................................................................................... 66 6.5.1 receive initiation .................................................................................... 66 6.5.2 preamble processing ............................................................................. 67 6.5.3 frame decapsulation ............................................................................. 67 6.5.4 terminating reception ........................................................................... 67 6.5.5 flow control ........................................................................................... 68 6.6 mac full-duplex operation ................................................................................ 68 6.7 mac loopback operations ................................................................................. 68 6.7.1 internal loopback mode......................................................................... 68
datasheet v IXF440 multiport 10/100 mbps ethernet controller 6.7.2 external loopback mode........................................................................69 6.8 sym mode...........................................................................................................69 7.0 IXF440 timing diagrams..................................................................................................71 7.1 ix bus port timing diagrams ..............................................................................71 7.1.1 transmit start-of-packet timing.............................................................71 7.1.2 transmit end-of-packet timing..............................................................72 7.1.3 transmit fifo control timing................................................................72 7.1.4 transmit ready (txrdy) timing ...............................................................73 7.1.5 receive start-of-packet timing..............................................................73 7.1.6 receive end-of-packet timing...............................................................74 7.1.7 fastest receive reaccess after eop ....................................................74 7.1.8 receive rxfail timing ..............................................................................75 7.1.9 receive rxabt timing..............................................................................75 7.1.10 receive rxkep timing.............................................................................76 7.1.11 receive header replay timing..............................................................76 7.1.12 receive fifo control timing.................................................................76 7.1.13 receive ready (rxrdy) control timing ...................................................77 7.1.14 consecutive transmit-transmit timing..................................................77 7.1.15 consecutive transmit-receive timing...................................................78 7.1.16 consecutive receive-transmit timing...................................................78 7.1.17 consecutive receive-receive timing....................................................78 7.2 mii/sym port timing diagrams...........................................................................78 7.2.1 packet transmission timing ..................................................................79 7.2.2 packet reception timing .......................................................................79 7.2.3 transmission with collision timing ........................................................79 7.2.4 false carrier timing...............................................................................79 8.0 electrical and environmental specifications.....................................................................81 8.1 functional operating range ...............................................................................81 8.2 absolute maximum rating ..................................................................................81 8.3 supply current and power dissipation................................................................82 8.4 temperature limit ratings ..................................................................................82 8.5 reset specification..............................................................................................82 8.6 fifo port specifications .....................................................................................83 8.6.1 clock specification .................................................................................83 8.6.2 3.3 volt dc specifications......................................................................83 8.6.3 5 volt dc specifications.........................................................................84 8.6.4 ix bus signals timing ............................................................................84 8.7 cpu port specifications ......................................................................................85 8.7.1 dc specifications ...................................................................................85 8.7.2 signals timing........................................................................................85 8.7.2.1 read timing ..............................................................................85 8.7.2.2 write timing ..............................................................................86 8.7.2.3 timing parameters ....................................................................87 8.8 mii/sym port specifications................................................................................87 8.8.1 dc specifications ...................................................................................87 8.8.2 signals timing........................................................................................87 8.8.2.1 clocks specifications ................................................................88 8.8.2.2 signals timing diagrams ..........................................................88 8.8.2.3 data timing parameters ...........................................................89
IXF440 multiport 10/100 mbps ethernet controller vi datasheet 8.9 jtag port specifications .................................................................................... 89 8.9.1 dc specifications ................................................................................... 89 8.9.2 signals timing........................................................................................ 90 9.0 mechanical specifications................................................................................................ 93 a joint test action group ? test logic ............................................................................... 95 a.1 general description ............................................................................................ 95 a.1.1 test access port controller.................................................................... 95 a.2 registers ............................................................................................................. 95 a.2.1 instruction register ................................................................................ 96 a.2.2 bypass register ..................................................................................... 96 a.2.3 boundary-scan register ........................................................................ 96
datasheet vii IXF440 multiport 10/100 mbps ethernet controller figures 1 IXF440 block diagram .......................................................................................... 9 2 transmit flow diagram .......................................................................................51 3 receive flow diagram ........................................................................................55 4 transmit start-of-packet timing..........................................................................71 5 transmit end-of-packet timing...........................................................................72 6 transmit fifo control timing.............................................................................72 7 transmit txrdy timing..........................................................................................73 8 receive start-of-packet timing...........................................................................73 9 receive end-of-packet timing............................................................................74 10 fastest receive reaccess after eop.................................................................74 11 receive rxfail timing ...........................................................................................75 12 receive rxabt timing...........................................................................................75 13 receive rxkep timing..........................................................................................76 14 receive header replay timing...........................................................................76 15 receive fifo control timing..............................................................................76 16 receive rxrdy timing...........................................................................................77 17 consecutive transmit-transmit timing...............................................................77 18 consecutive transmit-receive timing................................................................78 19 consecutive receive-transmit timing................................................................78 20 consecutive receive-receive timing.................................................................78 21 packet transmission timing ...............................................................................79 22 packet reception timing ....................................................................................79 23 transmission with collision timing .....................................................................79 24 false carrier timing............................................................................................79 25 ix bus clock timing diagram .............................................................................83 26 ix bus signals timing diagram...........................................................................84 27 cpu port read timing diagram .........................................................................86 28 cpu port write timing diagram .........................................................................86 29 mii/sym clock timing diagram ..........................................................................88 30 mii/sym port transmit timing diagram..............................................................88 31 mii/sym port receive timing diagram...............................................................89 32 mii/sym port carrier sense and collision timing diagram................................89 33 jtag port timing diagram .................................................................................90 34 part marking .......................................................................................................93 35 352-bga package - bottom view .......................................................................93 36 side view ............................................................................................................94 37 a ? a section view................................................................................................94
IXF440 multiport 10/100 mbps ethernet controller viii datasheet tables 1 IXF440 components description ........................................................................ 10 2 signal descriptions ............................................................................................. 11 3 IXF440 pin count................................................................................................ 16 4 IXF440 pin list.................................................................................................... 17 5 csr register mapping ....................................................................................... 22 6 network statistic register mapping .................................................................... 42 7 little endian, 64-bit bus (bend=0, bwid=1) ..................................................... 47 8 little endian, 32-bit bus (bend=0, bwid=0) ..................................................... 47 9 big endian, 64-bit bus (bend=1, bwid=1) ....................................................... 47 10 big endian, 32-bit bus (bend=1, bwid=0) ....................................................... 47 11 ix bus receive packet status ............................................................................ 52 12 snmp mib to IXF440 counters mapping ........................................................... 58 13 rmon statistics to IXF440 counters mapping................................................... 59 14 rmon host to IXF440 counters mapping.......................................................... 60 15 mii port signals versus standard signals........................................................... 62 16 ethernet frame description ................................................................................ 63 17 flow control field matching ................................................................................ 68 18 sym port signal description............................................................................... 69 19 functional operating range ............................................................................... 81 20 3.3 v ac signaling specifications....................................................................... 81 21 5 v ac signaling specifications.......................................................................... 81 22 absolute maximum rating .................................................................................. 82 23 supply current and power dissipation ............................................................... 82 24 temperature limit ratings.................................................................................. 82 25 ix bus clock timing specifications..................................................................... 83 26 ix bus 3.3 v signaling specifications ................................................................. 83 27 ix bus 5-v signaling specifications .................................................................... 84 28 ix bus signals timing specifications .................................................................. 84 29 cpu port dc specifications................................................................................ 85 30 timing parameters.............................................................................................. 87 31 mii/sym port dc specifications ......................................................................... 87 32 mii/sym port signals timing specifications ....................................................... 88 33 data timing parameters ..................................................................................... 89 34 jtag port dc specifications .............................................................................. 90 35 jtag port timing specifications ........................................................................ 91 36 352-bga dimensional attributes ........................................................................ 94 a-1 instructions register ........................................................................................... 96
IXF440 multiport 10/100 mbps ethernet controller datasheet 9 1.0 introduction 1.1 general description the IXF440 multiport ethernet controller includes eight independent 10/100 mbps ethernet macs and interfaces directly to mii standard phys or sym 100base-tx physical devices. the IXF440 handles snmp and rmon management counter sets, accessible through a generic cpu interface, which is also used for mode programming. each mac includes two 256-byte independent fifos for packet transmit and receive. all the packets are transferred onto a high-performance, common fifo interface, or ix bus. the IXF440 is fully compatible with ieee standards, including fast ethernet and flow-control support. it is implemented in a low-power 3.3 v cmos device within a 352-bga package. 1.2 IXF440 block diagram figure 1 is a simplified block diagram of the IXF440. table 1 provides brief descriptions of the major components shown in the figure. figure 1. IXF440 block diagram a7939-01 control port 0 jtag ix bus [63:32] ix bus [31:0] mii / sym clock logic snmp & rmon counts receive fifo (256 bytes) receive mac receive pcs transmit fifo (256 bytes) transmit mac transmit pcs cpu bus control port 7 mii / sym clock logic snmp & rmon counts receive fifo (256 bytes) receive mac receive pcs transmit fifo (256 bytes) [63:32] out [63:32] in [31:0] out [31:0] in transmit mac transmit pcs IXF440
IXF440 multiport 10/100 mbps ethernet controller 10 datasheet table 1. IXF440 components description component description transmit fifo handles the transmitted packets while taking care of retransmission in case of collision. the transmit fifo has direct interface to the ix bus. receive fifo handles the received packets and supports packet deletion in case of errors. the receive fifo has direct interface to the ix bus. transmit mac implements the ieee 802.3 transmit mac functions while interfacing between the transmit fifo and the front-end endec, providing full mii interface. receive mac implements the ieee 802.3 receive mac functions while interfacing between the front-end endec through mii interface and the receive fifo. pcs endec implementing the 100base-x pcs layer, including the 100base-tx scrambler/descrambler function. snmp and rmon handles network statistic counters for snmp and rmon. control handles the chip registers accessible through the cpu bus. clock logic generates the clocks required by the chip. jtag includes the jtag boundary scan logic.
IXF440 multiport 10/100 mbps ethernet controller datasheet 11 2.0 pinout this section describes the IXF440 pinout. 2.1 signal descriptions table 2 describes the signals that the IXF440 uses. the following conventions are used for the signal names: the following abbreviations are used for i/o: the following abbreviations are used in the pin descriptions: _l indicates that the pin is active low. {i} the i subscript appended to a pin name indicates that each port has its own pin (numbered from 0 to 7). x/y multiple function pin. the pin has name x for one function and name y for another. i input o output od open drain i/o input/output full 64-bit bidirectional ix bus mode narrow 32-bit bidirectional ix bus mode split 32-bit (dual) unidirectional ix bus mode table 2. signal descriptions signal name i/o pin description cpu interface cs_l i chip select. this pin must be asserted to enable cpu access to the chip registers. cps[2:0] i cpu port select. selects one of the 8 internal ports for register accesses. crd_l i read strobe. upon assertion, the address signals cadd[9:0], cs_l, and cps[2:0] are latched by the chip. deassertion occurs after the read data is latched from the cdat[7:0] bus. cwr_l i write strobe. upon assertion, the address signals cadd[9:0], cs_l, and cps[2:0] are latched by the chip. deassertion must occur while the data is valid on the cdat[7:0] bus. crdy_l od ready indication. when asserted, indicates that either data is stable on the cdat[7:0] bus during read access or that data was latched by the chip during write access.
IXF440 multiport 10/100 mbps ethernet controller 12 datasheet cadd[9:0] i address bus. selects one of the internal registers to be accessed. cdat[7:0] i/o cpu data bus. carries data to be written to or read from the registers. cint7_l/reserved od/i control interrupt 7/reserved in full or narrow, a control interrupt line for mac 7. asserted following a variety of programmable conditions. deassertion occurs after reading the event(s) that caused the interrupt, unless another interrupt is registered meanwhile. in split, this pin is reserved. cint6_l/tx_fps[2] od/i control interrupt 6/transmit fifo port select [2] in full or narrow, a control interrupt line for mac 6. asserted following a variety of programmable conditions. deassertion occurs after reading the event(s) that caused the interrupt, unless another interrupt is registered meanwhile. in split, this pin is used as bit 2 of the transmit fifo port select address. cint5_l/tx_fps[1] od/i control interrupt 5/transmit fifo port select [1] in full or narrow, a control interrupt line for mac 5. asserted following a variety of programmable conditions. deassertion occurs after reading the event(s) that caused the interrupt, unless another interrupt is registered meanwhile. in split, this pin is used as bit 1 of the transmit fifo port select address. cint4_l/tx_fps[0] od/i control interrupt 4/transmit fifo port select [0] in full or narrow, a control interrupt line for mac 4. asserted following a variety of programmable conditions. deassertion occurs after reading the event(s) that caused the interrupt, unless another interrupt is registered meanwhile. in split, this pin is used as the bit 0 of the transmit fifo port select address. cint3_l/reserved od/i control interrupt 3/reserved in full or narrow, a control interrupt line for mac 3. asserted following a variety of programmable conditions. deassertion occurs after reading the event(s) that caused the interrupt, unless another interrupt is registered meanwhile. in split, this pin is reserved. cint2_l/tx_sop od/i control interrupt 2/transmit start of packet (sop) in full or narrow, a control interrupt line for mac 2. asserted following a variety of programmable conditions. deassertion occurs after reading the event(s) that caused the interrupt, unless another interrupt is registered meanwhile. in split, this pin is the transmit sop input. cint1_l/tx_eop od/i control interrupt 1/transmit end of packet (eop) in full or narrow, a control interrupt line for mac 1. asserted following a variety of programmable conditions. deassertion occurs after reading the event(s) that caused the interrupt, unless another interrupt is registered meanwhile. in split, this pin is the transmit eop input. cint0_l/cint_any_l od control interrupt 0/control interrupt for any mac in full or narrow, a control interrupt line for mac 0. asserted following a variety of programmable conditions. deassertion occurs after reading the event(s) that caused the interrupt, unless another interrupt is registered meanwhile. in split, this pin is the logical nor of all control interrupt lines, mac7 through mac0. table 2. signal descriptions (continued) signal name i/o pin description
IXF440 multiport 10/100 mbps ethernet controller datasheet 13 reset_l i general reset. upon reset, all the registers are reset to their default values and the fifos are flushed. fifo interface clk i system clock. all the fifo data transfers are synchronized to this clock. txsel_l i transmit select. this pin must be asserted to enable transmit fifo write access. rxsel_l i receive select. this pin must be asserted to enable receive fifo read access. the following signals are driven upon assertion of rxsel_l: fdat[63:0], fbe_l[7:0], sop, eop and rxfail. fps[2:0]/rx_fps[2:0] i fifo port select/receive fifo port select. in full or narrow, selects one of eight port fifos for data transfer. in split, selects one of eight port fifos for reading data, through fdat[31:0], from the receive fifo of the selected port. fdat[63:32]/tx_fdat[31:0] i/o fifo data bus/transmit fifo data bus. in full, carries bits [63:32] of the data to be written to the transmit fifo or read from the receive fifo of the selected port. in narrow, fdat[63:32] should be connected to pull-up resistors. in split, carries bits [31:0] of the data to be written to the transmit fifo of the selected port. fdat[31:0]/rx_fdat[31:0] i/o fifo data bus/receive fifo data bus. in full, carries bits [31:0] of the data to be written to the transmit fifo or read from the receive fifo of the selected port. in split, carries bits [31:0] of the data to be read from the receive fifo of the selected port. fbe_l[7:4]/tx_fbe[3:0] i/o fifo byte enable/transmit fifo byte enable. in full: during transmit, indicates which of the bytes driven onto fdat[63:32] contain valid data (valid bytes need to be contiguous and at least one byte must be valid). during receive, indicates which bytes are valid. each fbe_l signal relates to a different fdat byte (for example, fbe_l[4] relates to fdat[39:32] and fbe_l[5] relates to fdat[47:40]). in narrow, fbe_l[7:4] should be connected to pull up resistors. in split, tx_fbe[3:0] are byte enables for tx_fdat[31:0] (input) that carries the data to be written to the transmit fifo of the selected port. fbe_l[3:0]/rx_fbe[3:0] i/o fifo byte enable/receive fifo byte enable. in full or narrow: during transmit, indicates which of the bytes driven onto fdat[31:0] contain valid data (valid bytes need to be contiguous and at least one byte must be valid). during receive, indicates which bytes are valid. each fbe_l signal relates to a different fdat byte (for example, fbe_l[2] relates to fdat[23:16] and fbe_l[0] relates to fdat[7:0]). in split, rx_fbe[3:0] are byte enables for rx_fdat[31:0] (output) that carries the data to be read from the receive fifo of the selected port. rxkep i receive keep. when asserted, this signal causes the last read data to be kept in the receive fifo. may be asserted only with rxsel_l assertion. table 2. signal descriptions (continued) signal name i/o pin description
IXF440 multiport 10/100 mbps ethernet controller 14 datasheet sop/rx_sop i/o start of packet/receive start of packet. in full or narrow, when asserted during transmit, indicates that the first data in the packet is written to the transmit fifo. during receive, sop is asserted when the first data of the packet is read from the receive fifo. in split, rx_sop is asserted when the first data of the packet is read from the receive fifo. eop/rx_eop i/o end of packet/receive end of packet. in full or narrow, when asserted during transmit, indicates that the final data in the packet is written to the transmit fifo. during receive, eop is asserted when the final data of the packet is read from the receive fifo. in the following fifo access, the packet status is driven onto the bus. in split, rx_eop is asserted when the final data of the packet is read from the receive fifo. in the following fifo access, the packet status is driven onto the bus. txasis/txerr i transmit as is/transmit error. when asserted during transmit, upon transfer of the packet ? s first data (together with sop assertion), no padding and/or crc is appended to the packet even if the port was programmed to do so. when asserted upon transfer of the packet ? s final data (together with eop assertion), the packet is transmitted with an mii error (if the port is programmed to append crc) and with a symbol error. rxfail o receive packet failure. this signal is asserted if a packet was received with errors, had started to appear on the ix bus, and was discarded from the receive fifo. rxabt i receive abort. this signal forces a received packet to be aborted and flushed from the receive fifo. may be asserted only with rxsel_l assertion. flct{i} i flow control. when asserted in the half-duplex mode, a collision is generated on each received packet. when asserted in the full-duplex mode, a flow-control packet with the programmed pause time is transmitted. upon deassertion, a flow-control packet with time equal to 0 is sent if programmed accordingly. txctl_l i transmit control enable. when asserted, this pin enables txrdy{i} output drivers to report the transmit fifo status. rxctl_l i receive control enable. when asserted, this pin enables rxrdy{i} output drivers to report receive fifo status. txrdy{i} o transmit fifo ready. indicates whether there is enough available space in the transmit fifo to load data according to the programmable threshold value. following transmission stop due to an error, the txrdy signal remains deasserted until the transmit error status is read. rxrdy{i} o receive fifo ready. indicates whether there is enough available data in the receive fifo to be stored according to the programmable threshold value or if the end of the transferred packet is in the fifo. the rxrdy signal may also be asserted when the packet header is in the fifo. rxrdy can also be asserted to report packet discard from the receive fifo due to an error together with the rxfail signal. vdd_clmp i vdd clamp. should be connected to the power of the highest signal level used on the ix bus. table 2. signal descriptions (continued) signal name i/o pin description
IXF440 multiport 10/100 mbps ethernet controller datasheet 15 mii / sym interface note: the pins have various functions according to the port mode: mii or sym. see a detailed description in section 6 , network interface operation. tclk{i} i transmit clock. txd{i}[3:0] o mii mode: nibble transmit data. sym mode: four low bits of the encoded transmit data. ten{i}/txd{i}[4] o mii mode: transmit enable signal. sym mode: the fifth bit of the encoded transmit data. rclk{i} i receive recovered clock. rxd{i}[3:0] i mii mode: nibble receive data. sym mode: four low bits of the encoded received data. dv{i}/rxd{i}[4] i mii mode: receive enable signal. sym mode: the fifth bit of the encoded received data. col{i}/act{i} i/o mii mode: collision detection signal (input). sym mode: activity indication (output). crs{i}/sd{i} i mii mode: carrier detection signal. sym mode: signal detection indicating link status. rerr{i} i mii mode: receive error signal. sym mode: must be connected to 0. terr{i}/lnk{i} o mii mode: transmit error signal. sym mode: link indication. mdc o mii management clock. mdio i/o mii management input/output serial data. jtag interface tck i jtag clock. if this pin is not used, it must be connected to 0. tms i jtag test mode. if this pin is not used, it must be connected to 1. tdi i jtag data serial input. if this pin is not used, it must be connected to 1. tdo o jtag data serial output. table 2. signal descriptions (continued) signal name i/o pin description
IXF440 multiport 10/100 mbps ethernet controller 16 datasheet 2.2 pin count table 3 summarizes the IXF440 pin count. 2.3 connection rules all the reserved pins must remain unconnected. all the od (open drain) signals must be connected to a pull-up device. all signals connected to a fixed value should be connected through a resistive device. the following are recommended resistor values: ? unused i/o pins: 10 k ? pull-up ? unused i pins: 1 ? 10 k ? pull-up or pull-down ? unused o pins: no pull-up required ? od pins: r=t/c (required signal deassertion time (t) divided by capacitive load (c)) table 3. IXF440 pin count pin common per port total cpu 26 1/1 of cint{i}_l 1 1. the number to the right of the slash applies when operating in split. 34/27 1 fifo 87/92 1 3 111/116 1 mii/sym 2 16 130 jtag 4 ? 4 total i/o 119 20 279 gnd 28 ? 28 vdd 24 ? 24 reserved 21 ? 21 total 352
IXF440 multiport 10/100 mbps ethernet controller datasheet 17 2.4 pin list table 4 lists the IXF440 pins and their associated names. table 4. IXF440 pin list pin number pin name pin number pin name pin number pin name a1 gnd b1 gnd c1 sop/rx_sop a2 gnd b2 vdd c2 gnd a3 fdat[0]/rx_fdat[0] b3 gnd c3 vdd a4 fdat[4]/rx_fdat[4] b4 fdat[1]/rx_fdat[1] c4 reserved a5 fdat[8]/rx_fdat[8] b5 fdat[5]/rx_fdat[5] c5 fdat[2]/rx_fdat[2] a6 fdat[12]/rx_fdat[12] b6 fdat[9]/rx_fdat[9] c6 fdat[6]/rx_fdat[6] a7 fdat[15]/rx_fdat[15] b7 fdat[13]/rx_fdat[13] c7 fdat[10]/rx_fdat[10] a8 fdat[19/]rx_fdat[19] b8 fdat[16]/rx_fdat[16] c8 fdat[14]/rx_fdat[14] a9 fdat[22]/rx_fdat[22] b9 fdat[20]/rx_fdat[20] c9 fdat[17]/rx_fdat[17] a10 fdat[26]/rx_fdat[26] b10 fdat[24]/rx_fdat[24] c10 fdat[21]/rx_fdat[21] a11 fdat[29]/rx_fdat[29] b11 fdat[27]/rx_fdat[27] c11 fdat[25]/rx_fdat[25] a12 txsel_l b12 fdat[31]/rx_fdat[31] c12 fdat[30]/rx_fdat[30] a13 gnd b13 rxsel_l c13 reserved a14 gnd b14 reserved c14 reserved a15 clk b15 fdat[32]/tx_fdat[0] c15 fdat[33]/tx_fdat[1] a16 fdat[34]/tx_fdat[2] b16 fdat[36]/tx_fdat[4] c16 fdat[38]/tx_fdat[6] a17 fdat[37]/tx_fdat[5] b17 fdat[39]/tx_fdat[7] c17 fdat[42]/tx_fdat[10] a18 fdat[41]/tx_fdat[9] b18 fdat[43]/tx_fdat[11] c18 fdat[46]/tx_fdat[14] a19 fdat[44]/tx_fdat[12] b19 fdat[47]/tx_fdat[15] c19 fdat[49]/tx_fdat[17] a20 fdat[48]/tx_fdat[16] b20 fdat[50]/tx_fdat[18] c20 fdat[53]/tx_fdat[21] a21 fdat[51]/tx_fdat[19] b21 fdat[54]/tx_fdat[22] c21 fdat[57]/tx_fdat[25] a22 fdat[55]/tx_fdat[23] b22 fdat[58]/tx_fdat[26] c22 fdat[61]/tx_fdat[29] a23 fdat[59]/tx_fdat[27] b23 fdat[62]/tx_fdat[30] c23 reserved a24 fdat[63]/tx_fdat[31] b24 gnd c24 vdd a25 gnd b25 vdd c25 gnd a26 gnd b26 gnd c26 fps[0]
IXF440 multiport 10/100 mbps ethernet controller 18 datasheet d1 fbe_l[6]/tx_fbe[2] e4 reserved j1 cdat[4] d2 eop/rx_eop e23 reserved j2 cdat[6] d3 reserved e24 fps[2] j3 cint1_l/tx_eop d4 vdd e25 rxfail j4 vdd d5 reserved e26 txctl_l j23 vdd d6 fdat[3]/rx_fdat[3] f1 cint6_l/tx_fps[2] j24 txrdy7 d7 fdat[7]/rx_fdat[7] f2 fbe_l[1]/rx_fbe[1] j25 rxrdy2 d8 fdat[11]/rx_fdat[11] f3 fbe_l[4]/tx_fbe[0] j26 rxrdy4 d9 vdd f4 fbe_l[7]/tx_fbe[3] k1 cdat[0] d10 fdat[18]/rx_fdat[18] f23 txasis /txerr k2 cdat[2] d11 fdat[23]/rx_fdat[23] f24 rxkep k3 cdat[5] d12 fdat[28]/rx_fdat[28] f25 rxctl_l k4 cint0_l/cint_any_l d13 reserved f26 txrdy2 k23 rxrdy0 d14 vdd g1 cint3_l/reserved k24 rxrdy3 d15 fdat[35]/tx_fdat[3] g2 cint5_l/tx_fps[1] k25 rxrdy6 d16 fdat[40]/tx_fdat[8] g3 fbe_l[0]/rx_fbe[0] k26 flct0 d17 fdat[45]/tx_fdat[13] g4 fbe_l[3]/rx_fbe[3] l1 crd_l d18 vdd g23 rxabt l2 crdy_l d19 fdat[52]/tx_fdat[20] g24 txrdy0 l3 cdat[1] d20 fdat[56]/tx_fdat[24] g25 txrdy3 l4 cdat[3] d21 fdat[60]/tx_fdat[28] g26 txrdy5 l23 rxrdy5 d22 reserved h1 cdat[7] l24 rxrdy7 d23 vdd h2 cint2_l/tx_sop l25 flct1 d24 reserved h3 cint4_l/tx_fps[0] l26 flct3 d25 fps[1]/rx_fps[1] h4 cint7_l/reserved m1 cps[1] d26 reserved h23 txrdy1 m2 cps[2] e1 fbe_l[2]/rx_fbe[2] h24 txrdy4 m3 cs_l e2 fbe_l[5]/tx_fbe[1] h25 txrdy6 m4 cwr_l e3 vdd_clmp h26 rxrdy1 m23 flct2 table 4. IXF440 pin list (continued) pin number pin name pin number pin name pin number pin name
IXF440 multiport 10/100 mbps ethernet controller datasheet 19 m24 flct4 t3 mdio w26 txd7[2] m25 flct5 t4 col0/act0 y1 rclk0 m26 flct6 t23 ten7/txd7[4] y2 dv0/rxd0[4] n1 gnd t24 rerr7 y3 rxd0[2] n2 cadd[9] t25 dv7/rxd7[4] y4 col1/act1 n3 cps[0] t26 rxd7[1] y23 terr6/lnk6 n4 vdd u1 mdc y24 dv6/rxd6[4] n23 flct7 u2 crs0/sd0 y25 rxd6[1] n24 reset_l u3 txd0[2] y26 rxd6[3] n25 tdo u4 txd0[0] aa1 rxd0[0] n26 gnd u23 txd7[3] aa2 rxd0[3] p1 gnd u24 txd7[0] aa3 txd1[3] p2 cadd[8] u25 terr7/lnk7 aa4 txd1[0] p3 cadd[7] u26 rclk7 aa23 txd6[2] p4 cadd[6] v1 txd0[3] aa24 ten6/txd6[4] p23 vdd v2 txd0[1] aa25 rerr6 p24 tms v3 ten0/txd0[4] aa26 rclk6 p25 tdi v4 vdd ab1 crs1/sd1 p26 gnd v23 vdd ab2 txd1[2] r1 cadd[5] v24 col7/act7 ab3 terr1/lnk1 r2 cadd[4] v25 txd7[1] ab4 reserved r3 cadd[3] v26 tclk7 ab23 reserved r4 cadd[1] w1 tclk0 ab24 txd6[3] r23 rxd7[0] w2 terr0/lnk0 ab25 txd6[0] r24 rxd7[2] w3 rerr0 ab26 tclk6 r25 rxd7[3] w4 rxd0[1] ac1 txd1[1] r26 tck w23 rxd6[0] ac2 ten1/txd1[4] t1 cadd[2] w24 rxd6[2] ac3 reserved t2 cadd[0] w25 crs7/sd7 ac4 vdd table 4. IXF440 pin list (continued) pin number pin name pin number pin name pin number pin name
IXF440 multiport 10/100 mbps ethernet controller 20 datasheet ac5 reserved ad8 terr2/lnk2 ae11 txd3[1] ac6 rxd1[0] ad9 dv2/rxd2[4] ae12 terr3/lnk3 ac7 crs2/sd2 ad10 rxd2[2] ae13 dv3/rxd3[4] ac8 txd2[1] ad11 txd3[3] ae14 rxd3[0] ac9 vdd ad12 ten3/txd3[4] ae15 crs4/sd4 ac10 rxd2[0] ad13 rerr3 ae16 txd4[1] ac11 crs3/sd3 ad14 rxd3[1] ae17 terr4/lnk4 ac12 txd3[0] ad15 col4/act4 ae18 dv4/rxd4[4] ac13 vdd ad16 txd4[0] ae19 rxd4[3] ac14 rxd3[2] ad17 rerr4 ae20 txd5[3] ac15 txd4[2] ad18 rxd4[2] ae21 ten5/txd5[4] ac16 ten4/txd4[4] ad19 col5/act5 ae22 rerr5 ac17 rxd4[1] ad20 txd5[0] ae23 rxd5[2] ac18 vdd ad21 dv5/rxd5[4] ae24 gnd ac19 txd5[1] ad22 rxd5[1] ae25 vdd ac20 terr5/lnk5 ad23 reserved ae26 gnd ac21 rxd5[0] ad24 vdd af1 gnd ac22 reserved ad25 gnd af2 gnd ac23 vdd ad26 crs6/sd6 af3 rclk1 ac24 reserved ae1 gnd af4 rxd1[1] ac25 col6/act6 ae2 vdd af5 col2/act2 ac26 txd6[1] ae3 gnd af6 txd2[0] ad1 tclk1 ae4 dv1/rxd1[4] af7 tclk2 ad2 gnd ae5 rxd1[2] af8 rclk2 ad3 vdd ae6 txd2[3] af9 rxd2[3] ad4 reserved ae7 ten2/txd2[4] af10 txd3[2] ad5 rerr1 ae8 rerr2 af11 tclk3 ad6 rxd1[3] ae9 rxd2[1] af12 rclk3 ad7 txd2[2] ae10 col3/act3 af13 gnd af14 gnd af19 rxd4[0] af24 rxd5[3] af15 rxd3[3] af20 crs5/sd5 af25 gnd af16 txd4[3] af21 txd5[2] af26 gnd af17 tclk4 af22 tclk5 af18 rclk4 af23 rclk5 table 4. IXF440 pin list (continued) pin number pin name pin number pin name pin number pin name
IXF440 multiport 10/100 mbps ethernet controller datasheet 21 3.0 register descriptions this section describes the IXF440 registers. each of the IXF440 ports includes an independent register set, enabling maximum flexibility. the registers in each port are divided into two groups: control and status registers (csrs) network statistics counters 3.1 register conventions all the registers in the IXF440 are implemented in each of its eight ports, unless mentioned otherwise in the text. in the register description tables throughout this chapter, the following abbreviations are used to indicate register access modes: 3.1.1 access rules the following access rules must be followed when accessing registers: unlisted addresses are reserved and must not be accessed. reserved bits on registers must be written as ? 0 ? and are unpredictable on read. the configuration and the serial registers are writable only when the port is in stop state (as reported in the interrupt status register ? int_stt), following transmit and receive disable programming. multibyte registers are ordered from low to high (the lower address points to the lower byte). r readable only. w writable only. r/w readable and writable.
IXF440 multiport 10/100 mbps ethernet controller 22 datasheet 3.2 csr register this section describes the IXF440 csr register mapping. 3.2.1 register mapping table 5 lists each csr register name, mnemonic, address offset, and the section that describes the register. table 5. csr register mapping register description mnemonic i/o address offset section base registers 3.2.2 chip interrupt summary register 1 1. these registers are valid in port 0 only. chip_int 00h 3.2.2.1 interrupt status register int_stt 01h 3.2.2.2 interrupt enable register int_en 02h 3.2.2.3 transmit status register txmt_stt 03h 3.2.2.4 receive status register recv_stt 04h 3.2.2.5 port control register port_ctr 05h 3.2.2.6 device identification number register1. dev_id 06h 3.2.2.7 revision identification number register1. rev_id 07h 3.2.2.8 serial command register ser_com 08h 3.2.2.9 configuration registers 3.2.3 fifo threshold register ffo_tshd 11h 3.2.3.1 ix bus mode register ffo_bus 12h 3.2.3.2 transmit parameters register tx_param 13h 3.2.3.3 transmit error mode register tx_err_mod 14h 3.2.3.4 transmit packet sending threshold and backoff limit register tx_tshd_boff 15h 3.2.3.5 receive parameters register rx_param 16h 3.2.3.6 receive filtering mode register rx_filt_mod 17h 3.2.3.7 transmit flow-control pause time register pause_time 18h ? 19h 3.2.3.8 maximum packet size register pkt_max_size 1ah ? 1bh 3.2.3.9 interpacket gap register ipg 32h ? 33h 3.2.3.10 serial registers 3.2.4 serial mode register ser_mod 21h 3.2.4.1 link status register lnk_stt 22h 3.2.4.2 physical address register phy_add 28h ? 2dh 3.2.4.3
IXF440 multiport 10/100 mbps ethernet controller datasheet 23 3.2.2 base registers the following sections describe the individual base registers. 3.2.2.1 chip interrupt summary register this register handles the interrupt status of all the ports. a set bit indicates that the corresponding port has generated an interrupt, and several bits located in its interrupt status register have been set. a bit will reset when the corresponding interrupts have been cleared. the interrupt summary register is valid only in port 0. bit name bit number bit description int7 7 port 7 interrupt int6 6 port 6 interrupt int5 5 port 5 interrupt int4 4 port 4 interrupt int3 3 port 3 interrupt int2 2 port 2 interrupt int1 1 port 1 interrupt int0 0 port 0 interrupt access rules register access r value after reset 00h
IXF440 multiport 10/100 mbps ethernet controller 24 datasheet 3.2.2.2 interrupt status register the interrupt status register handles information regarding events that cause an interrupt. a specific event sets a bit if it was programmed to generate an interrupt in the interrupt enable register (int_en). reading this register will reset all the bits, except for the txer and rxev bits. these bits are reset only when the corresponding status register is read. bit name bit number bit description ? 7 reserved stop 6 port stop. indicates that transmit or receive path is in the stop state, following disable programming in the port control register. if both transmit and receive paths are programmed to be stopped, this bit is set when they both reach the stop state. ovfc 5 counter overflow. indicates that at least one management counter has reached its highest possible value (and is stuck there). the overflowed counter needs to be reset to prevent further interrupt. lnch 4 link change. indicates that a link change has occurred while working in sym mode. the actual link status is reported in the link status register. txer 3 transmit error. a logical or bit for all the bits in the transmit error status register. txok 2 transmit ok. indicates successful packet transmission. rxev 1 receive event. a logical or of all the bits in the receive status register. this bit is set only after the packet is fully received by the chip. rxok 0 receive ok. indicates that a packet has been received without error. this bit is set only after the packet is fully transferred onto the chip. access rules register access r value after reset 00h
IXF440 multiport 10/100 mbps ethernet controller datasheet 25 3.2.2.3 interrupt enable register each bit in this register enables the generation of an interrupt when the corresponding event occurs. the event causing the interrupt will be reported in the interrupt status register (int_stt). bit name bit number bit description ? 7 reserved stope 6 port stop interrupt enable ovfce 5 counter overflow interrupt enable lnche 4 link change interrupt enable txere 3 transmit error interrupt enable txoke 2 transmit ok interrupt enable rxeve 1 receive event interrupt enable rxoke 0 receive ok interrupt enable access rules register access r/w value after reset 00h
IXF440 multiport 10/100 mbps ethernet controller 26 datasheet 3.2.2.4 transmit status register this register handles the causes for transmit stops. all bits, except pkc bits, are reset upon reading this register. the bits in this register are set only if packet transmission is programmed to be stopped following the corresponding error in the transmit error mode register (tx_err_mod). bit name bit number bit description pkc 7:6 packet count. indicates the number of packets currently stored in the transmit fifo. the packet count is incremented while loading the first byte of a packet and decremented following transmission of a packet. the packet count can get a maximum value of 2. ? 5:3 reserved xcl 2 excessive collision. indicates that a packet was sent 16 times unsuccessfully due to consecutive collisions. lcl 1 late collision. indicates that a collision has occurred after transmission of 64 bytes. unf 0 fifo underflow. indicates that data was not available in the transmit fifo during packet transmission, after transmission of 64 bytes. access rules register access r value after reset 00h a5989-01 76 pkc txmt_stt xcl lcl unf 543210
IXF440 multiport 10/100 mbps ethernet controller datasheet 27 3.2.2.5 receive status register this register reports events that have occurred during packet reception. all bits are reset upon reading this register. the bits in this register are set only if the receive logic is programmed to pass packets with the corresponding event in the receive filtering mode register (rx_filt_mod). if a packet with multiple errors is to be passed and not all the corresponding bits in the receive filtering mode register (rx_filt_mod) are set, none of the bits in this register are set. the receive status is also appended to the end of the packet in the receive fifo. bit name bit number bit description flc 7 flow control packet. indicates that a flow-control packet was received. ? 6 reserved mer 5 mii error. indicates either that a symbol error was detected in the sym mode or that an mii error signal was asserted in the mii mode during packet reception. rtl 4 too long packet. indicates that a packet longer than the maximum allowable size has been received. srt 3 short packet. indicates that a packet shorter than 64 bytes has been received. drb 2 alignment error. indicates that a packet was received with crc and framing errors. crc 1 crc error. indicates that a packet was received with a crc error but without a framing error. ovf 0 fifo overflow. indicates that there was not enough space available in the receive fifo during packet reception. access rules register access r value after reset 00h
IXF440 multiport 10/100 mbps ethernet controller 28 datasheet 3.2.2.6 port control register the port control register handles all the control bits of the port. bit name bit number bit description ? 7:6 reserved txstt 5 transmit restart. when set, the chip restarts the transmission process after stopping due to a transmit error. the txstt is a trigger bit (does not require reset before setting). txen 4 transmit enable. when this bit is set, the port enters the working mode. when reset, the port completes transmission of the packet currently processed, and then stops. stop state is reported in the stop bit located in the interrupt status register (int_stt). rxen 3 receive enable. when this bit is set, the port enters the working mode. when reset, the port completes reception of the packet currently processed, and then stops. stop state is reported in the stop bit located in the interrupt status register (int_stt). ptrst 2 port reset. when set, this bit causes the transmit and receive logic to reset. ctrst 1 control reset. when set, this bit resets all the registers, except port_ctr, to their default values. transmit and receive logic are also reset. cnrst 0 counter reset. when set, this bit resets all the network statistic counters. the reset process takes 100 cycles. during this time, the counters and port_ctr must not be accessed. this bit must not be set together with the ctrst bit. access rules register access r/w value after reset 00h
IXF440 multiport 10/100 mbps ethernet controller datasheet 29 3.2.2.7 device id register the device id register is valid only in port 0. 3.2.2.8 revision id register the revision id register is valid only in port 0. bit name bit number bit description did 7:0 device id. access rules register access r value after reset 01h bit name bit number bit description mrid 7:4 main revision id. this number is incremented for subsequent IXF440 revisions. srid 3:0 sub revision id. this number is incremented for subsequent IXF440 steps within the current revision. access rules register access r value after reset 11h
IXF440 multiport 10/100 mbps ethernet controller 30 datasheet 3.2.2.9 serial command register the serial command register handles the control of the serial interface. bit name bit number bit description ? 7:6 reserved mdm 5 mii data mode. when set, the mdio signal is in the output mode. when reset, the mdio signal is in the input mode. this bit is effective only in port ? 0 ? . mdio 4 mii data io. during write access to the mii management, the value written to this bit is driven onto the mdio signal. during read access, the mdio signal value is latched into this bit. this bit is effective only in port ? 0 ? . mdc 3 mii management clock. the value written to this bit is driven onto the mdc signal. each new written value must remain stable for at least 200 ns. this bit is effective only in port ? 0 ? . bkp 2 backpressure mode. when set, a transmission is generated upon reception of each packet to force a collision while the port is in the half-duplex mode. fct 1 flow-control packet trigger. when set, this bit initiates a flow-control packet transmission to the remote node, as defined in the 802.3 ieee standard, while the port is in the full-duplex mode. this bit can be used only if the xon disable bit on transmit parameters register (tx_param) is set. ? 0 reserved access rules register access r/w value after reset 00h
IXF440 multiport 10/100 mbps ethernet controller datasheet 31 3.2.3 configuration registers the following sections describe the individual configuration registers. 3.2.3.1 fifo threshold register the fifo threshold register handles the transmit and receive fifo threshold. bit name bit number bit description tth 7:4 this field defines the minimum amount of free space required in the transmit fifo in order to assert the txrdy signal. the effective threshold in bytes is equal to 8 (tth + 1). a value of 0 is not allowed. rth 3:0 this field defines the minimum amount of data required in the receive fifo in order to assert the rxrdy signal. the effective threshold in bytes is equal to 8 (rth + 1). a value of 0 is not allowed. access rules register access r/w value after reset 77h register field value (rth or tth) effective threshold (bytes) register field value (rth or tth) effective threshold (bytes) 0 not allowed 8 72 116980 2 241088 3321196 4 4012104 5 4813112 6 5614120 7 6415128
IXF440 multiport 10/100 mbps ethernet controller 32 datasheet 3.2.3.2 ix bus mode register the ix bus mode register controls the ix bus mode of operation. bit name bit number bit description ? 7:5 reserved splt 4 split ix bus mode. this bit is meaningful for mac0 only. for mac1 through mac7, this bit is reserved. if cleared to 0: and bwid (bit 1) is also 0, data is transmitted and received via fdat[31:0] (ix bus [31:0]). and bwid (bit 1) is 1, data is transmitted and received via fdat[63:0] (ix bus [63:0]). if set to 1: data is received via rx_fdat[31:0] (ix bus [31:0]) and transmitted via tx_dat[31:0] (ix bus [63:32]). ? 3 reserved hryd 2 header ready disable. when set, the rxrdy signal will not be asserted when a packet header is in fifo, but only according to fifo threshold values. bwid 1 bus width. defines the number of bits used on the ix bus. when set, 64 bits are used. when reset, the lower 32 bits are used. software must ensure that mac0 ffo_bus[4] (splt) is set to 0 if bwid is set. bend 0 big or little endian mode. defines the byte ordering mode on the ix bus. when set, the port uses big endian mode. when reset, little endian mode is used. access rules register access r/w value after reset 00h splt
IXF440 multiport 10/100 mbps ethernet controller datasheet 33 3.2.3.3 transmit parameters register the transmit parameters register handles the control of the transmit serial interface. bit name bit number bit description ? 7:5 reserved spm 4 single packet mode. when set, a packet is loaded in the transmit fifo only after the previous packet was fully transmitted without any error. xond 3 xon disable. when set, a flow-control packet will not be sent upon flct{i} signal deassertion. flce 2 flow-control mode enable. when set, transmission is stopped in the full-duplex mode while receiving flow-control packets. crcd 1 crc appending disable. when set, packets are transmitted without padding or crc appending to the end of the packet. this field is ignored if the txasis signal is asserted during the start of packet loading. padd 0 padding appending disable. when set, short packets are transmitted without the addition of bytes complementing their sizes to 64 bytes. when the crcd bit is set, this bit is ignored. this field is ignored if the txasis signal is asserted during the start of packet loading. access rules register access r/w value after reset 00h
IXF440 multiport 10/100 mbps ethernet controller 34 datasheet 3.2.3.4 transmit error mode register the transmit error mode register controls the events that cause transmission stop. if, during packet transmission, an error occurs and the corresponding bit is set, the transmit fifo is flushed, and transmission stops. the error is then reported in the transmit error status register (terr_stt), and can generate an interrupt according to the interrupt enable register (int_en). bit name bit number bit description ? 7:3 reserved xcls 2 stop transmission after excessive collisions. when set, packet retransmission stops after 16 attempts. when reset, packets will always be retransmitted following a collision until a successful transmission is achieved. lcls 1 stop transmission after late collision. when set, transmission stops if a collision occurs after transmission of 64 bytes. when reset, the packet will be flushed from the transmit fifo and the following packet will be transmitted. unfs 0 stop transmission after fifo underflow. when set, transmission stops if an underflow occurs after transmission of 64 bytes. when reset, the packet will be flushed from the transmit fifo, and the following packet will be transmitted. access rules register access r/w value after reset 00h
IXF440 multiport 10/100 mbps ethernet controller datasheet 35 3.2.3.5 transmit threshold and backoff register packet transmission starts when the amount of data in the transmit fifo is larger than or equal to this threshold, or the entire packet enters onto the fifo. the effective serial transmit threshold in bytes is equal to 8 x tsd + 4. if the sum of the effective serial transmit threshold and the effective ix bus transmit threshold (based upon ffo_tshd) is larger than 230 bytes, transmission can begin before the effective serial transmit threshold is reached in order to prevent deadlock. a value of 0 is not allowed. bit name bit number bit description bkl 7:4 backoff limit. this is the maximum number used in the retransmission time algorithm following a collision. lower numbers will cause faster retransmission times. according to ethernet standard, this value must be programmed to be 10 (decimal). tsd 3:0 packet transmission threshold. packet transmission starts when the amount of data in the transmit fifo is larger than or equal to the threshold, or the entire packet enters onto the fifo. the effective threshold in bytes is equal to 8 tsd + 4. if the sum of effective serial threshold and the effective parallel threshold is larger than 230 bytes, the transmission can start before threshold is reached to prevent deadlock. a value of 0 is not allowed. access rules register access r/w value after reset a3h packet transmission threshold effective threshold (bytes) packet transmission threshold effective threshold (bytes) 0 not allowed 8 68 112976 2201084 3281192 4 36 12 100 5 44 13 108 65214116 7 60 15 124
IXF440 multiport 10/100 mbps ethernet controller 36 datasheet 3.2.3.6 receive parameters register the receive parameters register defines the receive data flow on the ix bus. bit name bit number bit description crcr 7 crc remove. when set, the last four bytes of the received packet will not be transferred onto the ix bus. packets shorter than 4 bytes will cause invalid data to appear on the ix bus. hrpl 6 header replay. when set, packet header is transferred twice onto the ix bus. if this bit is set, the rx_filt_mod bit should be reset. hdrs 5:0 header size. header size is used for the header replay function and for rxrdy signal assertion (even if the header replay function is disabled). the header size is calculated in bytes as 4 hdrs (valid values: 4 hdrs 48). access rules register access r/w value after reset 10h
IXF440 multiport 10/100 mbps ethernet controller datasheet 37 3.2.3.7 receive filtering mode register when a packet with a specific event is programmed to be passed, the corresponding packets are not discarded and are transferred as regular packets. the status is reported in the receive status register (recv_stt) and can generate an interrupt according to the interrupt enable register (int_en). if a specific event is not programmed to enable reception of a packet, the corresponding packets are discarded from the receive fifo. failure will be reported onto the rxfail signal if the packet has already started to be transferred onto the ix bus. if a packet with multiple errors is to be passed, all corresponding bits must be set. bit name bit number bit description pflc 7 pass flow-control packets. ? 6 reserved pmer 5 pass packets with mii error. prtl 4 pass too long packets. psrt 3 pass short packets. pdrb 2 pass alignment error packets. pcrc 1 pass crc error packets. povf 0 pass fifo overflow. access rules register access r/w value after reset 00h
IXF440 multiport 10/100 mbps ethernet controller 38 datasheet 3.2.3.8 transmit pause time register the transmit pause time register handles the time field used in the flow-control packets. 3.2.3.9 maximum packet size register this register controls the maximum allowed packet size. bit name bit number bit description pstm 15:0 indicates the number of slot times during which the remote mode cannot send packets. this field is inserted into the transmitted flow-control packets. access rules register access r/w value after reset 0h bit name bit number bit description ? 15 reserved mps 14:0 packets received with a longer size are treated as too long packets. access rules register access r/w value after reset 1518 (decimal) pkt_max_size 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mps
IXF440 multiport 10/100 mbps ethernet controller datasheet 39 3.2.3.10 interpacket gap register the interpacket gap register controls the interpacket gap. the minimum value for ips1 and ips2 combined should be 22 (decimal) while the maximum value for ips1 and ips2 combined should be 100 (decimal). note that this means ips1 and ips2 may not both be their respective minimum values. bit name bit number bit description ips2 15:8 this field contains the number of serial clocks for the second part of the interpacket gap. even if a carrier is sensed on the serial line, the IXF440 continues to count time and transmit its packet, and thus forces a collision on the network. the interpacket gap value is in units of 4 bit times. therefore, the default value (09h) corresponds to 36 bit times and matches the standards requirements. the minimum value is 02h. ips1 7:0 this field contains the number of serial clock cycles for the first part of the interpacket gap. if a carrier is sensed on the serial line during these clock cycles (excluding the first 40-bit time after transmission), the IXF440 defers its transmission and waits until the line is idle. the interpacket gap value is in units of 4 bit times. therefore, the default value (0fh) corresponds to 60 bit times and matches the standards requirements. the minimum value is 0ah. access rules register access r/w value after reset 090f (hexadecimal) ipg 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ips1 ips2
IXF440 multiport 10/100 mbps ethernet controller 40 datasheet 3.2.4 serial registers the following sections describe the individual serial registers. 3.2.4.1 serial mode register the serial mode register controls the serial interface mode of work. bit name bit number bit description ? 7:6 reserved ilpk 5 internal loopback mode. when set, the port is disconnected from the line and all the transmitted packets are sent back to the receive side. packets are not transmitted onto the line (except in the sym mode) and packets received from the line are rejected. elpk 4 external loopback mode. when set, packets are being received and transmitted simultaneously. this mode is usable only when the external logic is programmed to loopback packets. fdx 3 full-duplex mode. when set, packets are being received and transmitted simultaneously. ? 2 reserved scr 1 scrambler mode. if a sym-100base-tx phy is connected, this bit must be set, and if a sym-100base-fx phy is connected, this bit must be reset. this bit is used only if the syp bit is set. syp 0 mii/sym port mode. this bit defines the mii/sym port mode. if an mii phy device is connected, this bit must be reset. if a sym phy device is connected, this bit must be set. access rules register access r/w value after reset 00h
IXF440 multiport 10/100 mbps ethernet controller datasheet 41 3.2.4.2 link status register the link status register indicates the link status . 3.2.4.3 physical address register the physical address register contains the ethernet physical address of the port. this address is inserted to transmitted flow-control packets in the source address field. bit name bit number bit description ? 7:1 reserved lnk100 0 100base-x link status. set if the line link is ok while in the sym mode. access rules register access r bit name bit number bit description ead 47:0 port ethernet address. access rules register access r/w value after reset 0h
IXF440 multiport 10/100 mbps ethernet controller 42 datasheet 3.3 network statistic counter mapping this section describes the IXF440 statistic counter mapping. 3.3.1 register mapping table 6 lists each network statistic IXF440 register name, mnemonic, and offset. i/o base address: 100h or 200h. table 6. network statistic register mapping (sheet 1 of 3) register description mnemonic i/o address offset transmit statistic counters the number of unicast packets transmitted without any errors. tx_uni_ok_cnt 00h ? 03h the number of multicast packets that are not broadcast, transmitted without any errors. tx_mlt_ok_cnt 04h ? 07h the number of broadcast packets transmitted without any errors. tx_brd_ok_cnt 08h ? 0bh the number of packets deferred upon the first transmit attempt due to a busy line. tx_defer_cnt 0ch ? 0fh the total number of regular collision events occurring during transmission. tx_col_cnt 10h ? 13h the number of packets transmitted without any error following a single collision. tx_scol_cnt 14h ? 17h the number of packets transmitted without any error following multiple collisions. tx_mcol_cnt 18h ? 1bh the number of packets that have experienced 16 consecutive collisions or more. tx_xcol_cnt 1ch ? 1fh the number of transmission abortions due to a collision occurring after transmission of packets that are 64 bytes in length. tx_lcol_cnt 20h ? 23h the number of transmitted packets, 64 bytes in length, including bad packets. tx_pkt_64_cnt 24h ? 27h the number of transmitted packets, 65 to 127 bytes in length, including bad packets. tx_pkt_65_cnt 28h ? 2bh the number of transmitted packets, 128 to 255 bytes in length, including bad packets. tx_pkt_128_cnt 2ch ? 2fh the number of transmitted packets, 256 to 511 bytes in length, including bad packets. tx_pkt_256_cnt 30h ? 33h the number of transmitted packets, 512 to 1023 bytes in length, including bad packets. tx_pkt_512_cnt 34h ? 37h the number of transmitted packets, 1024 to 1518 bytes in length, including bad packets. tx_pkt_1024_cnt 38h ? 3bh the number of transmitted packets with length larger than 1519 bytes, including bad packets. tx_pkt_1519_cnt 3ch ? 3fh the number of correct transmitted flow-control packets. tx_pause_cnt 40h ? 43h the number of packets transmitted with an error due to transmit fifo underflow or txerr signal assertion. tx_err_cnt 44h ? 47h transmit byte counters the number of bytes transmitted in good packets. tx_oct_ok_cnt 60h ? 64h
IXF440 multiport 10/100 mbps ethernet controller datasheet 43 the number of bytes transmitted in packets with errors. tx_oct_bad_cnt 68h ? 6ch receive byte counters the number of bytes received in good packets. rx_oct_ok_cnt 70h ? 74h the number of bytes received in packets with errors. rx_oct_bad_cnt 78h ? 7ch receive statistic counters the number of frames received without sfd detection but with carrier assertion. this counter must be reset after moving to the sym mode. rx_runt_cnt 80h ? 83h the number of receive packets not fully accepted due to receive fifo overflow. rx_ovf_cnt 84h ? 87h the number of packets, less than 64 bytes in length, received without any error. rx_short_ok_cnt 88h ? 8bh the number of packets less than 64 bytes in length, received with crc error. rx_short_crc_cnt 8ch ? 8fh the number of unicast packets with lengths between 64 bytes and the maximum packet size, received without any errors. rx_uni_ok_cnt 90h ? 93h the number of multicast packets with lengths between 64 bytes and the maximum packet size, received without any errors. rx_mlt_ok_cn 94h ? 97h the number of broadcast packets with lengths between 64 bytes and the maximum packet size, received without any errors. rx_brd_ok_cnt 98h ? 9bh the number of packets with lengths between 64 bytes and the maximum packet size, received with an integral number of bytes and a crc error. rx_norm_crc_cnt 9ch ? 9fh the number of packets with lengths between 64 bytes and the maximum packet size, received with a nonintegral number of bytes and a crc error. rx_norm_ali_cnt a0h ? a3h the number of packets, larger than the maximum packet size, received without any error. rx_long_ok_cnt a4h ? a7h the number of packets, larger than the maximum packet size, received with a crc error. rx_long_crc_cnt a8h ? abh the number of received packets, 64 bytes in length, including bad packets. rx_pkt_64_cnt ach ? afh the number of received packets, 65 to 127 bytes in length, including bad packets. rx_pkt_65_cnt b0h ? b3h the number of received packets, 128 to 255 bytes in length, including bad packets. rx_pkt_128_cnt b4h ? b7h the number of received packets, 256 to 511 bytes in length, including bad packets. rx_pkt_256_cnt b8h ? bbh the number of received packets, 512 to 1023 bytes in length, including bad packets. rx_pkt_512_cnt bch ? bfh the number of received packets, 1024 to 1518 bytes in length, including bad packets. rx_pkt_1024_cnt c0h ? c3h the number of received packets, with lengths between 1519 bytes and the maximum packet size (programmable value), including bad packets. rx_pkt_1519_cnt c4h ? c7h table 6. network statistic register mapping (sheet 2 of 3) register description mnemonic i/o address offset
IXF440 multiport 10/100 mbps ethernet controller 44 datasheet 3.3.2 network statistic counters access rules the network statistic counters access rules are as follows: the counters can be accessed with a base address equal to 100h or 200h. accessing the counters with the 100h base address causes them to reset. accessing them with the 200h will not reset the counter. any of the counter bytes can be read without reading the other bytes. only the accessed bytes are reset (if accessed with the 100h base address). the counters must be read from the lower to the upper bytes, in consecutive accesses. the statistic counters are not writable. note: counter overflow causes it to remain fixed at the highest value it has reached. receive statistic counters are updated even upon receive fifo overflow. all the byte counters take crc bytes into account, but exclude the framing bits in the packets. 3.4 access sequences this section describes the initialization, mode change, and interrupt handling sequences for the IXF440. 3.4.1 initialization sequence each IXF440 port must be initialized according to the following sequence: 1. disable the port and reset it by writing: 06h to the port control register (port_ctr), and then 01h to the same register 2. initialize the port by writing to the relevant configuration and serial registers. 3. enable port operation by writing a value of 18h to the port control register (port_ctr). 3.4.2 mode change sequence in order to change the IXF440 working mode without impacting packet transfer, the following sequence must be used: 1. disable the port by writing a value of 00h to the port control register (port_ctr). the number of correct received flow-control packets. rx_pause_cnt c8h ? cbh the number of false carrier events detected. rx_fals_crs_cnt cch ? cfh the number of received packets during which phy symbol errors were detected. rx_sym_err_cnt d0h ? d3h table 6. network statistic register mapping (sheet 3 of 3) register description mnemonic i/o address offset
IXF440 multiport 10/100 mbps ethernet controller datasheet 45 2. wait until the port enters the stop state. the stop state entry may generate an interrupt if enabled, and is reported by the stop bit in the interrupt status register (int_stt). 3. change the configuration and serial register values. 4. enable port operation by writing a value of 18h to the port control register (port_ctr). note: the ix bus mode register (ffo_bus) can only be updated by using the initialization sequence, which will cause an interruption of packet transfer. 3.4.3 interrupt handling sequence following interrupt, the subsequent sequence must be used to reset the interrupt: 1. if all ports are sharing the same interrupt line, read the chip interrupt summary register (chip_int), and perform steps 2 to 4 for each port that generates an interrupt. 2. read the port interrupt status register (int_stt) and act according to the interrupt cause. 3. if the receive event bit is set (int_stt), read the receive status register (recv_stt) and act according to the interrupt cause. 4. if the transmit error bit is set (int_stt), read the transmit status register (txmt_stt) and act according to the interrupt cause. to resume transmission, write a value of 38h to the port control register (port_ctr).

IXF440 multiport 10/100 mbps ethernet controller datasheet 47 4.0 fifo interface operation this chapter describes the IXF440 fifo interface operation, including the transmission and reception flows. 4.1 fifo interface the IXF440 uses a generic bus interface for data transfer to and from its fifos. the data bus is 64 bits wide but can be programmed to use only the lower 32-bits (ffo_bus). big and little endian byte ordering are both supported on 32-bit boundaries (ffo_bus). the different fifos are accessed according to port selection signals (fps[2:0]) as well as transmit or receive enabling signals (txsel_l, rxsel_l). data transfer is synchronized to the main clock (clk), and new data may be sent or received on each clock cycle. each fifo has a dedicated signal for each direction (txrdy, rxrdy), reporting if it is ready for data transfer according to predetermined thresholds (ffo_tshd). the burst size should be shorter than or equal to the effective threshold. the amount of data transferred during a fifo access may be dynamically changed from one access to the other. on receive, if the ffo_bus bit is reset, each first burst of a packet should be shorter than or equal to the header size. 4.1.1 byte ordering on ix bus on the ix bus, bytes are ordered according to the endian mode (ffo_bus) and the bus width (ffo_bus). table 7 and table 8 show the different options for little endian mode. table 9 and table 10 show the different options for big endian mode. table 7. little endian, 64-bit bus (bend=0, bwid=1) 63 32 31 0 8th byte 7th byte 6th byte 5th byte 4th byte 3rd byte 2nd byte 1st byte table 8. little endian, 32-bit bus (bend=0, bwid=0) 31 0* 4th byte 3rd byte 2nd byte 1st byte table 9. big endian, 64-bit bus (bend=1, bwid=1) 63 32 31 0 5th byte 6th byte 7th byte 8th byte 1st byte 2nd byte 3rd byte 4th byte table 10. big endian, 32-bit bus (bend=1, bwid=0) 31 0* 1st byte 2nd byte 3rd byte 4th byte
IXF440 multiport 10/100 mbps ethernet controller 48 datasheet 4.1.2 fifo status signaling the IXF440 reports the status of each fifo through dedicated signals. each transmit fifo has a txrdy signal indicating that there is enough free space to load new data. each receive fifo has a rxrdy signal indicating that there is enough data to be transferred onto the ix bus. the txrdy signals are driven by the IXF440 when the txctl_l signal is asserted, and the rxrdy signals are enabled by the rxclt_l signal.the txrdy signal of a specific port is asserted when the txctl_l signal is asserted and the specific port is selected (fps[2:0] or, alternatively, tx_fps[2:0] in split). the same applies for the rxrdy signal of a specific port, which is asserted with rxctl_l assertion and the specific port selection (fps[2:0]). 4.2 packet transmission the following sections describe the packet transmission policy. 4.2.1 packet loading the IXF440 loads packets from the ix bus into the transmit fifo during burst accesses. in order to guarantee a minimal amount of data transfer, the transmit fifo txrdy signal reports minimal space availability according to a programmable threshold (ffo_tshd). when a new packet is loaded in the fifo, the first cycle of the first burst must be signalled with sop signal assertion. if the txasis signal is asserted together with sop, the packet will be sent onto the network without padding or crc addition. at the end of a packet load, the last data must be signalled with the assertion of the eop signal in the last cycle of the last burst. if the txerr signal is asserted together with eop while sending the packet onto the network, the mii error signal terr will be asserted and the crc will be damaged if it was requested to be appended by the IXF440. up to two packets can be loaded in the transmit fifo, although the IXF440 may be programmed to handle only a single packet at a time (tx_param). byte masking signals (fbe_l[7:0]) may be used to load selective bytes. they can be used during packet transfer to load packet segments on byte boundaries and for loading the exact number of bytes at the end of a packet. valid bytes may start at any byte boundary, while all valid bytes in a given cycle need to be contiguous. for example, a packet may be built up from the following buffers, with each one being transferred in a different burst: buffer 1: buffer 2: b3 b2 b1 x x x x x b11 b10 b9 b8 b7 b6 b5 b4 xxxxxxxb12 xxxb14b13xxx
IXF440 multiport 10/100 mbps ethernet controller datasheet 49 buffer 3: 4.2.2 network transmission the IXF440 will start to transmit the packet if there is enough data in the transmit fifo according to the programmable transmission threshold (tx_tshd_boff), or if the full packet is loaded into the transmit fifo. during the first phase of transmission, which includes the first 64 bytes, the data is kept on the transmit fifo to ensure retransmission of the packet in case of collision without needing to reload the packet onto the transmit fifo. if the packet is transmitted without error, the next packet is continuously loaded into the fifo and transmitted onto the network, with a minimum gap between them. normal packet transmission may also generate an interrupt, if programmed to do so. during packet transmission, the following errors may occur: excessive collision a packet has collided during 16 consecutive attempts. late collision a collision occurred after transmission of 64 bytes. fifo underflow data was not ready in the fifo during packet transmission. the IXF440 can be programmed to stop or to continue working when a transmit error occurs. in the error continuing mode, the ix bus behaves the same way with or without an error. in both modes, according to the error, the appropriate statistic counters will be updated. 4.2.3 excessive collisions by default, the IXF440 automatically retransmits a packet until it is successfully transmitted, even after excessive collisions. if the IXF440 is programmed to stop after excessive collisions (tx_err_mod), no more packets will be transmitted. 4.2.4 late collision in standard networks, late collisions are not expected to occur. in cases of late collisions, the IXF440 aborts the current transmission and continues with the next packet. if the IXF440 is programmed to stop after late collision (tx_err_mod), it will flush the transmit fifo and no more packets will be transmitted. 4.2.5 fifo underflow following an underflow, packet transmission is truncated, an mii error is generated (terr signal assertion), and a bad crc is appended to the packet. if the underflow occurs before the transmission of 60 bytes, padding is added first and then the bad crc. x b19 b18 b17 b16 b15 x x xxb21b20xxxx
IXF440 multiport 10/100 mbps ethernet controller 50 datasheet if the underflow occurs during transmission of the first 64 bytes of a packet, the IXF440 will automatically retransmit the packet. if the underflow occurs later, by default the IXF440 will continue with the next packet. if the IXF440 is programmed to stop after underflow (tx_err_mod), the transmit fifo will be flushed and no more packets will be transmitted. 4.2.6 stopping mode on transmission errors if an error is programmed to cause the transmit process to stop, the IXF440 will flush all the data found in the transmit fifo. the number of packets flushed from the transmit fifo and the transmission stop cause are reported in the transmit status register (terr_stt). the subsequent packets will be loaded only after the fifo is restarted (port_ctr). transmission errors may also generate an interrupt, if programmed to do so. in the single-packet mode (tx_param), new packets are loaded into the transmit fifo only after successful transmit completion of the previous packet. in case of an error, only the erroneous packet is flushed from the fifo.
IXF440 multiport 10/100 mbps ethernet controller datasheet 51 4.2.7 transmit flow diagram figure 2 shows the transmit flow diagram. 4.3 packet reception the following sections describe the packet reception policy. figure 2. transmit flow diagram
IXF440 multiport 10/100 mbps ethernet controller 52 datasheet 4.3.1 packet storing packets received from the network are loaded into the receive fifo. received packets are transferred from the receive fifo onto the ix bus during burst accesses. to indicate the minimal amount of data available in the receive fifo, the rxrdy signal is asserted according to a programmable threshold (ffo_tshd). if the end of a packet is loaded onto the fifo, the rxrdy signal is asserted even if the amount of data available is below the threshold value. the fbe_l[7:0] signals are used to report which bytes driven onto the bus are valid. for example, they indicate which bytes are valid in the last bus transfer of a packet. the first packet data is signalled with the sop signal, while the last data is signalled with the eop signal. following the last data transfer of a received packet, a field describing the packet status is driven on the data bus, reporting the status of the packet and its length. the packet status is driven on the ix bus according to the description in table 11 . in 64-bit ix bus mode, the byte enables for the status word will report all eight data bytes as valid (fbe_l<7:0>=00h). in 32-bit ix bus mode, the lower four bytes are valid (fbe_l<7:0>=f0h). further reads from the receive fifo during the same access are ignored to prevent transfer of the next packet in the same burst. the byte enables for these additional read transactions will report that all bytes contain invalid data (fbe_l<7:0>=ffh). if the IXF440 is programmed to remove crc (rx_param), the last four bytes of the packet will not be transferred on the ix bus, and eop will be asserted on the packet ? s last data word. at a given time, multiple packets may be loaded in the receive fifo. the packet status is appended to any packet completely transferred onto the ix bus, and is driven onto the ix bus in the access following the last byte transfer. if the last byte was transferred on the last cycle of the burst, then the rxrdy signal is asserted again to indicate that the packet status was not transferred. the packet length indicates the number of bytes received in this packet on the serial line, independent of the packet transfer on the ix bus. for the 64-bit bus mode (ffo_bus), the packet status is passed on twice on the fbus: on the 32 low bits and on the 32 high bits. the status will always be driven as little endian data as described in table 7 and table 8 . during status transfer, the value of the fbe_l<7:0> signals can be ignored, as the full status word is always valid. table 11. ix bus receive packet status bit name bit number bit description len 31:16 packet length ? 15:11 reserved mlt 10 multicast packet brd 9 broadcast packet rok 8 receive ok flw 7 flow-control packet ? 6 reserved mer 5 mii error rtl 4 too long packet rnt 3 runt packet drb 2 alignment error crc 1 crc error ovf 0 receive fifo overflow (if set, len field is not valid)
IXF440 multiport 10/100 mbps ethernet controller datasheet 53 4.3.2 header preprocessing the IXF440 supports the ability to process the packet header in several ways. the header size is programmable (rx_param) and may be changed according to the required processing (for example, mac header, vlan header, or layer3 header). when header ready mode is enabled (ffo_bus=0) and a packet header has been fully loaded into the receive fifo, the IXF440 will assert the rxrdy signal, even if the header size is smaller than the programmed receive threshold. in this instance, the first burst of a packet must be shorter than or equal to the header size. the packet header may also be read from the receive fifo for processing without removing it from the fifo. if the IXF440 is programmed to work in the header replay mode (rx_param), the packet header will be transferred twice onto the ix bus: the first time for header processing and the second time with the packet transfer. 4.3.3 packet segmentation the IXF440 supports receive packet segmentation on any byte boundaries. when the rxkep signal is asserted on the last cycle of a burst, the last data transfer of that burst will be reissued on the next burst. the rxkep signal is ignored when it is asserted in one of the following cases: nonvalid data, last data of the packet, or last data of the header on header replay mode (rx_param). in the example, rxkep is asserted on the last cycle of a three octal word burst from the IXF440, causing the third octal word to be retained in the receive fifo. during the next receive burst, this same octal word will be driven as the first data word of the burst. any masking of data bytes to the buffers is performed by the host. in the example, the host places bytes 1 ? 19 in the first buffer (a result of the first burst) and bytes 20 ? 28 in the second buffer (a result of the second burst). buffer 1: buffer 2: 4.3.4 packet abortion during the transfer of a received packet onto the ix bus, the IXF440 supports the ability to prevent any further transfer of this packet. at any time during packet reception, the packet may be dynamically discarded from the receive fifo by asserting the rxabt signal during packet reading. any subsequent packet loaded into the receive fifo is not affected by rxabt assertion. the next fifo access will be the next packet. b8 b7 b6 b5 b4 b3 b2 b1 b16 b15 b14 b13 b12 b11 b10 b9 xxxxxb19b18b17 b24 b23 b22 b21 b20 x x x ? replayed xxxxb28b27b26b25
IXF440 multiport 10/100 mbps ethernet controller 54 datasheet 4.3.5 network reception a packet received from the network is loaded into the receive fifo. if the packet is received without any error, it is transferred to the ix bus. if an error occurs during reception, the packet is handled according onto the programming. the IXF440 may be programmed to work in two modes: reject the erroneous packet or accept it (rx_filt_mod). in both modes, according to the error, the appropriate statistic counters will be updated, even if the packet was rejected due to packet error or fifo overflow. even in case of errors, any following packets continue to be accepted and loaded to the receive fifo. the following events are considered as reception errors: fifo overflow crc error alignment error short packet too long packet mii error 4.3.6 rejecting mode on reception errors if a packet with a reception error is programmed to be rejected, the IXF440 discards the packet from the receive fifo without affecting previous packets that may still be in the receive fifo. if the packet had not yet started to be transferred on the ix bus, it will be discarded without affecting ix bus activity. if the packet had already started to be transferred onto the ix bus, or rxrdy was already asserted, the rxfail signal will be asserted on the next fifo access, indicating that the currently transferred packet was discarded from the receive fifo. packet status will not be driven for such a packet. runt packets that may be received due to collision on the network can be filtered by the IXF440 by programming the receive threshold to be greater than 64 bytes. 4.3.7 accepting mode on reception errors if a packet with a specific event is programmed to be accepted, it is transferred to the ix bus as a regular packet and the event type is reported in the packet status appended to the end of the packet. such a packet may also generate an interrupt, if programmed to do so. the cause of the interrupt is reported in the receive status register (recv_stt).
IXF440 multiport 10/100 mbps ethernet controller datasheet 55 4.3.8 receive flow diagram figure 3 shows the receive flow diagram. figure 3. receive flow diagram
IXF440 multiport 10/100 mbps ethernet controller 56 datasheet
IXF440 multiport 10/100 mbps ethernet controller datasheet 57 5.0 cpu interface operation the following sections describe the cpu interface operation. 5.1 cpu interface the IXF440 has a dedicated port for a cpu interface, enabling access to the different registers without interfering with packet transfer through the fifos. the cpu interface is generic and supports a wide range of standard controllers. each of the eight IXF440 ports has its own independent registers. each of the port registers is accessible through an 8-bit data bus and a 10-bit address bus. a specific port is addressed by using the port select signals (cps[2:0]), which may be considered a part of the address bus. each port has a dedicated interrupt signal (cint_l) to report special events to the cpu. each control and status register is 1 byte wide and accessible through a single cpu access. network statistic counters are multibyte wide and require multiple cpu accesses to be fully read. 5.2 network management the IXF440 includes network statistic counters defined by ethernet snmp mib and rmon mib standards. each event counter is 32 bits wide and each byte counter is 40 bits wide. to assemble each counter value, its bytes must be read from the lower to the upper addresses. partial byte reading is also possible. if the exact counter value is not required, the lower counter byte may not be read. if the counter is read often, the upper byte will always remain null and may not be read. each counter is accessible through two different addresses. one address will cause the read byte to reset, while the other will not. when a counter overflows, it remains stuck on the highest value it has reached, and can generate an interrupt if programmed accordingly. receive statistic counters are updated according to analysis of the received packet, while ignoring the IXF440 filtering mode or the receive fifo status. when the port is in the disable mode, the counters are not updated.
IXF440 multiport 10/100 mbps ethernet controller 58 datasheet 5.2.1 snmp mib support the IXF440 supports ethernet mib according to table 12 . table 12. snmp mib to IXF440 counters mapping snmp mac counters IXF440 statistic counters framestransmittedok tx_uni_ok_cnt + tx_mlt_ok_cnt + tx_brd_ok_cnt singlecollisionframes tx_scol_cnt multiplecollisionframes tx_mcol_cnt framesreceivedok rx_uni_ok_cnt + rx_mlt_ok_cnt + rx_brd_ok_cnt frameschecksequenceerrors rx_norm_crc_cnt alignmenterrors rx_norm_ali_cnt octetstransmittedok tx_oct_ok_cnt frameswithdeferredxmissions tx_defer_cnt latecollisions tx_lcol_cnt framesabortedduetoxscolls tx_xcol_cnt octetsreceivedok rx_oct_ok_cnt frametoolongerrors rx_long_ok_cnt + rx_long_crc_cnt multicastframesxmittedok tx_mlt_ok_cnt broadcastframesreceivedok rx_brd_ok_cnt multicastframesreceivedok rx_mlt_ok_cnt broadcastframesxmittedok tx_brd_ok_cnt pauseframestransmitted tx_pause_cnt pauseframesreceived rx_pause_cnt
IXF440 multiport 10/100 mbps ethernet controller datasheet 59 5.2.2 rmon statistic group support table 13 describes the IXF440 support of the rmon statistic group. if packets are loaded into the IXF440 to be transmitted as bad packets, they must be counted in the error counters, too. table 13. rmon statistics to IXF440 counters mapping rmon statistic counters IXF440 statistic counters etherstatsdropevents rx_ovf_cnt etherstatsoctets tx_oct_ok_cnt + tx_oct_bad_cnt + rx_oct_ok_cnt + rx_oct_bad_cnt etherstatspkts tx_uni_ok_cnt + tx_lcol_cnt + rx_uni_ok_cnt + etherstatsbroadcastpkts + etherstatsmulticastpkts + etherstatscrcalignerrors + etherstatsundersizepkts + etherstatsfragments + etherstatsoversizepkts + etherstatsjabber etherstatsbroadcastpkts tx_brd_ok_cnt + rx_brd_ok_cnt etherstatsmulticastpkts tx_mlt_ok_cnt + rx_mlt_ok_cnt etherstatscrcalignerrors rx_norm_ali_cnt + rx_norm_crc_cnt + tx_err_cnt etherstatsundersizepkts rx_short_ok_cnt etherstatsoversizepkts rx_long_ok_cnt etherstatsfragments rx_short_crc_cnt + tx_col_cnt etherstatsjabber rx_long_crc_cnt etherstatscollisions rx_runt_cnt + rx_short_crc_cnt + tx_col_cnt + tx_lcol_cnt etherstatspkts64octets tx_pkt_64_cnt + rx_pkt_64_cnt etherstatspkts65to127octets tx_pkt_65_cnt + rx_pkt_65_cnt etherstatspkts128to255octets tx_pkt_128_cnt + rx_pkt_128_cnt etherstatspkts256to511octets tx_pkt_256_cnt + rx_pkt_256_cnt etherstatspkts512to1023octets tx_pkt_512_cnt + rx_pkt_512_cnt etherstatspkts1024to1518octets tx_pkt_1024_cnt + rx_pkt_1024_cnt etherstatsdropevents rx_ovf_cnt etherstatsoctets tx_oct_ok_cnt + tx_oct_bad_cnt + rx_oct_ok_cnt + rx_oct_bad_cnt
IXF440 multiport 10/100 mbps ethernet controller 60 datasheet 5.2.3 rmon host group support table 14 describes the IXF440 support of the rmon host group when a single node is connected to a port. if packets are loaded into the IXF440 to be transmitted as bad packets, they must be counted in the error counters, too. table 14. rmon host to IXF440 counters mapping rmon host counters IXF440 statistic counters hostinpkts tx_uni_ok_cnt + tx_mlt_ok_cnt + tx_brd_ok_cnt hostoutpkts rx_uni_ok_cnt + rx_mlt_ok_cnt + rx_brd_ok_cnt+ rx_norm_ali_cnt + rx_norm_crc_cnt + rx_short_ok_cnt + rx_short_crc_cnt + rx_long_ok_cnt + rx_long_crc_cnt + tx_col_cnt + tx_lcol_cnt hostinoctets tx_oct_ok_cnt hostoutoctets rx_oct_ok_cnt + rx_oct_bad_cnt hostouterrors rx_norm_ali_cnt + rx_norm_crc_cnt + rx_short_ok_cnt + rx_short_crc_cnt + rx_long_ok_cnt + rx_long_crc_cnt + tx_col_cnt + tx_lcol_cnt hostoutbroadcastpkts rx_brd_ok_cnt hostoutmulticastpkts rx_mlt_ok_cnt
IXF440 multiport 10/100 mbps ethernet controller datasheet 61 6.0 network interface operation this chapter describes the mii/sym port operation. it also describes media access control (mac), flow control, full-duplex, and loopback operations. the IXF440 supports full implementation of the mac sublayer according to the ieee 802.3 standard. 6.1 operating modes each of the IXF440 eight ports supports mii or sym interfaces. in the mii mode, the mii port provides a standard and simple interconnection between the mac sublayer and the phy layer. in this mode, the IXF440 can be used with any device with an mii interface that implements the 100base-tx, 100base-fx, 100base-t4, or 10base-t standards. through the mii interface, phys can also be connected beyond a connector. the mii interface comprises the following characteristics: supports both 100 mbps and 10 mbps data rates includes data and delimiters that are synchronous to clock references provides independent, 4-bit transmit and receive data paths utilizes ttl signal levels provides a simple management interface provides the capability to drive a limited length of shielded cable in the sym mode, the pcs encoding/decoding is done by the IXF440, which enables connection of simple fddi phy devices implementing the 100base-tx or 100base-fx standards. for 100base-tx connections, the IXF440 also implements scrambler and descrambler functions according to the ansi tp-pmd standard. the sym port is multiplexed together with the mii port.
IXF440 multiport 10/100 mbps ethernet controller 62 datasheet 6.2 mii port interface in the mii mode (ser_mod=0), the mii/sym port implements the ieee 802.3 standard mii interface. table 15 describes the mii port signal names as they refer to the appropriate ieee 802.3 signal names. the mii management signals (mdc and mdio) are common to all eight ports. table 15 describes the mii port signals versus standard signals. table 15. mii port signals versus standard signals mii signals ieee 802.3 signals purpose tclk{i} tx_clk transmit clock, synchronizes all transmit signals (ten{i}, txd{i}[3:0], terr{i}). in the 100 mbps data rate, operates at 25 mhz. in the 10 mbps data rate, operates at 2.5 mhz. rclk{i} rx_clk receive clock, synchronizes all receive signals (dv{i}, rxd{i}[3:0], rerr{i}). in the 100 mbps data rate, operates at 25 mhz. in the 10 mbps data rate, operates at 2.5 mhz. ten{i} tx_en transmit enable, asserted by the mac sublayer when the first transmit preamble nibble is driven over the mii. it remains asserted for the remainder of the frame, up to the last crc nibble. txd{i}[3:0] txd[3:0] these lines provide transmit data, driving a nibble on each tclk{i} cycle when ten{i} is asserted. terr{i} tx_err transmit error, asserted by the mac layer to generate a coding error on the nibble currently being transferred over txd{i}[3:0]. dv{i} rx_dv receive data valid, asserted by the phy layer when the first received preamble nibble is driven over the mii. it remains asserted for the remainder of the frame, up to the last crc nibble. rxd{i}[3:0] rxd[3:0] these lines provide receive data, driving a nibble on each rclk{i} cycle when dv{i} is asserted. rerr{i} rx_err receive error, asserted by the phy layer to indicate an error the mac cannot detect. if asserted during packet reception, indicates a coding error on the frame currently being transferred on rxd{i}[3:0]. if asserted while dv{i} is deasserted with rxd{i}[3:0] equal to 1110, indicates that a false carrier was detected by the phy layer. crs{i} crs carrier sense, asserted by the phy layer when either the transmit or receive medium is active (not idle). col{i} col collision, asserted by the phy layer when it detects a collision on the medium. remains asserted while this condition persists. mdc mdc management data clock, the mdio signal clock reference. mdio mdio management data input/output, used to transfer control signals between the phy layer and the manager entity. the IXF440 is capable of initiating control signal transfer between the IXF440 and the phy devices.
IXF440 multiport 10/100 mbps ethernet controller datasheet 63 6.3 mac frame format ethernet is the generic name for the network type implementing the ieee 802.3 standard. an ethernet frame has a minimum length of 64 bytes and a maximum length of 1518 bytes, excluding the preamble and the sfd bytes. an ethernet frame format consists of the following fields: preamble start frame delimiter (sfd) two address fields type or length field data field frame check sequence (crc value) note: numbers in parentheses indicate field length in bytes. table 16 describes the ethernet frame fields. the crc polynomial, as specified in the 802.3 standard, is as follows: fcs(x) = x 31 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 +x 8 +x 7 +x 5 +x 4 +x 2 +x 1 +1 the 32 bits of the crc value are placed in the fcs field so that the x31 term is the right-most bit of the first octet. the crc bits are thus transmitted in the following order: x31, x30,..., x1, x0. preamble sfd destination address source address type/length data fcs (7) (1) (6) (6) (2) (46..1500) (4) table 16. ethernet frame description field description preamble a 7-byte field of alternating 1s and 0s: 10101010. sfd (start frame delimiter) a single-byte field containing the value 10101011. destination address a 6-byte field containing either a specific station address, or the broadcast address, or a multicast (logical) address, all of which indicate the frame ? s destination. source address a 6-byte field containing the specific station address of frame origin. type/length a 2-byte field indicating whether the frame is in the ieee 802.3 format or the ethernet format. a field greater than 1500 is interpreted as a type field, which defines the protocol type. a field smaller than or equal to 1500 (05-dc) is interpreted as a length field, indicating the number of data bytes in the frame. data a data field consisting of 46 to 1500 information bytes. this data field is fully transparent because any arbitrary sequence of bits can occur. a data field shorter than 46 bytes, specified by the length field, is allowed. in its default mode, padding is enabled and up to 46 bytes are added to the data field by the IXF440 when transmitting. fcs (frame check sequence) a 32-bit cyclic redundancy check (crc), computed as a function of the destination address field, source address field, type field, and data field. the fcs is appended to each transmitted frame and is used during reception to determine if the received frame is valid.
IXF440 multiport 10/100 mbps ethernet controller 64 datasheet a frame octet is transferred on the serial line from the lsb to the msb. the octet d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 , where d 7 is the msb, is transferred on the mii data signals as two consecutive nibbles: first d 3 d 2 d 1 d 0 and then d 7 d 6 d 5 d 4. 6.4 mac transmit operation this section describes the transmit operation in detail, as supported by the IXF440. transmit activities are registered into the network management registers, which are accessible through the cpu port. 6.4.1 transmit initiation after the transmit fifo is adequately filled up to the programmed threshold level (tx_tshd_boff), or after there is a full frame loaded into the transmit fifo, the IXF440 starts to encapsulate the frame. the transmit encapsulation is performed by the transmit controller, which delays the actual transmission of the data onto the network until it has been idle for a minimum interpacket gap (ipg) time. 6.4.2 initial deferral the IXF440 constantly monitors the line. actual transmission of the data onto the network occurs only if it has been idle for a 96-bit time period and any backoff time requirements have been satisfied. in accordance with the standard, the IXF440 begins to measure the ipg in full-duplex mode from the tendeassertion, and from crs deassertion in half-duplex mode. because crs deassertion is an asynchronous event, it may be necessary to adjust the ipg used by the IXF440 in half-duplex mode (depending on the mii or sym physical-layer selection). care should be taken to maintain standards compliance if these fields are modified. the ipg time includes two parts, ips1 and ips2: ips1 time (60 ? bit time) the IXF440 monitors the network for an idle state. if a carrier is sensed on the serial line during this time, the IXF440 defers and waits until the line is idle again before restarting the ips1 time count. if a carrier is sensed during the first 40-bit time after transmission of the IXF440, the IXF440 does not defer (carrier sense inhibition period). ips2 time (36 ? bit time) the IXF440 continues to count time even if a carrier has been sensed on the network, and thus forces collisions on the network. this enables all network stations to fairly access the serial line. 6.4.3 frame encapsulation the transmit data frame encapsulation stream includes the appending of the 56 preamble bits and the sfd to the basic frame beginning, and the fcs to the basic frame end. the basic frame loaded from the bus includes the destination address field, the source address field, the type/length field, and the data field. if the data field length is shorter than 46 bytes, and padding as well as crc appending are not disabled (tx_param), the IXF440 pads the basic frame with the pattern 00 for up to 46 bytes. at the end of the frame, the IXF440 appends the fcs field if crc appending is not disabled. if during the beginning of the packet load, the txasis signal is asserted, the IXF440 ignores the programmed mode and transmits the frame without the padding and the fcs field.
IXF440 multiport 10/100 mbps ethernet controller datasheet 65 in the mii mode, the transmit enable signal (ten{i}) is asserted together with the first preamble byte transmission and is deasserted with the last crc byte transmission. 6.4.4 collision a collision occurs on a half-duplex network when concurrent transmissions from two or more nodes take place. during transmission, the IXF440 monitors the line condition. in the mii mode, the IXF440 detects a collision when the collision detect signal (col{i}) asserts. when the IXF440 detects a collision while transmitting, it halts transmission of the data and transmits a 32-bit jam pattern. if the collision was detected during the preamble or the sfd transmission, the jam pattern is transmitted after completing the sfd. this results in a minimum 96-bit fragment. note: the jam pattern is a fixed pattern that is not compared to the actual frame crc. it has a very low probability (0.5 32 ) of having a jam pattern identical to the crc. in standard networks, collisions will always occur before transmission of 64 bytes (including preamble and sfd), in which case the IXF440 begins the backoff wait period. the IXF440 scheduling of retransmission is determined through a controlled randomization process, termed the truncated binary exponential backoff. the delay time is represented by an integer multiple of slot times (1 slot is equal to a 512-bit time period). the number of the delay slot times, before the n th retransmission attempt, is chosen as a uniformly distributed random integer in the range: 0 r < 2 k k = min(n, n) the maximum backoff time is programmable by limiting the ? n ? number (tx_tshd_boff). in the ieee 802.3 standard, ? n ? is equal to 10. when 16 transmission attempts have been made, all terminated by collisions, the IXF440 reports an excessive collision event. the IXF440 then stops transmission if programmed to do so (tx_err_mod). otherwise, it will continue to transmit the same packet again and again, while restarting the backoff algorithm as if it were a new packet (n = 0). in network topology violating standard requirements, collision may occur after transmission of 64 bytes. if the IXF440 was programmed to stop upon late collision (tx_err_mod), it will flush the transmit fifo and stop transmitting. otherwise, the IXF440 will discard the packet from its fifo, and resume transmission with the next packet. 6.4.5 terminating transmission a specific frame transmission is terminated under any of the following conditions: normal the frame has been transmitted successfully. after the last byte is serialized, the pad and crc are optionally appended and transmitted, thus concluding frame transmission. crc error the txerr signal was asserted during packet loading. the IXF440 infects the crc it is building and sends a bad crc onto the network. an mii error is generated as well (terr assertion in mii mode). underflow transmit data is not ready when needed for transmission. the packet is terminated on the network with a bad crc and an mii error generation (terr assertion in mii mode). excessive collisions
IXF440 multiport 10/100 mbps ethernet controller 66 datasheet a collision occurs 16 consecutive times during transmission attempt of the same frame. late collision a collision occurs after the collision window (transmitting at least 64 bytes). the transmission is cut off. 6.4.6 backpressure the IXF440 provides the ability to prevent packet reception in the half-duplex mode. the backpressure mode can be activated by programming (ser_com) or by asserting the flct{i} signal. if any one of these is asserted, each receive activity detection triggers a transmit activity that will cause a collision. this transmission consists of a 96-bit pattern. in the backpressure mode, following a collision, the IXF440 resends packets with minimal ipg and without using the random backoff algorithm. 6.4.7 flow control in the full-duplex mode, the IXF440 supports the standard flow control defined in the ieee 802.3 standard, enabling the stopping of remote node transmissions. upon triggering, the IXF440 sends a flow control frame in the following format: the source address field (ea1 ? ea6) is taken from the phy_add register. upon assertion of the flct{i} signal or setting of the flow control trigger bit (ser_com), a flow control frame is sent with the pause time field (pt1 ? pt2) equal to the pause_time register. upon deassertion, another flow control frame will be sent with the pause time field equal to zero, meaning that the remote node may resume transmission. if the xon mode is disabled (tx_param), the flow control frame will not be transmitted on deassertion. if the chip is transmitting, the next flow control frame sent will be according to the last flow control trigger. 6.5 mac receive operation this section describes the detailed receive operation as supported by the IXF440. receive activities are registered into network management registers, which are accessible through the cpu port. 6.5.1 receive initiation the IXF440 continuously monitors the network when reception is enabled. when an activity is recognized, the IXF440 starts to process the incoming data. in the mii mode, the IXF440 detects activity when the data valid signal (dv{i}) asserts. destination address source address type op-code pause time padding fcs byte count 6 6 2 2 2 42 4 value (canonic form) 01-80-c2-00-00-01 ea1-ea2-..-ea6 88 - 08 00 - 01 pt1 - pt2
IXF440 multiport 10/100 mbps ethernet controller datasheet 67 after detecting receive activity on the line, the IXF440 starts to process the preamble bytes. 6.5.2 preamble processing the ieee 802.3 standard allows a maximum size of 56 bits (7 bytes) for the preamble, while the IXF440 allows any arbitrary preamble length. the IXF440 checks for the start frame delimiter (sfd) byte. if the IXF440 receives a binary 11 before receiving 6 bits or a binary 00 anywhere while checking for sfd, the reception of the current frame is aborted. the frame is not received, and the IXF440 waits until the network activity stops before monitoring the network activity for a new preamble. the interpacket gap (ipg) between received frames should be at least 32-bit times. 6.5.3 frame decapsulation while the frame is being assembled, the IXF440 continues to monitor the line condition. in the mii mode, the IXF440 detects the end of frame when the data valid signal (dv{i}) deasserts. reception terminates with a frame error if the frame is not a valid mac frame, or if an mii error was detected during frame reception. in the mii mode, an mii error is detected when the receive error signal (rerr{i}) asserts during frame reception. the IXF440 refers to the last 4 full bytes received as the crc. it checks the crc bytes of all received frames and reports all errors. only whole bytes are run through the crc check. 6.5.4 terminating reception when reception terminates, the IXF440 determines the status of the received frame and loads the status into the receive fifo. the IXF440 can report the following events at the end of frame reception: overflow the IXF440 receive fifo is not emptied as rapidly as it is filled, and an error occurs as frame data is lost. if the fifo is already full when a new frame is received, it will not be loaded in the fifo. crc error the 32-bit crc, transmitted with the frame, did not match the crc calculated upon reception. alignment error the frame did not end on a byte boundary, but with a spare nibble (4 bits), and a crc error has also occurred. if the frame was not composed of an integral number of bytes, but the crc was okay, the frame is considered good and no error is reported. mii error an mii error was detected during frame reception. frame too short a frame containing less than 64 bytes was received (including crc). frame too long
IXF440 multiport 10/100 mbps ethernet controller 68 datasheet a frame containing more than the programmed maximum size was received. 6.5.5 flow control in the full-duplex mode, the IXF440 identifies standard flow control frames during reception. if a flow control frame is received and flow control mode is enabled (tx_param), frame transmission will be stopped until expiration of the pause time. if flow control frames are received during frame transmission, the frame will be completely transmitted on the line, and then transmission will stop. the IXF440 identifies flow control frames according to the field matching described in table 17 , and correctness of the crc. the value of fields 17 ? 18 in the frame indicates the transmit pause time, represented in units of slot times. flow control frames are not loaded into the receive fifo. they are discarded following identification, unless the IXF440 is programmed to pass them (rx_filt_ mod). 6.6 mac full-duplex operation in full-duplex mode (ser_mod), the IXF440 activates the transmit and receive processes simultaneously. it also supports receive back-to-back packets with a minimal interpacket gap (ipg), in parallel with the transmission of back-to-back packets with an ipg of 96 bit times. in this mode, the mac will ignore both the carrier sense (crs{i}) and the collision detect (col{i}) signals. 6.7 mac loopback operations the IXF440 supports two loopback modes: internal loopback external loopback 6.7.1 internal loopback mode the internal loopback mode enables verification that the internal logic operates correctly. in this mode, frames loaded in the transmit fifo are transferred to the receive fifo through the transmit logic and receive logic. in the internal loopback mode, the IXF440 disconnects from the network. frames are not transmitted onto the line (except in sym mode), and frames received from the line are rejected. table 17. flow control field matching byte number value (canonic form) destination address 1 ? 6 01-80-c2-00-00-01 type 13 ? 14 88-08 op-code 15 ? 16 00-01
IXF440 multiport 10/100 mbps ethernet controller datasheet 69 6.7.2 external loopback mode the external loopback mode enables verification that the logic up to the wire operates correctly. in the external loopback mode (ser_mod), the external logic must be programmed to loop back frames from the transmit side to the receive side. in sym mode, the loopback will work properly even if the link detection signal (sd) is not asserted. 6.8 sym mode in the sym mode (ser_mod=1), the 100base-x pcs encoding and decoding is performed by the IXF440. the functions implemented in this mode include: 4-bit to 5-bit encoding in the transmit path 5-bit to 4-bit decoding in the receive path start-of-stream delimiter (ssd) and end-of-stream delimiter (esd) detection and generation bit alignment carrier detect collision detect symbol error detection link timer in the 100base-tx mode (ser_mod=1), the IXF440 also performs the scrambling and descrambling functions. in the sym mode, the mii/sym port works as a sym port. table 18 describes the sym port signal names and their appropriate functions. table 18. sym port signal description sym signals description tclk{i} 25 mhz transmit clock, synchronizing the txd{i} signals. rclk{i} 25 mhz receive clock, synchronizing the rxd{i} signals. txd{i}[4:0] transmit data lines, driving a symbol on each tclk{i} cycle. rxd{i}[4:0] receive data lines, driving a symbol on each rclk{i} cycle. lnk{i} link signal, asserted by the IXF440 when the pcs logic detects a link to a remote node. if the descrambler is enabled, the signal will not be asserted unless it is locked. sd{i} signal detect, asserted by the phy layer when it detects link connection to the remote mode. act{i} activity signal, asserted by IXF440 when it transmits a frame or is receiving a frame. rerr{i} not used. must be connected to 0.
IXF440 multiport 10/100 mbps ethernet controller 70 datasheet when operating in the sym mode, the IXF440 encapsulates and decapsulates the frames according to the ieee 802.3 100base-x standard. the mii port then serves as an internal port between the mac layer and the sym port. during transmit, encapsulation is performed according to the following rules: the first byte of the preamble in the mac frame is replaced with the jk symbol pair. all of the mac frame data is encoded according to 4b/5b standard encoding. after the fcs byte of the mac frame, the tr symbol pair is inserted. an idle symbol is transmitted between frames. mii error generation is translated to illegal symbol generation. during receive, decapsulation is performed according to the following rules: a non idle symbol will cause the internal carrier sense signal to be asserted. an ijk symbol sequence causes the internal data valid signal to be asserted (start of receive activity). the jk symbol pair is replaced by a preamble byte. all of the data symbol stream is decoded according to 5b/4b standard decoding. the tr symbol sequence will cause the internal data valid signal to be deasserted (end of receive activity). in the sym mode, collision is detected when the receive input is active while the IXF440 transmits. when the collision is detected, the internal collision detect signal is asserted. during receive, the IXF440 expects the frame to start with the symbol sequence ijk followed by the preamble. if an ijk symbol sequence is not detected, the reception of the current frame is aborted (not received), and the IXF440 waits until the network activity stops before monitoring the network activity for a new frame. during reception, the IXF440 also checks symbol validity. if an invalid symbol is being received, or if the frame does not end with the tri symbol sequence, the IXF440 reports an internal mii error.
IXF440 multiport 10/100 mbps ethernet controller datasheet 71 7.0 IXF440 timing diagrams this section contains the ix bus port and mii/sym port timing diagrams. 7.1 ix bus port timing diagrams this section describes the ix bus port timing diagrams. 7.1.1 transmit start-of-packet timing figure 4 shows the transmit start-of-packet timing. figure 4. transmit start-of-packet timing a4916-01 fbe_l[7:0] clk txsel_l fps[2:0] fdat[63:0] port number port number d1 d2 d3 d4 d5 d6 d7 be1 be2 be3 be4 be5 be6 be7 sop txasis/txerr eop note: txasis will only assert if no padding or crc error is to be appended.
IXF440 multiport 10/100 mbps ethernet controller 72 datasheet 7.1.2 transmit end-of-packet timing figure 5 shows the transmit end-of-packet timing. 7.1.3 transmit fifo control timing figure 6 shows the transmit fifo control timing. figure 5. transmit end-of-packet timing a4917-01 fbe_l[7:0] clk txsel_l fps[2:0] fdat[63:0] sop port number d1 d2 d3 d4 d5 d6 d7 d8 be1 be2 be3 be4 be5 be6 be7 be8 txasis/txerr eop note: txasis will only assert if the packet is to be transmitted with an mii error. figure 6. transmit fifo control timing
IXF440 multiport 10/100 mbps ethernet controller datasheet 73 7.1.4 transmit ready (txrdy) timing figure 7 shows the transmit ready (txrdy) timing. txrdy will assert a minimum of two cycles after the assertion of txctl_l, provided the available space in the transmit fifo meets the programmed threshold. txrdy assertion must also be at least two cycles after the deassertion of txsel_l. txrdy deasserts two cycles after the assertion of txsel_l. 7.1.5 receive start-of-packet timing figure 8 shows receive start-of-packet timing. note: rxsel_l must be deasserted for at least two cycles between two accesses to the same port. figure 7. transmit txrdy timing figure 8. receive start-of-packet timing
IXF440 multiport 10/100 mbps ethernet controller 74 datasheet 7.1.6 receive end-of-packet timing figure 9 shows the receive end-of-packet timing. 7.1.7 fastest receive reaccess after eop figure 10 shows the fastest receive reaccess to the same port after eop (to get status) figure 9. receive end-of-packet timing figure 10. fastest receive reaccess after eop a4919-01 clk rxsel# fps[2:0] port number status dn+2 dn+1 dn port number fdat[63:0] eop fbe#[7:0] be 00 ff 00 00
IXF440 multiport 10/100 mbps ethernet controller datasheet 75 7.1.8 receive rxfail timing figure 11 shows the receive rxfail timing. 7.1.9 receive rxabt timing figure 12 shows the receive rxabt timing. figure 11. receive rxfail timing figure 12. receive rxabt timing
IXF440 multiport 10/100 mbps ethernet controller 76 datasheet 7.1.10 receive rxkep timing figure 13 shows the receive rxkep timing. 7.1.11 receive header replay timing figure 14 shows the receive header replay timing. 7.1.12 receive fifo control timing figure 15 shows the receive fifo control timing. figure 13. receive rxkep timing figure 14. receive header replay timing figure 15. receive fifo control timing
IXF440 multiport 10/100 mbps ethernet controller datasheet 77 7.1.13 receive ready (rxrdy) control timing figure 16 shows the receive ready (rxrdy) control timing. rxrdy will asset a minimum of two cycles after the assertion of rxctl_l, provided the amount of data in the receive fifo meets the programmed threshold. rxrdy assertion must also be at least two cycles after the deassertion of rxsel_l. rxrdy deasserts two cycles after the assertion of rxsel_l. 7.1.14 consecutive transmit-transmit timing figure 17 shows the consecutive transmit-transmit timing. figure 16. receive rxrdy timing a4918-01 clk rxctl_l rxrdy{n} port number n rxsel_l fps[2:0] figure 17. consecutive transmit-transmit timing
IXF440 multiport 10/100 mbps ethernet controller 78 datasheet 7.1.15 consecutive transmit-receive timing figure 18 shows the consecutive transmit-receive timing. 7.1.16 consecutive receive-transmit timing figure 19 shows the consecutive receive-transmit timing. 7.1.17 consecutive receive-receive timing figure 20 shows the consecutive receive-receive timing. 7.2 mii/sym port timing diagrams this section shows the mii mii/sym port timing diagrams. the mii/sym port timing specification is compliant with the ieee 802.3 standard. figure 18. consecutive transmit-receive timing figure 19. consecutive receive-transmit timing figure 20. consecutive receive-receive timing
IXF440 multiport 10/100 mbps ethernet controller datasheet 79 7.2.1 packet transmission timing figure 21 shows the packet transmission timing. 7.2.2 packet reception timing figure 22 shows the packet reception timing. 7.2.3 transmission with collision timing figure 23 shows the transmission with collision timing. 7.2.4 false carrier timing figure 24 shows the false carrier timing. figure 21. packet transmission timing figure 22. packet reception timing figure 23. transmission with collision timing figure 24. false carrier timing

IXF440 multiport 10/100 mbps ethernet controller datasheet 81 8.0 electrical and environmental specifications this section contains the electrical and environmental specifications for the IXF440. the IXF440 supports both 5 v and 3.3 v signaling environments for all pins. 8.1 functional operating range table 19 lists the functional operating range. refer to section 8.2 for details about the absolute maximum ratings. the signalling environment for the ix bus pins are dependent on vdd_clmp. table 20 lists the ac parameters for the 3.3 v signaling levels. table 21 lists the ac parameters for the 5 v signaling levels. 8.2 absolute maximum rating applying stresses beyond the absolute maximum may cause unrecoverable damage to the device. operation of this product is not implied for any condition beyond the ranges specified in the functional operation range described in section 8.1 . operating this product at the absolute maximum rating for a prolonged period can negatively impact device reliability. table 19. functional operating range parameter minimum maximum power supply (vdd) 3 v 3.6 v vdd_clmp (5.0 v signaling) 4.75 v 5.25 v vdd_clmp (3.3 v signaling) 3 v min. (3.6 v, vdd + 0.3 v) esd protection voltage ? 2000 v esd protection voltage for vdd_clmp ? 1900 v table 20. 3.3 v ac signaling specifications parameter condition minimum icl (low clamp current) ? 3 v < vin < ? 1 v ? 25 + (vin + 1)/0.015 ma ich (high clamp current) vdd + 4 > vin > vdd + 1 25 + (vin ? vdd ? 1)/0.015 ma table 21. 5 v ac signaling specifications parameter condition minimum icl (low clamp current) ? 5 v < vin < ? 1v ? 25 + (vin + 1)/0.015 ma
IXF440 multiport 10/100 mbps ethernet controller 82 datasheet table 22 lists the absolute maximum rating for the IXF440. 8.3 supply current and power dissipation the values listed in table 23 are based on a 66 mhz ix bus clock frequency. 8.4 temperature limit ratings table 24 lists the temperature limit ratings. 8.5 reset specification the IXF440 reset signal (reset_l) is an asynchronous signal that must be active for at least 10 ix bus clock (clk) cycles with stable power. table 22. absolute maximum rating parameter maximum rating supply voltage (vdd) 3.9 v signal pins (vsig) 5.5 v junction temperature (tj) 125 c table 23. supply current and power dissipation power supply maximum current maximum power 3.3 v 750 ma 2.5 w 3.6 v 830 ma 3 w table 24. temperature limit ratings parameter minimum maximum storage temperature ? 55 c 125 c operating temperature 0 c 70 c
IXF440 multiport 10/100 mbps ethernet controller datasheet 83 8.6 fifo port specifications this section describes the fifo port specifications. 8.6.1 clock specification figure 25 shows the ix bus clock timing diagram. table 25 lists the specifications of the ix bus clock. 8.6.2 3.3 volt dc specifications table 26 lists the dc parameters for the ix bus 3.3 v signaling levels. figure 25. ix bus clock timing diagram table 25. ix bus clock timing specifications symbol parameter condition minimum maximum freq clock frequency ? 25 mhz 1 1. for testing purposes, the minimum frequency is 16 mhz. 66.6 mhz tc c y cl e t i me ? 15 ns 40 ns th clock high time ? 6 ns ? tl clock low time ? 6 ns ? vptp clock peak to peak (0.2 vdd to 0.6 vdd) 3.3 v clock 0.4 vdd ? vh clock high threshold 3.3 v clock 0.5 vdd ? vl clock low threshold 3.3 v clock ? 0.3 vdd vptp clock peak to peak (0.4 v to 2.4 v) 5 v clock 2 v ? vh clock high threshold 5 v clock 2 v ? vl clock low threshold 5 v clock ? 0.8 v table 26. ix bus 3.3 v signaling specifications symbol parameter condition minimum maximum vih input high voltage ? 0.5 vdd vdd_clmp + 0.5 v 1 1. overvoltage protection maximum is +7.1 v through a series 29 ? resistor for 11 ns. vil input low voltage ?? 0.5 v 2 0.3 vdd ii input leakage current 0 < vin < vdd ? 15 a 15 a voh output high voltage iout = ? 500 a 0.9 vdd ? vol output low voltage iout = 1500 a ? 0.1 vdd cin pin capacitance ? 5 pf 10 pf
IXF440 multiport 10/100 mbps ethernet controller 84 datasheet 8.6.3 5 volt dc specifications table 27 lists the dc parameters for the ix bus 5 v signaling levels. 8.6.4 ix bus signals timing figure 26 shows the ix bus signals timing diagram. table 28 lists the timing specifications of the ix bus signals. 2. overvoltage protection minimum is ? 3.5 v through a series 28 ? resistor for 11 ns. table 27. ix bus 5-v signaling specifications symbol parameter condition minimum maximum vih input high voltage ? 2.0 v vdd_clmp + 0.5 v 1 1. overvoltage protection maximum is +11 v through a series 29 ? resistor for 11 ns. vil input low voltage ?? 0.5 v 2 2. overvoltage protection minimum is ? 5.5 v through a series 28 ? resistor for 11 ns. 0.8 v ii input leakage current 0.5 v < vin < 2.7 v ? 15 a 15 a voh output high voltage iout = ? 2 ma 2.4 v ? vol output low voltage iout = 6 ma ? 0.55 v cin pin capacitance ? 5 pf 10 pf figure 26. ix bus signals timing diagram table 28. ix bus signals timing specifications symbol parameter minimum (ns) maximum (ns) tval clock-to-signal valid delay 2 7 tsu input signal valid setup time before clock 4 ? th input signal hold time from clock 1 ?
IXF440 multiport 10/100 mbps ethernet controller datasheet 85 8.7 cpu port specifications this section describes the cpu port electrical specifications. 8.7.1 dc specifications table 29 lists the cpu port dc specifications. 8.7.2 signals timing this section describes the timing diagram of the cpu port. 8.7.2.1 read timing figure 27 shows the cpu port read timing diagram. table 29. cpu port dc specifications symbol parameter condition minimum maximum vih input high voltage ? 2v ? vil input low voltage ?? 0.8 v voh output high voltage ioh = ? 4 ma 2.4 v ? vol output low voltage iol = 4 ma ? 0.4 v ii input leakage current ?? 15 a 15 a cin pin capacitance ? 5 pf 10 pf iol crdy_l, cint{i}_l output low current vol = 0.55 v 20 ma 50 ma
IXF440 multiport 10/100 mbps ethernet controller 86 datasheet 8.7.2.2 write timing figure 8-4 shows the cpu port write timing diagram. figure 27. cpu port read timing diagram figure 28. cpu port write timing diagram
IXF440 multiport 10/100 mbps ethernet controller datasheet 87 8.7.2.3 timing parameters table 30 lists the cpu bus clock timing parameters. 8.8 mii/sym port specifications the mii/sym port electrical specifications are compliant with the ieee 802.3 standard. 8.8.1 dc specifications table 31 lists the mii/sym port dc specifications. 8.8.2 signals timing this section describes the timing diagram of the mii/sym port. table 30. timing parameters symbol parameter minimum maximum tcas cadd[9:0], cps[2:0], cs_l setup time 10 ns ? tcah cadd[9:0], cps[2:0], cs_l hold time 10 ns ? tcrr crdy_l assertion to crd_l deassertion 10 ns ? tcrh crd_l high width 3 tc 1 1. tc is the ix bus clock cycle time. ? tcdrs cdat[7:0] to crdy_l setup time 10 ns ? tcdrh crd_l to cdat[7:0] hold time tc 4 tc tcdrd read cdat[7:0] driving delay 3 tc 15 tc tci crd_l to cint_l clear delay ? 5 tc tcwl cwr_l low width 3 tc ? tcwh crdy_l to cwr_l hold time 2 tc ? tcdws cdat[7:0] to cwr_l setup time 10 ns ? tcdwh crdy_l to cdat[7:0] hold time 10 ns ? tcdwd write cdat[7:0] latching delay 2 tc 4 tc tcyd crdy_l width in write cycle 4 tc 4 tc trtw read crdy_l deassertion to cwr_l assertion 4 tc ? twtr write crdy_l deassertion to crd_l assertion 4 tc ? table 31. mii/sym port dc specifications symbol parameter condition minimum maximum vih input high voltage ? 2v ? vil input low voltage ?? 0.8 v voh output high voltage ioh = ? 4 ma 2.4 v ? vol output low voltage iol = 4 ma ? 0.4 v ii input leakage current ?? 15 a 15 a cin pin capacitance ? 5 pf 10 pf
IXF440 multiport 10/100 mbps ethernet controller 88 datasheet 8.8.2.1 clocks specifications figure 29 shows the mii/sym port clocks timing diagram. table 32 lists the mii/sym port signals timing specifications. 8.8.2.2 signals timing diagrams figure 30 shows the mii/sym port transmit timing characteristics. figure 31 shows the mii/sym port receive timing characteristics. figure 29. mii/sym clock timing diagram table 32. mii/sym port signals timing specifications symbol parameter minimum maximum fm10 tclk, rclk frequency in 10 mbps 2.5 mhz ? 100 ppm 2.5 mhz + 100 ppm fm100 tclk, rclk frequency in 100 mbps 25 mhz ? 100 ppm 25 mhz + 100 ppm tmc tclk, rclk cycle time ?? tmh tclk, rclk high time 0.35 tmc 0.65 tmc tml tclk, rclk low time 0.35 tmc 0.65 tmc vmh tclk, rclk high threshold 2 v ? vml tclk, rclk low threshold ? 0.8 v figure 30. mii/sym port transmit timing diagram
IXF440 multiport 10/100 mbps ethernet controller datasheet 89 figure 32 shows the mii/sym port carrier sense and collision timing diagram. 8.8.2.3 data timing parameters table 33 describes the data timing parameters. 8.9 jtag port specifications this section describes the jtag port electrical specifications. 8.9.1 dc specifications table 34 lists the jtag port dc specifications. figure 31. mii/sym port receive timing diagram figure 32. mii/sym port carrier sense and collision timing diagram table 33. data timing parameters symbol parameter minimum maximum tmv 1. txd, terr, output valid hold after tclk 0 ns ? 2. ten, output valid hold after tclk 0 ns ? tmval tclk to output valid delay ? 16 ns tmsu input setup time before rclk 10 ns ? tmh input hold time after rclk 10 ns ? tmw col, crs high time 20 ns ?
IXF440 multiport 10/100 mbps ethernet controller 90 datasheet 8.9.2 signals timing figure 33 shows the jtag port timing characteristics. table 34. jtag port dc specifications symbol parameter condition minimum maximum vih input high voltage ? 2v ? vil input low voltage ?? 0.8 v voh output high voltage ioh = ? 4 ma 2.4 v ? vol output low voltage iol = 4 ma ? 0.4 v ii input leakage current (tck) ?? 20 a 20 a iip input leakage current with internal pull-up (tdi, tms) ?? 1500 a 20 a io tristate output leakage current (tdo) ?? 20 a 20 a cin pin capacitance ? 5 pf 10 pf figure 33. jtag port timing diagram
IXF440 multiport 10/100 mbps ethernet controller datasheet 91 table 35 lists the jtag port timing specifications. table 35. jtag port timing specifications symbol parameter minimum maximum tjc tck cycle time 90 ns ? tjh tck high time 0.4 tjc 0.6 tjc tjl tck low time 0.4 tjc 0.6 tjc tjval tck fall to tdo valid delay ? 20 ns tjsu tms and tdi setup time before tck 20 ns ? tjh tms and tdi hold time from tck 5 ns ?
IXF440 multiport 10/100 mbps ethernet controller 92 datasheet
IXF440 multiport 10/100 mbps ethernet controller datasheet 93 9.0 mechanical specifications the IXF440 is contained in a 352-bga package. figure 34 shows the part marking. figure 35 , figure 36 , and figure 37 show the 352-bga package. table 36 lists the dimensions in millimeters. figure 34. part marking a8038-01 gcIXF440ac ffffffff intel 2000 korea country of origin fpo # intel legal name pin #1 c m
IXF440 multiport 10/100 mbps ethernet controller 94 datasheet figure 36. side view figure 37. a?a section view figure 35. 352-bga package - bottom view table 36. 352-bga dimensional attributes dimension symbol minimum nominal maximum package overall thickness a 1.41 1.54 1.67 ball height a 1 0.56 0.63 0.7 body thickness a2 0.85 0.91 0.97
IXF440 multiport 10/100 mbps ethernet controller datasheet 95 body size e 34.9 35 35.1 ball footprint e 1 31.65 31.75 31.85 ball matrix ?? 26 26 ? number of rows deep ?? 4 ? ball diameter b 0.6 0.75 0.9 minimum distance encapsulation to balls d ? 0.6 ? ball pitch e ? 1.27 ? coplanarity aaa ?? 0.20 parallel bbb ?? 0.15 top flatness ccc ?? 0.2 seating plane clearance ddd 0.15 0.33 0.5 encapsulation height p 0.2 0.3 0.35 solder ball placement s ?? 0.635 table 36. 352-bga dimensional attributes dimension symbol minimum nominal maximum
IXF440 multiport 10/100 mbps ethernet controller datasheet 95 joint test action group ? test logic a this appendix describes the joint test action group (jtag) test logic and the associated registers. a.1 general description jtag test logic supports testing, observation, and modification of circuit activity during normal operation of the components. the IXF440 supports the ieee standard 1149.1 test access port and boundary scan architecture. the IXF440 jtag test logic allows boundary scan to be used to test both the device and the board it is installed in. the jtag test logic consists of the following four signals to serially interface within the IXF440: tck ? jtag clock tdi ? test data and instructions in tdo ? test data and instructions out tms ? test mode select note: if jtag test logic is not used, the tck pin should be connected to ? 0 ? , and both the tms and tdi pins should be connected to ? 1 ? . the tdo signal should remain unconnected. if jtag logic is used, a 1149.1 ring is created by connecting one device ? s tdo pin to another device ? s tdi pin and so on, to create a serial chain of devices. in this application, the IXF440 receives the same tck and tms signals as the other devices. the entire 1149.1 ring is connected to either a motherboard test connector for test purposes or to a resident 1149.1 controller. a.1.1 test access port controller the test access port (tap) controller interprets ieee p1149.1 protocols received on the tms pin. the tap controller generates clocks and control signals to control the operation of the test logic. the tap controller consists of a state machine and a control dispatch logic. the IXF440 fully implements the tap state machine as described in the ieee p1149.1 standard. a.2 registers in jtag test logic, three registers are implemented in the IXF440: instruction register bypass register boundary-scan register
IXF440 multiport 10/100 mbps ethernet controller 96 datasheet a.2.1 instruction register the IXF440 jtag test logic instruction register is a 3-bit scan-type register that is used to program the jtag machine to the appropriate operating mode. its contents are interpreted as test instructions. table a-1 lists the instructions register. a.2.2 bypass register the bypass register is a 1-bit shift register that provides a single-bit serial connection between the tdi and tdo signals. this register is used when the instruction register is set to bypass mode or after powerup. a.2.3 boundary-scan register the boundary-scan register consists of cells located on all the pads. this register provides the ability to perform board-level interconnection tests by shifting data inside through tdi and outside through tdo. it also provides additional control and observation of the IXF440 pins. for example, the IXF440 boundary-scan register can observe the output enable control signals of the i/o pads. table a-1. instructions register ir<2> ir<1> ir<0> description 000 extest mode (mandatory instruction). test data is shifted into the IXF440 boundary-scan register and then transferred in parallel to the output pins. 001 sample-preload mode (mandatory instruction). test data is loaded in parallel from the input pins into the IXF440 boundary-scan register and then shifted out for examination. 010 ixf-extest mode (mandatory instruction). used when the IXF440 is configured as split (32-bit dual unidirectional ix bus). test data is shifted into the IXF440 boundary-scan register and then transferred in parallel to the output pins. 011 ixf-sample-preload mode (mandatory instruction). used when the IXF440 is configured as split (32-bit dual unidirectional ix bus). test data is loaded in parallel from the input pins into the IXF440 boundary-scan register and then shifted out for examination. 100reserved 101 tristate mode (optional instruction). allows the IXF440 to enter the power-saving mode. in this mode, all the port pads are tristated. 110 continuity mode (optional instruction). allows the IXF440 continuity test. in this mode, all the port pads get a ? 0 ? value. 111 bypass mode (mandatory instruction). allows the test features on the IXF440 test logic to be bypassed. bypass mode is selected automatically when power is applied.
IXF440 multiport 10/100 mbps ethernet controller datasheet 97

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