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september 2010 ? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsa2269 / fsa2269ts ? rev. 1.1.3 fsa2269 / fsa2269ts ? low-voltage dual-spdt (0.4 fsa2269 / fsa2269ts ? low-voltage dual-spdt (0.4 ) analog switch with negative swing audio capability features ? 0.4 ? typical on resistance (r on ) for +3.0v supply ? 0.25 ? maximum r on flatness for +3.0v supply ? -3db bandwidth: > 50mhz ? low-i cct current over an expanded control input range ? packaged in 10-lead micropak?, umlp, and wlcsp ? power-off protection on common ports ? broad v cc operating range: 1.65 to 4.5v ? noise immunity termination resistors in fsa2269ts applications ? cell phone, pda, digital camera, and notebook ? lcd monitor, tv, and set-top box description the fsa2269 is a high-performance, dual single-pole double-throw (spdt) analog switch with negative swing audio capability. the fsa2269 features ultra-low r on of 0.4 (typical) at 3.0v v cc . the fsa2269 operates over a wide v cc range of 1.65v to 4.5v, is fabricated with sub-micron cmos technology to achieve fast switching speeds, and is designed for break-before- make operation. the select input is ttl-level compatible. the fsa2269 features very low quiescent current even when the control voltage is lower than the v cc supply. this feature suits mobile handset applications by allowing direct interface with baseband processor general-purpose i/os with minimal battery consumption. the fsa2269ts includes termination resistors that improve noise immunity during overshoot excursions, off-isolation coupling, or ?pop-minimization.? important note: for additional information, please contact analogswitch@fairchildsemi.com . ordering information part number top mark package description fsa2269l10x hl 10-lead, micropak , jedec mo-255, 1.6 x 2.1mm fsa2269umx hp 10-lead, quad ultrathin molded leadless package (umlp), 1.4 x 1.8mm, 0.4mm pitch fsa2269tsl10x hu 10-lead, micropak , jedec mo-255, 1.6 x 2.1mm fsa2269tsumx ht 10-lead, quad ultrathin molded leadless package(umlp), 1.4 x 1.8mm, 0.4mm pitch FSA2269UCX n9 12-ball, wafer-level chip scale package (wlcsp),1.2 x 1.6mm, 0.4mm pitch analog symbols figure 1. fsa2269 figure 2. fsa2269ts (with slow turn on) 1b0 1b1 1a s1 2b0 2b1 2a s2 2b0 2b1 2a gnd s2 10k 1b0 1b1 1a gnd s1 10k 3s t on 3s t on
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsa2269 / fsa2269ts ? rev. 1.1.3 2 fsa2269 / fsa2269ts ? low-voltage dual-spdt (0.4 2 1 3 4 gnd v cc 10 2b1 1b1 1b0 2b0 2a s1 1a s2 5 9 8 7 6 pin configuration figure 3. 10-pin umlp (top through view) figure 4. 10-pin micropak? (top through view) figure 5. 12-ball wlcsp (bump side view) figure 6. 12-ball wlcsp (top side view) pin descriptions pin # umlp pin # micropak wlcsp name description 1 2 b1 1b1 data ports 2 3 d3 2b0 data ports 3 4 b3 2b1 data ports 4 5 b2,c2 gnd ground 5 6 c3 2a data ports 6 7 a3 s2 switch select pins 7 8 a1 s1 switch select pins 8 9 c1 1a data ports 9 10 d2 v cc supply voltage 10 1 d1 1b0 data ports truth table control input, sn function low logic level nb0 connected to na (fsa2269/2269ts); nb1 terminated to gnd (fsa2269ts only) high logic level nb1 connected to na (fsa2269/226 9ts); nb0 terminated to gnd (fsa2269ts only) v cc gnd 8 5 4 3 2 1b0 1b1 2b0 2b1 s1 s2 2a 1a 9 10 6 7 1
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsa2269 / fsa2269ts ? rev. 1.1.3 3 fsa2269 / fsa2269ts ? low-voltage dual-spdt (0.4 stresses exceeding the absolute maximum ratings may damage the device. functional operation above the recommended operating conditions is not implied. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cc supply voltage -0.5 5.5 v v sw switch i/o voltage (1) 1b0, 1b1, 2b0, 2b1, 1a, 2a pins v cc -4.6 v cc +0.3 v v cntrl control input voltage (1) s1, s2 -0.5 v cc +0.3 v i sw switch i/o current (continuous) 350 ma i swpeak peak switch current pulsed at 1ms duration, <10% duty cycle 500 ma t stg storage temperature range -65 +150 c t j maximum junction temperature +150 c t l lead temperature soldering, 10 seconds +260 c msl moisture sensitivity level, jedec j-std-020a 1 esd human body model, jedec: jesd22-a114 i/o to gnd 12 kv i/o to gnd FSA2269UCX 11 power to gnd 8 all other pins 7 charged device model, jedec: jesd22-c101 2 note : 1. input and output negative ratings may be exceeded if input and output diode current ratings are observed. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit v cc supply voltage (2) 1.65 4.50 v v s1, s2 control input voltage 0v v cc v v sw switch i/o voltage v cc -4.3 v cc v t a operating temperature -40oc +85 oc note : 2. for 4.5v operation, sel frequency (pins s1 & s2) should not exceed 100hz and 50ns edge rate.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsa2269 / fsa2269ts ? rev. 1.1.3 4 fsa2269 / fsa2269ts ? low-voltage dual-spdt (0.4 all typical values are t a =25oc unless otherwise specified. symbol parameter conditions v cc (v) t a =+25oc t a =-40 to +85oc unit min. typ. max. min. max. v ih input voltage high 3.60 to 4.50 1.70 3.00 to 3.60 1.50 v 2.70 to 3.00 1.35 2.30 to 2.70 1.30 1.65 to 1.95 0.90 v il input voltage low 3.60 to 4.50 0.7 v 2.70 to 3.60 0.5 v 2.30 to 2.70 0.4 1.65 to 1.95 0.4 i in control input leakage (s1,s2) v in =0 to v cc 1.65 to 4.50 -0.5 0.5 a i no(0ff), i nc(off) off leakage current of port nb0 and nb1 (fsa2269 only) na=0.5v, v cc ?0.5v nb0 or nb1=v cc - 0.5v, 0.5v, or floating figure 8 1.95 to 4.50 -50 50 -250 250 na i a(on) on leakage current of port na na=0.5v, v cc ?0.5v nb0 or nb1=v cc - 0.5v, 0.5v, or floating figure 9 1.95 to 4.50 -20 20 -150 150 na i off power-off leakage current (common port only 1a, 2a) (fsa2269) common port (1a, 2a), v in =0v to 4.5v, v cc =0v nb0, nb1=floating 0 1 a power-off leakage current (common port only 1a, 2a) (fsa2269ts) common port (1a, 2a), v in =0v to 4.5v, v cc =0v nb0, nb1=0v or floating 0 45 a r on switch on resistance (3,6) i on =100ma, nb0 or nb1=0.7v, 3.6v, 4.5v figure 7 4.50 0.30 ? i on =100ma, nb0 or nb1=0.7v, 3.6v, figure 7 3.00 0.40 0.80 i on =100ma, nb0 or nb1=0v, 0.7v, 1.6v, 2.3v, figure 7 2.30 0.52 i on =100ma, nb0 or nb1=0v, 0.7v, 1.65v figure 7 1.65 1.00 ? r on on resistance matching between channels (4) i on =100ma, nb0 or nb1=0.7v 4.50 0.04 0.13 ? 3.00 0.06 0.13 2.30 0.12 1.65 1.00 continued on the following page?
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsa2269 / fsa2269ts ? rev. 1.1.3 5 fsa2269 / fsa2269ts ? low-voltage dual-spdt (0.4 dc electrical characteristics (continued) all typical values are t a =25oc unless otherwise specified. symbol parameter conditions v cc (v) t a =+25oc t a =-40 to +85oc unit min. typ. max. min. max. r flat(on) on resistance flatness (5) i out =100ma, nb0 or nb1=0v to v cc 4.50 0.25 ? 3.00 0.25 2.30 0.5 1.65 0.6 r term internal termination resistors (6) (fsa2269ts only) 10 k ? i cc quiescent supply current v in =0 or v cc , i out =0 4.50 -100 100 -500 500 na i cct increase in i cc per input input at 2.6v 4.50 3.0 10.0 a input at 1.8v 7.0 15.0 notes : 3. on resistance is determined by the voltage drop between a and b pins at the indicated current through the switch. 4. ? r on =r on max ? r on min measured at identical v cc , temperature, and voltage. 5. flatness is defined as the difference between the maximum and minimum value of on resistance (r on ) over the specified range of conditions. 6. guaranteed by characterization, not production tested.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsa2269 / fsa2269ts ? rev. 1.1.3 6 fsa2269 / fsa2269ts ? low-voltage dual-spdt (0.4 ac electrical characteristics all typical value are t a =25oc unless otherwise specified. symbol parameter conditions v cc (v) t a =+25oc t a =-40 to +85c unit figure min. typ. max. min. max. t on turn-on time fsa2269 nb0 or nb1=1.5v, r l =50 ? , c l =35pf 3.60 to 4.50 55 15 60 ns figure 10 figure 11 2.70 to 3.60 60 15 65 2.30 to 2.70 100 15 110 1.65 to 1.95 70 turn-on time FSA2269UCX nb0 or nb1=1.5v, r l =50 ? , c l =35pf 3.60 to 4.50 105 15 110 ns figure 10 figure 11 2.70 to 3.60 115 15 150 2.30 to 2.70 180 15 185 1.65 to 1.95 110 turn-on time fsa2269ts nb0 or nb1=1.5v, r l =50 ? , c l =35pf 3.60 to 4.50 3.5 0.5 4.0 s figure 10 figure 11 2.70 to 3.60 4.5 0.5 5.0 2.30 to 2.70 6.0 0.5 7.0 1.65 to 1.95 8.0 t off turn-off time fsa2269 nb0 or nb1=1.5v, r l =50 ? , c l =35pf 3.60 to 4.50 50 5 55 ns figure 10 figure 11 2.70 to 3.60 55 5 60 2.30 to 2.70 60 5 65 1.65 to 1.95 40 turn-off time FSA2269UCX nb0 or nb1=1.5v, r l =50 ? , c l =35pf 3.60 to 4.50 100 5 105 ns figure 10 figure 11 2.70 to 3.60 110 5 115 2.30 to 2.70 120 5 125 1.65 to 1.95 80 turn-off time fsa2269ts nb0 or nb1=1.5v, r l =50 ? , c l =35pf 3.60 to 4.50 45 5 50 ns figure 10 figure 11 2.70 to 3.60 50 5 55 2.30 to 2.70 55 5 60 1.65 to 1.95 50 t bbm break-before- make time fsa2269 nb0 or nb1=1.5v, r l =50 ? , c l =35pf 3.60 to 4.50 3 1 ns figure 12 2.70 to 3.60 5 2 2.30 to 2.70 10 2 1.65 to 1.95 5 2 t bbm break-before- make time FSA2269UCX nb0 or nb1=1.5v, r l =50 ? , c l =35pf 3.60 to 4.50 9.5 11.0 ns figure 12 2.70 to 3.60 17 19 2.30 to 2.70 22 22 1.65 to 1.95 46 42 t bbm break-before- make time fsa2269ts nb0 or nb1=1.5v, r l =50 ? , c l =35pf 3.60 to 4.50 1.5 1.0 s figure 12 2.70 to 3.60 3.0 1.5 2.30 to 2.70 4.0 2.5 1.65 to 1.95 5.0 3.0 continued on the following page?
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsa2269 / fsa2269ts ? rev. 1.1.3 7 fsa2269 / fsa2269ts ? low-voltage dual-spdt (0.4 (continued) all typical value are t a =25oc unless otherwise specified. symbol parameter conditions v cc (v) t a =+25oc t a =-40 to +85c unit figure min. typ. max. min. max. q charge injection c l =1.0nf, v s =0v, r s =0 ? 1.65 to 4.50 25 pc figure 16 oirr off isolation f=100khz, r l =50 ? , c l =0pf 1.65 to 4.50 -70 db figure 14 xtalk crosstalk f=100khz, r l =50 ? , c l =0pf 1.65 to 4.50 -70 db figure 15 bw -3db bandwidth r l =50 ? , c l =0pf 1.65 to 4.50 >50 mhz figure 13 thd total harmonic distortion f=20hz to 20khz, r l =32 , v in =2v pp v bias =0v 1.65 to 4.50 .06 % figure 19 capacitance symbol parameter conditions v cc (v) t a =+25oc unit figure min. typ. max. c in control pin input capacitance f=1mhz 0 2.5 pf figure 17 c off b port off capacitance f=1mhz 3.3 30 pf figure 17 c on a port on capacitance f=1mhz 3.3 120 pf figure 18
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsa2269 / fsa2269ts ? rev. 1.1.3 8 fsa2269 / fsa2269ts ? low-voltage dual-spdt (0.4 test diagrams figure 7. on resistance figure 8. off leakage figure 9. on leakage figure 10. test circuit load figure 11. turn-on / turn-off waveforms select nb n na v sel = 0 or v cc i on v on r on = v on /i on gnd v in gnd v in select v sel = 0 orv cc nc a i a(off) v in gnd **each switch port is tested separately. v in selec t v sel = 0 o r v cc nc i a(on) v in gnd a i a(on) v in v in r l c l nb n na gnd gnd r s v sel v in gnd v out v in r l and c l are functions of the application environment (see ac/dc tables). c l includes test ficutre and stray capacitance. t rise = 2.5ns gnd v cc 90% 90% 10% 10% t fall =2.5ns v cc /2 v cc /2 input - v sel output - v out 90% v oh v ol t on t off 90%
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsa2269 / fsa2269ts ? rev. 1.1.3 9 fsa2269 / fsa2269ts ? low-voltage dual-spdt (0.4 test diagrams (continued) figure 12. break-before-make interval timing figure 13. bandwidth figure 14. channel off isolation v cc 0.9*v out v cc /2 d 0v v out input - v sel 0.9*v out t rise =2.5ns 90% 10% c l nb n r l na gnd gnd r s v sel v in gnd r l and c l are functions of the application environment (see ac/dc tables). c l includes test fixture and stray capacitance. v out v in gnd t - - r l and c l v ou t gnd gnd r t gnd gnd v s r s network analyzer v sel gnd r l and c l are functions of the application environment (see ac/dc tables). c l includes test fixture and stray capacitance. v in l v out gnd gnd r t gnd gnd v s r s network analyzer r t gnd r s and r t are functions of the application environment (see ac/dc tables). v sel gnd off-isolation = 20 log (v out /v in ) -
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsa2269 / fsa2269ts ? rev. 1.1.3 10 fsa2269 / fsa2269ts ? low-voltage dual-spdt (0.4 test diagrams (continued) figure 15. adjacent channel crosstalk figure 16. charge injection test figure 17. channel off capacitance figure 18. channel on capacitance figure 19. total harmonic distortion v out gnd gnd r t gnd gnd v s r s network analyzer r t gnd r s and r t are functions of the application environment (see ac tables for values). v s1, s2, s3 gnd crosstalk = 20 log (v out /v in ) v in nc r s v out q = v out ? c l v out v out v cc 0v input ? v sel generator gnd v s c l v sel v in b ns n gnd c l includes test fixture and stray capacitance gnd off on off ma v sel = 0 or v c c nb n capacitance meter ns n nb n f=1mhz v sel = 0 orv cc nb n capacitance meter ns n nb n f=1mhz v out gnd gnd r t gnd gnd v s r s audio analyzer v cntrl gnd v in r s and r t are functions of the application environment (see ac tables for specific values). v sel = 0 or v cc
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsa2269 / fsa2269ts ? rev. 1.1.3 11 fsa2269 / fsa2269ts ? low-voltage dual-spdt (0.4 physical dimensions figure 20. 10-lead micropak? package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . bottom view top view recommended land pattern side view 2x 2x notes: a. package conforms to jedec registration mo-255, variation uabd . b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 1994. d. presence of center pad is package supplier dependent. if present it is not intended to be soldered and has a black oxide finish. e. drawing filename: mkt-mac10arev5. 0.10 c 0.10 c 0.10 cab 0.05 c pin1 ident is 2x longer than other lines a b c 0.35 0.25 9x 9x 14 9 6 0.25 0.15 10 5 0.50 0.56 1.62 0.05 0.00 0.05 c 0.55 max 0.05 c 1.60 2.10 (0.35) (0.25) 0.50 10x 10x (0.11) 1.12 1.62 keepout zone, no traces or vias allowed (0.20) (0.15) 0.35 0.25 0.35 0.25 detail a detail a 2x scale 0.35 0.25 0.65 0.55 d all features (0.36) (0.29) 0.56
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsa2269 / fsa2269ts ? rev. 1.1.3 12 fsa2269 / fsa2269ts ? low-voltage dual-spdt (0.4 physical dimensions (continued) figure 21. 10-lead, quad ultrathin molded leadless package (umlp) package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . a. dimensions are in millimeters. b. dimensions and tolerances per asme y14.5m, 1994 top view bottom view recommended land pattern 0.15 c 0.08 c b a c 0.15 c 2x 2x side view seating plane 0.10 c 0.050 3 6 1 0.10 cab 0.05 c 0.55 max. pin #1 ident 10 1.40 1.80 0.40 0.15 0.25 10x 0.45 0.55 0.35 0.45 9x 1.700 2.100 0.400 0.663 0.563 9x 0.225 10x 1 0.152 0.100 0.100 0.500 0.100 detail a pin #1 terminal scale: 2x 1.850 1.450 0.550 0.400 0.225 10x 9x 0.450 optional minimial toe land pattern c. drawing filename: umlp10arev2
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsa2269 / fsa2269ts ? rev. 1.1.3 13 fsa2269 / fsa2269ts ? low-voltage dual-spdt (0.4 (continued) product specific dimensions product d e x y FSA2269UCX 1.560mm 1.160mm 0.180mm 0.180mm figure 22. 12-ball, wafer level chip-scale package (wlcsp) package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. bottom view side views top view recommended land pattern (nsmd pad type) notes: a. no jedec registration applies. b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 1994. d. datum c is defined by the spherical crowns of the balls. e. package nominal height is 586 microns 39 microns (547-625 microns). f. for dimensions d, e, x, and y see product datasheet. g. drawing filename: mkt-uc012acrev1. 0.40 0.40 0.80 1.20 ?0.2600.02 12x (x)0.018 (y)0.018 a b c d 123 2x pin 1 area 0.03 c e d a b 2x 0.03 c 0.05 c 0.625 0.547 c 0.3780.018 0.2080.021 seating plane d f f (?0.200) cu pad (?0.300) solder mask 0.40 0.80 1.20 0.40 0.005 cab
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsa2269 / fsa2269ts ? rev. 1.1.3 14 fsa2269 / fsa2269ts ? low-voltage dual-spdt (0.4

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