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78P2254 stm-1/sts-3 transceiver june 2002 description the 78P2254 is a transceiver ic designed for 155.52mbit/s (sts-3 or stm-1) transmission. it is used at the interface to a 75 ? coaxial cable using cmi coding. interfacing to digital framer circuits is accomplished via a serial pecl or parallel cmos interfaces. the transmitter includes a pll to multiply the reference clock to the transmission frequency. the receiver provides adaptive equalization for accurate clock and data recovery. the 78P2254 is built in a bicmos technology for high performance and low power operation. it operates with a 3.3v or 5v power supply and is packaged in a 64-pin tqfp. features ? 155.52mbit/s interface for cmi coded transmission using 75 ? ? ? ? coaxial cable ? compliant with itu-t g.703 and telcordia tr-nwt-00253 ? integrated clock recovery unit (cru) ? serial pecl interface to framer ? four and eight bit parallel cmos interfaces to framer ? synchronous 311mhz clock generated by transmit plo ? adaptive equalization ? integrated clock multiplier pll ? advanced bicmos process block diagram tx311p,n cmioutp cmioutn cmiinp cmiinn crystal oscillator clock generator binary to cmi adaptive equalizer clock recovery cmi to binary signal detector bias hub/ host par/ ser 8bit/ $bit xtal1 xtal2 ckin txck txckp,n rlback txdtp,n txdt[7:0] rxdtp,n rxdt[7:0] rfo rxckp,n rxck lf llback los
78P2254 stm-1/sts-3 transceiver 2 functional description the 78P2254 contains all the necessary transmit and receive circuitry for connection between 155.52mbit/s signals and digital framer/deframer ics. operating rate the line interface of the 78P2254 operates at stm1 or sts3 rates over coax. the digital interface of the 78P2254 can be either serial pecl, 4-bit parallel cmos or 8-bit parallel cmos as described in the following table. mode par/ ser ser ser ser 8bit/ $bit $bit $bit $bit data pins clock pins clock frequency serial 0 x txdtp,n rxdtp,n txckp,n rxckp,n 155.52 mhz 4-bit parallel 1 0 txdt[3:0] rxdt[3:0] txck rxck 38.88 mhz 8-bit parallel 1 1 txdt[7:0] rxdt[7:0] txck rxck 19.44 mhz transmit timing is derived from either the reference clock (the crystal oscillator or ckin), or the recovered receive clock. llback and rlback control the local and remote loopback modes respectively. llback rlback hub/ host host host host transmit clock derived from 0 0 1 reference 1 0 1 reference x 1 1 receiver x x 0 receiver transmitter operation the transmitter section generates an analog signal for transmission through a transformer onto the coaxial cable. when the par/ ser pin is low, the chip is in serial mode. serial data is input from the digital framer/deframer ic to the 78P2254 on the txdtp and txdtn pins at pecl levels. the data is timed with the clock generated by the 78P2254 on the txckp and txckn pins. in this mode the 8bit/ $bit pin is ignored. when the par/ ser pin is high, the chip is in parallel mode. parallel data is input from the digital framer/deframer ic to the 78P2254 on the txdt[7:0] pins. the input data is timed with the transmit clock output from txck. when 8bit/ $bit is high, all eight bits of txdt[7:0] are used and the clock frequency at txck is one-eighth the standard frequency. when 8bit/ $bit is low, the lower four bits, txdt[3:0], are used and txck is one-fourth the standard frequency. note that the first bit output from the cmi interface (cmioutp,n) is the most significant bit on the parallel interface, txdt7 in eight bit mode, txdt3 in four bit mode. the clock is generated by a phase-locked oscillator (plo). the plo can be locked to a crystal oscillator operating at one-eighth of the standard clock frequency, 19.44mhz for sts-3 and stm-1. this is shown in figure 1a. an external clock signal at ckin may also be substituted for a crystal as the reference frequency for the chip. in this mode, xtal1 and xtal2 must be configured as shown in figure 1b. note that in serial mode the reference clock is also output from txck. in parallel mode, the parallel transmit clock is output from txck. the hub/ host input changes the reference signal for the clock generator. in the hub mode (hub/ host high), the transmit clock reference is derived from either the crystal oscillator or ckin. in host mode (hub/ host low), the transmit clock reference is derived from the recovered receive clock. figure 1a: using crystal
78P2254 stm-1/sts-3 transceiver 3 functional description (continued) xtal1 xtal2 ckin 19.440 mhz figure 1b : using external clock 311 mhz serial clock the transmit plo also generates a 311 mhz synchronous, differential clock on the tx311p and tx311n pins that can be used to recover the transmitted cmi signal data on the receiving unit. this clock complies with the same jitter specifications of the transmitter. receiver operation the receiver accepts serial, cmi coded data at 155.52mbit/s from the cmi inputs. the inputs, cmiinp and cmiinn, receive the input signal from a coaxial cable that is transformer-coupled to the chip. the clock signal is recovered using a low jitter pll circuit. the received signal is equalized for dispersive cable attenuation and decoded in the cmi to binary decoder. in serial mode, the received data is output on the rxdtp and rxdtn pins and the recovered clock is output on the rxckp and rxckn pins. in parallel mode, the received data is converted to parallel, eight bits if 8bit/ $bit is high and four if it is low. the first bit received will arrive on the most significant output pin, rxdt[7] in eight bit mode and rxdt3 in four bit mode. the recovered clock is output on the rxck pin. the los pin goes high when the signal detector detects a loss-of-signal condition. loopback operation the 78P2254 is capable of performing signal loopback in two ways: the rlback pin selects the remote loopback mode. in this mode, the received signal is ?looped back? and sent out of transmitter in place of the transmit input signal. the llback pin selects the local loop-back mode, and causes the receiver to use the transmitter output signal as its input. local loopback is disabled when hub/ host is low or rlback is high.
78P2254 stm-1/sts-3 transceiver 4 pin description legend type description type description a analog pin pi pecl digital input ci cmos digital input po pecl digital output co cmos digital output s supply pin transmit pins name pin type description txdtp txdtn 19 20 pi transmit data inputs - serial mode. txckp txckn 22 23 po transmit clock output - serial mode. txdt[7:0] 11-18 ci transmit data inputs ? parallel mode. txdt[7:4] are ignored in 4 bit mode. txck 10 co reference clock output ? serial mode. transmit clock output ? parallel mode. cmioutp cmioutn 60 59 a transmit outputs . tx311p tx311n 56 55 po transmitted 311mhz clock (line side). should be both tied to vcc when unused. receive pins name pin type description cmiinp cmiinn 50 49 a receive inputs. transformer coupled from the coaxial cable. rxckp rxckn 25 26 po recovered receive clock ? serial mode. rxck 38 co recovered receive clock ? parallel mode. rxdtp rxdtn 27 28 po receive data ? serial mode. rxdt[7:0] 30-37 co receive data ? parallel mode. in 4 bit mode rxdt[3:0] are used and rxdt[7:4] are pulled low. reference clock pins name pin type description xtal1 xtal2 5 6 a crystal pins. connect as in figure 1a. ckin 9 ci reference clock input. the crystal oscillator connections should be left open when used. connect as in figure 1b.
78P2254 stm-1/sts-3 transceiver 5 pin description (continued) control and status pins name pin type description rlback 41 ci loopback receiver output to transmitter input. llback 42 ci loopback transmitter output to receiver input. disabled when hub/ host is low or rlback is high. hub/ host 2 ci in hub mode (input high) the transmit reference clock is derived from the ckin pin or the crystal oscillator. in host mode (input low) the transmit reference clock is derived from the recovered receive clock. 8bit/ $bit 63 ci selects 8 bit parallel data when high and 4 bit parallel mode when low. in serial mode this pin is ignored. par/ ser 62 ci selects parallel mode when high and serial mode when low. los 39 co high during a loss-of-signal condition. analog pins name pin type description rfo 46 a external reference resistor. lf 44 a pll loop filter capacitor. power supply pins it is recommended that all vcc pins be connected to a single power supply plane and all gnd pins be connected to a single ground plane. name pin type description vcc 1, 3, 8, 24, 40, 43, 51, 52, 53, 54, 57 s power supply. gnd 4, 7, 21, 29, 45, 47, 48, 58, 61, 64 s ground.
78P2254 stm-1/sts-3 transceiver 6 electrical specifications absolute maximum ratings operation beyond these limits may permanently damage the device. parameter rating supply voltage 7 vdc storage temperature -65 to 150 c pin voltage -0.3 to (v cc +0.3) vdc pin current 100 ma recommended operating conditions unless otherwise noted all specifications are valid over these temperatures and supply voltage ranges. parameter rating dc voltage supply, vcc 3.3 0.3 vdc; 5 0.5 vdc ambient operating temperature -40 to 85c dc characteristics: parameter symbol conditions min nom max unit supply current (parallel mode) icc vcc = 3.3v vcc = 5.0v 140 150 165 175 ma supply current (serial mode) icc vcc = 3.3v vcc = 5.0v 210 280 245 330 ma
78P2254 stm-1/sts-3 transceiver 7 electrical specifications (continued) digital input characteristics pins of type ci parameter symbol conditions min nom max unit input voltage low vil vcc/2 - 0.9 vcc/2 + 0.9 v input voltage high vih vcc/2 - 0.9 vcc/2 + 0.9 v input current iil, iih -10 10 a input capacitance cin 10 pf pins of type pi parameter symbol conditions min nom max unit input voltage low vil relative to vcc -1.5 v input voltage high vih relative to vcc -1.1 v digital output characteristics pins of type co parameter symbol conditions min nom max unit output voltage low vol 0.6 0.7 v output voltage high voh below vcc 0.6 0.7 v transition time tt 3.5 ns pins of type po parameter symbol conditions min nom max unit output voltage low vol vcc reference, biased at vcc ?1.5v with 50 ohn -1.7 -1.5 -1.3 v output voltage high voh vcc reference, biased at vcc ?1.5v with 50 ohn -1.1 -0.9 -0.7 v rise time tr 1 3 ns fall time tf 1 3 ns
78P2254 stm-1/sts-3 transceiver 8 electrical specifications (continued) digital timing characteristics transmit interface txckp - txckn txdtp - txdtn t sus t hs parameter symbol conditions min nom max unit transmit setup time t sus serial mode 1.5 ns transmit hold time t hs serial mode 1.5 ns txckp,n duty cycle 40 60 % txck txdt[7:0] t sup t hp parameter symbol conditions min nom max unit transmit setup time t sup parallel mode 3.5 ns transmit hold time t hp parallel mode 2.5 ns txck duty cycle 40 60 % cmioutp - cmioutn tx311p - tx311n t prop t parameter symbol conditions min nom max unit tx311p,n propagation delay t propt 2.1 2.67 3.2 ns propagation delay variance 20 %
78P2254 stm-1/sts-3 transceiver 9 electrical specifications (continued) digital timing characteristics receive interface rxckp - rxckn rxdtp - rxdtn t props parameter symbol conditions min nom max unit receive propagation delay t props serial mode 2.4 3.0 ns rxckp,n duty cycle 40 60 % rxck rxdt[7:0] t propp parameter symbol conditions min nom max unit receive propagation delay t propp parallel mode 4.0 6.0 ns rxckp,n duty cycle 40 60 %
78P2254 stm-1/sts-3 transceiver 10 electrical specifications (continued) digital timing characteristics: reference clock interface ckin txckp - txckn t props parameter symbol conditions min nom max unit ckin to txckp/n delay t props serial mode 3.1 4.6 5.6 ns ckin txck t propp parameter symbol conditions min nom max unit ckin to closes phase of txck delay t propp parallel 8 bit mode 1.6 3.7 5.7 ns
78P2254 stm-1/sts-3 transceiver 11 electrical specifications (continued) transmitter output jitter the transmit jitter specification ensures compliance with itu-t g.825, g.958 and ansi t1.105.03-1994 for stm-1 and sts-3 rates. the corner frequency of the transmit pll is nominally 3.0 mhz. parameter condition min nom max unit transmitter output jitter 200 hz to 3.5 mhz 0.075 ui transmitter specifications for cmi interface in sts-3 (stm-1) mode bit rate: 155.52mbit/s 20ppm code: coded mark inversion (cmi) the following specifications are met with the external components for sts-1 operation configured with a recommended 1:1 transformer. with the coaxial output port driving a 75 ? load, the output pulses conform to the templates in figure 2 and figure 3. parameter condition min nom max unit peak-to-peak output voltage template 0.9 1.1 v rise/ fall time 10-90% 2 ns transition timing tolerance negative transitions positive transitions at interval boundaries positive transitions at mid- interval -0.1 -0.5 -0.35 0.1 0.5 0.35 ns ns ns transmission performance parameter condition min nom max unit return loss 7mhz to 240mhz 15 db transmitter output jitter detector measured jitter amplitude 200 hz 3.5 mhz 20db/decade
78P2254 stm-1/sts-3 transceiver 12 electrical specifications (continued) note 1 ? the maximum ?steady state? amplitude should not exceed the 0.55v limit. overshoots and other transients are permitted to fal l into the shaded area bounded by the amplitude levels 0.55v and 0.6v, provided that they do not exceed the steady state level by more than 0.05v. note 2 ? for all measurements using these masks, the si gnal should be ac coupled, using a capacitor of not less than 0.01 f, to the input of the oscilloscope used for measurements. the nominal zero level for both masks s hould be aligned with the oscilloscope trace with no input signal. with the signal then applied, the vertical position of the trace can be adjusted with the objective of meeting the limi ts of the masks. any such adjustment should be the same for both masks and should not exceed 0.05v. this may be checked by removing the input signal again and verifying that the trace lies with 0.05v of the nominal zero level of the masks. note 3 ? each pulse in a coded pulse sequence should meet the limits of the relevant mask, irrespective of the state of the preceding or succeeding pulses, with both pulse masks fixed in the same relation to a common timing reference, i.e. with their nominal start and finish edges coincident. the masks allow for hf jitter caused by intersymbol interference in the output stage, but not for jitter pres ent in the timing signal associated with the source of the interface signal. when using an oscilloscope technique to determine pulse compliance w ith the mask, it is important that successive traces of the pulses overlay in order to suppress the effects of low frequency jitter. this can be accomplished by several techniques [e.g. a) triggering the oscilloscope on the measured waveform or b) providing both the oscilloscope and t he pulse output circuits with the same clock signal]. note 4 ? for the purpose of these masks, the rise time and decay time should be measured between ?0.4v and 0.4v, and should not exceed 2ns. figure 2 ? mask of a pulse corresponding to a binary zero in sts-3 mode. (note 1) (note 1) (note 1) 0.60 0.55 0.50 0.45 0.40 0.05 -0.05 -0.50 -0.55 -0.60 -0.45 -0.40 (note 1) 0.35ns nominal zero level (note 2) t = 6.43ns 0.1ns 0.1ns 1ns 1.608ns 1.608ns 1.608ns 1.608ns 1ns 1ns 1ns 0.1ns 0.1ns 1ns 1ns nominal pulse 0.35ns v
78P2254 stm-1/sts-3 transceiver 13 note 1 ? the maximum ?steady state? amplitude should not exceed the 0.55v limit. overshoots and other transients are permitted to fal l into the shaded area bounded by the amplitude levels 0.55v and 0.6v, provided that they do not exceed the steady state level by more tha n 0.05v. note 2 ? for all measurements using these masks, the signal should be ac coupled, using a capacitor of not less than 0.01 f, to the input of the oscilloscope used for measurements. the nominal zero level for both masks s hould be aligned with the oscilloscope trace with no input signal. with the signal then applied, the vertical position of the trace can be adjusted with the objective of meeting the limits of th e masks. any such adjustment should be the same for both masks and should not exceed 0.05v. this may be checked by removing the input signal again and verifying that the trace lies with 0.05v of the nominal zero level of the masks. note 3 ? each pulse in a coded pulse sequence should meet the limits of the relevant mask, irrespective of the state of the preceding or succeeding pulses, with both pulse masks fixed in the same relation to a common timing reference, i.e. with their nominal start and finish edges coincident. the masks allow for hf jitter caused by intersymbol interference in the output stage, but not for jitter present in the timing signal associated with the source of the interface signal. when using an oscilloscope technique to determine pulse compliance with the mask, it is important that successive traces of the pulses overlay in order to suppress the effects of low frequency jitter. this can be ac complished by several techniques [e.g. a) triggering the oscilloscope on the measured waveform or b) providing both the oscilloscope and the pulse ou tput circuits with the same clock signal]. note 4 ? for the purpose of these masks, the rise time and decay time should be measured between ?0.4v and 0.4v, and should not excee d 2ns. note 5 ?the inverse pulse will have the same characteristics, noting that the timing tolerance at the level of the negative and posit ive transitions are 0.1ns and 0.5ns respectively. figure 3 ? mask of a pulse corresponding to a binary one in sts-3 mode (note 1) (note 1) 0.60 0.55 0.50 0.45 0.40 0.05 -0.05 -0.50 -0.55 -0.60 -0.45 -0.40 (note 1) nominal zero level (note 2) 6.43ns 0.1ns 0.1ns 1ns 1.608ns 1ns nominal pulse v 3.215ns 1.2ns 1.2ns 3.215ns 1.608ns 1ns 1ns 0.5ns 0.5ns
78P2254 stm-1/sts-3 transceiver 14 electrical specifications (continued) receiver specifications the following specifications are met with the external components. parameter condition min nom max unit los threshold 0.05 0.1 0.2 v reception performance return loss 7mhz to 240mhz 15 db receiver jitter tolerance sts-3 jitter tolerance specifications are in ansi t1.105.05-1994 and telcordia tr-nwt-000253, issue 2, dec. 1991. stm-1 specifications are in itu-t g.825. they are identical except that stm-1 specifies both jitter and wander. the stm-1 specification is the tightest and covers the largest frequency range. parameter condition min nom max unit receiver jitter tolerance note 1: not tested in production 12 hz to 178 hz 1.6mhz to 15.6mhz 125mhz to 19.3 hz 500hz to 6.5khz 65khz to 3.5mhz 2800 311 39 1.5 0.15 ui 0.01 0.1 1 10 100 1000 10000 1.e-06 1.e-05 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 stm-1
78P2254 stm-1/sts-3 transceiver 15 electrical specifications (continued) receiver jitter transfer function the receiver clock recovery loop filter characteristics such that the receiver has the following transfer function. the corner frequency of the pll is approximately 100 khz. -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1.00e+03 1.00e+04 1.00e+05 1.00e+06 1.00e+07 parameter condition min nom max unit receiver jitter transfer function below 100 khz 0.1 db jitter transfer function roll-off note 1: not tested in production 20 db per decade
78P2254 stm-1/sts-3 transceiver 16 application information external components: component pin(s) value units tolerance reference resistor rfo 31.6 k ? 1% filter capacitor lf1 470 nf 5% transformer specifications: component value units tolerance turns ratio 1:1 3% suggested manufacturer: halo, minicircuits crystal specifications: component value units tolerance center frequency 19.44 mhz +/- 20ppm load capacitor ? xtal1 to ground; xtal2 to ground please check datasheet of crystal manufacturer for optimal load capacitor values. 27 pf pecl interface components: component value units tolerance output bias resistor, r bias v cc = 5v v cc = 3.3v 250 140 ? ? 5% 5% termination resistor, r term 100 ? 5% when the pecl signals travel one inch or less, lower power operation can be achieved by increasing r bias and eliminating r term . r bias r bias r term figure 4. pecl interface
78P2254 stm-1/sts-3 transceiver 17 mechanical specifications 64-tqfp (jedec lqfp) mechanical specification
78P2254 stm-1/sts-3 transceiver 18 package pin designations (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 gnd gnd rfo gnd lf vcc llback rlback vcc los rxck rxdt0 rxdt1 rxdt2 rxdt3 rxdt4 17 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 vcc hub/ host vcc gnd xtal1 xtal2 gnd vcc ckin txck txdt7 txdt6 txdt5 txdt4 txdt3 txdt2 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 txdt1 txdt0 txdtp txdtn gnd txckp txckn vcc rxckp rxckn rxdtp rxdtn gnd rxdt7 rxtd6 rxdt5 8bit/ $bit par/ ser gnd cmioutp cmioutn gnd vcc tx311p tx311n vcc vcc vcc vcc cmiinp cmiinn 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 gnd 64-pin tqfp (jedec lqfp) 78P2254-igt ordering information part description order number packaging mark 78P2254 64- pin thin quad flatpack 78P2254-igt 78P2254-igt preliminary data sheet: this preliminary data sheet describes a product not completely released to production. the specifications are based on preliminary evaluations and may not be accurate. samples of the described product are available and limited quantities can be purchased. tdk semiconductor corporation should be consulted contacted for contacted to obtain the most current up-to-date inf ormation about the product. this product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. tdk semiconductor corporation (tsc) reserves the right to make chan ges in specifications at any time without notice. accordingly, the reader is cautioned to verify that a data sheet is current before p lacing orders. tsc assumes no liability for applications assistance. tdk semiconductor corp., 2642 michelle dr., tustin, ca 92780 tel (714) 508-8800, fax (714) 508-8877, http://www.tdksemiconductor.com ? 2002 ? tdk semiconductor corporation 06/13/02 ? rev 1.9 caution: use handling procedures necessary for a static sensitive component.

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