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" for more information + ! " unlocking the secrets of bypass mode application note publication number 22281 revision a amendment 0 issue date november 1, 1998
publication# 22281 rev: a amendment/ 0 issue date: november 1998 8-31 unlocking the secrets of bypass mode application note this document explains the functionality provided by unlock bypass mode and demonstrates the advan- tages (and disadvantages) of using bypass mode to perform bulk programming operations. amd flash programming operations programming of an amd flash memory device is ac- complished through a 4-bus-cycle sequence. this sequence involves writing two unlock commands to the device. first, the data 0xaa (hex) is written to flash offset 0xaaa. second, the data 0x55 is written to off- set 0x555. this two cycle unlock sequence enables the flash state machine to accept the program command that follows. the software driver then writes the program command 0xa0 to offset 0xaaa. the next bus cycle contains the data to program into the device, as well as the desired offset. the flash state machine then writes the data using an embedded algorithm. once complete, the flash device returns to reading array data. the purpose of bypass mode is to speed the program- ming operation by removing the unlock requirement before programming a byte (or word, depending on the operating mode of the flash). when the flash is placed into bypass mode, only the two bus cycles of the pro- gram command are required to program any location in the flash, which reduces the total software/hardware overhead to perform a programming operation. bypass mode is not available on all amd flash devices. only low voltage devices manufactured using amd?s 0.35 m process technology (or smaller) contain this feature. devices containing a ?b? at the end of the den- sity designation signify this process technology (for example, am29lv800b). note: the ?b? designator should not be confused with the bottom boot designation. older boot block devices will also contain a ?b? at the end of the density designation, to signify that the device has a bottom boot sector organization. new 0.35 m (or smaller) devices will contain an additional ?b? in addition to the boot sector organization (for example, am29dl800bb or am29dl800bt). unlock bypass command bypass mode is a three-bus-cycle operation. first, a two-bus-cycle unlock sequence is written to the part (detailed in the previous section), then the data 0x20 is written to the part (address is don?t care). while in bypass mode, only the unlock bypass program and unlock by- pass reset commands are valid. the flash device will reject all other programming (or bus) sequences. to program a byte (or word), the two bus cycle unlock bypass program command is written. it consists of a single bus write cycle of 0xa0 (address don?t care), fol- lowed by the program data and desired offset. overall system bus cycles are reduced from four cycles to two. from a system bus standpoint, overall byte (or word) programming bus traffic is reduced by 50%. to exit from bypass mode, the system must issue the two bus cycle unlock bypass reset command, per- formed by writing 0x90 (address don?t care) to the device. writing of data 0x00 (address don?t care) to the device completes the reset command, returning the part to reading array data. advantages and disadvantages of unlock bypass mode use of bypass mode is most appropriate whenever large amounts of data are bulk programmed into a flash device. this occurs most often when the flash device is first programmed during manufacturing. using bypass mode can provide a measurable overall programming time reduction when the entire device is programmed. to illustrate this principle, consider the following equation: overall time to program a single byte/word = (n * t bus * cycles write ) + t whwh1 where n = number of bus cycles required by flash device (4 or 2, depending on bypass mode) t bus = flash bus clock period cycles write = number of system/processor bus cycles re- quired for a write operation t whwh1 = time to perform embedded program algorithm (listed in amd datasheet)
8-32 unlocking the secrets of bypass mode for example, an am29lv800bb-90ei (8 mbit) device is examined, in conjunction with a 12 clock write cycle pro- cessor operating at 33 mhz. using typical datasheet parameters, the theoretical time required to program a single byte (or word) programmed in-system would be: (4 * 12 * 30 ns) + 9 s = 10.44 s/byte using bypass mode, the result becomes: (2 * 12 * 30 ns) + 9 s = 9.72 s/byte this results in a 6.9% overall theoretical reduction in programming time, or 720 ns per byte. thus, for this 8 mbit device, the overall time reduction is 0.75 seconds (or 750 ms). note: the above calculations assume zero wait states, zero bus access latency, and zero system margin, cached instruc- tion fetch). when bulk programming using a commercial program- ming device, typical bus cycle latency is much higher (this is due to the internal bus latency of a high voltage programming device, and the internal delay of its state machine). given bus cycle timings in a microsecond resolution, the observed time savings can be signifi- cantly higher. assuming a 1 s bus cycle (a bus operating with single cycle write timing, with a clock period of 1 s), the above equations become: (4 * 1 * 1 s) + 9 s = 13 s/byte using bypass mode, the result becomes: (2 * 1 * 1 s) + 9 s = 11 s/byte this results in an average 15% theoretical reduction in byte programming time, or 2 s per byte. for an 8 mbit device, the overall time reduction is 2.1 seconds. note: commercial programmers vary widely in operational characteristics. individual programmer results will vary widely from theoretical calculations. the actual time reduction is dependent on several fac- tors, including processor speed, wait states, instruction fetch cycles (which may be essentially zero for proces- sors with cache), flash command write instruction execution cycles, bus speed when memory does not reside on the same processor bus, etc. in a typical sys- tem environment the actual time for programming an 8 mbit am29lv800bb-90ei flash device was measured in both normal and byte unlock modes. the system en- vironment was comprised of: amd 486 dx4-120 processor with 16k cache en- abled. 120 mhz processor core, 40 mhz local bus, 33 mhz pci bus wait state setting of 3-1-1-1 the flash memory was located in pci bus address space, and the flash device was operating in 16-bit word mode. normal mode programming (in-system) of the entire 8mbit device required 15.21 seconds and bypass mode required 15.1 seconds, yielding an overall savings of 1% (or 11 ms). results on specific systems will vary widely given the above system considerations outlined above. the same test was performed using a data i/o psx se- ries programmer, in both normal and bypass mode. time to program the same am29lv800b device was reduced from 96 seconds to 56 seconds, resulting in a 27.4% decrease in overall programming time. there are some minor disadvantages to operating in bypass mode. since all command sequences other than the unlock bypass reset and the device reset commands are disabled during this mode, it is neces- sary to exit the bypass mode before performing any other operation. this can complicate system program- ming, since commands such as the autoselect sequences, sector erase, or erase suspend are no longer accepted. care must be practiced when entering bypass mode?preparations such as possibly disabling interrupts, and performing all required sector erasures prior to bypass mode programming may be appropriate. conclusion unlock bypass mode can be used to significantly de- crease bulk programming of amd flash devices, especially in high bus latency systems such as com- mercial programmers. in systems utilizing low latency, cached bus operations the time decrease is measur- able, but less significant. in general, as the number of required processor write cycles is increased, and as the speed of a write opera- tion decreases, the benefit (in terms of decreased overall device bulk programming time) of unlock by- pass mode increases.

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