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pbs package (top view) 31 30 29 28 27 9 10 pcmo pcmi dv ss dv dd scl sda nc nc pllv dd earv ss ear1on earv dd ear1op earv ss ear2o av dd 32 26 11 12 13 14 15 mbias mic1p mic1n mic2p nc 16 25 1234567 8 24 23 22 21 20 19 18 17 mic2n rext av ss mclk pllv ss v ss reset pwrupsel buzzcon pcmsyn pcmclk nc ? no internal connection TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 1 post office box 655303 ? dallas, texas 75265 qualification in accordance with aec-q100 ? qualified for automotive applications customer-specific configuration control can be supported along with major-change approval esd protection exceeds 2000 v per mil-std-883, method 3015; exceeds 200 v using machine model (c l = 200 pf, r l = 0) 2.7-v operation two differential microphone inputs, one differential earphone output, and one single-ended earphone output programmable gain amplifiers for transmit, receive, sidetone, and volume control ? contact factory for details. q100 qualification data available on request. earphone mute and microphone mute on-chip i 2 c bus, which provides a simple, standard, two-wire serial interface with digital ics programmable for 15-bit linear data or 8-bit companded ( -law or a-law) data available in a 32-pin thin quad flatpack (tqfp) package designed for analog and digital wireless handsets and telecommunications applications dual-tone multifrequency (dtmf) and single tone generator pulse density modulated (pdm) buzzer output description the voice-band audio processor (vbap) is designed to perform transmit encoding analog/ digital (a/d) conversion, receive decoding digital/analog (d/a) conversion, and transmit and receive filtering for voice-band communications systems. the device operates in either the 15-bit linear or 8-bit companded ( -law or a-law) mode, which is selectable through the i 2 c interface. the vbap generates its own internal clocks from a 2.048-mhz master clock input. available options t a tqfp pbs package part no. top-side marking ?40 c to 105 c tube tape and reel twl1103tpbsq1 twl1103tpbsrq1 twl1103t twl1103t copyright ? 2002, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. vbap is a trademark of texas instruments. all other trademarks are the property of their respective owners. production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 2 post office box 655303 ? dallas, texas 75265 functional block diagram pcmi (15) pcmsyn (18) pcmclk (17) mic1p (2) mic1n (3) mic2p (4) mic2n (5) mic amplifier 1 g = 23.5 db mic amplifier 2 g = 12 db or 0 db analog modulator tx filter and pga g = ? 10 db to 0 db pcm interface sidetone g = ? 24 db to ? 12 db rx control g = ? 18 db to 0 db rx filter and pga g = ? 6 db to +6 db digital modulator and filter ear amp1 ear amp2 dtmf generator control bus i 2 c i/f ref pll buzzer control power scl sda mbias rext mclk reset ss earv dd earv ss pllv dd pllv ss dv dd dv ss av dd av ss v pwrupsel (20) pcmo (16) ear1op (29) ear1on (27) ear2o (31) buzzcon (19) volume and reset (23) (32) (8) (13) (14) (25) (24) (28) (30, 26) (21) (22) (6) (1) (11) (12)
TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 3 post office box 655303 ? dallas, texas 75265 functional description power on/reset the power for the various digital and analog circuits is separated to improve the noise performance of the device. an external reset must be applied to the active low reset terminal to guarantee reset upon power on. after the initial power-on sequence the twl1103 can be functionally powered up and down by writing to the power control register through the i 2 c interface. there is a hardwired selectable power-up terminal in default mode option. the pwrupsel function allows the vbap to power up in the default mode and allows use without a microcontroller. reference a precision band gap reference voltage is generated internally and supplies all required voltage references to operate the transmit and receive channels. the reference system also supplies bias voltage for use with an electret microphone at terminal mbias. an external precision resistor is required for reference current setting at terminal rext. control interface the i 2 c interface is a two-wire bidirectional serial interface that controls the vbap by writing data to the six control registers: power control mode control transmit pga and sidetone control receive pga gain and volume control dtmf high tone dtmf low tone there are two power-up modes which may be selected at the pwrupsel terminal: the pwrupsel state (v dd at terminal 20) causes the device to power up in the default mode when power is applied. in the default mode, the i 2 c interface is not required, and the device may be used without an i 2 c interface. the programmable functions are fixed in the default modes. the pwrupsel state (ground at terminal 20) causes the device to go to a power-down state when power is applied. in this mode an i 2 c interface is required to power up the device. phase-locked loop the internal digital filters and modulators require a 10.24-mhz clock that is generated by phase locking to the 2.048-mhz master clock input. pcm interface the pcm interface transmits and receives data at the pcmo and pcmi terminals respectively. the data is transmitted or received at the pcmclk speed once every pcmsyn cycle. the pcmclk can be tied directly to the 2.048-mhz master clock (mclk). the pcmsyn can be driven by an external source or derived from the master clock and used as an interrupt to the host controller. microphone amplifiers the microphone input is a switchable interface for two differential microphone inputs. the first stage is a low- noise differential amplifier that provides a gain of 23.5 db. the second stage amplifier has a selectable gain of 0 db or 12 db.
TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 4 post office box 655303 ? dallas, texas 75265 functional description (continued) analog modulator the transmit channel modulator is a third-order sigma-delta design. transmit filter and pga the transmit filter is a digital filter designed to meet ccitt g.714 requirements. the device operates in either the 15-bit linear or 8-bit companded -law or a-law mode that is selectable through the i 2 c interface. the transmit pga defaults to 0 db. sidetone a portion of the transmitted audio is attenuated and fed back to the receive channel through the sidetone path. the sidetone path defaults to ? 12 db. the sidetone path can be enabled by writing to the power control register. receive volume control the receive volume control block acts as an attenuator with a range of ? 18 db to 0 db in 2 db steps for control of the receive channel volume. the receive volume control gain defaults to 0 db. receive filter and pga the receive filter is a digital filter that meets ccitt g.714 requirements with a high-pass filter that is selectable through the i 2 c interface. the device operates in either the 15-bit linear or 8-bit -law or a-law companded mode, which is selectable through the i 2 c interface. the gain defaults to ? 1 db representing a 3-dbm0 level for a 32- ? load impedance and the corresponding digital full scale pcmi code. the gain may be set to ? 2 db for the respective 3-dbm0 level for a 16- ? load impedance. digital modulator and filter the second-order digital modulator and filter convert the received digital pcm data to the analog output required by the earphone interface. earphone amplifiers the analog signal can be routed to either of two earphone amplifiers, one with differential output (ear1on and ear1op) and one with single-ended output (ear2o). clicks and pops are suppressed for ear1 differential output only. tone generator the tone generator provides generation of standard dtmf tones and single tone frequencies which are output to the following devices: 1) the buzzer driver, as a pulse density modulation (pdm) signal 2) the receive path digital/analog converter (dac) for outputting through the earphone. there are 255 possible single tones. the tone integer value is determined by the following formula: round (tone freq (hz)/7.8135 hz) the value is loaded into one of two 8-bit registers, the high-tone register (04), or the low-tone register (05). the tone output is 2 db higher when applied to the high-tone register (04). when generating dtmf tones, the high dtmf tone must be applied to the high-tone register and the low frequency tone to the low-tone register.
TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 5 post office box 655303 ? dallas, texas 75265 terminal functions terminal name no. i/o description name bga pbs av dd a1 32 i analog positive power supply av ss j1 8 i analog negative power supply buzzcon f9 19 o buzzer output, a pulse-density modulated signal to apply to external buzzer driver dv dd j6 13 i digital positive power supply dv ss j7 14 i digital negative power supply ear1on a6 27 o earphone 1 amplifier output ( ? ) ear1op a4 29 o earphone 1 amplifier output (+) ear2o a2 31 o earphone 2 amplifier output earv dd a5 28 i analog positive power supply for the earphone amplifiers earv ss a3, a7 30, 26 i analog negative power supply for the earphone amplifiers mbias b1 1 o microphone bias supply output, no decoupling capacitors mclk c9 22 i master system clock input (2.048 mhz) (digital) mic1p c1 2 i mic1 input (+) mic1n d1 3 i mic1 input ( ? ) mic2p e1 4 i mic2 input (+) mic2n f1 5 i mic2 input ( ? ) pcmi j8 15 i receive pcm input pcmo j9 16 o transmit pcm output pcmsyn g9 18 i pcm frame synchronization pcmclk h9 17 i pcm data clock pllv ss a9 24 i pll negative power supply pllv dd a8 25 i pll digital power supply pwrupsel e9 20 i selects the power-up default mode rext g1 6 i/o internal reference current setting terminal ? use precision 100 - k ? resistor and no filtering capacitors reset d9 21 i active low reset scl j5 12 i i 2 c-bus serial clock ? this input is used to synchronize the data transfer from and to the vbap sda j4 11 i/o i 2 c-bus serial address/data input/output ? this is a bidirectional terminal used to transfer register control addresses and data into and out of the codec. it is an open - drain terminal and therefore requires a pullup resistor to v dd (typical 10 k ? for 100 khz) v ss b9 23 i ground return for bandgap internal reference
TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 6 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ? supply voltage range, av dd , dv dd , pllv dd , earv dd ? 0.5 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o ? 0.5 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v f ? 0.5 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous total power dissipation see dissipation rating table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free air temperature range, t a (extended temperature) ? 40 c to 105 c . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, testing, t stg ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature 1,6 mm from case for 10 seconds 260 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. dissipation rating table package t a 25 c power rating derating factor above t a = 25 c t a = 85 c power rating t a = 105 c power rating pbs 680 mw 6.8 mw/ c 270 mw 134 mw recommended operating conditions (see notes 1 and 2) min nom max unit supply voltage, av dd , dv dd , pllv dd , earv dd 2.7 3.3 v high-level input voltage (v ih ) 0.7 x v dd v low-level input voltage (v il ) 0.3 x v dd v load impedance between ear1op and ear1on-r l 16 32 ? load impedance for ear2op-r l 32 ? operating free-air temperature, t a ? 40 105 c notes: 1. to avoid possible damage and resulting reliability problems to these cmos devices, the power-on initialization paragrap h must be followed, described in the principles of operations. 2. voltages are with respect to av ss , dv ss, pllv ss , and earv ss.
TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 7 post office box 655303 ? dallas, texas 75265 electrical characteristics, v dd = 2.7 v, t a = ? 40 c to 105 c (unless otherwise noted) supply current parameter test conditions min typ max unit operating, ear1 selected, micbias disabled 6 7 ma operating, ear2 selected, micbias disabled 5.4 6 ma i dd supply current from v dd power down, reg 2 bit 7 = 1, mclk not present (see note 3) 0.5 18 a power down, reg 2 bit 7 = 0, mclk not present (see note 3) 25 40 a t on(i) power-up time from power down 5 10 ms note 3: v ih = v dd , v il = v ss digital interface parameter test conditions min typ max unit v oh high-level output voltage, pcmo and buzzcon i oh = ? 3.2 ma, v dd = 3 v 2 v v ol low-level output voltage, pcmo and buzzcon i ol = 3.2 ma, v dd = 3 v 0.8 v i ih high-level input current, any digital input v i = v dd 10 a i il low-level input current, any digital input v i = v ss 10 a c i input capacitance 10 pf c o output capacitance 20 pf r l load impedance (buzzcon) 5 k ? microphone interface parameter test conditions min typ max unit v io input offset voltage at mic1n, mic2n see note 4 ? 5 5 mv i ib input bias current at mic1n, mic2n ? 600 600 na c i input capacitance at mic1n, mic2n 5 pf v n microphone input referred noise, psophometric weighted (c-message weighted is similar) micamp 1 gain = 23.5 db micamp 2 gain = 0 db 3.0 7.7 v rms i o max output source current mbias 1 1.2 ma v( mbias) microphone bias supply voltage (see note 5) 2.35 2.5 2.6 v micmute ? 80 db input impedance fully differential 35 60 100 k ? notes: 4. measured while mic1p and mic1n are connected together. less than 5 mv offset results in 0 value code on pcmout. 5. not a jedec symbol. speaker interface parameter test conditions min typ max unit ear p hone amp1 out p ut p ower (see note 6) v dd = 2.7 v, fully differential, 16- ? load, 3-dbm0 output, rgxpa = ? 2 db 120.9 151.1 mw earphone amp1 output power (see note 6) v dd = 2.7 v, fully differential, 32- ? load, 3-dbm0 output, rgxpa = ? 1 db 76.1 95.1 mw earphone amp2 output power (see note 6) v dd = 2.7 v, single ended, 32- ? load, 3-dbm0 output 10 12.5 mw v oo output offset voltage at ear1 fully differential 5 30 mv maximum out p ut current for ear1(rms) 3-dbm0 input, 16- ? load 86.9 108.6 i o max maximum output current for ear1(rms) 3-dbm0 input, 32- ? load 48.7 60.8 ma maximum output current for ear2 (rms) 3-dbm0 input 17.7 22.1 earmute ? 80 db note 6: maximum power is with a load impedance of approximately 12 ? .
TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 8 post office box 655303 ? dallas, texas 75265 electrical characteristics, v dd = 2.7 v, t a = ? 40 c to 105 c (unless otherwise noted) (continued) transmit gain and dynamic range, companded mode ( -law or a-law) or linear mode selected, transmit slope filter bypassed (see notes 7 and 8) parameter test conditions min typ max unit transmit reference-signal level (0 db) differential 175 mv pp overload signal level (3 dbm0) differential, normal mode 248 mv pp overload - signal level (3 dbm0) differential, extended mode 63 mv pp absolute gain error 0 dbm0 input signal, v dd = 2.7 v (minimum) ? 1 1 db linear mode gain error with in p ut level mic1n, mic1p to pcmo at 3 dbm0 to ? 30 dbm0 ? 0.5 0.5 linear mode gain error with in ut level relative to gain at ? 10 dbm0 mic1n, mic1n, mic1p to pcmo at ? 31 dbm0 to ? 45 dbm0 ? 1 1 db mic1p to pcmo mic1n, mic1p to pcmo at ? 46 dbm0 to ? 55 dbm0 ? 1.2 1.2 notes: 7. unless otherwise noted, the analog input is 0 db, 1020-hz sine wave, where 0 db is defined as the zero-reference point of the channel under test. 8. the reference signal level, which is input to the transmit channel, is defined as a value 3 db below the full-scale value of 88-mv rms . transmit gain and dynamic range, companded mode ( -law or a-law) or linear mode selected, transmit slope filter enabled (see notes 7 and 8) parameter test conditions min typ max unit transmit reference-signal level (0db) differential 175 mv pp overload signal level (3 dbm0) differential, normal mode 248 mv pp overload - signal level (3 dbm0) differential, extended mode 63 mv pp absolute gain error 0-dbm0 input signal, v dd = 2.7 v (minimum) ? 1 1 db linear mode gain error with in p ut level mic1n, mic1p to pcmo at 3 dbm0 to ? 30 dbm0 ? 0.5 0.5 linear mode gain error with in ut level relative to gain at ? 10-dbm0 mic1n, mic1n, mic1p to pcmo at ? 31 dbm0 to ? 45 dbm0 ? 1 1 db mic1p to pcmo mic1n, mic1p to pcmo at ? 46 dbm0 to ? 55 dbm0 ? 1.2 1.2 notes: 7. unless otherwise noted, the analog input is 0 db, 1020-hz sine wave, where 0 db is defined as the zero-reference point of the channel under test. 8. the reference signal level, which is input to the transmit channel, is defined as a value 3 db below the full-scale value of 88-mv rms . transmit filter transfer, linear mode selected, transmit slope filter bypassed, external high pass filter bypassed (mclk = 2.048 mhz) parameter test conditions min typ max unit f mic1 or f mic2 <100 hz ? 8.5 ? 6 f mic1 or f mic2 = 200 hz ? 4.5 ? 3 g i l ti t i t i l i t 1020 h i t l hi h f mic1 or f mic2 > 700 hz to 3 khz ? 0.5 0.5 gain relative to input signal gain at 1020 hz, internal high-pass filter disabled f mic1 or f mic2 = 3.4 khz ? 1.5 0 db filter disabled f mic1 or f mic2 = 4 khz ? 14 f mic1 or f mic2 = 4.6 khz ? 35 f mic1 or f mic2 = 8 k hz ? 47 gain relative to input si g nal g ain at 1020 hz, internal hi g h-pass f mic1 or f mic2 <100 hz ? 15 db gg , g filter enabled f mic1 or f mic2 = 200 hz ? 5 db
TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 9 post office box 655303 ? dallas, texas 75265 electrical characteristics, v dd = 2.7 v, t a = ? 40 c to 105 c (unless otherwise noted) (continued) transmit filter transfer, linear mode selected, transmit slope filter selected (mclk = 2.048 mhz) (see note 9) parameter test conditions min typ max unit f mic1 or f mic2 =100 hz ? 27 db f mic1 or f mic2 = 200 hz ? 8 db f mic1 or f mic2 = 250 hz ? 4 db f mic1 or f mic2 = 300 hz ? 1.80 db f mic1 or f mic2 = 400 hz ? 1.50 db f mic1 or f mic2 = 500 hz ? 1.30 db f mic1 or f mic2 = 600 hz ? 1.1 db f mic1 or f mic2 = 700 hz ? 0.8 db f mic1 or f mic2 = 800 hz ? 0.57 db f mic1 or f mic2 = 900 hz ? 0.25 db gain relative to in p ut signal gain at 1000 hz with slo p e filter selected f mic1 or f mic2 = 1000 hz 0 db gain relative to input signal gain at 1000 hz , with slope filter selected f mic1 or f mic2 = 1500 hz 1.8 db f mic1 or f mic2 = 2000 hz 4.0 db f mic1 or f mic2 = 2500 hz 6.5 db f mic1 or f mic2 = 3000 hz 7.6 db f mic1 or f mic2 = 3100 hz 7.7 db f mic1 or f mic2 = 3300 hz 8.0 db f mic1 or f mic2 = 3500 hz 6.48 db f mic1 or f mic2 = 4000 hz ? 13 db f mic1 or f mic2 = 4500 hz ? 35 db f mic1 or f mic2 = 5000 hz ? 45 db f mic1 or f mic2 = 8000 hz ? 50 db note 9: the pass-band tolerance is 0.25 db from 300 hz to 3500 hz. transmit idle channel noise and distortion, linear mode selected, slope filter bypassed parameter test conditions min typ max unit transmit idle channel noise txpga gain = 0 db, micamp 1 gain = 23.5 db, micamp 2 gain = 0.0 db ? 86.6 ? 78 dbm0 p mic1n, mic1p to pcmo at 3 dbm0 40 50 mic1n, mic1p to pcmo at 0 dbm0 50 65 mic1n, mic1p to pcmo at ? 5 dbm0 60 68 transmit si g nal-to-total distortion ratio with 1020-hz mic1n, mic1p to pcmo at ? 10 dbm0 55 70 db g sine-wave input mic1n, mic1p to pcmo at ? 20 dbm0 58 65 db mic1n, mic1p to pcmo at ? 30 dbm0 50 60 mic1n, mic1p to pcmo at ? 40 dbm0 38 50 mic1n, mic1p to pcmo at ? 45 dbm0 30 45
TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 10 post office box 655303 ? dallas, texas 75265 electrical characteristics, v dd = 2.7 v, t a = ? 40 c to 105 c (unless otherwise noted) (continued) transmit idle channel noise and distortion, linear mode selected, slope filter enabled parameter test conditions min typ max unit transmit idle channel noise txpga gain = 0 db, micamp 1 gain = 23.5 db, micamp 2 gain = 0.0 db ? 86.6 ? 78 dbm0 p mic1n, mic1p to pcmo at 3 dbm0 40 50 mic1n, mic1p to pcmo at 0 dbm0 50 65 mic1n, mic1p to pcmo at ? 5 dbm0 55 68 transmit si g nal-to-total distortion ratio with 1020-hz mic1n, mic1p to pcmo at ? 10 dbm0 55 70 db g sine-wave input mic1n, mic1p to pcmo at ? 20 dbm0 58 65 db mic1n, mic1p to pcmo at ? 30 dbm0 48 60 mic1n, mic1p to pcmo at ? 40 dbm0 38 50 mic1n, mic1p to pcmo at ? 45 dbm0 30 45 receive gain and dynamic range, ear1 selected, linear or companded ( -law or a-law) mode selected (see note 10) parameter test conditions min typ max unit overload signal level (3 0 db) 16- ? load rxpga = ? 2.0 db 3.93 v overload - signal level (3 . 0 db) 32- ? load rxpga = ? 1.0 db (default gain) 4.41 v pp absolute gain error 0-dbm0 input signal, v dd = 2.7 v (minimum) ? 1 1 db li d i ith t t l l pcmin to ear1on, ear1op at 3 dbm0 to ? 40 dbm0 ? 0.5 0.5 linear mode gain error with output level relative to gain at ? 10 dbm0 pcmin to ear1on, ear1op at ? 41 dbm0 to ? 50 dbm0 ? 1 1 db relative to gain at ? 10 dbm0 pcmin to ear1on, ear1op at ? 51 dbm0 to ? 55 dbm0 ? 1.2 1.2 note 10: rxpga = -1 db for 32 ? default mode or rxpga = -2 db for 16 ? , rxvol = 0 db, 1020 hz input signal at pcmi, output measured differentially between ear1on and ear1op receive gain and dynamic range, ear2 selected, linear or companded ( -law or a-law) mode selected (see note 11) parameter test conditions min typ max unit receive reference-signal level (0 db) 0-dbm0 pcm input signal 1.1 v pp overload-signal level (3 db) 1.6 v pp absolute gain error 0-dbm0 input signal, v dd = 2.7 v (minimum) ? 1 1 db li d i ith t t l l l ti t pcmin to ear2o at 3 dbm0 to ? 40 dbm0 ? 0.5 0.5 linear mode gain error with output level relative to gain at ? 10 dbm0 pcmin to ear2o at ? 41 dbm0 to ? 50 dbm0 ? 1 1 db gain at ? 10 dbm0 pcmin to ear2o at ? 51 dbm0 to ? 55 dbm0 ? 1.2 1.2 note 11: rxpga = -1 db, rxvol = 0 db
TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 11 post office box 655303 ? dallas, texas 75265 electrical characteristics, v dd = 2.7 v, t a = ? 40 c to 105 c (unless otherwise noted) (continued) receive filter transfer, linear mode selected (mclk = 2.048 mhz) (see note 11) parameter test conditions min typ max unit f ear1 or f ear2 < 100 hz ? 0.5 0.5 f ear1 or f ear2 = 200 hz ? 0.5 0.5 g i l ti t i t i l i t 1020 h i t l f ear1 or f ear2 = 300 hz to 3 khz ? 0.5 0.5 gain relative to input signal gain at 1020 hz, internal high -p ass filter disabled f ear1 or f ear2 = 3.4 khz ? 1.5 0 db high- ass filter disabled f ear1 or f ear2 = 4 khz ? 14 f ear1 or f ear2 = 4.6 khz ? 35 f ear1 or f ear2 = 8 khz ? 47 gain relative to input signal gain at 1020 hz, internal f ear1 or f ear2 < 100 hz ? 15 db gg high-pass filter enabled f ear1 or f ear2 = 200 hz ? 5 db note 11: rxpga = -1 db, rxvol = 0 db receive idle channel noise and distortion, ear1 selected, linear mode selected (see note 12) parameter test conditions min typ max unit receive noise, (20 hz to 20 khz brickwall window) pcmin = 0000000000000 ? 86 ? 83 dbm0 pcmin to ear1on, ear1op at 3 dbm0 65 78 pcmin to ear1on, ear1op at 0 dbm0 73 80 pcmin to ear1on, ear1op at ? 5 dbm0 72 78 receive si g nal-to-distortion ratio with 1020 hz pcmin to ear1on, ear1op at ? 10 dbm0 70 78 db g sine-wave input pcmin to ear1on, ear1op at ? 20 dbm0 60 76 db pcmin to ear1on, ear1op at ? 30 dbm0 50 67 pcmin to ear1on, ear1op at ? 40 dbm0 40 60 pcmin to ear1on, ear1op at ? 45 dbm0 33 55 intermodulation distortion, 2-tone ccitt method, ccitt g.712 (7.1), r2 50 db ,, composite power level, ? 13 dbm0 ccitt g.712 (7.2), r2 54 db note 12: rxpga = -1 db for 32 ? default mode or rxpga = -2 db for 16 ? , rxvol = 0 db, 1020 hz input signal at pcmi, output measured differentially between ear1on and ear1op. receive idle channel noise and distortion, ear2 selected, linear mode selected (see note 11) parameter test conditions min typ max unit receive noise, (20 hz to 20 khz brickwall window) pcmin = 0000000000000 ? 86 ? 82 dbm0 pcmin to ear2o at 3 dbm0 45 60 pcmin to ear2o at 0 dbm0 60 65 pcmin to ear2o at ? 5 dbm0 58 62 receive si g nal-to-distortion ratio with 1020-hz sine-wave input pcmin to ear2o at ? 10 dbm0 55 60 db g pcmin to ear2o at ? 20 dbm0 53 60 db pcmin to ear2o at ? 30 dbm0 52 58 pcmin to ear2o at ? 40 dbm0 44 57 pcmin to ear2o at ? 45 dbm0 33 52 intermodulation distortion, 2-tone ccitt method, composite ccitt g.712 (7.1), r2 50 db ,, power level, ? 13 dbm0 ccitt g.712 (7.2), r2 54 db note 11: rxpga = -1 db, rxvol = 0 db
TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 12 post office box 655303 ? dallas, texas 75265 electrical characteristics, v dd = 2.7 v, t a = ? 40 c to 105 c (unless otherwise noted) (continued) power supply rejection and crosstalk attenuation parameter test conditions min typ max unit supply voltage rejection, transmit channel mic1n, mic1p =0 v, v dd = 2.7 v + 100 mv peak to peak , f = 0 to 50 khz ? 80 ? 45 db supply voltage rejection, receive channel, ear1 selected (differential) pcm code = positive zero, v dd = 2.7 v + 100 mv peak to peak , f = 0 to 50 khz ? 90 ? 45 db crosstalk attenuation, transmit-to-receive (differential) mic1n, mic1p = 0 db, f = 300 to 3400 hz measured differentially between ear1on and ear1op 70 db crosstalk attenuation, receive-to-transmit pcmin = 0 dbm0, f = 300 to 3400 hz measured at pcmo, ear1 amplifier 70 db dtmf generator parameter test conditions min typ max unit dtmf high to low tone relative amplitude (preemphasis) 1.5 2 2.5 db micbias parameter test conditions min typ max unit load impedance 2.0 2.5 k ? timing requirements clock min nom max unit t t transition time, mclk 10 ns mclk frequency 2.048 2.048 mhz mclk jitter 37% number of pcmclk clock cycles per pcmsyn frame 256 256 t c(pcmclk) pcmclk clock period 156 488 512 ns duty cycle, pcmclk 45% 50% 68% transmit (see figure 6) min max unit t su(pcmsyn) setup time, pcmsyn high before pcmclk 20 t c(pcmclk) ? 20 ns t h(pcmsyn) hold time, pcmsyn high after pcmclk 20 t c(pcmclk) ? 20 ns receive (see figure 5) min max unit t su(pcsyn) setup time, pcmsyn high before pcmclk 20 t c(pcmclk) ? 20 ns t h(pcsyn) hold time, pcmsyn high after pcmclk 20 t c(pcmclk) ? 20 ns t su(pcmi) setup time, pcmi high or low before pcmclk 20 ns t h(pcmi) hold time, pcmi high or low after pcmclk 20 ns
TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 13 post office box 655303 ? dallas, texas 75265 timing requirements (continued) i 2 c bus (see figure 6) min max unit scl clock frequency 400 khz t high clock high time 600 ns t low clock low time 1300 ns t r sda and scl rise time 300 ns t f sda and scl fall time 300 ns t hd:sta hold time (repeated) start condition. after this period the first clock pulse is generated. 600 ns t su:sta setup time for repeated start condition 600 ns t hd:dat data input hold time 0 ns t su:dat data input setup time 100 ns t su:sto stop condition setup time 600 ns t buf bus free time 1300 ns switching characteristics propagation delay times, c lmax = 10 pf (see figure 5) min max unit t pd1 from pcmclk bit 1 high to pcmo bit 1 valid 35 ns t pd2 from pcmclk high to pcmo valid, bits 2 to n 35 ns t pd3 from pcmclk bit n low to pcmo bit n hi-z 30 ns
TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 14 post office box 655303 ? dallas, texas 75265 parameter measurement information note: slave = vbap a6 a5 a4 a0 r/w 0 ack 0 r7 r6 r5 r0 ack 0 d7 d6 d5 d0 ack 0 stop slave address register address data scl sda start figure 1. i 2 c bus write to vbap note: slave = vbap master drives ack and stop a6 a5 a0 r/w ack 00 r7 r6 r0 ack a6 a0 r/w ack 10 d7 d6 d0 ack slave address register address slave address slave drives the data repeated start scl sda start stop figure 2. i 2 c read from vbap: protocol a note: slave = vbap a6 a5 a0 r/w ack r7 00 r6 r0 ack a6 a5 a0 r/w ack d7 d0 ack master drives ack and stop slave address register address slave address slave drives the data stop stop start scl sda start figure 3. i 2 c read from vbap: protocol b
TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 15 post office box 655303 ? dallas, texas 75265 parameter measurement information register map addressing reg 07 06 05 04 03 02 01 00 power control 00 sidetone en txen rxen micsel biasen rxen earout sel pwrup mode control 01 comp sel tmen pcmlb comp en buzzen rxfltr en txfltr en txslope en txpga 02 pd0 tp3 tp2 tp1 tp0 st2 st1 st0 rxpga 03 rp3 rp2 rp1 rp0 rv3 rv2 rv1 rv0 high dtmf 04 hifreq sel7 hifreq sel6 hifreq sel5 hifreq sel4 hifreq sel3 hifreq sel2 hifreq sel1 hifreq sel0 low dtmf 05 lofreq sel7 lofreq sel6 lofreq sel5 lofreq sel4 lofreq sel3 lofreq sel2 lofreq sel1 lofreq sel0 register power-up defaults reg 07 06 05 04 03 02 01 00 power control ? 00 1 1 1 1 0 1 1 0 power control ? 00 1 0 0 1 1 0 1 1 mode control 01 0 0 0 0 0 0 1 0 txpga 02 0 1 0 0 0 0 0 0 rxpga 03 0 1 1 1 0 0 0 0 high dtmf 04 0 0 0 0 0 0 0 0 low dtmf 05 0 0 0 0 0 0 0 0 ? value when pwrupsel = 0 ? value when pwrupsel = 1
TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 16 post office box 655303 ? dallas, texas 75265 parameter measurement information register map table 1. power control register: address {00} hex bit number definitions 7 6 5 43210 definitions 1 1 1 1 0 1 1 0 default setting pwrupsel = 0 1 0 0 11011 default setting pwrupsel = 1 x x x x x x x 0 reference system, power down x x x x x x x 1 reference system, power up x x x x x x 1 x ear amp1 selected, ear amp2 power down x x x x x x 0 x ear amp2 selected, ear amp1 power down x x x x x 0 x x receive channel enabled x x 0 x x 1 x x receive channel muted x x 1 x x 1 x 0 receive channel, power down x x x x 1 x x x micbias selected x x x x 0 x x x micbias power down x x x 1 xxxx mic1 selected x x x 0 xxxx mic2 selected x 0 x xxxxxt ransmit channel enabled x 1 0 xxxxxt ransmit channel muted x 1 1 xxxxxt ransmit channel power down 0 x x xxxxx sidetone enabled 1 x x x x x x x sidetone muted table 2. mode control register: address {01} hex bit number definitions 7 6543210 definitions 0 0 0 0 0 0 1 0 default setting x x x x x x 0 0 tx channel high-pass filter enabled and slope filter enabled x x x x x x 0 1 tx channel high-pass filter enabled and slope filter disabled x x x x x x 1 0 tx channel high-pass filter disabled and slope filter enabled x x x x x x 1 1 tx channel high-pass filter disabled and slope filter disabled x x x x x 0 x x rx channel high-pass filter disabled (low pass only) x x x x x 1 x x rx channel high-pass filter enabled x x x x 0 x x x buzzcon disabled x x x x 1 x x x buzzcon enabled x x x 0 x x x x linear mode selected 1 x x 1 x x x x a-law companding mode selected 0 xx1xxxx -law companding mode selected x x 0 x x x x x tx and rx channels normal mode x x 1 x x x x x pcm loopback mode x 0 x x x x x x tone mode disabled x 1 x x x x x x tone mode enabled
TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 17 post office box 655303 ? dallas, texas 75265 parameter measurement information transmit pga and sidetone control register: address {02}hex bit definitions: 7 6 5 4 3 2 1 0 definition pdo tp3 tp2 tp1 tp0 st2 st1 st0 see table 2 and table 4 0 1 0 0 0 0 0 0 default setting receive volume control register: address {03}hex bit definitions : 7 6 5 4 3 2 1 0 definition rp3 rp2 rp1 rp0 rv3 rv2 rv1 rv0 see table 3 and table 5 0 1 1 1 0 0 0 0 default setting high tone selection control register: address {04}hex bit definitions: 7 6 5 4 3 2 1 0 definition x x x x x x x x dtmf (see table 7) 0 0 0 0 0 0 0 0 default setting low tone selection control register: address {05}hex bit definitions: 7 6 5 4 3 2 1 0 definition x x x x x x x x dtmf (see table 7) 0 0 0 0 0 0 0 0 default setting ??? ??? ??? ?????? ?????? ?????? ??? ??? ??? 01 2 34 n ? 2n ? 1 n n+1 transmit time slot 1234 n ? 2n ? 1n 80% 20% t su(pcmsyn) t h(pcmsyn) see note a see note c see note b t pd2 t pd1 see note d t su(pcmo) t pd3 80% 20% pcmclk pcmsyn pcmo notes: a. this window is allowed for pcmsyn high. b. this window is allowed for pcmsyn low (t h(pcmsyn) max determined by data collision considerations). c. transitions are measured at 50%. d. bit 1 = msb, bit n = lsb figure 4. transmit timing diagram
TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 18 post office box 655303 ? dallas, texas 75265 parameter measurement information 80% 20% see note c pcmi pcmsyn pcmclk 012 34 n ? 2n ? 1 n n +1 20% 80% ???? ???? ??? ??? ???? ???? 12 34 n ? 2n ? 1n see note d t h(pcmsyn) t su(pcmsyn) see note a t su(pcmi) t h(pcmi) see note b receive time slot a. this window is allowed for pcmsyn high. b. this window is allowed for pcmsyn low. c. transitions are measured at 50%. d. bit 1 = msb, bit n = lsb figure 5. receive timing diagram t buf t hd(sta) t low t r t f t hd(dat) t high t su(dat) t su(sta) t hd(sta) t su(sto) sto sta sta sto sda scl figure 6. i 2 c bus timing diagram
TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 19 post office box 655303 ? dallas, texas 75265 principles of operation power-on initialization an external reset with a minimum pulse width of 500 ns must be applied to the active low reset terminal to guarantee reset upon power on. all registers are set with default values upon external reset initialization. the desired selection for all programmable functions can be initialized prior to a power-up command using the i 2 c interface. table 3. power-up and power-down procedures (v dd = 2.7 v, earphone amplifier unloaded) device status procedure maximum power consumption power u p set bit 1 = 1 in power control register, ear1 enabled 16.2 mw power up set bit 1 = 0 in power control register, ear2 enabled 14.6 mw power down set bit 7 = 1 in txpga control register and bit 0 = 0 1.35 w power down set bit 7 = 0 in txpga control register and bit 0 = 0 67.5 w in addition to resetting the power-down bit in the power control register, loss of mclk (no transition detected) automatically enters the device into a power-down state with pcmo in the high impedance state. if during a pulse code modulation (pcm) data transmit cycle an asynchronous power down occurs, the pcm interface remains powered up until the pcm data is completely transferred. an additional power-down mode overrides the mclk detection function. this allows the device to enter the power-down state without regard to mclk. setting bit 7 of the tx filter and pga sidetone register to logic high enables this function. conversion laws the device can be programmed either for a 15-bit linear or 8-bit ( -law or a-law) companding mode. the companding operation approximates the ccitt g.711 recommendation. the linear mode operation uses a 15-bit twos-complement format. transmit operation microphone input the microphone input stage is a low noise differential amplifier that provides a preamplifier gain of 23.5 db. a microphone can be capacitively connected to the mic1n and mic1p inputs, while the mic2n and mic2p inputs can be used to capacitively connect a second microphone or an auxiliary audio circuit.
TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 20 post office box 655303 ? dallas, texas 75265 principles of operation transmit operation (continued) _ + _ + v ref 510 k ? 510 k ? 34 k ? 34 k ? c i mic1n c i mic1p m i c r mic r mic mbias figure 7. typical microphone interface microphone mute function transmit channel muting provides 80-db attenuation of input microphone signal. the micmute function can be selected by setting bit 6 of the power control register through the i 2 c interface. transmit channel gain control the values in the transmit pga control registers control the gain in the transmit path. the total tx channel gain can vary from 35.5 db to 13.5 db. the default total tx channel gain is 23.5 db table 4. transmit gain control bit name mic amp1 mic amp2 tx pga gain mode total tx gain tp3 tp2 tp1 tp0 gain gain gain min typ max unit 0 0 0 0 23.5 12 0 extended 35.3 35.5 35.7 db 0 0 0 1 23.5 12 ? 2 extended 33.3 33.5 33.7 db 0 0 1 0 23.5 12 ? 4 extended 31.3 31.5 31.7 db 0 0 1 1 23.5 12 ? 6 extended 29.3 29.5 29.7 db 0 1 0 0 23.5 12 ? 8 extended 27.3 27.5 27.7 db 0 1 0 1 23.5 12 ? 10 extended 25.3 25.5 25.7 db 1 0 0 0 23.5 0 0 normal 23.3 23.5 23.7 db 1 0 0 1 23.5 0 ? 2 normal 21.3 21.5 21.7 db 1 0 1 0 23.5 0 ? 4 normal 19.3 19.5 19.7 db 1 0 1 1 23.5 0 ? 6 normal 17.3 17.5 17.7 db 1 1 0 0 23.5 0 ? 8 normal 15.3 17.5 17.7 db 1 1 0 1 23.5 0 ? 10 normal 13.3 13.5 13.7 db
TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 21 post office box 655303 ? dallas, texas 75265 principles of operation receive operation receive channel gain control the values in the receive pga control registers control the gain in the receive path. pga gain is set from ? 6db to 6 db in 1-db steps through the i 2 c interface. the default receive channel gain is ? 1 db. table 5. receive pga gain control bit name relative gain rp3 rp2 rp1 rp0 min typ max unit 0 0 0 0 5.8 6 6.2 db 0 0 0 1 4.8 5 5.2 db 0 0 1 0 3.8 4 4.2 db 0 0 1 1 2.8 3 3.2 db 0 1 0 0 1.8 2 2.2 db 0 1 0 1 0.8 1 1.2 db 0 1 1 0 ? 0.2 0 0.2 db 0 1 1 1 ? 1.2 ? 1 ? 0.8 db 1 0 0 0 ? 2.2 ? 2 ? 1.8 db 1 0 0 1 ? 3.2 ? 3 ? 2.8 db 1 0 1 0 ? 4.2 ? 4 ? 3.8 db 1 0 1 1 ? 5.2 ? 5 ? 4.8 db 1 1 0 0 ? 6.2 ? 6 ? 5.8 db sidetone gain control the values in the sidetone pga control registers control the sidetone gain. sidetone gain is set from ? 12 db to ? 24 db in 2-db steps through the i 2 c interface. sidetone can be muted by setting bit 7 of the power control register. the default sidetone gain is ? 12 db. table 6. sidetone gain control bit name relative gain st2 st1 st0 min typ max unit 0 0 0 ? 12.2 ? 12 ? 11.8 db 0 0 1 ? 14.2 ? 14 ? 13.8 db 0 1 0 ? 16.2 ? 16 ? 15.8 db 0 1 1 ? 18.2 ? 18 ? 17.8 db 1 0 0 ? 20.2 ? 20 ? 19.8 db 1 0 1 ? 22.2 ? 22 ? 21.8 db 1 1 0 ? 24.2 ? 24 ? 23.8 db
TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 22 post office box 655303 ? dallas, texas 75265 principles of operation receive operation (continued) receive volume control the values in the volume control pga control registers provide volume control into the earphone. volume control gain is set from 0 db to ? 18 db in 2-db steps through the i 2 c interface. the default rx volume control gain is 0 db. table 7. rx volume control bit name relative gain rv3 rv2 rv1 rv0 min typ max unit 0 0 0 0 ? 0.2 0 0.2 db 0 0 0 1 ? 2.2 ? 2 ? 1.8 db 0 0 1 0 ? 4.2 ? 4 ? 3.8 db 0 0 1 1 ? 6.2 ? 6 ? 5.8 db 0 1 0 0 ? 8.2 ? 8 ? 7.8 db 0 1 0 1 ? 10.2 ? 10 ? 9.8 db 0 1 1 0 ? 12.2 ? 12 ? 11.8 db 0 1 1 1 ? 14.2 ? 14 ? 13.8 db 1 0 0 0 ? 16.2 ? 16 ? 15.8 db 1 0 0 1 ? 18.2 ? 18 ? 17.8 db earphone amplifier the analog signal can be routed to one of two earphone amplifiers: one with differential output (ear1on and ear1op) capable of driving a 16- ? load or one with single-ended output (ear2o) capable of driving a 32- ? load. earphone mute function muting can be selected by setting bit 3 of the power control register through the i 2 c interface. receive pcm data format companded mode: eight bits are received, the most significant (msb) first. linear mode: 15 bits are received, msb first.
TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 23 post office box 655303 ? dallas, texas 75265 principles of operation receive operation (continued) table 8. receive-data bit definitions bit no. companded mode linear mode 1 cd7 ld14 2 cd6 ld13 3 cd5 ld12 4 cd4 ld11 5 cd3 ld10 6 cd2 ld9 7 cd1 ld8 8 cd0 ld7 9 ? ld6 10 ? ld5 11 ? ld4 12 ? ld3 13 ? ld2 14 ? ld1 15 ? ld0 16 ? ?? transmit channel gain control bits always follow the pcm data in time: cd7 ? cd0 = data word in companded mode ld14 ? ld0 = data word in linear mode dtmf generator operation and interface the dual-tone multifrequency generator (dtmf) circuit generates the summed dtmf tones for push button dialing and provides the pdm output for the buzzcon user-alert tone. there are 255 possible single tones. the tone integer value is determined by the formula: round (tone frequency (hz)/7.8125 hz) the integer value is loaded into either one of two 8-bit registers, high-tone register (04), or low-tone register (05). the tone output is 2 db higher when applied to the high-tone register (04). when generating dtmf tones, the high frequency value must be applied to the high-tone register (04) and the low dtmf value to the low-tone register.
TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 24 post office box 655303 ? dallas, texas 75265 principles of operation dtmf generator operation and interface (continued) table 9. typical dtmf and single tone control dt7 dt6 dt5 dt4 dt3 dt2 dt1 dt0 integer value tone function tone / h z 0 0 0 0 0 0 0 0 0 off 0 0 0 1 0 1 1 0 1 45 f 349 0 0 1 0 1 1 1 1 47 f# 370 0 0 1 1 0 0 1 0 50 g 392 0 0 1 1 0 1 0 1 53 g# 415 0 0 1 1 1 0 0 0 56 a 440 0 0 1 1 1 1 0 0 60 a# 466 0 0 1 1 1 1 1 1 63 b 494 0 1 0 0 0 0 1 1 67 c 523 0 1 0 0 0 1 1 1 71 c# 554 0 1 0 0 1 0 1 1 75 d 587 0 1 0 1 0 0 0 0 80 d# 622 0 1 0 1 0 1 0 0 84 e 659 0 1 0 1 1 0 0 1 89 f 698 0 1 0 1 1 1 1 1 95 f# 740 0 1 1 0 0 1 0 0 100 g 784 0 1 1 0 1 0 1 0 106 g# 831 0 1 1 1 0 0 0 1 113 a 880 0 1 1 1 0 1 1 1 119 a# 932 0 1 1 1 1 1 1 0 126 b 988 1 0 0 0 0 1 1 0 134 c 1047 1 0 0 0 1 1 1 0 142 c# 1109 1 0 0 1 0 1 1 0 150 d 1175 1 0 0 1 1 1 1 1 159 d# 1245 1 0 1 0 1 0 0 1 169 e 1319 1 0 1 1 0 0 1 1 179 f 1397 1 0 1 1 1 1 0 1 189 f# 1480 1 1 0 0 1 0 0 1 201 g 1568 1 1 0 1 0 1 0 1 213 g# 1661 1 1 1 0 0 0 0 1 225 a 1760 1 1 1 0 1 1 1 1 239 a# 1865 1 1 1 1 1 1 0 1 253 b 1976 0 1 0 1 1 0 0 1 89 dtmf low 697 0 1 1 0 0 0 1 1 99 dtmf low 770 0 1 1 0 1 1 0 1 109 dtmf low 852 0 1 1 1 1 0 0 0 120 dtmf low 941 1 0 0 1 1 0 1 1 155 dtmf high 1209 1 0 1 0 1 0 1 1 171 dtmf high 1336 1 0 1 1 1 1 0 1 189 dtmf high 1477 1 1 0 1 0 0 0 1 209 dtmf high 1633
TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 25 post office box 655303 ? dallas, texas 75265 principles of operation dtmf generator operation and interface (continued) tones from the dtmf generator block are present at all outputs and are controlled by enabling or disabling the individual output ports. the values that determine the tone frequency are loaded into the tone registers (high and lo) as two separate values. the values loaded into the tone registers initiate an iterative table look-up function, placing a 6-bit or 7-bit in twos complement value into the the tone registers. there is a 2 db difference in the resulting output of the two registers, the high-tone register having the greater result. the resulting range of a tone set into the low register value is +31 {1f}hex to ? 32 {20}hex for a range of six bits and is in twos complement format. the resulting range of a tone set into the high register value is +39 {27}hex to ? 40 {d8}hex in twos-complement format, as well. the maximum range is six bits having a maximum value of {31}hex. the value {31} is represented as 01 1111. two zeros are added to the leading side of the value and then the value is padded with seven lsb zeros to create a value of 000 1111 1000 0000. because the maximum full scale value is 000 1111 1000 0000, the resulting output magnitude is 20 log (input value/maximum value) or 20 log (3968/16783) or ? 12.31 db below full scale. this is the result when all gains are set at default. buzzer logic section the single-ended output buzzcon is a pdm signal intended to drive a buzzer through an external driver transistor. the pdm begins as a selected tone, is generated and passed through the receive d/a channel, and is fed back to the transmit channel analog modulator, where a pdm signal is generated and routed to the buzzcon output. support section the clock generator and control circuit uses the master clock input (mclk) to generate internal clocks to drive internal counters, filters, and converters. register control data is written into and read back from the vbap registers via the control interface. i 2 c- bus protocols the vbap serial interface is designed to be i 2 c bus-compatible and operates in the slave mode. this interface consists of the following terminals: scl: i 2 c bus serial clock ? this input synchronizes the control data transfer from and to the codec. sda: i 2 c bus serial address/data input/output ? this is a bidirectional terminal that transfers register control addresses and data into and out of the codec. it is an open drain terminal and therefore requires a pullup resistor to v cc (typical 10 k ? for 100 khz). twl1103 has a fixed device select address of {e2}hex for write mode and {e3}hex for read mode. for normal data transfer, sda is allowed to change only when scl is low. changes when scl is high are reserved for indicating the start and stop conditions. data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is at high. changes in the data line while the clock line is at high are interpreted as a start or stop condition.
TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 26 post office box 655303 ? dallas, texas 75265 principles of operation table 10. i 2 c bus conditions condition status description a bus not busy both data and clock lines remain at high. b start data transfer a high to low transition of the sda line while the clock (scl) is high determines a start condition. all commands must proceed from a start condition. c stop data transfer a low to high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must end with a stop condition. d data valid the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. i 2 c bus protocols the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. when addressed, the vbap generates an acknowledge after the reception of each byte. the master device (microprocessor) must generate an extra clock pulse that is associated with this acknowledge bit. the vbap must pull down the sda line during the acknowledge clock pulse so that the sda line is at stable low state during the high period of the acknowledge related clock pulse. setup and hold times must be taken into account. during read operations, a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. in this case, the slave (vbap) must leave the data line high to enable the master to generate the stop condition. clock frequencies and sample rates a fixed pcmsyn rate of 8 khz determines the sampling rate.
TWL1103T-Q1 voice-band audio processor (vbap ? ) sgls120a ? april 2002 ? revised may 2002 27 post office box 655303 ? dallas, texas 75265 mechanical data pbs (s-pqfp-g32) plastic quad flatpack gage plane 16 9 0,13 nom 0,25 0,40 0,70 seating plane 0,10 min 4087735/a 11/95 17 0,17 0,23 8 5,05 4,95 sq 3,50 typ 24 25 1 32 6,90 7,10 sq 1,05 0,95 1,20 max 0,08 0,50 m 0,08 0 ? 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice.
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