1 dac7613 12-bit, voltage output digital-to-analog converter dac7613 description the dac7613 is a 12-bit, voltage output digital-to- analog converter with guaranteed 12-bit monotonic performance over the specified temperature range. the dac7613 accepts a 12-bit parallel input data, has double-buffered dac input logic and provides a readback mode of the internal input register. an asyn- chronous reset clears all registers to a mid-scale code of 800 h or to a zero-scale of 000 h . the dac7613 can operate from a single +5v supply or from +5v and C5v supplies. low power and small size makes the dac7613 ideal for data acquisition systems and closed-loop servo- control. the dac7613 is available in a plastic ssop-24 package, and offers guaranteed specifica- tions over the C40 c to +85 c temperature range. features l low power: 1.8mw l unipolar or bipolar operation l settling time: 10 m s to 0.012% l 12-bit linearity and monotonicity: C40 c to +85 c l data readback l double-buffered data inputs l 24-lead ssop package applications l process control l closed-loop servo-control l motor control l data acquisition systems ? 1998 burr-brown corporation pds-1500b printed in u.s.a. january, 2000 international airport industrial park ? mailing address: po box 11400, tucson, az 85734 ? street address: 6730 s. tucson bl vd., tucson, az 85706 ? tel: (520) 746-1111 twx: 910-952-1111 ? internet: http://www.burr-brown.com/ ? cable: bbrcorp ? telex: 066-6491 ? fax: (520) 889-1510 ? i mmediate product info: (800) 548-6132 ts dac register dac dac7613 input register i/o buffer data i/o cs 12 r/w v refl v out reset resetsel loaddac gnd v refh v dd v ss dac7613 for most current data sheet and other product information, visit www.burr-brown.com sbas105
2 dac7613 specification at t a = C40 c to +85 c, v dd = +5v, v ss = C5v, v refh = +2.5v, and v refl = C2.5v, unless otherwise noted. the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or o missions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. pr ices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems. dac7613e dac7613eb notes: (1) if v ss = 0v, specification applies at code 00a h and above. (2) lsb means least significant bit, when v refh equals +2.5v and v refl equals C2.5v, then one lsb equals 1.22mv. (3) ideal output voltage, does not take into account zero or full-scale error. (4) if v ss = C5v, full-scale 5v step. if v ss = 0v, full-scale positive 2.5v step and negative step from code fff h to 00a h . parameter conditions min typ max min typ max units accuracy linearity error (1) v ss = 0v or C5v 2 1 lsb (2) differential linearity error v ss = 0v or C5v 1 1 lsb monotonicity t min to t max 12 [ bits zero-scale error code = 000 h 4 [ lsb zero-scale drift 25 [[ ppm/ c full-scale error code = fff h 4 [ ls zero-scale error code = 00a h , v ss = 0v 8 [ lsb zero-scale drift v ss = 0v 5 10 [[ ppm/ c full-scale error code = fff h , v ss = 0v 8 [ lsb power supply rejection 30 [ ppm/v analog output voltage output (3) v refl = 0v, v ss = 0v 0 v refh [[ v v ss = C5v v refl v refh [[ v output current C1.25 +1.25 [[ ma load capacitance no oscillation 100 [ pf short-circuit current +5, C15 [ ma short-circuit duration indefinite [ reference input v refh input range v ss = 0v or C5v v refl + 1.25 +2.5 [[ v v refl input range v ss = 0v 0 v refh C 1.25 [[ v v refl input range v ss = C5v C2.5 v refh C 1.25 [[ v dynamic performance settling time (4) to 0.012% 5 10 [[ m s output noise voltage 0hz to 1mhz 40 [ nv/ ? hz digital input/output logic family cmos [ logic levels v ih i ih 10 m a 0.7 v dd v dd + 0.3 [[ v v il i il 10 m a C0.3 0.3 v dd [[ v v oh i oh = C0.8ma 3.6 v dd [[ v v ol i ol = 1.6ma 0.0 0.4 [[ v data format straight binary [ power supply requirements v dd 4.75 5.25 [[ v v ss if v ss 1 0v C5.25 C4.75 [[ v i dd 0.35 0.5 [[ ma i ss C0.65 C0.45 [[ ma power dissipation v ss = C5v 4 5.75 [[ mw v ss = 0v 1.8 2.5 [[ mw temperature range specified performance C40 +85 [[ c
3 dac7613 absolute maximum ratings (1) v dd to v ss ............................................................................. C0.3v to 11v v dd to gnd .......................................................................... C0.3v to 5.5v v refl to v ss .............................................................. C0.3v to (v dd C v ss ) v dd to v refh ............................................................. C0.3v to (v dd C v ss ) v refh to v refl .......................................................... C0.3v to (v dd C v ss ) digital input voltage to gnd ................................... C0.3v to v dd + 0.3v digital output voltage to gnd ................................. C0.3v to v dd + 0.3v maximum junction temperature ................................................... +150 c operating temperature range ........................................ C40 c to +85 c storage temperature range ......................................... C65 c to +150 c lead temperature (soldering, 10s) ............................................... +300 c note: (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability. electrostatic discharge sensitivity this integrated circuit can be damaged by esd. burr-brown recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. package/ordering information maximum maximum linearity differential package specification error linearity error drawing temperature ordering transport product (lsb) (lsb) package number range number (1) media dac7613e 2 1 ssop-24 338 C40 c to +85 c dac7613e rails """""" dac7613e/1k tape and reel dac7613eb 1 1 ssop-24 338 C40 c to +85 c dac7613eb rails """""" dac7613eb/1k tape and reel note: (1) models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /1k indicates 1000 dev ices per reel). ordering 1000 pieces of dac7613e/1k will get a single 1000-piece tape and reel.
4 dac7613 top view ssop pin descriptions pin configuration pin label description 1 db11 data bit 11, msb 2 db10 data bit 10 3 db9 data bit 9 4 db8 data bit 8 5 db7 data bit 7 6 db6 data bit 6 7 db5 data bit 5 8 db4 data bit 4 9 db3 data bit 3 10 db2 data bit 2 11 db1 data bit 1 12 db0 data bit 0, lsb 13 v refl reference input voltage low. sets minimum out- put voltage for the dac. 14 nic not internally connected 15 v refh reference input voltage high. sets maximum output voltage for the dac. 16 v ss negative analog supply voltage, 0v or C5v nominal. 17 gnd ground 18 v dd positive power supply 19 v out dac voltage output 20 loaddac the selected dac register becomes transparent when loaddac is low. it is in the latched state when loaddac is high. 21 reset asynchronous reset input. sets the dac register to either zero-scale (000 h ) or mid-scale (800 h ) when low. resetsel determines which code is active. 22 resetsel when low, a low on reset will cause the dac register to be set to code 000 h . when resetsel is high, a low on reset will set the registers to code 800 h . 23 cs chip select. active low. 24 r/w enabled by cs. controls data read and write from the input register. 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 db11 (msb) db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 (lsb) r/w cs resetsel reset loaddac v out v dd gnd v ss v refh nic v refl dac7613e
5 dac7613 typical performance curves: v ss = 0v at t a = +25 c, v dd = +5v, v refh = +2.5v, and v refl = 0v, representative unit, unless otherwise specified. linearity error and differential linearity error vs code 200 h 000 h digital input code dle (lsb) le (lsb) 0.50 0.00 ?.25 ?.50 0.50 0.25 0.00 ?.50 ?.25 0.25 400 h 600 h 800 h a00 h c00 h e00 h fff h linearity error vs code (?0 c and +85 c) 000 h digital input code le (lsb) le (lsb) 0.50 0.00 ?.25 ?.50 0.50 0.25 0.00 ?.50 ?.25 0.25 200 h 400 h 600 h 800 h a00 h c00 h e00 h fff h +85 c ?0 c differential linearity error vs code (?0 c and +85 c) 000 h digital input code dle (lsb) dle (lsb) 0.50 0.00 ?.25 ?.50 0.50 0.25 0.00 ?.50 ?.25 0.25 200 h 400 h 600 h 800 h a00 h c00 h e00 h fff h +85 c ?0 c zero-scale error vs temperature (code 010 h ) 20 ?0 100 ?0 0 40 temperature ( c) zero-scale error (lsb) ? 6 4 3 0 ? 5 1 2 60 80 full-scale error vs temperature (code fff h ) 20 ?0 100 ?0 0 40 temperature ( c) full-scale error (lsb) ? 6 4 3 0 ? 5 1 2 60 80
6 dac7613 typical performance curves: v ss = C 5v at t a = +25 c, v dd = +5v, v refh = +2.5v, and v refl = 0v, representative unit, unless otherwise specified. linearity error vs code 000 h digital input code le (lsb) le (lsb) 0.50 0.00 ?.25 ?.50 0.50 0.25 0.00 ?.50 ?.25 0.25 200 h 400 h 600 h 800 h a00 h c00 h e00 h fff h differential linearity error vs code 000 h digital input code dle (lsb) dle (lsb) 0.50 0.00 ?.25 ?.50 0.50 0.25 0.00 ?.50 ?.25 0.25 200 h 400 h 600 h 800 h a00 h c00 h e00 h fff h zero-scale error vs temperature (code 000 h ) 20 ?0 100 ?0 0 40 temperature ( c) zero-scale error (lsb) ?.0 3.0 2.0 1.5 0.0 ?.5 2.5 0.5 1.0 60 80 full-scale error vs temperature (code fff h ) 20 ?0 100 ?0 0 40 temperature ( c) full-scale error (lsb) ?.0 3.0 2.0 1.5 0.0 ?.5 2.5 0.5 1.0 60 80 linearity error and differential linearity error vs code 000 h digital input code dle (lsb) le (lsb) 0.50 0.00 ?.25 ?.50 0.50 0.25 0.00 ?.50 ?.25 0.25 200 h 400 h 600 h 800 h a00 h c00 h e00 h fff h
7 dac7613 theory of operation the dac7613 is a 12-bit, voltage output digital-to-analog converter (dac). the architecture is a classic r-2r ladder configuration followed by an operational amplifier that serves as a buffer. the minimum voltage output (zero-scale) and maximum voltage output (full-scale) are set by the exter- nal voltage references (v refl and v refh , respectively). the digital input is a 12-bit parallel word and the dac input register offers a readback capability. the converter can be powered from a single +5v supply or a dual 5v supply. the device offers a reset function which immediately sets the dac output voltage and dac register to mid-scale (code 800 h ) or to zero-scale (code 000 h ), depending on the status of the reset selection. see figures 1 and 2 for the basic operation of the dac7613. figure 1. basic single-supply operation of the dac7613. figure 2. basic dual-supply operation of the dac7613. 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 r/w cs resetsel reset loaddac v out v dd gnd v ss v refh nic v refl read/write chip select reset select reset dac load dac register 0v to +2.5v dac7613e +5v data bus +2.5v 0.1 f1 f 0.1 f + 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 r/w cs resetsel reset loaddac v out v dd gnd v ss v refh nic v refl read/write chip select reset select reset dac load dac register ?.5v to +2.5v dac7613e +5v data bus ?v 0.1 f1 f 1 f 0.1 f +2.5v 0.1 f ?.5v 0.1 f + +
8 dac7613 analog outputs when v ss = C5v (dual supply operation), the output ampli- fier can swing to within 2.25v of the supply rails, guaran- teed over the C40 c to +85 c temperature range. with v ss = 0v (single-supply operation), the output can swing to ground. note that the settling time of the output op amp will be longer with voltages very near ground. additionally, care must be taken when measuring the zero-scale error when v ss = 0v. since the output voltage cannot swing below ground, the output voltage may not change for the first few digital input codes (000 h , 001 h , 002 h , etc.) if the output amplifier has a negative offset. the behavior of the output amplifier can be critical in some applications. under short-circuit conditions (dac output shorted to ground), the output amplifier can sink a great deal more current than it can source. see the specifications table for more details concerning short-circuit current. reference inputs the reference inputs, v refl and v refh , can be any voltage between v ss + 2.25v and v dd C 2.25v provided that v refh is at least 1.25v greater than v refl . the minimum output of each dac is equal to v refl plus a small offset voltage (essentially, the offset of the output op amp). the maximum output is equal to v refh plus a similar offset voltage. note that v ss (the negative power supply) must either be connected to ground or must be in the range of C4.75v to C5.25v. the voltage on v ss sets several bias points within the converter. if v ss is not in one of these two configura- tions, the bias values may be in error and proper operation of the device is not guaranteed. the current into the v refh input depends on the dac output voltages and can vary from a few microamps to approxi- mately 0.1 milliamp. the v refh source will not be required to sink current, only source it. bypassing the reference voltage or voltages with at least a 0.1 m f capacitor placed as close to the dac7613 package is strongly recommended. digital interface table i shows the basic control logic for the dac7613. note that the internal register is level triggered and not edge triggered. when the appropriate signal is low, the register becomes transparent. when this signal is returned high, the digital word currently in the register is latched. the first register (the input register) is triggered via the r/w, and cs inputs. the second register (the dac register) is transparent when loaddac input is pulled low. the double-buffered architecture is mainly designed so that the dac input register can be written at any time and then the dac voltage updated by pulling loaddac low. input dac r/w cs rst loaddac register register mode l l h l write write write l l h h write hold write input h l h h read hold read input x h h l hold update update x h h h hold hold hold x h l x hold reset reset x = dont care. table i. dac7613 control logic truth table.
9 dac7613 v out = v refl + v refh v refl () n 4096 digital timing figure 3 and table ii provide detailed timing for the digital interface of the dac7613. digital input coding the dac7613 input data is in straight binary format. the output voltage is given by the following equation: (1) where n is the digital input code. this equation does not include the effects of offset (zero-scale) or gain (full-scale) errors. figure 3. digital input and output timing. t rcs cs t rds t rdh t csd t dz r/w data out data valid t wcs cs t ws t wh r/w t reset t lwd loaddac t ds t dh data in reset data output timing digital input timing symbol description min typ max units t rcs cs low for read 200 ns t rds r/w high to cs low 10 ns t rdh r/w high after cs high 0 ns t dz cs high to data bus in 100 ns high impedance t csd cs low to data bus valid 100 160 ns t wcs cs low for write 50 ns t ws r/w low to cs low 0 ns t wh r/w low after cs high 5 ns t ds data valid to cs low 0 ns t dh data valid after cs high 5 ns t lwd loaddac low 50 ns t reset reset low 50 ns table ii. timing specifications (t a = C40 c to +85 c).
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. customers are responsible for their applications using ti components. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 2000, texas instruments incorporated
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