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dual, 500khz, 12-bit, 2 + 2 channel, simultaneous sampling analog-to-digital converter features l 4 input channels l fully differential inputs l 2 m s total throughput per channel l guaranteed no missing codes l 1mhz effective sampling rate l low power: 40mw l ssi serial interface applications l motor control l multi-axis positioning systems l 3-phase power control description the ads7861 is a dual, 12-bit, 500khz, analog-to- digital converter with 4 fully differential input channels grouped into two pairs for high speed, simultaneous signal acquisition. inputs to the sample-and-hold ampli- fiers are fully differential and are maintained differen- tial to the input of the a/d converter. this provides excellent common-mode rejection of 80db at 50khz which is important in high noise environments. the ads7861 offers a high speed, dual serial interface and control inputs to minimize software overhead. the output data for each channel is available as a 12-bit word. the ads7861 is offered in a 24-lead ssop package and is fully specified over the C40 c to +85 c operating range. ads7861 ? 1998 burr-brown corporation pds-1508a printed in u.s.a. december, 1998 international airport industrial park ? mailing address: po box 11400, tucson, az 85734 ? street address: 6730 s. tucson bl vd., tucson, az 85706 ? tel: (520) 746-1111 twx: 910-952-1111 ? internet: http://www.burr-brown.com/ ? cable: bbrcorp ? telex: 066-6491 ? fax: (520) 889-1510 ? i mmediate product info: (800) 548-6132 ads7861 sar serial interface comp clock a0 m1 m0 convst cs rd busy serial data b serial data a cdac internal 2.5v reference sha ch a0 ch a0+ ref in ch a1 ch a1+ sar comp cdac sha ch b0 ch b0+ ch b1 ch b1+ ref out sbas110
2 ads7861 specifications all specifications t min to t max , +v a + v d = +5v, and v ref = internal +2.5v, f clk = 8mhz, f sample = 500khz, unless otherwise noted. the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or o missions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. pr ices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems. ads7861e ads7861eb parameter conditions min typ max min typ max units resolution 12 [ bits analog input input voltage range-bipolar v center = internal v ref at 2.5v Cv ref +v ref [[ v input capacitance 15 [ pf input leakage current 1 [ m a system performance no missing codes 12 [ bits integral linearity 0.75 2 0.5 1 lsb integral linearity match 0.5 1 [[ lsb differential linearity 1 0.5 1 lsb bipolar offset error referenced to ref in 0.5 3 [[ lsb bipolar offset error match 3 2 lsb positive gain error referenced to ref in 0.15 0.75 0.10 0.50 % of fsr positive gain error match 2 1 lsb negative gain error referenced to ref in 0.15 0.75 0.10 0.50 % of fsr negative gain error match 2 1 lsb common-mode rejection ratio at dc 80 [ db v in = 1.25vp-p at 50khz 80 [ db noise 120 [ m vrms power supply rejection ratio 0.5 2 [[ lsb sampling dynamics conversion time per a/d 1.625 [ m s acquisition time 0.375 [ m s throughput rate 500 [ khz aperture delay 3.5 [ ns aperture delay matching 100 [ ps aperture jitter 50 [ ps small-signal bandwidth 40 [ mhz dynamic characteristics total harmonic distortion v in = 2.5vp-p at 100khz C72 C76 db sinad v in = 2.5vp-p at 100khz 70 [ db spurious free dynamic range v in = 2.5vp-p at 100khz 72 76 db channel-to-channel isolation v in = 2.5vp-p at 100khz C80 [ db voltage reference internal 2.475 2.5 2.525 [[[ v internal drift 25 [ ppm/ c internal noise 50 [ m vp-p internal source current 2 [ ma internal load rejection 0.005 [ mv/ m a internal psrr 80 [ db external voltage range 1.2 2.5 2.6 [[[ v input current 0.05 1 [[ m a input capacitance 5 [ pf digital input/output logic family cmos [ logic levels: v ih i ih = +5 m a 3.0 +v dd + 0.3 [[ v v il i il = +5 m a C0.3 1 [[ v v oh i oh = 2 cmos loads 3.5 [ v v ol i ol = 2 cmos loads 0.4 [ v external clock, optional 0.2 8 [[ mhz data format binary twos complement [ power supply requirements power supply voltage, +v 4.75 5 5.25 [[[ v quiescent current, +v a 58 [[ ma power dissipation 25 40 [[ mw [ specifications same as ads7861e.
3 ads7861 pin name description 1 dgnd digital ground. connect directly to analog ground (pin 12). 2 ch b1+ non-inverting input channel b1 3 ch b1C inverting input channel b1 4 ch b0+ non-inverting input channel b0 5 ch b0C inverting input channel b0 6 ch a1+ non-inverting input channel a1 7 ch a1C inverting input channel a1 8 ch a0+ non-inverting input channel a0 9 ch a0C inverting input channel a0 10 ref in reference input 11 ref out 2.5v reference output 12 agnd analog ground. connect directly to digital ground (pin 1). 13 +v a analog power supply, +5vdc. connect directly to digital power supply (pin 24). decouple to analog ground with a 0.1 m f ceramic capacitor and a 10 m f tantalum capacitor. 14 m1 selects between the serial outputs. when m1 is low, both serial output a and serial output b are selected for data transfer. when m1 is high, serial output a is configured for both channel a data and channel b data; serial output b goes into tri-state (i.e., high impedance). 15 m0 selects between two-channel and four-channel opera- tion. when m0 is low, two-channel operation is se- lected and operates in conjunction with a0. when a0 is high, channel a1 and channel b1 are being con- verted. when a0 is low, channel a0 and channel b0 are being converted. when m0 is high, four-channel operation is selected. in this mode, all four channels are converted in sequence starting with channels a0 and b0, followed by channels a1 and b1. 16 a0 a0 operates in conjunction with m0. with m0 low and a0 high, channel a1 and channel b1 are converted. with m0 low and a0 low, channel a0 and channel b0 are converted. 17 convst convert start. when convst switches from low to high, the device switches from the sample to hold mode, independent of the status of the external clock. 18 rd synchronization pulse for the serial output. 19 cs chip select. when low, the serial output a and serial output b outputs are active; when high, the serial outputs are tri-stated. 20 clock an external cmos-compatible clock can be applied to the clock input to synchronize the conversion process to an external source. the clock pin controls the sampling rate by the equation: clock = 16 ? f sample . 21 busy busy goes high during a conversion and returns low after the third lsb has been transmitted on either the serial a or serial b output pin. 22 serial the serial output data word is comprised of channel information and 12 bits of data. in operation, data is valid on the falling edge of dclock for 16 edges after the trailing edge of the rd. 23 serial the serial output data word is comprised of channel information and 12 bits of data. in operation, data is valid on the falling edge of dclock for 16 edges after the trailing edge of the rd. when m1 is high, both channel a data and channel b data are available. 24 +v d digital power supply, +5vdc. connect directly to pin 13. must be +v a . pin configuration top view ssop pin descriptions absolute maximum ratings analog inputs to agnd, any channel input ........ C0.3v to (+v d + 0.3v) ref in ..................................................................... C0.3v to (+v d + 0.3v) digital inputs to dgnd .......................................... C0.3v to (+v d + 0.3v) ground voltage differences: agnd, dgnd ................................... 0.3v +v d to agnd ......................... C0.3v to +6v power dissipation .......................................................................... 325mw maximum junction temperature ................................................... +150 c operating temperature range ........................................ C40 c to +85 c storage temperature range ......................................... C65 c to +150 c lead temperature (soldering, 10s) ............................................... +300 c electrostatic discharge sensitivity this integrated circuit can be damaged by esd. burr-brown recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifi- cations. data b data a dgnd ch b1+ ch b1 ch b0+ ch b0 ch a1+ ch a1 ch a0+ ch a0 ref in ref out agnd 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 +v d serial data a serial data b busy clock cs rd convst a0 m0 m1 +v a ads7861
4 ads7861 minimum relative maximum specification package accuracy gain error temperature drawing ordering transport product (lsb) (%) range package number (1) number (2) media ads7861e 2 0.75 C40 c to +85 c 24-lead ssop 352 ads7861e rails " " " " " " ads7861eb/2k5 tape and reel ads7861eb 1 0.5 C40 c to +85 c 24-lead ssop 352 ads7861e rails " " " " " " ads7861eb/2k5 tape and reel notes: (1) for detailed drawing and dimension table, please see end of data sheet, or appendix c of burr-brown ic data book. (2 ) models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2k indicates 2000 devices per reel). ordering 2000 pieces o f ads7861e/2k will get a single 2000- piece tape and reel. for detailed tape and reel mechanical information, refer to appendix b of burr-brown ic data book. package/ordering information basic circuit configuration m0 m1 a0 two-channel/four-channel operation data on serial outputs channels converted 0 0 0 two channel a and b a0, b0 0 0 1 two channel a and b a1, b1 0 1 0 two channel a only a0, b0 0 1 1 two channel a only a1, b1 1 0 x four channel a and b sequential 1 1 x four channel a only sequential x = dont care. truth table dgnd ch b1+ ch b1 ch b0+ ch b0 ch a1+ ch a1 ch a0+ ch a0 ref in ref out agnd 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 +v d serial data a serial data b busy clock cs rd convst a0 m0 m1 +v a busy output clock input chip select read input conversion start a0 address select m0 address select m1 address select ads7861 10 f + 0.1 f +5v analog supply +
5 ads7861 typical performance curves at t a = +25 c, +v a + v d = +5v, and v ref = internal +2.5v, f clk = 8mhz, f sample = 500khz, unless otherwise noted. frequency spectrum (4096 point fft; f in = 99.9khz, ?.5db) frequency (khz) 0 ?0 ?0 ?0 ?0 ?00 ?20 amplitude (db) 0 62.5 125 250 187.5 frequency spectrum (4096 point fft; f in = 199.9khz, ?.5db) frequency (khz) 0 ?0 ?0 ?0 ?0 ?00 ?20 amplitude (db) 0 62.5 125 250 187.5 change in positive gain match vs temperature (maximum deviation for all four channels) temperature ( c) 0.6 0.5 0.4 0.3 0.2 0.1 0 change in positive gain match (lsb) ?0 25 85 150 change in signal-to-noise ratio and signal-to-(noise+distortion) vs temperature temperature ( c) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 ?.1 delta from +25 c (db) ?0 25 85 snr sinad change in spurious free dynamic range and total harmonic distortion vs temperature temperature ( c) 7 6 5 4 3 2 1 0 ? +1 0 ?.5 ? ?.5 ? ?.5 ? ?.5 sfdr delta from +25 c (db) thd delta from +25 c (db) ?0 25 85 thd sfdr signal-to-noise ratio and signal-to-(noise+distortion) vs input frequency 10k 100k 1k 1m input frequency (hz) snr and sinad (db) 74 72 70 68 66 64 76 sinad snr
6 ads7861 integral linearity error vs code hex btc code typical of all four channels 1 0.75 0.5 0.25 0 ?.25 ?.5 ?.75 ? ile (lsb) 800 000 7ff typical performance curves (cont) at t a = +25 c, +v a + v d = +5v, and v ref = internal +2.5v, f clk = 8mhz, f sample = 500khz, unless otherwise noted. change in negative gain match vs temperature (maximum deviation for all four channels) temperature ( c) 0.2 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 change in negative gain match (lsb) ?0 25 85 150 change in reference voltage vs temperature temperature ( c) 2.51 2.505 2.5 2.495 2.49 2.485 change in reference (v) ?0 25 85 150 change in bipolar zero vs temperature temperature ( c) 0.75 0.5 0.25 0 ?.25 ?.5 ?.75 change in bipolar zero (lsb) ?0 25 a channel b channel 85 150 change in cmrr vs temperature temperature ( c) 86 85 84 83 82 81 80 79 78 change in cmrr (db) ?0 ? 25 55 85 change in bpz match vs temperature temperature ( c) 1 0.75 0.5 0.25 0 change in bipolar match (lsb) ?0 25 85 150
7 ads7861 differential linearity error vs code hex btc code typical of all four channels 1 0.75 0.5 0.25 0 ?.25 ?.5 ?.75 ? dle (lsb) 800 000 7ff typical performance curves (cont) at t a = +25 c, +v a + v d = +5v, and v ref = internal +2.5v, f clk = 8mhz, f sample = 500khz, unless otherwise noted. differential linearity error vs temperature temperature ( c) 0.8 0.6 0.4 0.2 0 ?.2 ?.4 ?.6 ?.8 dle error (lsb) ?0 25 positive dle negative dle 85 150 integral linearity error match vs code channel a0/channel a1 (same converter, different channels) hex btc code 0.25 0.2 0.15 0.1 0.05 0 ?.05 ?.1 ?.15 ?.2 ?.25 ile (lsb) 800 000 7ff integral linearity error match vs code channel a0/channel b1 (different converter, different channels) hex btc code 0.25 0.2 0.15 0.1 0.05 0 ?.05 ?.1 ?.15 ?.2 ?.25 ile (lsb) 800 000 7ff integral linearity error vs temperature positive ile negative ile temperature ( c) 0.8 0.7 0.6 0.4 0.2 0 ?.2 ?.4 ?.6 ?.8 change in ile (lsb) ?0 25 85 150 integral linearity error match vs temperature channel a0/channel b0 (different converter, different channels) temperature ( c) 0.47 0.46 0.45 0.44 0.43 0.42 0.41 0.40 0.39 0.38 change in inl match (lsb) ?0 25 85 150
8 ads7861 reference under normal operation, the ref out pin (pin 2) should be directly connected to the ref in pin (pin 1) to provide an internal +2.5v reference to the ads7862. the ads7862 can operate, however, with an external reference in the range of 1.2v to 2.6v for a corresponding full-scale range of 2.4v to 5.2v. the internal reference of the ads7862 is double-buffered. if the internal reference is used to drive an external load, a buffer is provided between the reference and the load ap- plied to pin 2 (the internal reference can typically source 2ma of current loadcapacitance should not exceed 100pf). if an external reference is used, the second buffer provides isolation between the external reference and the cdac. this buffer is also used to recharge all of the capacitors of both cdacs during conversion. analog input the analog input is bipolar and fully differential. there are two general methods of driving the analog input of the ads7861: single-ended or differential (see figures 1 and 2). when the input is single-ended, the Cin input is held at the common-mode voltage. the +in input swings around the same common voltage and the peak-to-peak amplitude is the (common-mode +v ref ) and the (common-mode Cv ref ). the value of v ref determines the range over which the common-mode voltage may vary (see figure 3). when the input is differential, the amplitude of the input is the difference between the +in and Cin input, or (+in) C (Cin). the peak-to-peak amplitude of each input is 1/2v ref around this common voltage. however, since the inputs are 180 out of phase, the peak-to-peak amplitude of the differential volt- age is +v ref to Cv ref . the value of v ref also determines the range of the voltage that may be common to both inputs (see figure 4). introduction the ads7861 is a high speed, low power, dual, 12-bit a/d converter that operates from a single +5v supply. the input channels are fully differential with a typical common-mode rejection of 80db. the part contains dual, 2 m s successive approximation adcs, two differential sample-and-hold am- plifiers, an internal +2.5v reference with ref in and ref out pins and a high-speed parallel interface. the ads7861 requires an external clock. in order to achieve the maximum throughput rate of 500khz, the master clock must be set at 8mhz. a minimum of 16 clock cycles are required for each 12-bit conversion. there are four analog inputs that are grouped into two chan- nels (a and b). channel selection is controlled by the m0 (pin 14), m1 (pin 15) and a0 (pin 16) pins. each channel has two inputs (a0 and a1 and b0 and b1) that can be sampled and converted simultaneously, thus preserving the relative phase information of the signals on both analog inputs. the part accepts an analog input voltage in the range of Cv ref to +v ref , centered around the internal +2.5v reference. the part will also accept bipolar input ranges when a level shift circuit is used at the front end (see figure 7). all conversions are initiated on the ads7861 by bringing the convst pin high for a minimum of 15ns. convst high places both sample-and-hold amplifiers in the hold state simultaneously and the conversion process is started on both channels. the rd pin (pin 18) can be connected to convst to simplify operation. depending on the status of the m0, m1 and a0 pins, the ads7861 will (a) operate in either two-channel or four-channel mode and (b) output data on both the serial a and serial b output or both channels can be transmitted on the a output only. note: see the timing and control section of this data sheet for more information. sample-and-hold section the sample-and-hold amplifiers on the ads7861 allow the adcs to accurately convert an input sine wave of full-scale amplitude to 12-bit accuracy. the input bandwidth of the sample-and-hold is greater than the nyquist rate (nyquist equals one-half of the sampling rate) of the adc even when the adc is operated at its maximum throughput rate of 500khz. the typical small-signal bandwidth of the sample- and-hold amplifiers is 40mhz. typical aperture delay time or the time it takes for the ads7861 to switch from the sample to the hold mode following the convst pulse is 3.5ns. the average delta of repeated aperture delay values is typically 50ps (also known as aperture jitter). these specifications reflect the ability of the ads7861 to capture ac input signals accurately at the exact same moment in time. ads7861 ads7861 single-ended input common voltage ? ref to +v ref peak-to-peak differential input common voltage v ref peak-to-peak v ref peak-to-peak figure 1. methods of driving the ads7861 single-ended or differential.
9 ads7861 figure 3. single-ended input: common-mode voltage range vs v ref . 1.0 1.5 1.2 2.0 2.5 2.6 3.0 v ref (v) common voltage range (v) ? 0 1 2 3 4 5 2.7 2.3 4.1 0.9 v cc = 5v single-ended input differential input 1.0 1.5 1.2 2.0 2.5 2.6 3.0 v ref (v) common voltage range (v) ? 0 1 2 3 4 5 4.7 0.3 v cc = 5v 4.05 0.90 figure 2. using the ads7861 in the single-ended and differential input modes. figure 4. differential input: common-mode voltage range vs v ref . in each case, care should be taken to ensure that the output impedance of the sources driving the +in and Cin inputs are matched. otherwise, this may result in offset error, gain error and linearity error which will change with both tem- perature and input voltage. the input current on the analog inputs depend on a number of factors: sample rate, input voltage, and source impedance. essentially, the current into the ads7861 charges the inter- nal capacitor array during the sampling period. after this capacitance has been fully charged, there is no further input current. the source of the analog input voltage must be able to charge the input capacitance (15pf) to a 12-bit settling level within 2 clock cycles. when the converter goes into the hold mode, the input impedance is greater than 1g w . care must be taken regarding the absolute analog input voltage. the +in input should always remain within the range of gnd C 300mv to v dd + 0.3v. cm +v ref +v ref ? ref single-ended inputs t +in cm voltage cm ? ref cm +1/2v ref differential inputs notes: common-mode voltage (differential mode) = common-mode voltage (single-ended mode) = in? (in+) + (in? 2 the maximum differential voltage between +in and ?n of the ads7862 is v ref . see figures 2 and 3 for a further explanation of the common voltage range for single-ended and differential inputs. t +in ?n cm voltage cm ?/2v ref ?n = cm voltage +v ref ? ref
10 ads7861 code (decimal) 8000 7000 6000 5000 4000 3000 2000 1000 0 number of conversions 2044 2045 2046 2047 2048 figure 5. histogram of 8,000 conversions of a dc input. figure 6. test circuits for timing specifications. figure 7. level shift circuit for bipolar input ranges. transition noise figure 5 shows a histogram plot for the ads7861 following 8,000 conversions of a dc input. the dc input was set at output code 2046. all but one of the conversions had an output code result of 2046 (one of the conversions resulted in an output of 2047). the histogram reveals the excellent noise performance of the ads7861. bipolar inputs the differential inputs of the ads7861 were designed to accept bipolar inputs (Cv ref and +v ref ) around the internal reference voltage (2.5v), which corresponds to a 0v to 5v input range with a 2.5v reference. by using a simple op amp circuit featuring a single amplifier and four external resis- tors, the ads7861 can be configured to except bipolar inputs. the conventional 2.5v, 5v, and 10v input ranges can be interfaced to the ads7861 using the resistor values shown in figure 7. timing and control the operation of the ads7861 can be configured in four different modes by using the address pins m0 (pin 14), m1 (pin 15) and a0 (pin 16). the m0 pin selects between two- and four-channel operation (in two-channel operation, the a0 pin selects between chan- nels 0 and 1; in four-channel operation the a0 pin is ignored and the channels are switched automatically after each conversion). the m1 pin selects between having serial data transmitted simultaneously on both the serial a data output (pin 23) and the serial b data output (pin 22) or having both channels output data through the serial a port. the a0 pin selects either channel 0 or channel 1 (see pin descriptions and serial output truth table for more information). the next four sections will explain the four different modes of operation. mode i (m0 = 0, m1 = 0) with the m0 and m1 pins both set to 0, the ads7861 will operate in two-channel operation (the a0 pin must be used to switch between channels a and b). a conversion is initiated by bringing convst high for a minimum of 15ns. it is very important that convst be brought high a minimum of 10ns prior to a rising edge of the external clock or 5ns after the rising edge. if convst is brought r 1 r 2 +in ?n ref out (pin 2) 2.5v 4k w 20k w bipolar input bipolar input r 1 r 2 10v 1k w 5k w 5v 2k w 10k w 2.5v 4k w 20k w opa132 ads7861 data 1.4v test point 3k w 100pf c load t r data voltage waveforms for data rise and fall times t r , and t f . v oh v ol t f description analog input full-scale input span Cv ref to +v ref (1) least significant (Cv ref to +v ref )/4096 (2) bit (lsb) +full scale 4.99878v 0111 1111 1111 7ff midscale 2.5v 0000 0000 0000 000 midscale C 1 lsb 2.49878v 1111 1111 1111 fff Cfull scale 0v 1000 0000 0000 800 notes: (1) Cv ref to +v ref around v ref . with a 2.5v reference, this corre- sponds to a 0v to 5v input span. (2) 1.22mv with a 2.5v reference. table i. ideal input voltages and output codes. digital output binary twos complement binary code hex code
11 ads7861 figure 8. conversion mode. high within this window, it is then uncertain as to when the ads7861 will initiate conversion (see figure 8 for a more detailed description). sixteen clock cycles are required to perform a single conversion. immediately following convst switching to high, the ads7861 will switch from the sample mode to the hold mode asynchronous to the external clock. the busy output pin will then go high and remain high for the duration of the conversion cycle. on the falling edge of the first cycle of the external clock, the ads7861 will latch in the address for the next conversion cycle depending on the status of the a0 pin (high = channel 1, low = channel 0). the address must be selected 15ns prior to the falling edge of cycle one of the external clock and must remain held for 15ns following the clock edge. for maximum throughput time, the convst and rd pins should be tied together. cs must be brought low to enable the two serial outputs. data will be valid on the rising edge of all 16 clock cycles per conversion. the first bit of data will be a status flag for either channel 0 or 1, the second bit will be a second status flag for either channel a or b. the subsequent data will be msb-first through the lsb, followed by two zeros (see table ii and figures 9 and 10). symbol description min typ max units comments t conv conversion time 1.75 m s when t ckp = 125ns t acq acquisition time 0.25 m s when t ckp = 125ns t ckp clock period 125 5000 ns t ckl clock low 40 ns t ckh clock high 40 ns t f dout fall time 25 ns t r dout rise time 30 ns t 1 convst high 15 ns t 2 address setup time 15 ns address latched on falling edge of clk cycle 2 t 3 address hold time 15 t 4 rd setup time 15 ns before falling edge of clock t 5 rd to cs hold time 15 ns after falling edge of clock t 6 convst low 20 ns t 7 rd low 20 ns t 8 cs to data valid 25 ns t 9 clock to data valid delay 30 ns maximum delay following rising edge of clock t 10 data valid after clock (1) 1 ns time data is valid after second rising edge of clock note: (1) n C 1 data will remain valid 1ns after rising edge of next clock cycle. timing specifications clock cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 serial data ch0 or ch1 cha or chb db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 table ii. serial data output format. note: all convst commands which occur more than 10ns before the rising edge of cycle ? of the external clock (region ?? will initiate a conversion on the rising edge of cycle ?? all convst commands which occur 5ns after the rising edge of cycle ? or 10ns before the rising edge of cycle 2 (region ?? will initiate a conversion on the rising edge of cycle ?? all convst commands which occur 5ns after the rising edge of cycle ? (region ?? will initiate a conversion on the rising edge of the next clock period. the convst pin should never be switched from low to high in the region 10ns prior to the rising edge of the clock and 5ns after the rising edge (gray areas). if convst is toggled in this gray area, the conversion could begin on either the same rising edge of the clock or the following edge. clock convst cycle 1 cycle 2 t ckp 125ns 10ns 5ns 10ns 5ns a b c
12 ads7861 mode ii (m0 = 0, m1 = 1) with m1 set to 1, the ads7861 will output data on the serial data a pin only. all other pins function in the same manner as mode i except that the serial data b output will tri-state (i.e., high impedance) after a conversion following m1 going high. another difference in this mode involves the convst pin. since it takes 32 clock cycles to output the results from both a/d converters (rather than 16 when m1 = 0), the ads7861 will take 4 m s to complete a conversion on both a/ds. therefore, every second convst command will be ignored by the ads7861 since it will require two conversion cycles to transmit both channels out the serial a port. see figure 11. mode iii (m0 = 1, m1 = 0) with m0 set to 1, the ads7861 will cycle through chan- nels 0 and 1 sequentially (the a0 pin is ignored). at the same time, setting m1 to 0 places both serial outputs, a and b, in the active mode. see figure 12. mode iv (m0 = 1, m1 = 1) similar to mode ii, mode iv uses the serial a output line to transmit data exclusively. following the first conversion after m1 goes high, the serial b output will go into tri- state. see figure 13. as in mode ii, the second convst command is always ignored when m1 = 1. reading data in all four timing diagrams, the convst pin and the rd pins are tied together. if so desired, the two lines can be separated. data on the serial output pins (a and b) will become valid following the third external clock cycle fol- lowing a rd low. refer to table ii for data output format. layout for optimum performance, care should be taken with the physical layout of the ads7861 circuitry. this is particu- larly true if the clock input is approaching the maximum throughput rate. the basic sar architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections and digital inputs that occur just prior to latching the output of the analog comparator. thus, driving any single conver- sion for an n-bit sar converter, there are n windows in which large external transient voltages can affect the conver- sion result. such glitches might originate from switching power supplies, nearby digital logic or high power devices. the degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the exter- nal event. their error can change if the external event changes in time with respect to the clock input. with this in mind, power to the ads7861 should be clean and well bypassed. a 0.1 m f ceramic bypass capacitor should be placed as close to the device as possible. in addition, a 1 m f to 10 m f capacitor is recommended. if needed, an even larger capacitor and a 5 w or 10 w series resistor may be used to low pass filter a noisy supply. on average, the ads7861 draws very little current from an external reference as the reference voltage is internally buffered. however, glitches from the conversion process appear at the v ref input and the reference source must be able to handle this. whether the reference is internal or external, the v ref pin should be bypassed with a 0.1 m f capacitor. an additional larger ca- pacitor may also be used, if desired. if the reference voltage is external and originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscilla- tion. no bypass capacitor is necessary when using the internal reference (tie pin 10 directly to pin 11). the gnd pin should be connected to a clean ground point. in many cases, this will be the analog ground. avoid connections which are too near the grounding point of a microcontroller or digital signal processor. if required, run a ground trace directly from the converter to the power supply entry point. the ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry. applications an applications section will be added featuring the ads7862 interfacing to popular dsp processors. the updated data sheet will be available in the near future on the burr-brown web site: http: //www.burr-brown.com/
13 ads7861 figure 9. mode i with timing specifications. figure 10. mode i, timing diagram for m0 = 0 and m1 = 0. a0 rd cs busy serial data a 1 clock convst 2345 7 68910111213141516123456 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 d11 d10 d9 d8 00 serial data b d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 d11 d10 d9 d8 00 t 3 t 1 t conv conversion 1 start of conversion 2 t acq t conv t 7 t 10 t 9 t 6 t ckh t ckl 0 t 2 t 4 t 8 t 5 1 clock convst a0 rd cs serial data a serial data b busy time 0 1 2 3 4 5 6 time (seconds) conversion of chx 12-bit data of chx 12-bit data of chx 12-bit data of cha1 12-bit data of chb1 conversion of ch0 16 cs high, outputs in tri-state conversion of ch1 a0 high, next conversion: ch1 a0 low, next conversion: ch0 conversion of ch0 conversion of ch1 rd connected to convst
14 ads7861 figure 12. mode iii, timing diagram for m0 = 1 and m1 = 0. figure 11. mode ii, timing diagram for m0 = 0 and m1 = 1. clock convst a0 rd m1 cs serial data a serial data b busy 0 time 5 10 time (seconds) m1 = 1 serial data b in tri-state c h b c h a c h b c h a conversion of chx m1 = 1 and 1 st convst conversion a0 high next conversion ch1 rd connected with convst 12-bit data of chax 12-bit data of chbx m1 = 1 and 1 st convst data of cha m1 = 1 and 2 nd convst data of chb m1 = 1 and 1 st convst data of cha m1 = 1 and 2 nd convst data of chb conversion of chx m1 = 1 and 1 st convst conversion m1 = 1 and 2 nd convst no conversion m1 = 1 and 1 st convst conversion m1 = 1 and 2 nd convst no conversion cs low output active a0 low next conversion ch0 a0 low next conversion ch0 m1 = 1 and 2 nd convst no conversion m1 = 1 and 1 st convst conversion m1 = 1 and 2 nd convst no conversion 16 1 m1 high only serial data a used as output starting with 1 st conversion 1 clock convst a0 rd m0 cs serial data a serial data b busy time 0 1 2 3 4 5 6 time (seconds) 12-bit data of chax 12-bit data of chbx 12-bit data of cha0 12-bit data of chb0 12-bit data of chb1 c h 1 12-bit data of cha1 c h 1 c h 0 c h 0 16 cs low, output is active m0 = 1 a0 ignored 4-ch operation and 1 st conversion ch0 4-ch operation and 2 nd conversion ch1 rd connected with convst m0 = 1, 4-ch operation starts with next conversion
15 ads7861 figure 13. mode iv, timing diagram for m0 = 1 and m1 = 1. clock convst a0 rd m0 cs serial data a serial data b busy 0 time 5 10 time (seconds) m1 = 1 serial data b in tri-state c h b c h 0 c h a c h 1 c h b c h 1 c h a c h 0 conversion of chx m1 = 1 and 1 st convst conversion m0 high 4-ch operation starts, a0 ignored m0 high 4-ch operation starts m0 = 1 and 1 st active convst ch0 m0 = 1 and 2 nd active convst ch1 m1 m1 high only serial data a used as output starting with 1 st conversion rd connected with convst 12-bit data of chax 12-bit data of chbx m1 = 1 and 1 st convst data of cha0 m1 = 1 and 2 nd convst data of chb0 m1 = 1 and 1 st convst data of cha1 m1 = 1 and 2 nd convst data of chb1 conversion of chx m1 = 1 and 1 st convst conversion m1 = 1 and 2 nd convst no conversion m1 = 1 and 1 st convst conversion m1 = 1 and 2 nd convst no conversion cs low output active m1 = 1 and 2 nd convst no conversion m1 = 1 and 1 st convst conversion m1 = 1 and 2 nd convst no conversion 1 16
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