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" for more information + ! " interfacing the am29pl160 to the motorola coldfire tm processor application note publication number 22277 revision a amendment 0 issue date november 1, 1998
publication# 22277 rev: a amendment/ 0 issue date: november 1998 8 -8 interfacing the am29pl160 to the motorola coldfire ? processor application note this application note describes a possible interface be- tween the motorola coldfire? processor and the am29pl160 page mode flash device. the design uti- lizes a wait state generator to assert a ta (transfer ac- knowledge) signal to terminate a bus read cycle. advantages of page mode read operations the am29pl160 page mode device allows for higher performance system operation by reducing the flash random access time from a typical 70 ns to lower than 25 ns for same page reads. by designing a ?smart? in- terface between the processor and flash system, same page reads can benefit from the reduced aggre- gate access times. the am29pl160 has an initial access time of 75 ns (at 100 pf loading), and subsequent accesses within the same page are at 25 ns (a page is defined as a memory region governed by flash address bits a3-a19). thus the initial read would require 1 or more wait states (de- pending on the bus frequency), and sequential access require fewer wait states (again, depending on frequency). knowing the bus frequency of the processor, the re- quired number of wait states for initial and sequential read accesses can be calculated. this document discusses a 33 mhz bus speed inter- face (with conservative timings), as bolded in table 1. table 1. possible bus timings page mode interface overview the page mode controller (labeled pmc in figure 1) consists of a single logic function block which has two functions: first, to compare incoming addresses gov- erning flash read requests, and second, to generate the appropriate number of wait states depending on the type of access (whether or not the access leaves the current page). figure 1. page mode controller system interface the pmc interfaces between the processor and flash device, with address and control signals being watched by the pmc as inputs. the only asserted output of the pmc is the ta signal, which indicates the completion of a read transfer cycle. the mcf5307 processor will hold the state of the bus until the ta signal is asserted, sig- naling the end of the read transfer cycle. page mode controller operation the function of the pmc is broken into two parts: first, it must detect and latch the incoming address pattern in order to determine if a read from flash is occurring within the current page address. since a page as defined as any memory address governed by a3 through a19 (a0 through a2 define a specific word within that page), it can detect a page transition whenever any of the address bits a3 through a19 change on subsequent read cycles. the address comparator sub-circuit of the pmc (see figure 2) accomplishes this detection mechanism. frequency (mhz) period (ns) ideal bus read cycle timings conservative bus read cycle timings (10% margin) 16 62.5 1-0-0-0 1-0-0-0 25 40 2-0-0-0 2-0-0-0 33 30.3 3-0-0-0 3-1-1-1 40 25 3-0-0-0 4-1-1-1 66 15.2 5-2-2-2 6-3-3-3 90 11.1 7-3-3-3 8-3-3-3 ta # r/w# oe# csx rst0# bclk0 a0 a19 a3 a19 ta r/w oe cs reset clk we# oe# ce# reset# pmc am29pl160 mcf5307
interfacing the am29pl160 to the motorola coldfire ? processor 8-9 figure 2. page mode controller block diagram depending on whether or not a page transition is de- tected, the pmc must assert an appropriate number of wait states. given the 3-1-1-1 read timings outlined in table 1, if the pmc detects a page transition, it must assert at least 3 wait states in order to meet the 70 ns initial read access time of the pl160 device. if no tran- sition was detected, it must assert only 1 wait state. the wait state generator sub-circuit of the pmc (see figure 2) performs assertion of wait states. the small block below the address comparator (la- beled iawsgen) is responsible for producing an inter- nal signal named iaws (which stands for arewesure?). this signal is a logical combination of the oe (output enable), rw (read/write), and cs (chip select) signals. the iaws signal is asserted neg- ative whenever the oe and cs signals are low, and the rw signal is high. this signal provides an internal en- abling signal to the other logic functions so that they are only active when the flash device is selected for read- ing. page mode controller vhdl description the entire pmc interface was designed and testing using vhdl, which provides a specification that is eas- ily tested, simulated, and synthesized using software tools. by providing a vhdl representation of this cir- cuit, it can be easily integrated into existing fpga con- trollers or asics. all vhdl code is displayed in fixed font format, with keywords boldfaced. address comparator design the following text shows the vhdl code for the ad- dress comparator block. -- address comparitor for pl interface to coldfire processors -- copyright amd 1998 library ieee; use ieee.std_logic_1164.all; entity addresscomparitor is port ( clk, reset: in std_logic; addin: in std_logic_vector(16 downto 0); diff: out std_logic ); end addresscomparitor; architecture behavioral of addresscomparitor is address comparator a3 a19 clk reset oe rw cs wait state generator idiff iaws ta iawsgen
8-10 interfacing the am29pl160 to the motorola coldfire ? processor -- prevaddress stores the addres incoming on the last -- clock event signal prevaddress: std_logic_vector(16 downto 0); begin addcomp: process (clk, reset, addin) begin if (reset = ?0?) then prevaddress <= "00000000000000000"; -- clear internal regs elsif rising_edge(clk) then if (addin = prevaddress) then diff <= ?1?; -- don?t assert diff if addresses match else diff <= ?0?; end if ; prevaddress <= addin; -- save current address for next time end if ; end process; end behavioral; -- end code the code describing the address comparator is very simple. the comparator accepts 3 incoming signals: a clock, a reset signal, and an incoming address (17 lines). the outgoing (or driven) signal is called diff, which is asserted low whenever the current address does not match the previous address. the prevad- dress signal is used to force a storage element for this entity (so the previous address is saved on the rising edge of each clock). on each incoming clock, the current address and the previous address are compared. if they are the same (meaning that the system is accessing the same page), then the output signal diff is driver high, indicated a page hit. if the addresses differ in any bit, the diff sig- nal is driven low indicating a page miss. note: since the mcf5307 will hold the state of the bus until assertion of the ta signal, it is not required to latch both the current state as well as the previous state of the bus. by only latching one set of addresses, the synthesized circuit is saved over 17 flip-flops. whenever the reset signal is asserted low, the state of the address latch will be cleared to all zeroes. this will force the first flash read cycle to be properly con- strained by the 3 wait state timings. wait state generator design the wait state generator comprises of a simple state machine, and state decoding equations. it features a one-hot encoded design, which provides for a high speed interface in systems which may have high inter- connect latencies by minimizing the complexity of the next-state decoding circuitry. the bubble chart for the state machine design in shown in figure 3. it consists of seven valid states: a waiting state, which is the default state, 4 transition states (to apply the wait states), and 2 assertion states where the ta signal is driven low.
interfacing the am29pl160 to the motorola coldfire ? processor 8-11 figure 3. wait state generator bubble chart from the waiting state, the wait state generator will ei- ther apply one or three wait states, depending on the logic level of the diff input signal. state transitions are overridden by the aws input signal, so that the state machine will only switch states whenever the aws signal is low (this is to prevent the machine from applying wait states while the page mode device is not being accessed by the system). the machine will reset to the waiting state whenever the reset input is as- serted low, or whenever the aws signal is held high. this assures that the state machine is always in the waiting state whenever the flash is accessed on non- sequential bus cycles (to prevent the state machine from applying the wrong number of wait states). the following text show the vhdl representation of the wait state generator. -- wait state generator for pl interface to coldfire processors -- copyright amd 1998 library ieee; use ieee.std_logic_1164.all; entity waitstategenerator is port ( clk, aws, diff, reset: in std_logic; ta: out std_logic); end waitstategenerator; architecture behavioral of wait- stategenerator is -- state machine utilizes one-hot encoding to -- minimize interconnect delays subtype states is std_logic_vector(6 downto 0); constant assertta1: states := "0000001"; waiting ta assertta2 !ta waitstate3 ta waitstate2 ta waitstate1 ta assert ta1 !ta onewait ta reset=?0? aws = ?0? aws = ?0? aws = ?0? aws = ?0? @else @else @else @else diff=?1? and aws=?0? diff=?0? and aws=?0?
8-12 interfacing the am29pl160 to the motorola coldfire ? processor constant assertta2: states := "0000010"; constant onewait: states := "0000100"; constant waiting: states := "0001000"; constant waitstate1: states := "0010000"; constant waitstate2: states := "0100000"; constant waitstate3: states := "1000000"; signal currentstate, nextstate: states; begin -- first, set up sm transition registers streg: process ( clk ) begin if rising_edge(clk) then currentstate <= nextstate; end if ; end process ; -- second, outline state transi- tions sttrans: process (currentstate, aws, diff,reset) begin if (reset = ?0? or reset?event) then nextstate <= waiting; ta <= ?1?; end if ; if currentstate(3) = ?1? then -- waiting ta <= ?1?; if (diff = ?1? and aws = ?0?) then nextstate <= onewait; elsif (diff = ?0? and aws = ?0?) then nextstate <= waitstate1; else nextstate <= waiting; end if ; end if ; if currentstate(2) = ?1? then -- onewait ta <= ?1?; if (aws = ?0?) then nextstate <= assertta1; else nextstate <= waiting; end if ; end if ; if currentstate(0) = ?1? then -- assertta1 ta <= ?0?; nextstate <= waiting; end if ; if currentstate(4) = ?1? then -- waitstate1 ta <= ?1?; if (aws = ?0?) then nextstate <= waitstate2; else nextstate <= waiting; end if ; end if ; if currentstate(5) = ?1? then -- waitstate2 ta <= ?1?; if (aws = ?0?) then nextstate <= waitstate3; else nextstate <= waiting; end if ; end if ; if currentstate(6) = ?1? then -- waitstate3
interfacing the am29pl160 to the motorola coldfire ? processor 8-13 ta <= ?1?; if (aws = ?0?) then nextstate <= assertta2; else nextstate <= waiting; end if ; end if ; if currentstate(1) = ?1? then -- assertta2 ta <= ?0?; nextstate <= waiting; end if ; end process ; end behavioral; -- end code the complete page mode controller all that remains is to instantiate the two main compo- nents of the page mode controller into a single design entity. this entity contains a single wait state genera- tor, a single address comparator, and a simple logic function to produce the internal iaws signal. the following text shows the vhdl code that repre- sents the page mode controller. the vhdl description of the pmc takes a structural form, merely serving to connect the two components with internal signals. it also calculates the iaws signal used to enable the two components. -- page mode controller vhdl code -- copyright amd 1998 library ieee; use ieee.std_logic_1164.all; use work.addresscomparitor; use work.waitstategenerator; entity pagemodecontroller is port ( pmcclk, pmcreset: in std_logic; pmccs, pmcrw, pmcoe: in std_logic; pmcaddin: in std_logic_vector(16 downto 0); pmcta: out std_logic); end pagemodecontroller; architecture structural of pagemo- decontroller is component addresscomparitor port ( clk, reset: in std_logic; addin: in std_logic_vector(16 downto 0); diff: out std_logic); end component ; component waitstategenerator port (clk, aws, diff, reset: in std_logic; ta: out std_logic); end component ; -- local interconnect signals signal iaws, idiff: std_logic; begin -- instantiate our low level entities wsg: waitstategenerator port map ( clk => pmcclk, reset => pmcreset, diff => idiff, aws => iaws, ta => pmcta ); ac: addresscomparitor port map ( clk => pmcclk, reset => pmcreset, diff => idiff, addin => pmcaddin ); pmcfunc: process ( pmcoe, pmcrw, pmccs, pmcclk, pmcreset, pmcaddin) begin
8-14 interfacing the am29pl160 to the motorola coldfire ? processor -- calc the iaws signal based on input control signals iaws <= (pmcoe or pmccs or ( not pmcrw)); end process ; end structural; -- end code simulation of the page mode controller simulation of the pmc was performed using the vss ? tool from synopsys. the input clock frequency was set to 33 mhz, and simulated bus cycles are applied to the pmc to test the ta output signal. the results of the simulation are shown in figure 4. figure 4. simulation results the simulation results in figure 4 show four separate events. the first valid flash access (a valid flash ac- cess is described by the conditions cs low, rw high, oe low, and an address on the address lines) occurs at t1 (120 ns). the ta signal is then asserted 3 wait states (or 3 rising clock edges) after event t1. event t2 (at time 330 ns) shows another flash access of the same page (0x1fbbf). since this access falls within the same page, the ta signal is asserted low after one wait state (or 1 rising clock edge) after event t2. event t3 is the same as event t2, only it occurs at time 480 ns. event t4 shows the next flash access, but this time to a dif- ferent page (0x1fb8f). since this is a page miss, the ta signal is asserted after 3 wait states (or 3 rising clock edges). of important note is the assertion of the reset signal prior to the initial access of the flash device. it is im- portant to assert this signal for at least one clock period prior to the first flash access, to ensure that all flip-flip storage elements are cleared to predetermined states (so that the address comparator latches are cleared to zeroes, and the initial state of the wait state generator is waiting). test bench source code the following text shows the vhdl source for the test bench used to generate the simulation in figure 4. -- test bench for page mode con- troller -- copyright amd 1998 library ieee, std; use std.textio.all; use ieee.std_logic_1164.all;
interfacing the am29pl160 to the motorola coldfire ? processor 8-15 use work.pagemodecontroller; entity testbench is end testbench; architecture test of testbench is -- create a page mode controller component pagemodecontroller port ( pmcclk, pmcreset: in std_logic; pmccs, pmcrw, pmcoe: in std_logic; pmcaddin: in std_logic_vector(16 downto 0); pmcta: out std_logic); end component ; -- local signals signal tclk, treset, tcs, trw, toe: std_logic; signal taddin: std_logic_vector(16 downto 0); signal tta: std_logic; begin -- create instance of low level entity pmc1: pagemodecontroller port map (pmcclk => tclk, pmcreset => treset, pmccs => tcs, pmcoe => toe, pmcrw => trw, pmcta => tta, pmcaddin => taddin); -- first, set up our running 33 mhz clock process begin tclk <= ?0?; wait for 0 ns; while true loop tclk <= ?1?; wait for 15 ns; tclk <= ?0?; wait for 15 ns; end loop ; end process ; -- assert our test stimulus process begin treset <= ?1?; -- assert all false taddin <= "00000000000000000"; toe <= ?1?; tcs <= ?1?; trw <= ?1?; wait for 30 ns; treset <= ?0?; -- assert reset for 1 clock wait for 30 ns; -- to clear comparitor treset <= ?1?; -- turn off reset wait for 60 ns; -- we can now apply bus stimu- lus, using this definition: -- a valid read cycle occurs when: -- 1) oe is low -- 2) rw is high -- 3) ce is low -- 4) valid address on bus -- on each read, we will wait for the ta signal to be -- asserted tcs <= ?0?; toe <= ?0?; trw <= ?1?; taddin <= "11111101110111111"; wait until (tta = ?0?); -- this should be a 3ws read wait for 30 ns; tcs <= ?1?; toe <= ?1?; trw <= ?1?; taddin <= "11111101110111111"; wait for 60 ns; -- read opera- tion not to flash tcs <= ?0?; toe <= ?0?; trw <= ?1?; taddin <= "11111101110111111"; wait until (tta = ?0?); -- read same address - should be 1ws
8-16 interfacing the am29pl160 to the motorola coldfire ? processor wait for 30 ns; tcs <= ?1?; toe <= ?1?; trw <= ?0?; wait for 60 ns; tcs <= ?0?; toe <= ?0?; trw <= ?1?; taddin <= "11111101110111111"; wait until (tta = ?0?); -- read same address - should be 1ws wait for 30 ns; tcs <= ?1?; toe <= ?1?; trw <= ?0?; wait for 60 ns; tcs <= ?0?; toe <= ?0?; trw <= ?1?; taddin <= "11111101110001111"; wait until (tta = ?0?); -- read diff address - should be 3ws wait for 30 ns; wait for 300 ns; wait for 1 ns; wait ; end process ; end test; -- end code other considerations the vhdl representation of the page mode controller can be considered an ideal system. system margin, in- terconnect latency, and internal signal/gate delays are not considered due to the wide variation in synthesis techniques. for a more accurate simulation, vhdl after statements can be added to next state and signal assignments for a more accurate circuit simulation. for example, the statement: iaws <= (pmcoe or pmccs or ( not pmcrw)); could be replaced by: iaws <= (pmcoe or pmccs or ( not pmcrw)) after 2 ns; this would more accurately simulate a typical gate delay in a fpga or asic implementation. appropriate values can be substituted depending on the implemen- tation method used by the system designer.
interfacing the am29pl160 to the motorola coldfire ? processor 8-17

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