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W93902 pocsag decoder for pagers publication release date: october 1997 - 1 - revision a3 general description the W93902 is a very-low-power decoder for pagers that is fully compatible with ccir radio paging code number 1 (pocsag code) operating at 512, 1200, or 2400 bps using a single 76.8 khz crystal. to enhance the sensitivity of the pager system, a digital filter and digital pll have been incorporated to remove the noise factor generated by the rf part and lock the signal phase. to reduce the rf turn-on time and minimize power consumption, an advanced synchronization algorithm (1/18 turn on-time, as opposed to 1/17 or 1/16) is used to provide synchronization. synchronization skip mode is also available for power reduction. for convenient pager programming, the decoder provides fully software-programmable options and a simple cpu control format (data output packaged as 4/7/8 bits or not packaged). also included are independent buzzer and led frequency control outputs and a reference clock (32768 hz, 64 hz, 16 hz, 1/60 hz) that can be output or disabled. the decoder supports four independent user addresses, which can be assigned to different frames. features data rate of 512, 1200, or 2400 bps 32768 hz or 76800 hz crystal embedded digital filter and digital pll real two-random-bit error correction or one-bit error correction ability, plus four-bit burst error correction can be selected 1/18 rf enable time (more efficent than 1/17 or 1/16) four real independent user address in different frames 25% to 75% duty cycle data capability in receive mode 2.7/3.2/2/4 khz frequency output controlled by two pins, fbuz1 and fbuz2 6-bit/8-bit preamble acknowledge selection four preamble search delay time settings selection of from 1 to 15 sync search retry attempts multi-frequency output for led or other usage inversion or non-inversion nrzin signal and bs1/bs2/bs3 selection 4/7/8 bits package per byte output selection for receiving messages independent power-saving control pin allows device to enter or exit reception mode at any time 16 selections for rf and pll stable time five selections for out-of-range indication two selections for end-of-message condition embedded power-on reset circuit four rxclk rate selection 2.5 to 5v operating voltage range packaged in small size 24-pin ssop
W93902 - 2 - pin configuration 1 3 2 4 5 6 7 8 9 11 12 10 24 22 23 21 20 19 18 17 16 14 13 15 osc1 osc2 v bs1 bs2 bs3 fbuz1 nrzin txclk txdata on fbuz2/btlin v falm fout2 ai efout2 fout1 synval rxclk rxdata adddt xreset btldt dd ss pin description pin symbol i/o description 1 osc1 input crystal oscillator input (32768 hz or 76.8 khz) 2 osc2 output crystal oscillator output 3 v ss power ground 4 bs1 output rf control pin 5 bs2 output rf quick charge pin 6 bs3 output pll control pin 7 fbuz1 input buzzer frequency select pin 1 (with internal pull-up) 8 nrzin input nrz signal input (inversion or non-inversion) 9 txclk input address data and option data strobe clock 10 txdata input address data and option data input 11 on input receive mode enable pin 12 fbuz2/btlin input buzzer frequency select pin 2 (with internal pull-up resistor) 13 btldt output battery low detect indicator output 14 xreset input chip reset pin (internal pull-up resistor, low reset) 15 adddt output address received detector output (normal high)
W93902 publication release date: october 1997 - 3 - revision a3 pin description, continued pin symbol i/o description 16 rxdata output received data output pin 17 rxclk output received data output strobe clock 18 synval output sync word detector output (out-of-range indicator output) 19 fout1 output clock output (32768 hz, 64 hz,16 hz,1/60 hz or disable) 20 efout2 input multi-frequency output enable pin (internal pull-down resistor) 21 ai input falm buzzer output enable pin (internal pull-down resistor) 22 fout2 output multi-frequency output 23 falm output 2.7 khz, 3.2 khz, 2 khz, 4 khz, buzzer output (normal high) 24 v dd power power supply input (2.5 to 5v) block diagram digital noise filter digital pll data register timing generator m e m o r y data compare error correction oscillator power-on reset cpu interface nrzin bs1 bs2 bs3 on txdata fbuz1 fbuz2 efout2 ai xreset rxdata rxclk adddt synval fout2 fout1 falm o s c 1 o s c 2 v s s btldt txclk v d d
W93902 - 4 - functional description operation flow chart power on txclk wait mode on = high 128 txclk reset mode off mode board test mode y n reset sync catch mode 1 to 15 times idle mode lock mode n l o s t s y n c c a t c h s y n c y switch off y n catch sync r e s e t txclk wait mode after the power-on stage or the xreset pin goes from low to high, the W93902 enters txclk wait mode. in this mode, the cpu should send 128 clock inputs to the txclk pin and address and options data to the txdata pin. after 128 clocks are sent, the chip is programmed and enters the mode determined by the on pin. if more than 128 strobe clocks are sent to txclk, the chip ignores the extra clocks. the programming timing is shown in figure 1, and programming data are shown in table 1 to table 30. data are latched at the rising edge of the strobe clock.
W93902 publication release date: october 1997 - 5 - revision a3 xreset total 128 clocks txclk at least 2 ms at least 2 ms txdata d0 d1 d2 d3 d4 d5 d123 d124 d125 d126 d127 figure 1. programming timing off mode after the W93902 has received 128 txclks it will enter sync catch mode, if the on pin is high, or off mode, if the on pin is low. when the chip is in off mode, all output pins are inactive except for the fout pin. thus in off mode the chip provides only a timer reference clock function. the chip can be switched on or off at any time by setting the on pin to high or low, respectively. sync catch mode in sync catch mode, the W93902 uses special timing to detect the synchronization codeword. first, when the on pin goes from low to high, bs1 and bs3 remain high for up to four batches (4.5 sec for 512 bps and 1.92 sec for 1200 bps) to search for the preamble codeword or synchronization codeword. the detailed timing is shown below. xreset txclk at least 2 ms at least 2 ms total 128 clocks on bs1 4 batches bs3 bs2 figure 2 note: the bs1 is to control the rf power, the bs2 is to discharge, and the bs3 is used to control the pll power.
W93902 - 6 - if no preamble or synchronization codeword is detected during the first four batches, the chip enters the second stage, in which 1/3 turn-on time is used every 576 bits (one batch) to detect synchronization or preamble for 1 to 15 batches, depending on the setting of td1 to td3. if a synchronization codeword is matched during these two stages, the chip enters lock mode. if no codeword is matched, the chip enters idle mode. on bs1 bs2 bs3 total 1 to 15 times 4 batches 576 bits t bs2 t bs3 192 bits figure 3 idle mode in sync catch mode the chip attempts to achieve synchronization in a short period of time, but the rf power consumption in this mode is quite high. consequently if there is no meaningful signal input, the chip enters idle mode to reduce the power consumption. if a preamble or synchronization codeword is present, however, it can still be detected by using 1/18 rf turn-on time (t on = 32 bits duration time). on bs1 bs2 bs3 t bs3 t bs2 576 bits 32 bits t on figure 4
W93902 publication release date: october 1997 - 7 - revision a3 lock mode if a synchronization codeword is detected in sync catch mode or in idle mode, then the chip enters lock mode. while in the lock mode the chip will check the addresses assigned in txclk wait mode. if a matching address codeword appears, an adddt low signal will be generated and the message will be received. the message will then be sent from the rxdata pin and the data strobe clock will be generated from rxclk pin. the format used to send data from the rxdata pin depends on the options convl and conv2. the data consist of an output address word followed by the message words and then terminated by a termination word. the format is depicted below. while in the lock mode, if the synchronization word is lost for a period of time, predefined by the option outr1, outr2, and eoutr, the chip will return to sync catch mode. on bs1 bs2 bs3 t bs3 t bs2 32 bits no address detected 512 bits continue to receive message t bs3 adddt address detected pint = 1 address detected pint = 0 adddt adddt rxdata address word message word termination word rxclk (43 ms for 512 bps,18.3 ms for 1200 bps) 22 data bits pint = 0 figure 5
W93902 - 8 - reset mode pulling the xreset pin low for more than 2 ms places the W93902 in reset mode, which causes all configurations to be cleared. to release the configuration mode, let the xreset pin return to high for 2 ms. the W93902 will then automatically enter txclk wait mode, and so another 128 txclk are needed. if the xreset pin is low for more than 2 ms and the on pin is high, the chip enters board test mode. board test mode to place the W93902 in board test mode, set the on pin high in reset mode. in board test mode bs1 and bs3 remain high until the on pin returns to low. when the xreset pin returns to high, the W93902 exits both board test mode and reset mode. board test mode is usually used for the rf adjust function. when in board test mode, the nrzin signal will output to falm pin, so that we can trim the rf trimmer by buzzer frequency. address & option list clock data clock data clock data clock data d0 nbs1 d32 nbs2 d64 nbs3 d96 eoutr d1 prectl d33 efout1 d65 td3 d97 ert0 d2 rate0 d34 rate1 d66 ertr d98 ert1 d3 ada17 d35 adb17 d67 adc17 d99 add17 d4 ada16 d36 adb16 d68 adc16 d100 add16 d5 ada15 d37 adb15 d69 adc15 d101 add15 d6 ada14 d38 adb14 d70 adc14 d102 add14 d7 ada13 d39 adb13 d71 adc13 d103 add13 d8 ada12 d40 adb12 d72 adc12 d104 add12 d9 ada11 d41 adb11 d73 adc11 d105 add11 d10 ada10 d42 adb10 d74 adc10 d106 add10 d11 ada9 d43 adb9 d75 adc9 d107 add9 d12 ada8 d44 adb8 d76 adc8 d108 add8 d13 ada7 d45 adb7 d77 adc7 d109 add7 d14 ada6 d46 adb6 d78 adc6 d110 add6 d15 ada5 d47 adb5 d79 adc5 d111 add5 d16 ada4 d48 adb4 d80 adc4 d112 add4 d17 ada3 d49 adb3 d81 adc3 d113 add3 d18 ada2 d50 adb2 d82 adc2 d114 add2 d19 ada1 d51 adb1 d83 adc1 d115 add1 d20 ada0 d52 adb0 d84 adc0 d116 add0 d21 fa3 d53 fb3 d85 fc3 d117 fd3 d22 fa2 d54 fb2 d86 fc2 d118 fd2
W93902 publication release date: october 1997 - 9 - revision a3 address & option list, continud clock data clock data clock data clock data d23 fa1 d55 fb1 d87 fc1 d119 fd1 d24 freq0 d56 ena d88 pl1 d120 conv1 d25 baud0 d57 enb d89 pl2 d121 conv2 d26 inv d58 enc d90 pl3 d122 outr1 d27 ebtl d59 end d91 pl4 d123 outr2 d28 over d60 shmt d92 msgone d124 sf10 d29 epre0 d61 pkgsel d93 td1 d125 sf11 d30 epre1 d62 baud1 d94 td2 d126 sf20 d31 nopkg d63 extadd d95 pint d127 sf21 table 1 option list function option crystal baud rate freq0 baud0 baud1 76.8k 512 bps 1 0 0 76.8k 1200 bps 1 1 0 76.8k 2400 bps 1 x 1 32k 512 bps 0 x x table 2 function option address a, b, c, d ena, enb, enc, end disable 0 enable 1 table 3 function option nrz signal inv non-inversion 0 inversion 1 table 4
W93902 - 10 - function option nrz signal/rf cycle shmt ertr with schmitt trigger, rf 1/18 turn-on 1 0 without schmitt trigger, rf 1/18 turn-on cycle 0 x without schmitt trigger, rf 1/9 turn-on 1 1 table 5 function option message reception termination condition over reception termination on first uncorrectable codeword 0 reception termination on two uncorrectable codeword 1 table 6 function option t bs2 pl2 pl1 512 bps 1200/2400 bps 3.90 ms 1.67 ms 0 0 11.71 ms 5.00 ms 0 1 19.53 ms 8.33 ms 1 0 27.34 ms 11.67 ms 1 1 table 7 note: pll pre-on time =t bs2 + t bs3 , rf pre-on time = t bs2 function option t bs3 pl4 pl3 512 bps 1200/2400 bps 0.00 ms 0.00 ms 0 0 31.25 ms 13.33 ms 0 1 62.50 ms 26.67 ms 1 0 93.75 ms 40.00 ms 1 1 table 8
W93902 publication release date: october 1997 - 11 - revision a3 option list nbs1/nbs2/nbs3 setting when nbs1 = 0, nbs2 = 0, and nbs3 = 0, the timing is as follows: bs1 bs2 bs3 t bs3 t bs2 32 bits t bs2 figure 6 when nbs1 = 1, nbs2 = 1, and nbs3 = 1, the timing is as follows: bs1 bs3 bs2 t bs3 + t bs2 32 bits figure 7 if the bs1 pin is used to turn rf on, then the pre-on time for rf is equal to t bs2 (max.11.67 ms). if the bs3 pin is used to turn rf on, then the pre-on time will be equal to t bs2 ?? t bs3 (max.51.67 ms). the bs3 pin can also be used to turn on the pll circuit. function option sync retry times td1 td2 td3 1 0 0 1 3 1 0 1 5 0 1 1 7 1 1 1 9 0 0 0 11 1 0 0 13 0 1 0 15 1 1 0 table 9
W93902 - 12 - function option out-of-range hold time when synchronization is lost outr1 outr2 eoutr 512 bps 1200/2400 bps 36 sec 31 sec 0 0 0 72 sec 61 sec 0 1 0 144 sec 123 sec 1 0 0 288 sec 246 sec 1 1 0 0 sec 0 sec x x 1 table 10 function option preamble recognization prectl 8 bit 0 6 bit 1 table 11 function option preamble search delay epre1 epre0 512 bit 0 0 896 bit 0 1 1024 bit 1 0 1792 bit 1 1 table 12 error correction method option list : function option correction method ert1 ert0 two-bit random 0 0 four-bit burst + two-bit random 0 1 four-bit burst 1 0 one bit 1 1 table 13 note: when option msgone = 0, the error correction methods of address and message all follow the above setting, if msgone = 1, the error correction method follows the setting when receiving the address word. the message receiving method is always one-bit error correction, however.
W93902 publication release date: october 1997 - 13 - revision a3 error message, for one-bit random, two-bit random, or four-bit burst error correction method: one-bit/two-bit random/4-bit burst error correction method before after parity 4-bit package and ertr = 1 7/8-bit package correction correction error er0 er1 er2 er3 error flag no error - no error 0 0 1 0 0 no error - error 1 0 1 0 0 error no error no error 0 1 1 0 0 error no error error 1 1 1 0 1 error error no error 0 1 1 1 1 error error error 1 1 1 1 1 table 14 notes: 1. when ertr = 0, in the 4-bit package er0 = 0, er1 = 1, er2 = 1, er3 = error flag. 2. if 3-bit random errors (or more than three) are detected or five (or more) burst errors are detected, no error correction method will be activated and er0 to er3 will be set or the error flag will be set directly. error message, for two-bit random plus four-bit burst error correction method two-bit random with 4-bit burst error correction method detect random detect burst parity error random/ burst 4-bit package and ertr = 1 7/8-bit package before correction after correction before correction after correction correct result er0 er1 er2 er3 error flag no error - no error - no error original 0 0 0 0 0 no error - no error - error original 1 0 0 0 0 error no error error no error no error burst 0 1 0 0 0 error no error error no error error burst 1 1 0 0 1 error error error error no error random 0 1 1 1 1 error error error error error random 1 1 1 1 1 error error error no error no error burst 0 1 0 1 1 error error error no error error burst 1 1 0 1 1 error no error error error no error random 0 1 1 0 1 error no error error error error random 1 1 1 0 1 table 15 notes: 1. when ertr = 0, in the 4-bit package er0 = 0, er1 = 1, er2 = 1, er3 = error flag. 2. if 3-bit random errors (or more than three) are detected or five (or more) burst errors are detected, no error correction method will be activated and the display mode will be set as mode f.
W93902 - 14 - note: when ertr = 0, in the 4-bit package er0 = 0, er1 = 1, er2 = 1, er3 = error flag. *generally, er0 represents the parity error and er1 represents the error condition before correction. er2 represents the burst error correction result and er3 represents the random error correction result. data transfer timing while the chip detects the proper address in the lock mode, the chip will send the message to the uc from rxdata pin as shown in figure 5. the detailed timing is depicted below. rxdata address word first message word a0 a1 a2 a3 a4 a5 a6 a7 rxclk (416 s to 26 s for 1200 bps) (7.5 ms to 3.3 ms) t rxc1 t rxc2 rxdata m0 m1 m2 m3 m4 m5 rxclk m6 m7 ?] 6.7 ms to 630 s) message word n-1 message word n message word n+1 t rxc3 rxdata t0 t1 t2 rxclk t3 t4 t5 t6 t7 last message word termination word m m m figure 8 note: the timing of trxc1, trxc2, and trxc3 depends on the setting of ratel and rate0.
W93902 publication release date: october 1997 - 15 - revision a3 rxclk and rxdata transmission rate option list: function option rxclk rate (t rxc1 ) rate1 rate0 2* data rate 0 0 8* data rate 0 1 16* data rate 1 0 32* data rate 1 1 table 16 address word format function code call address check bits error bit bit 0 bit 1 bit 2 bit 3 address bit 4 bit 5 bit 6 bit 7 bit 21 of bit 20 of 0 0 a address address 0 1 b ra0 ra1 ra2 0 word word 1 0 c 1 1 d table 17 notes: 1. if ertr = 1, then ra0 indicates a parity error, ra1 indicates the error condition before correction, and ra2 indicates whether the address has been corrected. for example, if (ra0, ra1, ra2) = (0, 1, 0), then the codeword has no parity error, there is an error before error correction, but no error is found after correction. 2. the error bit for address code is set when this code matches the address assigned in the setting but is not correctable. function option package method nopkg with package(4 / 7 / 8 bit format) 0 without package 1 table 18 note: when nopkg = 1, 24 bits will be transferred to the cpu from the decoder and divided into three groups of eight bits. when nopkg = 0, five groups of eight bits are transferred. message word format, nopkg = 0 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 package message bits error flag (note) 7/8 bit message bits er0 er1 er2 er3 4 bit table 19 note: error flag = 1 indicates that an error condition has occurred.
W93902 - 16 - message word format, nopkg = 1 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 m0 m1 m2 m3 m4 m5 m6 m7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 m8 m9 m10 m11 m12 m13 m14 m15 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 m16 m17 m18 m19 er0 er1 er2 er3 table 20 termination word format bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 0 0 1 0 0 0 0 error flag table 21 note: if the alphanumeric format option is selected, then the termination words will be seven bits of zeros with error flag followed by the upper termination word. that is, when this option is selected, the ascii format "04" (eot) will be se nt. function option adddt polarity pint active low 0 active high 1 table 22 adddt rxdata address word message word termination word rxclk address word note 1 note 2 pint = 0 figure 9 note: when ertr = 0, the adddt pin will remain low while addresses continue to be detected. when ertr = 1, a high low pulse will be generated and addresses will continue to be received. if nopkg = 1, a termination word will not be generated.
W93902 publication release date: october 1997 - 17 - revision a3 data format options the W93902 automatically converts message codewords received in numeric or alphanumeric format into ascii format. depending on the setting of conv1, conv2, pkgsel, and the function bits in the received address codeword, conversion takes place as shown in table 23. when a conversion from alphanumeric format to ascii takes place, the received message codewords are split into message blocks seven bits in length. after the error flag is added, the message blocks are transferred as message words. in this option, one message word may exceed two codewords in length. when a conversion from numeric format to ascii takes place, the received message codewords are split into blocks four bits in length, as shown in table 24. after the error flag is added, the blocks are transferred as message words. when a conversion from numeric format to 4-bit package takes place, the received message codewords are spilt into blocks four bits in length, as shown in table 25. after the error status bits er0 to er3 are added, the blocks are transferred as message words. when no conversion takes place, the received message codewords are spilt into blocks eight bits in length. the last four bits are combined with the error status bits er0 to er3, and then the blocks are transferred as message words. data format options pkgsel = 0 data format option txdata output data format conv1 conv2 numeric 4-bit format 0 0 numeric 8-bit format 0 1 alphanumeric 7-bit format 1 0 numeric/alphanumeric format depends on function bits 1 1 conv1 = 1, conv2 = 1, pkgsel = 0 data format function bit txdata output data format bit 21 bit 20 numeric 8-bit format 0 0 alphanumeric 7-bit format 0 1 alphanumeric 7-bit format 1 0 alphanumeric 7-bit format 1 1
W93902 - 18 - pkgsel = 1 data format option txdata output data format conv1 conv2 numeric 8-bit format 0 0 alphanumeric 7-bit format 0 1 alphanumeric 7-bit format 1 0 alphanumeric 7-bit format 1 1 table 23 numeric 8-bit format input data character output data bit0 bit1 bit2 bit3 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 0 0 0 0 "0" 0 0 0 0 1 1 0 error flag 1 0 0 0 "1" 1 0 0 0 1 1 0 " 0 1 0 0 "2" 0 1 0 0 1 1 0 " 1 1 0 0 "3" 1 1 0 0 1 1 0 " 0 0 1 0 "4" 0 0 1 0 1 1 0 " 1 0 1 0 "5" 1 0 1 0 1 1 0 " 0 1 1 0 "6" 0 1 1 0 1 1 0 " 1 1 1 0 "7" 1 1 1 0 1 1 0 " 0 0 0 1 "8" 0 0 0 1 1 1 0 " 1 0 0 1 "9" 1 0 0 1 1 1 0 " 0 1 0 1 "*" 0 1 0 1 0 1 0 " 1 1 0 1 "u" 1 0 1 0 1 0 1 " 0 0 1 1 " " 0 0 0 0 0 1 0 " 1 0 1 1 "-" 1 0 1 1 0 1 0 " 0 1 1 1 " ?j " 1 0 1 1 1 0 1 " 1 1 1 1 " ?i " 1 1 0 1 1 0 1 " table 24
W93902 publication release date: october 1997 - 19 - revision a3 numeric 4-bit format input data character output data bit0 bit1 bit2 bit3 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 0 0 0 0 "0" 0 0 0 0 0 1 1 error flag 1 0 0 0 "1" 1 0 0 0 0 1 1 " 0 1 0 0 "2" 0 1 0 0 0 1 1 " 1 1 0 0 "3" 1 1 0 0 0 1 1 " 0 0 1 0 "4" 0 0 1 0 0 1 1 " 1 0 1 0 "5" 1 0 1 0 0 1 1 " 0 1 1 0 "6" 0 1 1 0 0 1 1 " 1 1 1 0 "7" 1 1 1 0 0 1 1 " 0 0 0 1 "8" 0 0 0 1 0 1 1 " 1 0 0 1 "9" 1 0 0 1 0 1 1 " 0 1 0 1 "*" 0 1 0 1 0 1 1 " 1 1 0 1 "u" 1 1 0 1 0 1 1 " 0 0 1 1 " " 0 0 1 1 0 1 1 " 1 0 1 1 "-" 1 0 1 1 0 1 1 " 0 1 1 1 " ?j " 0 1 1 1 0 1 1 " 1 1 1 1 " ?i " 1 1 1 1 0 1 1 " table 25 note: when ertr = 1, then bit4 = er0, bit5 = er1, bit6 = er2, and bit7 = er3. frequency output option list: function option fout1 output efout1 output enable 0 output disable 1 table 26 note: if fout1 is not used, the option efout1 should be set to 1. function option fout1 output sf11 sf10 32768 hz 0 0 64 hz 0 1 16 hz 1 0 1/60 hz 1 1 table 27
W93902 - 20 - fout2 will output frequency when efout2 is high: function option fout2 output sf21 sf20 16 khz(32768hz crystal)/19 khz (76800hz) 0 0 64 hz 0 1 16 hz 1 0 1/60 hz 1 1 table 28 note: when fout1 and fout2 are assigned the same frequency, they will have a different phase. buzzer output operation (fbuz1 and fbuz2 normally pulled high): function pin falm output fbuz2 fbuz1 2 khz low low 4 khz low high 3.2 khz high low 2.7 khz high high table 29 notes: 1.the frequency of flam output is controled by the voltage of fbuz1 and fbuz2 pin. 2. fbuz2 is active only when ebtl = 1. if use the battery low detection function (ebtl = 0), the fbuz2 is internally pull high and falm can only output 2.7 khz or 3.2 khz. battery low detection circuit enable options: function option fbuz2/btlin ebtl btlin 0 fbuz2 1 table 30 the battery low detect function samples the btlin pin (when ebtl = 0) each time bs1 is active. if the level of this pin is detected to be high four times in a row, then a high signal will be output through the btldt pin, until the btlin pin is detected to be low four times in a row. buzzer, led, and timer reference clock output the W93902 provides an ai pin to enable the falm pin output and frequency selection through the fbuz1 and fbuz2 pins, as shown in table 29. when ai is low, falm is at high impedance. when ai is high, falm outputs the specified frequency with an n-channel open drain mos architecture. falm should be connected to an external pull-up resistor in normal usage, so that the power consumption can be controlled when the buzzer is active.
W93902 publication release date: october 1997 - 21 - revision a3 fout2 output control is similar, but the output stage is slightly different. when efout2 is high, the fout2 output clock is selected by the sf20 and sf21 bits, as shown in table 28. when efout2 is low, fout2 provides a high-level dc output. its output stage is a complementary cmos output. it is not necessary to connect a pull-up resistor. the W93902 also supports a 32768 hz real-time clock reference output, which is active after the txclk wait mode. when this clock output is not needed, the efout1 bit should be set to 1. fout1 and fout2 also provide a complementary clock output of 64 hz, 16 hz, or 1/60 hz for use as a reference timer. option extadd is used for proprietary algorithm. for normal operation, extadd should be set to 0. dc characteristics sym. parameter conditions min. typ max. unit supply v dd supply voltage 2.5 3.0 5.0 v i ss supply current v dd = 3 osc = 32 khz 20 40 m a v dd = 3 osc = 76.8 khz 25 45 m a input v ih high-level input voltage nrzin, txclk, txdata, on, xreset, efout2, ai, fbuz1, fbuz2 0.8 v dd v il low-level input voltage nrzin, txclk, txdata, on, xreset, efout2, ai, fbuz1, fbuz2 0.2 v dd i il low-level input current xreset, fbuz1, fbuz2 v dd = 3v, v in = 0v 10.0 m a i ih high-level input current. ai, efout2 v dd = 3v, v in = 3v 10.0 m a i ol low-level output current bs1, bs2, bs3, adddt, rxdata, rxclk, synvzl, fout1, fout2 v dd = 2.7v, v out = 1.35v 7.34 ma i ol low-level sink current. falm v dd = 2.7v, v out = 1.35v 14.68 ma i oh high-level output current bs1, bs2, bs3, adddt rxdata, rxclk synval, fout1, fout2 v dd = 2.7v, v out = 1.35v 3.52 ma
W93902 - 22 - typical application circuit vdd w921f840 (with flash eprom) vss vdd fout2 falm txdata txclk xreset adddt rxdata rxclk synval fout1 ai on fbuz1 W93902 vss osc1 osc2 nrzin bs1 bs2 bs3 vdd receiver vss vss 15p 15p 32768 hz or 76800 hz rf antenna lcd switch m dc/dc 1.5v 3.0v switch for 32 khz crystal rf = 20 m ohm for 76 khz crystal rf = 10 m ohm btldt efout2 fbuz2 btlin 1.5v headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792697 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-7197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice.

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