complete chip set for adsl modem functions compliance with ansi t1.413 issue 1 & issue 2 implements discrete multitone (dmt) modulation and demodulation data rates up to 8mbps downstream and to 1mbps upstream with 32kbps granularity built-in atm transport support adaptive rate mode in 32mbps increments applicable at both ends of loop: atu-c (lt) and atu-r (nt) 255 carriers with 4.3125khz spacing dedicated software driver avail- able processor independent c++ source compilation frequency division multiplexing (fdm) for high robustness in pres- ence of crosstalk reed-solomon forward error cor- rection trellis coder and decoder programmable simultaneous sup- port of interleaved and non-inter- leaved channels (dual latency) full, reduced and minimal atm over- head framing modes bit stream mode capablity for stm transport direct connection to atm systems via utopia interface (level 1 or 2) microcontroller interface with 16 bits multiplexed address/data bus low power technology: 1.3w total single 3.3v power supply -40 to +85 c operating temp range applications high speed internet access remote access to corporate net- work for telecommuters and branch offices video-on-demand over twisted pair adsl modems, dslams, routers, and concentrators adsl pc nic's lite-adsl t1.413 based for nt-side splitterless applications general description the adsl modem chip set with atm interface provides all the active functions required to build a complete atm-based adsl modem from line interface to atm utopia bus. the chip set em- ploys discrete multitone modulation as specified in ansi t1.413. the chip set can operate at either end of the loop (in atu-c or atu-r mode) with only changes in the microcontroller code. reed-solomon forward error correction plus trel- lis coding with or without interleaving in internal interleaving ram provides maximum noise immu- nity. this is preliminary information on a new product now in development. details are subject to change without notice. november 1998 ? ordering numbers: stlc60134 (tqfp64) stlc60135 (pqfp144) stlc60134 stlc60135 adsl modem chip set product preview tqfp64 pqfp144 dmt modem stlc60135 utopia m control mem afe utp stlc60134 d98tl390 figure 1. adsl modem block configuration. 1/7
interleaving is optional and can be used simulta- neously on a slow channel (e.g., for data or con- trol info) while a fast channel (e.g., video) oper- ates without interleaving. ics include rate adaptation capabilities during show time. in transmit direction the chip set allows to select an attenuation of the signal in case of short loops or large echo (politeness). in receive direction the chip set can optionally control an external multi- plexer to select an external attenuation of the sig- nal in case of short loops. TOSCA chip set TOSCA is a two-chip adsl modem transceiver. st also provides the necessary software for transceiver's external controller. TOSCA can easily be hooked up with atm sys- tems through the built-in utopia level 2 inter- face. that allows atm traffic to be carried, at up to 8mbit/s downstream and 1mbit/s upstream, over a very plain and widespread twisted pair. TOSCA can be used at both ends of the loop (atu-c and atu-r ends). the modem control software can be compiled as c++ code, independentlyon the processor used. the driver can be interfaced to any external real time operating system. these pages block diagrams show the main func- tions built-in in stlc60134 and stlc60135. TOSCA chip set supports three different rate ad- aptation modes: fixed rate adaptation mode, fixed with capability to boost within fixed range, dy- namic rate adaptationduring show time. modem's performances are set by the following parameters: rate adaptation mode, downstream and upstream bit rate for both latency paths, noise margins (min, max and target typically at 10e-7 ber without rs, interleaving and trellis), maximum power spectral density for downstream, maximum power for both up and downstream, carrier mask (which tones are disabled), maxi- mum interleaving delay. tones from number 8 to number 255 can be used: from 8 to 31 for upsteam signals and from 32 to 255 for downstream signals. numbers 16 and 64 are dedicated to pilot tones which are employed for synchronisation purposes between atu-c and atu-r ends. the software sets the use of tones for optimisation of performances. at atu-r, time recovery is carried out by the chip-set through the pilot tones. this activity is undertaken in two steps in order to achieve no more than 2ppm between atu-c and atu-r. the transceiver controller software monitors line and channel. as far as line is concerned noise margin, attenuation, power, carrier load, relative capacity occupation are checked. channel's monitoring deals with cell-delineation, actual atm (fast and interleaved) up and downstream rates, achievable atm ds and us rates (only at atu-c side). TOSCA ics TOSCA consists of an analog front end (stlc60134) and a discrete multitone modem (stlc60135) integrated circuits which are pro- duced by stmicroelectronics. here below we will briefly go through the main topics of both the ics. dac mux 4 12 bits/8.8mhz dac mux 4 12 bits/8.8mhz adc mux 4 12 bits/8.8mhz transmit-side lpf 1.1mhz lpf 138khz lpf 1.1mhz lpf 138khz atu-r atu-r atu-c atu-c lpf 138khz lpf 1.1mhz atu-r atu-c vcodac xtal driver g=15...0db step 1db g=15...0db step 1db 35.328mhz g=0...31db step 1db d98tl391 agc agc lna receive-side figure 2. analog front end block diagram. TOSCA stlc60134/stlc60135 2/7
analog front end (stlc60134) hcmos5a (0.5 m m) mixed digital and analog technology has been chosen to produce this component that embodies the analog functions of the TOSCA. automatic gain control amplifiers, placed at the analog functions of the TOSCA. automatic gain control amplifiers, placed at the analog interface of transmit and receive paths, al- low for line's high attenuation in order to keep ac- ceptable noise level of the signal adc's and dac's resolution, that is 12-bit wide with 8.8mhz sampling rate. thanks to the symmetrical archi- tecture the same channel filter can be used as a part of either the upstream or the downstream path: atu-c or atu-r end. a built-in driver allows for single external clock generation using a xtal (atu-c) or a vcxo (atu-r). stlc60134 analog front end's main features: rx automatic gain control: 0-31db in 1db steps two input ports allow selection of rx signals, e.g. with or without external attenuation second transmit port available (i.e. echo can- cellation) programmable low pass and band pass filters 12-bit dac and adc, sampling at 8.832mhz xtal: 35.328mhz, 50ppm, the accuracy of the frequency is determined by the external xtal direct connection to stlc60135 dtm modem error correction on adc output test interface for digital and analog sections analog and digital loop back modes single 3.3v supply, or 3.3v analog and 3.0v digital supplies power dissipation 0.4w power-down mode 0.1w tqfp-64 (10 x 10mm body, 0.5mm pitch) discrete multitone digital modem (stlc60135) the dmt modem has been developed in hcmos6 (0.35 m m) technology. it performs pmd (physycal medium dependant) sub-layer and tc (transmission convergence) sub-layer functions. in other words we can think to split up the chip into two separate blocks: the first one which carries out modem functions (pmd sub layer) and a second one in charge of atm framing. the chip is controlled and programmed by an ex- ternal processor and is seen as a memory mapped device. modem functions the modem part of the chip includes all the nec- essary blocks needed for digitally dmt mapping and demapping. a 14-bit code for every carrier al- lows constellations with up to 16383 points. internally digital filters carry out time equalization to reduce the effects of the inter symbol inter- faces. that is followed by fast fourier transform (in transmit direction an inverse fft is per- formed) in order to change from time domain to frequency domain. afterwards a frequency equalization cuts down carrier by carrier the channel distortion; signal's amplitude attenuation and phase rotation. by efficient algorithms, this rx dsp fe tc sublayer cell based funct. adsl afe rx interf. d98tl406 tx dsp fe fft demapper viterbi r/s decoder de- framer atm (utopia) ifft mapper viterbi signal monitoring & feq update & dpll pmd sublayer r/s coder framer cell based funct. tx interf. interleaved fast fast interleaved figure 3. dmt modem block diagram. TOSCA stlc60134/stlc60135 3/7
block drives, through the stlc60134's integrated vcxo controller, the nt crystal oscillator which comes up in an excellent synchronisation (less than 2ppm) between atu-c and atu-r. framing functions stlc60135 performs framing functions for ge- neric and atm tc sub layers. atm tc sub layer performs cell level functions: de- lineation, idle cells or unassigned cells insertion/ex- traction, payload scrambling, header error correc- tion (hec) check and data frame generation. in order to comply with t1.413 issue 2 rules and full interoperability with other manufacturers' mo- dems (providing they guarantee compliance with either issue 1 or issue 2) framing features (such as interleaving and fast mode) are implemented with programmable parameters. atm frames can be bypassed in order to carry non-atm bit streams, which makes the chip set very fit for applications using dedicated framing such as frame-relay, etc. stlc60135 dtm modem main features: time-domain equalisation decimation, interpolation, fft and ifft, with different length and sam- pling rate at atu-c and atu-r side rotor and frequency-domain equalisation mapping/demapping trellis coding and decoding using viterbi algo- rithm error and noise monitoring on individual tones reed-solomon encoding and decoding (de) framing and (de) interleaving cell hec generation/verification payload (de) scrambling atm cell insertion/extraction idle &/or unassigned cell insertion/filtering vpi/vci filtering utopia interface (level 1 or 2) microcontroller interface with 16-bit multi- plexed address/data bus and big/little endian format supported jtag test port single 3.3v supply, 1.0w pqfp144 (28 x 28mm body, 0.65mm pitch) adsl modem control software the adsl transceiver is based on a programma- ble dmt modem (stlc60135) whose configura- tion is loaded by an external controller. additionally the control functions, stmicroelec- tronics provides the dtm modem software. the software is written in c++ language, and is de- signed to be portable to any processor. the driver has to be interfaced with a real time os kermel, it is compatible with any standard product available on the market. the kernel man- ages the tasks dedicated to modem software. the modem 5w core comes with three additional two software modules: a board support package (bsp) and two application program interfaces (api). bsp manages the hardware dependent features (i.e. interrupts, peripheral mapping). apis interface to the higher level application soft- ware and to the os. adsl loop performances the hereafter tables show the performances that a system, which houses TOSCA, can achieve for ansi and etsi loops. the following results refer to an end-to end adslequipment with no exter- nal disturbance. ansi loop (26awg) length downstream upstream 9kft 7.47 e +0.6 1.05 e +06 12kft 3.69 e +0.6 9.37 e +05 15kft 1.56 e +0.6 7.25 e +05 etsi loop (loop 2, noise model a) length downstream upstream 2km 8.00 e +0.6 8.32 e +05 4km 4.07 e +0.6 6.72 e +05 5km 1.70 e +0.6 4.72 e +05 user high level software adsl management application sw os interface modem sw board support package adsl hardware d98tl392 figure 4. software architecture. TOSCA stlc60134/stlc60135 4/7
tqfp64 dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.18 0.23 0.28 0.007 0.009 0.011 c 0.12 0.16 0.20 0.0047 0.0063 0.0079 d 12.00 0.472 d1 10.00 0.394 d3 7.50 0.295 e 0.50 0.0197 e 12.00 0.472 e1 10.00 0.394 e3 7.50 0.295 l 0.40 0.60 0.75 0.0157 0.0236 0.0295 l1 1.00 0.0393 k 0 (min.), 7 (max.) a a2 a1 b c 16 17 32 33 48 49 64 e3 d3 e1 e d1 d e 1 k b tqfp64 l l1 seating plane 0.10mm outline and mechanical data TOSCA stlc60134/stlc60135 5/7
pqfp144 dim. mm inch min. typ. max. min. typ. max. a 4.07 0.160 a1 0.25 0.010 a2 3.17 3.42 3.67 0.125 0.135 0.144 b 0.22 0.38 0.009 0.015 c 0.13 0.23 0.005 0.009 d 30.95 31.20 31.45 1.219 1.228 1.238 d1 27.90 28.00 28.10 1.098 1.102 1.106 d3 22.75 0.896 e 0.65 0.026 e 30.95 31.20 31.45 1.219 1.228 1.238 e1 27.90 28.00 28.10 1.098 1.102 1.106 e3 22.75 0.896 l 0.65 0.80 0.95 0.026 0.031 0.037 l1 1.60 0.063 k 0 (min.), 7 (max.) a a2 a1 b c 36 37 72 73 108 109 144 e3 d3 e1 e d1 d e 1 k b pqfp144 l l1 seating plane 0. 10mm .004 outline and mechanical data TOSCA stlc60134/stlc60135 6/7
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics TOSCA ? is trademark of stmicroelectronics ? 1998 stmicroelectronics and alcatel alsthom, paris printed in italy all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com TOSCA stlc60134/stlc60135 7/7
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