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february 1999 1 copyright ? 1997, 1998 by lsi logic corporation. all rights reserved. ? L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) preliminary datasheet lsi logics L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) is a highly integrated set-top box control and communication device, combining most of the logic needed for a digital broadcast system (dbs) or cable set-top box onto a single chip. the L64118s embedded 32-bit tinyrisc? mips cpu core provides processing power to support transport and system data, as well as general-purpose system control. the L64118 interfaces directly to lsi logics l64704 and l64724 (satellite), and the l64768 (cable) single-chip channel decoders, as well as to the l64105 mpeg-2 a/v decoder. the mpeg-2 transport and system demultiplexer can handle 32 packet identi?cations (pids) simultaneously, including audio, video, and general- purpose data services. it integrates a digital video broadcasting (dvb)- compliant descrambler block, substantially increasing the security of the set-top box. the L64118s synchronous external system bus (ebus) communicates with external peripherals. the L64118 communicates with peripherals through serial, parallel, smartcard, and infrared ports. several general- purpose i/o pins are provided that let system designers expand the systems capabilities. the L64118 supports industry-standard sdram memory of up to 16 mbytes, using 16 and 64 mbit sdrams. the sdram interface supports pc66/100-compliant sdrams. the L64118 is offered in lsi logics 3.3 v g10 ? -p cell-based technology and is packaged in a 256-pin pbga (if) package. 118bds page 1 wednesday, february 3, 1999 12:37 pm
2 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) figure 1 typical set-top box using the L64118 the L64118s embedded 32-bit mips cpu (tr4101) runs at 54 mhz. the chips cpu block is 32 bit, while the bus interface to external memory (through the sdram controller) is 16 bit. the cpu can run mips16 and mips32 instructions. the 32-bit operations allow high-performance operation, while 16-bit operations allow for code optimization and memory savings. since most transport processing and ?ltering is implemented in hardware, much of the cpus processing power can be devoted to system processing. tuner l64724 L64118 16 mbyte vcxo l64105 1 m x 16 sdram sdram pal / ntsc ntsc pa l s-video l-speaker r-speaker ccir601video pcm-audio encoder satellite/cable 16 16 27mhz 8 1 mbyte x 16 flash line driver 3 x rs232 line driver ieee1284 22 16 /l64768 in aclk external system bus optional 1 mbyte x 16 sdram fast parallel port pc modem pes ts i 2 c port aux 27 mhz 2 2 2 2 gp i/os smartcards 2 x pcm dac optional 16/32 ir blaster/ receiver flash 1 mbyte x 16 (max.) teletext interface 118bds page 2 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 3 the L64118 processes the transport data packets in the pid processing unit (ppu) according to the mpeg-2 standard draft 13818-1, making packetized elementary stream (pes), program speci?c information (psi), service information (si), and private data available to the system. it also buffers and transfers audio and video pes data packets to the external decoder device. the L64118 interfaces directly to lsi logics l64105 mpeg-2 a/v decoder. it outputs demultiplexed audio and video pes streams for processing by the l64105. this decoders extended channel buffer feature lets you use part of the L64118 sdram space to store a/v pes data directed to the l64105. one bene?t of this is that it lets you free memory in the l64105 and increases its on-screen display (osd) capability. the L64118 also interfaces directly to lsi logics family of single-chip channel decoders (l64704, l64724, and l64768), which allows channel data to be transferred in parallel or serial modes. the L64118 implements an automatic sync locking mechanism with a programmable hysteresis function for reliable locking onto mpeg-2 (0x47) transport packet sync bytes. the external system bus (ebus) is a general-purpose, 32-bit wide system bus. it is controlled by the L64118 for communication with external components in the system. this bus provides the system designer with an interface that permits the glueless connection of devices such as flash, roms, and external peripherals. the L64118s peripheral interface blocks let you connect external systems directly to the set-top box. the rs232 ports let you connect a pc, modem, or terminal directly to the chip. the ieee1284 parallel port lets you connect to fast peripheral devices and transfer ?ltered transport packets. the ieee1284 parallel port includes an on-chip dma controller for expediting data transfers between memory to, and from, the port. the L64118 includes an infrared transmitter (blaster) port for applications such as (remotely) programming a vcr, as well as two independent infrared receiver ports, which can be used to program the set-top box using a remote controller. 118bds page 3 wednesday, february 3, 1999 12:37 pm
4 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) the 27 mhz system clock drives the L64118 internal demultiplexer block, as well as most of the peripheral modules. the pll block generates 54 mhz from the 27 mhz system clock to drive the cpu logic. the L64118 includes four dma channels (one dedicated to the ieee1284 port, three independent) that can be used to transfer data between peripheral ports and memory, from one memory location to another, or from memory to an external system device. features the L64118 provides additional system features for a set-top box application, including: channel compliance with iso/iec 13818-1 (mpeg-2) transport speci?cations sustained rates up to 90 mbits/s serial and up to 13.0 mbytes/s parallel transport stream input interface direct interface to lsi logic single-chip channel decoder devices, such as the l64704, the l64768, and the l64724 demux pid ?ltering (32 user-programmable pids) C hardware-assisted section ?ltering for 30 general-purpose pids (psi, si, and private) C each ?lter includes 12 match bytes and 12 mask bytes C each pid can select up to 32 ?lters simultaneously support of a program clock reference (pcr) pid crc32 in parallel to all sections in the ?ltering process descrambler core compliant to dvb common scrambling speci?cations support for transport-level and pes-level descrambling seamless support of scrambled and unscrambled data support of up to 12 pairs of 64-bit keys 118bds page 4 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 5 two 256-byte transport buffers for supporting audio and video pes streams 32 programmable cyclic buffers in sdram memory assignable to a pid or section ?lter index support for an additional programmable cyclic buffer in sdram to post data to adaptation ?elds program clock reference (pcr) recovery and locking automatic detecting and switching of audio and video pids on splice points audio oversampling (256 or 384 times oversampling) clock generation cpu and subsystems integration of the cpu system: C 32-bit tr4101 54 mhz tinyrisc cpu C mips16 and mips-ii instruction set compatible C four kbyte data (direct mapped) and eight kbyte (two-way set associative) instruction cache C basic bus and cache controller unit (bbcc) C multiply/divide unit (mdu) C debugger building module (dbx) C 32-bit timers and interrupt controller C in-circuit emulator (ice) port two interrupt handling modes: C interrupt compatibility mode supports 12 interrupt ports and six main interrupt levels. this mode is compatible with the l64108 interrupt structure. C interrupt extension mode supports 25 interrupt ports with a software index to each interrupt source. this new mode can reduce interrupt latency. 118bds page 5 wednesday, february 3, 1999 12:37 pm
6 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) peripherals programmable audio clock generator for oversampling audio dac (aclk) three rs232 serial i/o channels ieee1284 parallel interface port (shared with the aux port) two iso7816 smartcard interfaces two infrared (ir) receivers one ir transmitter auxiliary (aux) fast input/output port with multiple con?gurations and settings (shared with the ieee1284 port) teletext serial interface port with direct interface to ntsc or pal encoders i 2 c-compatible interface port supporting multimaster or slave modes for interfacing to external devices four dma channels (one dedicated to ieee1284 port, three independent) synchronous extension bus C 32-bit external addressing C 8-/16-/32-bit data bus width C multiplexed address/data as well as eight demultiplexed address pins C synchronous to a 27 mhz output clock up to 47 general-purpose pins six programmable chip-select output signals (?ve dedicated and one multiplexed) enhanced serial i/o for modem use sdram controller sdram controller supports 16 and 64 mbit sdram devices sdram controller support for up to 16 mbytes 118bds page 6 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 7 general on-chip pll (54 mhz) with internal loop ?lter jtag support 256-pin plastic ball grid array (pbga) package commercial temperature range 0 cC70 c ambient low-power, 3.3 v ( 10%) process architectural overview the components of the L64118 are integrated to provide a complete system solution for demultiplexing and processing incoming mpeg-2 transport stream packets. figure 2 shows the three main blocks of the L64118: the tr4101 cpu and associated core building blocks, the transport (demultiplexer) block, and the peripheral device interfaces. additionally, the L64118 has three main buses: basic bus (bbus) the bbus is an internal 32-bit bus that connects the cpu core and building blocks with internal memory and peripherals through the cpu-to-peripheral (c2p) bridge. peripheral bus (pbus) the pbus is the internal peripheral bus; it links the cpu to sdram memory, internal peripheral devices, and the demultiplexer using the c2p bridge. external system bus (ebus) the ebus is a general-purpose 16- and 32-bit synchronous system bus that lets the L64118 communicate with external components in the system. the ebus connects to the bbus through the ebus controller. the following subsections provide an overview of the chips main blocks. 118bds page 7 wednesday, february 3, 1999 12:37 pm
8 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) figure 2 L64118 internal block diagram video pes buffer audio pes buffer video audio channel decoder i 2 c- interface teletext interface vcx0 27 mhz interface tr4101 tinyrisc core interrupt register file descrambler dispatcher pcr clock recovery c2p cache controller ebus controller 1284 parallel port pid processor transport stream sdram sdram controller cpu block transport block peripherals l64105 interface external pes bus bus controller cache system bus audio clock generator aclk timers bbus compatible smartcard interface controller internal peripheral bus (pbus) mdu dma controller dbx iceport ir port 3 serial ports aux parallel port pbus 118bds page 8 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 9 tinyrisc mips cpu core with its powerful mips cpu, the L64118 can support all of the systems general-purpose control requirements, including: complete set-top system initialization and testing security handling communication ports protocol processing remote control handling pcr recovery and locking audio/video synchronization for lip-syncing the cpu also supports transport and system data software processing on data posted to the sdram by the transport processing block. this includes operations such as: psi and dvb si table maintenance (program association table (pat), conditional access table (cat), program map table (pmt), network information table (nit)) private section ?ltering subtitle processing and osd overlay closed caption and teletext electronic program guide the mips cpu in the L64118 has more than enough processing power to implement all the tasks listed above. the cpu core can be programmed with 16- or 32-bit instructions. the 32-bit operations allow high-performance operation; using the 16-bit architecture permits a reduced code size, saving memory. both 16- and 32-bit instructions can be used in the same design. 118bds page 9 wednesday, february 3, 1999 12:37 pm
10 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) the L64118s tr4101 mips cpu is part of lsi logics coreware a technology. the chip integrates the complete cpu subsystem, including: cpu (tr4101) cache memory for instruction ( 2x4kb yte) and data (4 kbyte) cache basic biu and cache controller (bbcc) timers (including watchdog timer) interrupt controller debugger building module (dbx) multiply/divide unit (mdu) ice port (full-duplex, serial receive and transmit port) cpu-to-peripheral bus (c2p) the L64118s embedded 32-bit mips cpu runs at 54 mhz. this clock rate permits a peak processing rate of 54 mips. the chips internal cpu core is implemented in 32-bit architecture, but it can execute both 16-bit and 32-bit instructions. the L64118 has a 16-bit data interface to external sdram, and a 32-bit data interface to the external system bus (ebus). the cpu operates in big endian 1 mode. since most transport processing and ?ltering is implemented in hardware, much of the cpus processing power can be devoted to system processing. the chip includes address decoding logic for directly interfacing to external memory (flash, sdram) without requiring external glue logic. the interface between the cpu subsystem and the rest of the L64118 is implemented by the c2p unit. the c2p module translates 32-bit data accesses by the cpu to 8- and 16-bit data accesses on the peripheral bus, which connects all other blocks. the pbus is synchronous to the 27 mhz system clock. transport demultiplexer block the transport demultiplexer block processes the transport stream data coming from the channel interface. the input of the L64118 transport block interfaces to the channel decoder; the output interfaces to the 1. big-endian means that the address of a multiple-byte data type is the address of its most signi?cant byte. 118bds page 10 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 11 sdram controller module. the block includes a pid processor unit (ppu) that is compliant with dvb and jsat and meets the requirements of many other service providers, including canal+, skyperfect, and bskyb. the unit can process up to 32 pids simultaneously. it provides extensive ?ltering of psi, si, and private sections. the psi, si, and private sections are ?ltered according to 32 user-programmable match/mask pids. section data that passes ?ltering is stored in cyclic buffers (in off- chip memory) associated with each pid. each section in each pid can be ?ltered against 32 ?lters. (every section undergoes a crc32 check. an enable bit controls the crc checking of all section types.) the on- chip descrambler unit increases system security. the audio and video data are reduced to pes streams and delivered to the a/v decoder. sdram controller the sdram controller and resource arbitration logic makes ef?cient use of sdram bandwidth. this chips low-cost system implementation approach dictates usage of the external sdram for both transport and general system functions. the L64118 supports various sdram con?gurations using 16 mbit and 64 mbit devices, for a total memory size of 2, 8, or 16 mbytes of external sdram. the sdram controller arbitrates access to the external sdram. this logic provides the maximum possible sdram bandwidth to the on-chip cpu without increasing the need for buffers or other resources. external system bus (ebus) the external system bus is a general-purpose 16- and 32-bit system bus used for communication with external components in the system. this bus provides the system designer with an interface that permits the glueless connection of devices like flash, roms, and external peripherals. the ebus comprises a 32-bit wide interface with multiplexed address and data. eight address bits are available as demultiplexed bits for easy interface to devices that do not need the full address space. in addition a demultiplexed mode can be con?gured to provide a 24-bit address and 16-bit data bus. 118bds page 11 wednesday, february 3, 1999 12:37 pm
12 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) the ebus controller registers let the user program customized timing for each address space used in a given system. six address spaces are supported, each with a dedicated chip select output. the main features of the ebus are: 32-bit physical addressing space 32-bit data width synchronized to 27 mhz clock five external interrupt ports the ebus supports the following main signals: 32-bit multiplexed address/data 8-bit demultiplexed (low order) address bits rdn wrn eackn ale (address latch enable) five dedicated chip-selects and one multiplexed (with memory strobe) chip select 4-bit byte enable bus 27 mhz output clock peripherals the L64118 integrates several serial and parallel ports, providing a high degree of connectivity to various types of peripherals. the communication ports include: three 8251 rs232 serial communication ports connect the set-top box to a dumb monitor, modem, or pc. the modem communicates between the subscriber and the main station, or back channel. one serial i/o includes a v24-compatible uart for a glueless connection to modem datapump ics. 118bds page 12 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 13 one ieee1284 parallel communication port for fast communication with a pc or workstation. the L64118 includes an on-chip dma controller dedicated for data transfers between the ieee1284 parallel communication port and the main memory. one i 2 c-compatible serial communication port to communicate with devices using i 2 c data links. this type of bus is common in video encoders, audio dacs, remote control devices, and rf tuners. two independent smartcard ports iso-7816-3 compliant smartcard ports interface through a smartcard coupler, and support the t = 0, t = 1 asynchronous protocol. the ports also feature v cc ,v pp control. one teletext port that interfaces to an ntsc or pal encoder and allows for direct insertion of teletext data into an ntsc or pal video encoder device. the teletext data usually is transmitted using a special-purpose pid. the data is then extracted by the transport processor and posted to sdram. finally, the L64118 controller transfers the teletext data to the teletext port upon request from the video encoder device. the teletext port includes a fifo between the real-time timing required on the output pins and the internal data transfer. an aux parallel port for outputting/inputting transport packets from/to the internal demultiplexer. the ports direction is controlled through a con?guration bit or through the auxtx input pin. the port can be programmed to deliver or receive transport packets at various points within the demultiplexers pipeline. this port is multiplexed with signals from the ieee1284 port. an infrared port with a single ir blaster with two identical output pins and two identical, yet independent, ir receiver modules. the irt (transmitter) can be used to communicate with off-board elements (e.g., to program a vcr). the two ir receivers, ir0 and ir1, support remote control of the stb. forty-seven general-purpose i/o pins (gpios) are con?gurable and can be used to control and monitor a subset of processor functions, thus easing system integration and minimizing external glue logic. forty-one of these i/os are multiplexed, six are dedicated gpios. 118bds page 13 wednesday, february 3, 1999 12:37 pm
14 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) dma controller the L64118 integrates a four-channel dma controller that reduces a major portion of the load the cpu might incur during data transfer between peripheral ports, memory, and elements residing on the ebus. one dma channel is dedicated for data transfers between the ieee1284 port and main memory. the other three dma channels are general- purpose. one general-purpose dma channel (channel #1) supports transfers between pbus and ebus devices. in typical applications, one dma channel can be assigned to a smartcard, one channel to a serial port, and one to memory to memory data transfers. addressing the mips architecture uses two types of addresses: virtual addresses (used in a program), and physical addresses (that appear on an address bus). this allows support of kernel and user modes, while combining cacheable and noncacheable addresses. virtual addresses are partitioned into four, ?xed-size segments: kuseg , kseg0 , kseg1 , and kseg2 , according to table 1. table 1 memory segment address mapping the kuseg addresses are accessible in user and kernel mode; they are for use by user-mode programs, while also providing direct access (requiring no system call) to those same addresses in kernel mode. because the L64118 does not have a memory management unit (mmu), kuseg addresses are mapped unchanged to physical addresses. the L64118 does not map kseg2 ; thus, kseg2 addresses cannot be used by virtual cpu address [31:29] segment size 0b000C0b011 kuseg 2 gbytes 0b100 kseg0 (cache) 512 mbytes 0b101 kseg1 (noncache) 512 mbytes 0b110C0b111 kseg2 (not used) 1 gbytes 118bds page 14 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 15 the programmer. noncacheable kseg1 addresses are used for accessing peripheral registers and for code that requires noncacheability (for example, initialization code that is executed before the caches have been ?ushed). cacheable kseg0 addresses are used for all other code. the on-chip cpu performs virtual to physical address translation; the resultant 32-bit physical addresses are output on the internal bbus. the cpu to peripheral (c2p) bridge module maps the 32-bit bbus address to the internal 24-bit pbus address. the ebus interface module (which resides on the internal bbus) maps the 32-bit bbus address to the 24/32 1 -bit ebus address, according to the mode in which the ebus interface is con?gured and the width of the area being accessed. the L64118 supports a 16 or 32 mbyte physical address space (depending on the size of the sdram supported in the system). virtual addresses in kseg0 and kseg1 are always mapped to the same physical addresses, namely to the lowest 16 (or 32) mbytes of physical memory. the programmer can differentiate between cacheable and noncacheable addresses by using a virtual address either in kseg0 or kseg1 (e.g., psi/pes data is stored in a noncacheable location, since they are posted by the pid processor). as part of the cpu subsystem, the L64118 a small module (the mmu stub) that maps the kseg0 and kseg1 segments to the same physical address. it does this by clearing the three most signi?cant bits of the address in the kseg0 and kseg1 segments presented by the cpu (on the internal cpu bus). segments kuseg and kseg2 are unaffected by the mmu stub. note that the L64118 cpu operates only in big-endian mode; the ebus must be set to operate in big-endian mode. a strap option on the gpio[42] pin (sampled during reset) determines the physical connection on the ebus. 1. the ebus uses either a 24-bit address or a 32-bit address, depending on the address space being accessed. 118bds page 15 wednesday, february 3, 1999 12:37 pm
16 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) the address space of the L64118 is partitioned into the following areas: cpu/peripheral this address space contains the control and status registers for the cpu and core building blocks. con?guration register space the space contains registers that de?ne the con?guration of each peripheral on the pbus. it is partitioned into 1 kbyte segments, where each segment corresponds to the con?guration register entry for each pbus component. see table 3. attribute register space the attribute register space contains the attribute register 0 for each peripheral on the pbus. this space is partitioned into 1 kbyte segments, where each segment corresponds to the attribute register entry for each pbus component. see table 3. internal i/o the internal i/o space contains i/o registers and functions for each peripheral on the pbus. it is partitioned into 256 4 kbyte segments, where each segment corresponds to an i/o entry for a pbus component. see table 3. external rom external rom contains the operating system, users application programs ( kseg0 ), con?guration code, and initialized data ( kseg1 ). external space for the ebus the external space is used for user-de?ned external memory and external devices residing on the ebus. it is divided into three subspaces, each one supporting devices with a different width (8, 16, 32 bits). primary sdram the lowest 2/8/16 mbytes of addressable space are mapped to the external sdram through the internal sdram controller. see table 2, pbus to ebus address mapping, 118bds page 16 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 17 table 2 pbus to ebus address mapping : note that the pbus addresses are not driven on the ebus, but rather are routed to the sdram controller. the two mbyte and eight mbyte mode are software compatible with the l64108 code, since the external space 2 (es2) of the l64108 is located at pbus address 0x0080.0000 (by default). table 3 summarizes the L64118 address space. 118 ebus pbus address 2 mbytes sdram 0x0000.0000C0x1f.ffff 8 mbytes sdram 0x0100.0000C0x017f.ffff 16 mbytes sdram 0x0100.0000C0x01ff.ffff table 3 L64118 address mapping virtual cpu base address bbus base address address space name pbus/ebus physical base address size (mbytes) noncache kseg1 cache kseg0 0xbfff.0000 n/a 0x1fff.0000 cpu/peripheral (reserved 1 ) not used 0.50 0xbff8.0000 n/a 0x1ff8.0000 not used not used 0.50 0xbff4.0000 n/a 0x1ff4.0000 internal con?guration registers 0xf4.0000 (pbus) 0.25 0xbff0.0000 n/a 0x1ff0.0000 internal attribute registers 0xf0.0000 (pbus) 0.25 0xbfe0.0000 n/a 0x1fe0.0000 internal i/o 0xe0.0000 (pbus) 1 0xbfc0.0000 0x9fc0.0000 0x1fc0.0000 external rom 0xc0.0000 (ebus demux mode) 2 0xb800.0000 2 0x9800.0000 0x1800.0000 8-bit devices in the external space 0x00.0000 (ebus demux mode) 3 64 0xb400.0000 4 0x9400.0000 0x1400.0000 16-bit devices in the external space 0x00.0000 (ebus demux mode) 5 64 0xb000.0000 6 0x9000.0000 0x1000.0000 32-bit devices in the external space 0x1000.0000 (ebus mux mode) 7 64 118bds page 17 wednesday, february 3, 1999 12:37 pm
18 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) signals this section describes the signals used by the L64118. figure 3 shows the L64118 non-gpio mode signals in functional groups and figure 4 shows the L64118 gpio mode signals. the signals are described by group. within each group, signals are listed in alphabetic order. 0xa000.0000 0x8000.0000 0x0000.0000 primary sdram when 2 mbytes of sdram is used 0x0000.0000 (pbus) 2 0xa000.0000 0x8000.0000 0x0000.0000 primary sdram when 8 or 16 mbytes of sdram is used 0x0100.0000 (pbus) 8or16 1. these transactions do not appear on the pbus. this space is used only when the cpu accesses bbus components (bbcc, timer, c2p, intc, iceport). 2. within this range, used for 8-bit devices, speci?c address ranges can be selected (and the mode in which they are accessed) using the ebus address compare registers. 3. bits [23:0] of the bbus address are re?ected onto the ebus address bus for eight-bit devices. 4. within this range used for 16-bit devices, speci?c address ranges can be selected (and the mode in which they are accessed) using the ebus address compare registers. 5. bits [23:0] of the bbus address are re?ected onto the ebus address bus for 16-bit devices. 6. within this range used for 32-bit devices, speci?c address ranges can be selected (and the mode in which they are accessed) using the ebus address compare registers. 7. same address used on the ebus and bbus when 32-bit devices are accessed. table 3 L64118 address mapping (cont.) virtual cpu base address bbus base address address space name pbus/ebus physical base address size (mbytes) noncache kseg1 cache kseg0 118bds page 18 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 19 figure 3 L64118 i/o signal summary (non-gpio modes) rxd1/ice_rx csn[4:0] resetn ad[31:0] addr[7:0] ale wrn ben[3:0] external system sclk pllvdd mpeg (pcr) phase-locked loop sdet avd[7:0] vvalid avalid averrn vreqn areqn audio/video L64118 initn/auxpid[2] sba[1:0] sbd[15:0] swen sa[11:0] sdram interface aclk avdd avss audio clock select/auxpid[1] busy/auxsb ackn/auxnm selectinn/aux_adp/aux_err stroben/aux_tx faultn/auxclk perror/auxpid[0] ieee 1284 parallel autofdn/auxv sda ttxreq ttxdata scl i 2 c-compatible cclk cvalid channel interface eackn cerrn i/o pin symbol srasn intn[4:0] pllvss sdqml sdqmh teletext port eclk iddtn op_mode[1:0] scasn sdclk decoder port generator ctsn0 dtrn0 dsrn0 rtsn0 rxd0 rxd2 txd0 txd1/ice_tx txd2 serial port/ rdn test signals ztestn ctsn1/iceclk rtsn1 smartcard0 port trstn tck ieee1149.1 tms tdo tdi cdata[7:0] jtag port port sc0_i/o sc0_rstn sc0_detect sc0_vcc_enn sc0_clk sc0_vpp_enn sc0_c4 sc0_c8 smartcard1 port sc1_i/o sc1_rstn sc1_detect sc1_vcc_enn sc1_clk sc1_vpp_enn gpio[49:48,46:45,43:42] bus csn[5]/memstbn irrx0 irrx1 irtx irbl infrared port cpu_clk pdata_dir/op_mode[2] rclk tclk iceport pdata[7:0] and auxiliary port general-purpose i/os miscellaneous iref 118bds page 19 wednesday, february 3, 1999 12:37 pm
20 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) figure 4 L64118 i/o signal summary (gpio mode) rxd1/ice_rx csn[3:0] resetn ad[31:0] addr[7:0] ale wrn ben[1:0] external system sclk pllvdd mpeg (pcr) phase-locked loop sdet avd[7:0] vvalid avalid averrn vreqn areqn audio/video L64118 gpio25 sba[1:0] sbd[15:0] swen sa[11:0] sdram interface aclk avdd avss audio clock gpio27 gpio15 ackn/auxnm gpio28 gpio29 gpio24 gpio26 ieee 1284 parallel gpio14 sda gpio12 gpio13 scl i 2 c-compatible cclk cvalid channel interface eackn cerrn i/o pin symbol srasn intn[4:0] pllvss sdqml gpio6 teletext port eclk iddtn op_mode[1:0] scasn sdclk decoder port generator gpio7 gpio8 gpio9 gpio10 gpio11 rxd2 txd0 txd1/ice_tx txd2 serial port/ rdn test signals ztestn ctsn1/iceclk rtsn1 smartcard0 port trstn tck ieee1149.1 tms tdo tdi cdata[7:0] jtag port port sc0_i/o gpio30 gpio31 gpio32 gpio33 gpio34 sc0_c4 sc0_c8 smartcard1 port sc1_i/o gpio35 gpio36 gpio37 gpio38 gpio39 gpio[49:48,46:45,43:42] bus csn[5]/memstbn gpio40 gpio41 gpio44 gpio47 infrared port cpu_clk pdata_dir/op_mode[2] rclk tclk iceport gpio[23:16] and auxiliary port general-purpose i/os miscellaneous gpio[3:2] gpio1 iref 118bds page 20 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 21 table 4 lists the default values of the output and bidirectional signals. note that during reset, all bidirectional signals (and some output signals) are ?oating. table 4 default values for L64118 output and bidirectional signals after reset 1 signal default value notes ackn/auxnm not asserted aclk inactive (low) ad[31:0] driving an unknown value addr[7:0] driving an unknown value ale not asserted autofdn/auxv not asserted avalid not asserted avd[7:0] driving an unknown value averrn not asserted ben[3:0] not asserted busy/auxsb not asserted csn[4:0] not asserted csn[5]/memstbn not asserted dtrn0 not asserted faultn/auxsb not asserted gpio42, 43, 45, 46, 48, 49 ?oating initn/auxpid[0] not asserted irtx not asserted pdata_dir/ op_mode[2] drives assertion pdata[7:0] ?oating rdn not asserted 118bds page 21 wednesday, february 3, 1999 12:37 pm
22 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) rtsn0/1 not asserted sa[11:0] driving an unknown value sba[1:0] driving an unknown value sbd[15:0] ?oating sc0_c4, sc0_c8 pulled up by an external pull-up resistor scasn not asserted scx_clk not asserted scx_detect ?oating serves as an input scx_io pulled up by an external pull-up resistor scx_rstn not asserted scx_vpp_enn not asserted scx_vcc_enn not asserted scl pulled up using an external pull-up resistor sda pulled up using an external pull-up resistor sdclk toggling sdqmh not asserted sdqml not asserted srasn not asserted swen not asserted table 4 default values for L64118 output and bidirectional signals after reset 1 (cont.) signal default value notes 118bds page 22 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 23 channel interface port these signals provide the physical connection to channel interface devices, such as lsi logics l64724 or l64768. this port supports both parallel and serial connections. cclk channel clock input when cvalid is asserted high, the L64118 latches cdata[7:0] on the rising edge of cclk. in serial mode, the L64118 uses only cdata[0]. in serial mode, the maximum clock rate is 60 mhz; in parallel mode, it is 13 mhz. the cclk must toggle during reset to ensure proper reset of the channel interface block. cdata[7:0] channel data input these signals deliver channel information to the L64118. when cvalid is asserted, the chip latches the data on every rising edge of cclk. when the L64118 is in parallel input mode, all cdata[7:0] signals deliver data. when the L64118 is in serial mode, only cdata[0] delivers data. ttxreq/gpio12 ?oating behaves as an input ttxdata not asserted txd0/2 asserted txd1/ice_tx vvalid not asserted wrn not asserted 1. a few cycles after reset (resetn is driven high), the L64118 initiates a transaction on the ebus, changing some of the default values in this table. table 4 default values for L64118 output and bidirectional signals after reset 1 (cont.) signal default value notes 118bds page 23 wednesday, february 3, 1999 12:37 pm
24 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) cerrn channel data error input this active low input signal indicates that an uncorrected error occurred in the preceding channel interface. when cvalid is asserted, cerrn is latched on the rising edge of cclk. cvalid channel data valid input this active high input signal indicates that cdata[7:0] and cerrn are carrying valid data. when cvalid is asserted, a rising edge of cclk latches the cdata[7:0] signals into the L64118. mpeg program clock reference (pcr) recovery these signals recover the program clock reference (pcr). they interface to the external vcxo, which provides the 27 mhz clock to the decoder. sclk 27 mhz system clock input this input provides the clock signal to the L64118. it must be driven by the external 27 mhz vcxo (the voltage control input is controlled by sdet and the external rc ?lter). sdet system clock sigma-delta control voltage output this converter output signal from a 16-bit sigma-delta modulator inside the L64118 drives a simple low-pass ?lter to produce an analog control voltage to an external vcxo. phase-locked loop (pll) these signals supply power and ground to the internal pll, which generates the internal 54 mhz cpu clock from the external 27 mhz sclk input. the 54 mhz internal clock is then divided by two to generate the internal 27 mhz clock used by other internal modules. isolate the pllvdd and the pllvss signals from digital noise and digital logic on the pcb using layout and bypass ?ltering techniques. pllvdd pll analog vdd input this provides a separate ?ltered 3.3 v to the pll circuit through pllvdd so that switching noise from the digital portion of the chip can not affect pll stability. 118bds page 24 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 25 pllvss pll analog vss input this provides a separate ground to the pll circuit through pllvss so that switching noise from the digital portion of the chip does not affect pll stability. external system bus (ebus) the ebus comprises a 32-bit wide interface with multiplexed address and data. eight address bits are available as demultiplexed bits for an easy interface to devices that do not need the full address space. all bus transactions are synchronous to the 27 mhz output cpu_clk. a subset of these signals can be programmed to act as general-purpose i/o signals by setting bit [0] in the general-purpose mode register. ad[31:0] multiplexed address/data bus bidirectional ad[31:0] is the multiplexed address/data bus. the L64118 can be programmed to drive the full address on this bus at access start. after this address phase the bus presents write data for a write or the external device drives data on the bus in a read. addr[7:0] demuxed address bus output addr[7:0] provides eight bits of demultiplexed address bits. this bus allows some designs to remove the external address latch on the multiplexed address/data bus to hold the address throughout the transaction. the ebus uses byte addressing. all 16-bit devices must ignore addr[0]. all 32-bit devices must ignore addr[1:0]. ale address latch enable output this active high signal controls the latches for demultiplexing the address from the ad bus. ben[1:0] byte enables output the four byte enable outputs are asserted during a read or write transaction on the ebus to control which of the four byte lanes are enabled. the byte lane selection is dependent on the width of the transaction (word, halfword, or byte) and the data width of the external device (32, 16, or 8 bits). 118bds page 25 wednesday, february 3, 1999 12:37 pm
26 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) the byte enables always correspond to the same physical lines on the ad bus: ben[1] corresponds to ad[15:8], ben[0] to ad[7:0]. ben[2] byte enable output the four byte enable outputs are asserted during a read or write transaction on the ebus to control which of the four byte lanes are enabled. the byte lane selection is dependent on the width of the transaction (word, halfword, or byte) and the data width of the external device (32, 16, or 8 bits). the byte enables always correspond to the same physical lines on the ad bus: ben[2] corresponds to ad[23:16]. gpio2 bidirectional ben[2] can serve as a general-purpose i/o signal (gpio2) by setting bit 0 in the general-purpose mode register. ben[3] byte enable output the four byte enable outputs are asserted during a read or write transaction on the ebus, to control which of the four byte lanes are enabled. the byte lane selection is dependent on the width of the transaction (word, halfword, or byte) and the data width of the external device (32, 16, or 8 bits). the byte enables always correspond to the same physical lines on the ad bus: ben[3] corresponds to ad[31:24]. gpio3 bidirectional ben[3] can serve as a general-purpose i/o signal (gpio4) by setting bit 0 in the general-purpose mode register. cpu_clk ebus output clock output this 27 mhz output clock is generated dividing the on-chip 54 mhz clock by two. this clock serves as the reference signal for all transactions on the ebus. the timing relationship between the sdclk output clock, the 27 mhz sclk input and the 27 mhz cpu_clk output is unknown. 118bds page 26 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 27 csn[3:0] programmable chip selects output each chip select pin can be programmed to assert in a speci?c address area. these pins are used to select speci?c external devices according to on-chip address decoding. they make interfacing to various peripherals easier, as they can remove the need for external address decoders. csn[4] programmable chip select output this pin is similar in function to the other ?ve chip select output pins. it is used to select speci?c external devices according to on-chip address decoding. gpio1 bidirectional csn[4] can serve as a general-purpose i/o signal (gpio1) by setting bit 0 in the general-purpose mode register. csn[5]/memstbn chip select[5] or memory strobe output this pin is similar in function to the other ?ve chip select output pins but holds the characteristic of being able to function as the memstbn (active low memory strobe) signal. the memstbn signal is a general-purpose signal. it can be used to indicate that a memory transaction is in progress. it is asserted in both read and write cycles. the timing on this signal is programmable. eackn target acknowledge input this signal indicates to the L64118 that the external device is ready to complete the current read or write cycle. the transaction will ?nish if both eackn is asserted and the internal wait state generator has expired. this mechanism allows devices to extend an access beyond the number of wait states programmed for that particular address area. eackn can be programmed to be either active high or low, using the xpos bit in the cebusmode register. eackn must be deasserted before the next transaction acknowledge cycle. for self-acknowledge devices, the external eackn pin can be ignored, so the transaction completes when the wait state generator expires. this is controlled by the xack bit in the cecfgn register. 118bds page 27 wednesday, february 3, 1999 12:37 pm
28 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) intn4 interrupt input this unmaskable interrupt can be used for highest priority system needs. intn[3:0] interrupts input these four external interrupts can be programmed to be level- or edge-triggered sensitive. interrupts intn[3:0] are maskable and for general-purpose use. when the L64118 receives an interrupt, the internal cpu completes the execution of the current instruction and jumps to a preprogrammed location in the memory containing the handler for this interrupt. by default, these signals are level triggered after reset. rdn read output the active low read strobe is asserted during read operations, and deasserted during writes. wrn write enable output the active low write strobe is asserted during write operations and deasserted during reads. miscellaneous signals these general signals are not necessarily associated with a speci?c function or module of the L64118. op_mode[1:0] operational mode input these signals, along with op_mode[2], are used as strap options to con?gure various lsi logic test modes. for normal operation, con?gure op_mode[2:0] to 0b000. that is, op_mode[1:0] should be tied low, and op_mode[2] should be pulled low with a 10 k w resistor. op_mode[2]/pdata_dir operational mode input this signal is used as a strap option during reset in conjunction with the op_mode[1:0] pins, and must be pulled low with a 10 k w resistor for proper device operation. 118bds page 28 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 29 parallel data direction output after reset, this signal serves as the pdata_dir output, which controls the parallel data bus buffers for the 1284 pdata[7:0] data lines. when the 1284 port is used as an aux port, this pin is driven high. resetn asynchronous reset input asserting this active low signal resets the L64118 to its power on state. to ensure a complete reset of the L64118, resetn must be asserted for at least 16 sclk cycles. test signals these signals are for lsi logic test purposes. they must be tied to a constant value in normal operational mode. eclk connect to vss input this is an lsi logic manufacturing test pin. iddtn connect to vss input this is an lsi logic manufacturing test pin. ztestn connect to vdd input this is an lsi logic manufacturing test pin. it is deasserted high for normal chip operation. serial port/iceport these signals connect the L64118 to an external modem, pc, terminal, or other host that includes an rs232 interface. the L64118 contains three serial ports that comply with the asynchronous speci?cation of the rs232 standard. the on-chip baud rate generators support the standard bit rate for serial communication. three of the sio1 signals can be con?gured to serve the internal iceport module. ctsn0 clear to send port 0 input when reset low, this signal indicates that the external receiver is ready for data transfer through txd0/rxd0. if the transmit enable bit in the sio command register is set high when ctsn0 is reset low, data from the transmit register of port 0 is serialized through txd0. 118bds page 29 wednesday, february 3, 1999 12:37 pm
30 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) gpio7 bidirectional ctsn0 can serve as a general-purpose i/o signal (gpio7) by setting bit 1 in the general-purpose mode register. ctsn1/iceclk clear to send port1 input this pin can serve as either the clear to send signal of sio1, or as the iceport clock input for the iceport module. the strap option on gpio[43] controls this pins functionality and usage. if gpio[43] is sampled high during reset, this pin serves as ctsn1. when reset low, this signal indicates that the external receiver is ready for data transfer through txd1/rxd1. if the transmit enable bit in the sio command register is set high when ctsn1 is reset low, data from the transmit register of port 1 is serialized through txd1. serial ice clock input when serial ice mode is enabled, this pin functions as iceclk, the synchronous ice port clock input. dsrn0 data set ready port 0 input when reset to low, this general-purpose input control signal indicates that an external terminal device is ready for data transfer. the polarity of dsrn0 is latched in port 0 status register for the cpu to read. gpio9 bidirectional dsrn0 can serve as a general-purpose i/o signal (gpio9) by setting bit 1 in the general-purpose mode register. dtrn0 data terminal ready port 0 output when this general-purpose output control signal is reset to low, data for the external terminal device is ready to be transmitted. dtrn0 can be set or reset by programming the dtr bit in the sio command register. by default, this signal is not asserted after reset. gpio8 bidirectional dtrn0 can serve as a general-purpose i/o signal (gpio8) by setting bit 1 in the general-purpose mode register. 118bds page 30 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 31 rclk receive serial data clock input this signal is used for the receive clock input in the enhanced uart mode. rtsn0 request to send port 0 output when this general-purpose, programmable control signal is reset to low, port 1 is ready to send data through txd1. this signal is set and reset by programming the rts bit in the sio command register. by default, this signal is not asserted after reset. gpio10 bidirectional rtsn0 can serve as a general-purpose i/o signal (gpio10) by setting bit 1 in the general-purpose mode register. rtsn1 request to send port1 output when this general-purpose, programmable control signal is reset to low, port 1 is ready to send data through txd1. this signal is set and reset by programming the rts bit in the sio command register. rxd0 receive data port 0 input this signal provides serial data from an external rs232 device. its protocol is similar to that of txd0. the receive baud rate can be programmed in the sio baud rate register. the data received on rxd0 is latched in the receive register of port 0. gpio11 bidirectional rxd0 can serve as a general-purpose i/o signal (gpio11) by setting bit 1 in the general-purpose mode register. rxd1/ice_rx receive data port 1 input this pin serves either as the receive port signal of sio1, or as the iceport receive input for the iceport module. the strap option on gpio[43] controls this pins functionality and usage. if gpio[43] is sampled high during reset, this pin serves as rxd1. in that case, this signal provides serial data from an external rs232 device. 118bds page 31 wednesday, february 3, 1999 12:37 pm
32 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) the protocol of this pin is similar to that of txd1. the receive baud rate is determined by programming the sio baud rate register. the data received on rxd1 is latched in the receive register of port 1. if gpio[43] is sampled low during reset, then this pin serves as the receive port for the iceport in the L64118. receive data - serial ice port input when the serial ice mode is enabled, this pin functions as ice_rx, the receive data port input. rxd2 receive data port 2 input this signal provides serial data from an external rs232 device. the protocol of this pin is similar to that of txd2. the receive baud rate is determined by programming the sio baud rate register. the data received on rxd2 is latched in the receive register of port 2. tclk transmit serial data clock input this signal is used for the transmit clock in the enhanced uart mode. txd0 transmit data port 0 output this signal outputs data in compliance with the rs232 protocols asynchronous speci?cation. the transmit baud rate is determined by programming the sio baud rate register. data transmitted on txd0 comes from the transmit register of port 0. by default, this signal is not asserted after reset. txd1/ice_tx transmit data port 1 output this pin can serve as either the transmit data port signal of sio1, or as the iceport receive input for the iceport module. the strap option on gpio[43] controls this pins functionality and usage. if gpio[43] is sampled high during reset, this pin serves as txd1. when set to txd1, this signal outputs data in compliance with the rs232 protocols asynchronous speci?cation. the data rate on this pin is determined by programming the sio baud rate register. data transmitted on txd1 comes from the transmit register of port 1. 118bds page 32 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 33 transmit data - serial iceport output if gpio[43] is sampled low during reset, this pin serves as ice_tx, the serial ice transmit data output port. by default, this signal is not asserted after reset. txd2 transmit data port 2 output this signal outputs data in compliance with the rs232 protocols asynchronous speci?cation. the data rate on this pin is determined by programming the sio baud rate register. data transmitted on txd2 comes from the transmit register of port 2. by default, this signal is not asserted after reset. sdram interface the following group of signals provides the interface between the L64118 and external sdram devices. the sdram interface works with pc66/100 compliant sdrams. the L64118 sdram interface runs at 54 mhz and is capable of accessing 2, 4, 8, or 16 mbyte memory con?gurations using 16 mbit or 64 mbit devices. this interface has a 16-bit data bus (sbd[15:0]). the upper and lower byte mask signals (sdqmh and sdqml) control halfword and byte accesses. the sba[1:0] outputs support two- and four-bank sdram devices. the L64118 automatically performs sdram refreshes. the L64118 does not support the chip select (csn) and clock enable (cke) signals. tie these sdram signals active low and high, respectively, on the sdram device(s) used. sa[11:0] sdram address bus output these signals carry the 12-bit sdram address bus. the number of row and column address bits used is programmable in the sdram con?guration register. sba[1:0] sdram bank select output these signals allow access to sdram devices with either two or four banks. the number of bank select bits used is programmable in the sdram con?guration register. 118bds page 33 wednesday, february 3, 1999 12:37 pm
34 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) sbd[15:0] sdram data bus bidirectional this data bus is driven by the sdram during a read operation, and driven by the L64118 during a write operation. it is 3-stated after reset and when there are no memory accesses. scasn column address strobe output this signal is the active low column address strobe. it is used in conjunction with the srasn and swen outputs to form the sdram command. sdclk sdram clock output this is the master sdram clock. all output signals are referenced to the rising edge of sdclk. the programmable sdram timing parameters are expressed in sdclk periods. sdqmh high byte mask output this active high signal is the high byte data mask, which controls the high byte input/output buffer of the external sdram. when asserted, it disables (masks) the high data byte of the sdram data bus. gpio6 bidirectional sdqmh can serve as a general-purpose i/o signal (gpio6) by setting bit [0] in the general-purpose mode register. sdqml low byte mask output this active high signal is the low byte data mask, which controls the low byte input/output buffer of the external sdram. when asserted, it disables (masks) the low data byte of the sdram data bus. srasn row address strobe output this signal is the active low row address strobe. srasn is used in conjunction with the scasn and swen outputs to form the sdram command. swen write enable output this signal is the active low write enable strobe. swen is used in conjunction with the srasn and scasn outputs to form the sdram command. 118bds page 34 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 35 audio/video decoder port these signals provide the interface between the L64118 and an external mpeg-2 audio/video decoder. this interface supports a seamless connection between the L64118 and lsi logics l64105 a/v decoders. it supports a serial data transfer rate up to 27 mbits/s in serial mode, 9 mbytes/s in parallel mode. the actual data rate is controlled by the audio and video request signals coming out from the a/v decoder device. areqn audio data request input when asserted, this signal indicates that the external a/v decoder is requesting the audio bit to be clocked in to the external a/v decoder. deassertion of areqn indicates that the a/v decoder is not ready to accept audio data. avalid audio data valid output when asserted, this signal indicates that valid audio data is available on the avd[7:0] bus. a low-to-high transition of sclk causes the audio data bit on avd to be latched in the external a/v decoder. in serial mode, avalid is active high. in parallel mode, avalid latches data on the rising edge. this signal is not asserted after reset. avd[7:0] audio video compressed data bidirectional this bus provides data to the external a/v decoder. in serial mode, avd[0] carries the data. in parallel mode, the entire bus carries the byte-wide data. the L64118 outputs pes audio and video data from the on-chip buffers and sdram buffers through avd[7:0]. these signals drive an unknown value after reset. averrn audio video data error output when asserted, this signal indicates that there is an uncorrected error in the bit stream entering the external a/v decoder. the L64118 generates averrn as a result of detection of discontinuity in the transport packets of the audio and/or video program being decoded. usually, the discontinuity is the result of loss of packets from uncorrected errors. this signal is not asserted after reset. vreqn video data request input when asserted, this signal indicates that the external a/v decoder device is requesting the video bit to be 118bds page 35 wednesday, february 3, 1999 12:37 pm
36 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) clocked in to the external a/v decoder. deassertion of vreqn indicates that the a/v decoder is not ready to accept video data. vvalid video data valid output when asserted, this signal indicates that valid video data is available on the avd line. the low-to-high transition of sclk causes the video data bit on the avd[7:0] bus to be latched in the external a/v decoder. in serial mode, vvalid is active high. in parallel mode, vvalid latches data on the rising edge. this signal is not asserted after reset. audio clock generator these signals generate the oversampling audio clock, which drives the l64105 external a/v decoder and a low-cost audio dac. the audio clock generation circuit provides oversampling audio frequencies locked to the 27 mhz program clock. the fully programmable circuit supports a wide range of oversampling audio frequencies. it is implemented using advanced mixed-signal technology. aclk audio clock output aclk provides the oversampling audio clock that drives the l64105 audio clock input and the system clock input pin of conventional stereo audio dac. this signal is driven low after reset. avdd analog vdd 3.3 v input avdd provides the power voltage to the analog circuit of the audio clock generator. it must be isolated from the digital vdd (dvdd) by a 10 m h ferrite insulator. avss analog ground input avss provides the analog ground to the audio clock generator circuit. it should must be isolated from the digital ground supply (dgnd). iref current reference this pin must be connected as shown in figure 5. 118bds page 36 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 37 figure 5 iref connection to rc devices ieee 1149.1 (jtag) port this group of signals drive the ieee1149.1 test access port (tap). tck test clock input this is the clock pin to sample the jtag input data. tdi test data in input this line is for the jtag input test data. tdo test data out output this line is for the jtag output test data. tms test mode select input this line lets you select between active and jtag mode. when in jtag mode, the i/os are serialized. active mode is for normal operation. trstn test port reset input when asserted low, this signal resets the internal jtag controller. it does not reset the chip. 18-bit dac iref dac controlled oscillator digital fsc aclk ref_div 18 16 27 mhz fsc_cntl 14 dco_div 16 0.1 m f L64118 avdd 16.9 k w 1% avss iref 118bds page 37 wednesday, february 3, 1999 12:37 pm
38 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) ieee1284 parallel port and auxiliary port these signals provide a parallel connection between the L64118 and an external peripheral device. the port complies to ieee1284 standards and supports several modes. the 1284 mode is enabled when the aux_sel bit is reset (system mode register, bit 4). this port also serves as an auxiliary port for receiving and transmitting transport bitstreams from various points in the on-chip demultiplexer pipeline. the aux mode is enabled when the aux_sel bit is set (system mode register, bit 4). the following list shows each pins functionality as an ieee1284 port and aux port signal. some of these pins also can serve as general-purpose i/o pins. ackn/auxnm 1284 - acknowledge output when the L64118 asserts this signal, valid data is latched in the L64118 ieee1284 input register. by default, this signal is not asserted after reset. aux - aux no match output in aux mode, this signal functions as auxnm to indicate that the data being sent through the auxiliary port is for a transport packet that failed pid ?ltering. autofdn/auxv 1284 - autofeed input in 1284 mode, this pin functions as the autofeed input. aux - data valid bidirectional in aux mode, this pin functions as auxv, which is used as a quali?er indicating that the data presented on the auxiliary data bus is valid. gpio14 bidirectional this signal can serve as a general-purpose i/o signal (gpio14) by setting bit 3 in the general-purpose mode register. 118bds page 38 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 39 busy/auxsb 1284 - peripheral busy bidirectional in 1284 mode, this signal functions as busy. when this signal is high, the 1284 port is not ready for a data transfer. by default, this signal is not asserted after reset. aux - sync byte bidirectional in aux mode, this signal functions as auxsb to indicate that the data being sent through the auxiliary port is the ?rst byte (sync byte) of a transport packet. gpio15 bidirectional this signal can serve as a general-purpose i/o signal (gpio15) by setting bit 3 in the general-purpose mode register. faultn/auxclk 1284 - peripheral fault operation bidirectional in 1284 mode, this signal functions as faultn. this signal indicates that the 1284 port encountered an error during operation. typically, this error is due to overrun, underrun, or parity error. aux - aux port clock bidirectional in aux mode, this signal functions as auxclk, which is the reference clock for all transactions on the auxiliary port. when the aux port is con?gured as an output port, this signal is an output with programmable frequencies of 13.5, 6.75 and 3.375 mhz. when the aux port is con?gured as an input port, this signal is an input with a frequency based on the input transport stream data rate. gpio24 bidirectional this signal can also serve as a general-purpose i/o signal (gpio24) by setting bit 3 in the general-purpose mode register. init/auxpid[2] 1284 - peripheral initialization input in 1284 mode, this signal functions as initn. when reset low, this signal resets the ieee1284 port and returns the logic to the compatibility and idle state. 118bds page 39 wednesday, february 3, 1999 12:37 pm
40 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) aux - packet id [2] output in aux mode, this signal is part of a three-bit packet id that can be assigned to pids that are output to the aux port. gpio25 bidirectional this signal can also serve as a general-purpose i/o signal (gpio25) by setting bit 3 in the general-purpose mode register. pdata[7:0] parallel i/o data signals 1284 bidirectional in 1284 mode, these signals carry the data transferred between the host and the ieee1284 port. aux bidirectional in aux mode, pdata[7:0] carry the transport packets from/to the L64118 demultiplexer and the aux port. gpio[23:16] bidirectional these signals can also serve as a general-purpose i/o bus (gpio[23:16]) by setting bit 3 in the general-purpose mode register. by default, this signal is not asserted after reset. pdata_dir/op_mode[2] 1284 - peripheral data direction output after reset, this signal serves as the pdata_dir output signal that controls the parallel data bus buffers in 1284 mode. in aux mode, this pin is driven high. operational mode 2 input this signal is used as a strap option during reset. for normal device operation, use a 10 k w to pull this signal low during reset. perror/auxpid[0] 1284 - peripheral error output in 1284 mode, this signal functions as perror. when high, this signal indicates that the L64118 ieee1284 port encountered an error during the data processing. faultn is asserted whenever perror is activated. 118bds page 40 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 41 aux - packet id [0] output in aux mode, this signal is part of a three-bit packet id that can be assigned to pids that are output to the aux port. gpio26 bidirectional this signal can also serve as a general-purpose i/o signal (gpio26) by setting bit 3 in the general-purpose mode register. select/auxpid[1] 1284 - peripheral select output when set high, this signal indicates that the L64118 ieee1284 port was selected and is connected to the host. aux - packet id [1] output in aux mode, this signal is part of a three-bit packet id that can be assigned to pids that are output to the aux port. gpio27 bidirectional this signal can also serve as a general-purpose i/o signal (gpio27) by setting bit 3 in the general-purpose mode register. selectinn/aux_adp/aux_err 1284 - peripheral selection indicator input in 1284 mode, this signal (when asserted low) indicates that the external host is attempting to select a peripheral. aux - adaptation field flag output in aux output mode, this signal functions as aux_adp, which indicates if the output byte is part of an adaptation ?eld. aux - error indicator input in aux input mode, this signal functions as aux_err, which indicates if the incoming byte is part of a packet that has an error. gpio28 bidirectional this signal can also serve as a general-purpose i/o signal (gpio28) by setting bit 3 in the general-purpose mode register. 118bds page 41 wednesday, february 3, 1999 12:37 pm
42 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) stroben/aux_tx 1284 - data strobe input in 1284 mode, this signal functions as stroben. when set low, this signal indicates that valid data is present on pdata[7:0]. L64118 latches the data on the rising edge of stroben. aux - aux port direction input in aux mode, this signal is used to specify the direction of the aux port if the pinact bit (bit 4) is set in the aux control register. if aux_tx is high, then the aux port is an output. if aux_tx is low, then the aux port is an input. gpio29 bidirectional this signal can also serve as a general-purpose i/o signal (gpio29) by setting bit 3 in the general-purpose mode register. i 2 c-compatible port these signals connect the L64118 to an external i 2 c device. the L64118 uses them to initialize external devices in the system that have this interface. scl serial clock bidirectional scl provides the clock signal for transmitting and receiving data through sda. sda serial data bidirectional sda provides the data connection to the i 2 c-compatible port. data is transmitted and received through this line according to the i 2 c protocol. this signal should be pulled high by an external pull-up resistor. 118bds page 42 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 43 teletext port these signals connect the L64118 to an external ntsc/pal video encoder with a teletext port. ttxdata teletext data master output this signal supplies the teletext data to the external video encoder. the L64118 outputs teletext data when ttxreq is asserted and there are enough bits in the teletext output buffer to supply one complete teletext line. by default, this signal is not asserted after reset. gpio13 bidirectional ttxdata can serve as a general-purpose i/o signal (gpio13) by setting bit 2 in the general-purpose mode register. ttxreq teletext data request master input when set high, this signal indicates that the external video encoder device requests teletext data to be transferred through ttxdata. the L64118 outputs teletext data on the ttxdata pin as long as ttxreq is asserted. you must program the video encoder device so the length of assertion of ttxreq is compatible with the exact number of teletext bits per line. the L64118 teletext port supports a direct connection to the teletext port of ntsc/pal video encoders. during normal opera- tion, this is an input signal. by default, this signal is not asserted after reset. gpio12 bidirectional ttxreq can serve as a general-purpose i/o signal (gpio12) by setting bit 2 in the general-purpose mode register. smartcard port these signals provide the connection between the L64118 and external smartcard devices. these signals are used by the L64118 to initialize external devices in a system with such a port. the L64118 supports two independent smartcard devices. 118bds page 43 wednesday, february 3, 1999 12:37 pm
44 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) sc0_c4 smartcard 0 pin 4 bidirectional this signal is connected to the c4 pin on the smartcard. this signal should be pulled up by an external pull-up resistor after reset. sc0_c8 smartcard 0 pin 8 bidirectional this signal is connected to the c8 pin on the smartcard. this signal should be pulled up by an external pull-up resistor after reset. sc0_clk smartcard 0 clock output this signal is the output clock for smartcard 0. gpio33 bidirectional sc0_clk can serve as a general-purpose i/o signal (gpio33) by setting bit 4 in the general-purpose mode register. by default, this signal is not asserted after reset. sc0_detect smartcard 0 detect input when high, this signal indicates that a card is inserted in slot 0. gpio31 bidirectional sc0_detect can serve as a general-purpose i/o signal (gpio31) by setting bit 4 in the general-purpose mode register. by default, this signal ?oats after reset. sc0_i/o smartcard 0 i/o bidirectional this signal transfers data (using the coupler) between smartcard 0 and the smartcard port of the L64118. it is open-drain. this signal must be pulled up by an external resistor after reset. sc0_rstn smartcard 0 reset output this signal resets smartcard 0. gpio30 bidirectional sc0_rstn can serve as a general-purpose i/o signal (gpio30) by setting bit 4 in the general-purpose mode register. by default, this signal is not asserted after reset. 118bds page 44 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 45 sc0_vcc_enn smartcard 0 vcc enable output this signal turns the power supply of smartcard 0 on or off. when low, it enables the vcc supply. gpio32 bidirectional sc0_vcc_enn can serve as a general-purpose i/o signal (gpio32) by setting bit 4 in the general-purpose mode register. by default, this signal is not asserted after reset. sc0_vpp_enn smartcard 0 vpp enable output this signal turns the power supply of smartcard 0 on or off. when low, it enables the vcc supply. gpio34 bidirectional sc0_vpp_enn can serve as a general-purpose i/o signal (gpio34) by setting bit 4 in the general-purpose mode register. by default, this signal is not asserted after reset. sc1_clk smartcard 1 clock output this signal clocks the output of smartcard1. gpio38 bidirectional sc1_clk can serve as a general-purpose i/o signal (gpio38) by setting bit 5 in the general-purpose mode register. by default, this signal is not asserted after reset. sc1_detect smartcard 1 detect input when high, this signal indicates that a card is inserted in slot 1. gpio36 bidirectional sc1_clk can serve as a general-purpose i/o signal (gpio36) by setting bit 5 in the general-purpose mode register. by default, this signal ?oats after reset. 118bds page 45 wednesday, february 3, 1999 12:37 pm
46 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) sc1_i/o smartcard 1 i/o bidirectional this signal transfers the data (using the coupler) between smartcard1 and the smartcard port of the L64118. it is open-drain. this signal must be pulled up by an external resistor after reset. sc1_rstn smartcard 1 reset output this signal resets smartcard1. gpio35 bidirectional sc1_rstn can serve as a general-purpose i/o signal (gpio35) by setting bit 5 in the general-purpose mode register. by default, this signal is not asserted after reset. sc1_vcc_enn smartcard 1 vcc enable output this signal turns the power supply of smartcard1 on or off. when low, it enables the vcc supply. gpio37 bidirectional sc1_vcc_enn can serve as a general-purpose i/o signal (gpio37) by setting bit 5 in the general-purpose mode register. by default, this signal is not asserted after reset. sc1_vpp_enn smartcard 1 vpp enable output this signal turns the power supply of smartcard 0 on or off. when low, it enables the vpp pin. gpio39 bidirectional sc1_vpp_enn can serve as a general-purpose i/o signal (gpio39) by setting bit 4 in the general-purpose mode register. by default, this signal is not asserted after reset. 118bds page 46 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 47 infrared port these signals provide the connection between the L64118 and an external infrared receiver and transmitter. irbl infrared blaster output this signal is the infrared blaster output. this signal can be con?gured to re?ect the value of the infrared transmitter output. gpio47 bidirectional irbl can serve as a general-purpose i/o signal (gpio47) by setting bit 7 in the general-purpose mode register. by default, this signal ?oats after reset. irrx0 infrared receiver 0 input this signal serves as the receive port for the demodulated signal of one of the two infrared receivers ports. gpio40 bidirectional irrx0 can serve as a general-purpose i/o signal (gpio40) by setting bit 7 in the general-purpose mode register. by default, this signal ?oats after reset. irrx1 infrared receiver 1 input this signal serves as the receive port for the demodulated signal of one of the two infrared receivers ports. gpio41 bidirectional irrx1 can serve as a general-purpose i/o signal (gpio41) by setting bit 7 in the general-purpose mode register. by default, this signal ?oats after reset. 118bds page 47 wednesday, february 3, 1999 12:37 pm
48 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) irtx infrared transmitter output this signal serves as the infrared transmitter output. gpio44 bidirectional irrx1 can serve as a general-purpose i/o signal (gpio44) by setting bit 7 in the general-purpose mode register. by default, this signal ?oats after reset. general-purpose pins the general-purpose i/o signals for the L64118 let you control and monitor various external events. these signals consist of eight groups. group 7 contains dedicated gpio signals, whereas the other groups multiplex the gpio signals with other functions. note that all pins within a gpio group must be enabled or disabled as a group; however, individual gpio pins can be con?gured as inputs or outputs using the general-purpose control register. the gpio groups and associated pins are listed in table 5 through table 12. table 5 group 1: ebus signals pin name gpio signal 1 1. the gpio3 and gpio5 signals are not available on the L64118. csn[4] gpio1 ben[2] gpio2 ben[3] gpio4 sdqmh gpio6 118bds page 48 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 49 table 6 group 2: sio signals pin name gpio signal ctsn0 gpio7 dtrn0 gpio8 dsrn0 gpio9 rtsn0 gpio10 rxdn0 gpio11 table 7 group 3: teletext signals pin name gpio signal ttxreq gpio12 ttxdata gpio13 table 8 group 4: pio (ieee 1284) signals pin name gpio signal autofdn gpio14 busy gpio15 pdata[7:0] gpio[23:16] faultn gpio24 initn gpio25 perror gpio26 select gpio27 selectinn gpio28 stroben gpio29 118bds page 49 wednesday, february 3, 1999 12:37 pm
50 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) table 9 group 5: smartcard 0 signals pin name gpio signal sc0_rstn gpio30 sc0_detect gpio31 sc0_vcc_en gpio32 sc0_clk gpio33 sc0_vpp_enn gpio34 table 10 group 6: smartcard 1 signals pin name gpio signal sc1_rstn gpio35 sc1_detect gpio36 sc1_vcc_enn gpio37 sc1_clk gpio38 sc1_vpp_enn gpio39 table 11 group 8: infrared signals pin name gpio signal irrx0 gpio[40] irrx1 gpio[41] irtx gpio[44] irbl gpio[47] 118bds page 50 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 51 gpio[49, 48, 46, 45, 43, 42] dedicated gpio bidirectional these are the dedicated general-purpose i/o signals. by default, these signals ?oat after reset. note that for lsi logic manufacturing test purposes, gpio46 must be pulled high during reset. programming the general-purpose pins to use a general-purpose pin, enable the entire group by writing to the general-purpose mode register; then select the input/output for each pin within the group by writing to the speci?c general-purpose control register. (note that no group has more than 16 general-purpose pins.) after each pin is de?ned, the programmer can read the value of the gpio signal using the general-purpose data registers, or write the value of a gpio signal to the general-purpose data registers. latency of gpio updates the use of the gpio pins is intended for controlling/monitoring external logic by the software. you should consider a delay between the time when the software writes a value to a general-purpose output pin and the time the value is valid on the output pin. this delay is caused by the transaction time between the on-chip processor to the on-chip peripheral component, and the delay time of the general-purpose module. the delay that the general-purpose module inserts in writing to an output general-purpose pin is not more than 1 m s (for sclk = 27 mhz). table 12 group 7: dedicated gpio signals pin name gpio signal gpio[43:42] gpio[43:42] gpio[46:45] gpio[46:45] gpio[49:48] gpio[49:48] 118bds page 51 wednesday, february 3, 1999 12:37 pm
52 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) when the processor reads a value from a general-purpose pin con?gured to be an input pin, there is no extra delay inserted; however, the register holding general-purpose input values is updated every 2 m s (for sclk = 27 mhz). electrical requirements this section speci?es the electrical requirements for the L64118. five tables list electrical data in the following categories: absolute maximum ratings (table 13) recommended operating conditions (table 14) capacitance (table 15) dc characteristics (table 16) pin description summary (table 17) the following tables provide the maximum ratings, operating conditions, and capacitances for the 3.3 v, g10-p implementation of the L64118. table 13 absolute maximum ratings symbol parameter limits 1 1. referenced to v ss . unit v dd dc supply - 0.3 to + 3.9 v v in 5 v compatible input voltage - 1.0 to 6.0 v v in 3.3 v input voltage - 0.8 to 4.7 v i in dc input current 10 ma t stgp storage temperature range (plastic) - 40 to + 125 c 118bds page 52 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 53 table 14 recommended operating conditions symbol parameter limits unit v dd dc supply + 3.0 to + 3.6 v t a ambient temperature 0 to + 70 c table 15 capacitance symbol parameter 1 1. measurement conditions are v in = tbd v, t a =25 c, and clock frequency = 1 mhz. min typ max units c in input capacitance 5.0 C C pf c out output capacitance 5.0 C C pf c io i/o bus capacitance 5.0 C C pf 118bds page 53 wednesday, february 3, 1999 12:37 pm
54 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) table 16 dc characteristics symbol parameter condition 1 1. speci?ed at v dd equals 3.3 v 5% at ambient temperature over the speci?ed range. min typ max units v il voltage input low ttl cmos C C C C 0.8 0.2 v dd v v v ih voltage input high ttl cmos 5 v compatible 2.0 0.7 v dd 2.0 C C C C C 5.5 v v v v ol voltage output low 2-ma output buffers 4-ma output buffers 6-ma output buffers i ol = 2.0 ma i ol = 4.0 ma i ol = 6.0 ma C C C 0.2 0.2 0.2 0.4 0.4 0.4 v v v v oh voltage output high 2-ma output buffers 4-ma output buffers 6-ma output buffers i oh = - 2.0 ma i oh = - 4.0 ma i oh = - 6.0 ma 2.4 2.4 2.4 C C C C C C v v v i il current input leakage 2 with pulldown with pullup 2. for cmos and tll inputs. v in =v dd or v ss v in =v dd v in =v ss - 10 35 - 214 10 115 - 115 +10 222 - 35 m a m a m a i oz current 3-state output leakage v dd = max, v out =v ss or v dd - 10 1+10 m a i osp4 current p-channel output short circuit (4-ma output buffers) 3, 4 3. not more than one output may be shorted at a time for a maximum duration of one second. 4. these values scale proportionally for output buffers with different drive strengths. v dd = max, v out =v ss - 117 - 75 - 40 ma i osn4 current n-channel output short circuit (4-ma output buffers) 3, 4 v dd = max, v out =v dd 37 90 140 ma i dd quiescent supply current v in =v dd or v ss =0ma 10 10 10 ma i dd dynamic supply current v in =v ih or v il = 27 mhz 215 215 215 ma 118bds page 54 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 55 table 17 pin description summary mnemonic description type 1 drive (ma) active 2 pull-up/ down ackn/ auxnm 1284 acknowledge aux no match output output 6 6 low high C aclk audio clock output 4 C C ad[31:0] ebus address/data bidirectional 8 C C addr[7:0] ebus address/data bidirectional 8 C C ad[15:0] ebus address/data bidirectional 8 C C areqn audio data request input C low u 3 ale ebus address latch enable output 8 low C autofdn/ auxv gpio14 1284 auto feed aux data valid general-purpose io 14 input bidirectional bidirectional C 6 6 low C avalid audio data valid output 6 high C avd[7:0] audio/video data bidirectional 6 C C avdd analog power input C C C averrn audio/video error output 2 low C avss analog ground input C C C ben[1:0] ebus byte enable bidirectional 8 low C ben[3:2] gpio[3:2] ebus byte enable output bidirectional 6 6 low C busy/ auxsb gpio15 1284 busy aux sync byte general-purpose io 15 bidirectional 6 low C cclk channel data clock input C C C cdata[7:0] channel data input C C C cerrn channel data error input C low u cpu_clk ebus clock output output 6 low C csn[3:0] ebus chip select output 8 low C 118bds page 55 wednesday, february 3, 1999 12:37 pm
56 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) csn[4] gpio1 ebus chip select general-purpose io 1 output bidirectional 6 6 low C csn[5] / memstbn ebus chip select memory strobe output 6 low C ctsn0 gpio7 clear to send (sio 0) general-purpose i/o 7 input bidirectional C 6 low u ctsn1 iceclk clear to send (sio 1) serial ice clock input C low u cvalid channel data enable input C high d 4 dsrn0 gpio9 data send ready (sio 0) general-purpose i/o 9 input bidirectional C 6 low u dtrn0 gpio8 data terminal ready (sio 0) general-purpose i/o 8 output bidirectional 6 6 low C eackn ebus data acknowledge input C low u eclk pll test clock input C C C faultn/ auxclk gpio24 1284 fault aux port clock general-purpose i/o 24 bidirectional 6 low C gpio[42:43] general-purpose i/o bidirectional 4 C C gpio[46:45] general-purpose i/o bidirectional 4 C u gpio[48:49] general-purpose i/o bidirectional 4 C C iddtn test pin input C high C initn/ auxpid[2] gpio25 1284 initialization auxpacketid2 general-purpose i/o 25 input output bidirectional C 6 6 low C intn[3:0] interrupt input C low u intn4 interrupt bidirectional (open drain) 6low C irbl gpio47 ir blaster general-purpose i/o 47 output bidirectional 4 4 high C table 17 pin description summary (cont.) mnemonic description type 1 drive (ma) active 2 pull-up/ down 118bds page 56 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 57 iref current reference C C C C irrx0 gpio40 ir receiver port 0 general-purpose i/o 40 input bidirectional C 4 CC irrx1 gpio41 ir receiver port 1 general-purpose i/o 41 input bidirectional C 4 CC irtx gpio44 ir transmitter port general-purpose i/o 44 output bidirectional 4 4 CC op_mode[1:0] operational mode input C C C pdata[7:0] 1284 data bidirectional 4 C C pdata_dir / op_mode[2] 1284 data direction or operational mode[2] output input 6 C CC perror/ auxpid[0] gpio26 1284 peripheral error aux packet id [0] general-purpose i/o 26 output output bidirectional 6 6 6 high C pllvdd pll analog vdd input C C C pllvss pll analog vss input C C C rclk uart receive clock (sio 0) input 4 C C rdn ebus read strobe output 8 low u resetn reset input (schmitt trigger) Clow u rtsn0 gpio10 request to send (sio 0) general-purpose i/o 10 output bidirectional 6 6 low C rtsn1 request to send (sio 1) output 6 low C rxd0 gpio11 receive data (sio 0) general-purpose i/o 11 input bidirectional C 6 Cu rxd1/ ice_rx receive data (sio 1) receive data serial ice port input 4 C u rxd2 receive data (sio 2) input C C u sa[11:0] sdram address bus output 6 C C table 17 pin description summary (cont.) mnemonic description type 1 drive (ma) active 2 pull-up/ down 118bds page 57 wednesday, february 3, 1999 12:37 pm
58 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) sba[0] sdram bank select 0 output 6 C C sba[1] sdram bank select 1 output 6 C C sbd[15:0] sdram data bus bidirectional 6 C C sc0_c4 smartcard 0 c4 bidirectional (open drain) 6C C sc0_c8 smartcard 0 c8 bidirectional (open drain) 6C C sc0_clk gpio33 smartcard 0 clock general-purpose i/o 33 output bidirectional 6 6 CC sc0_detect gpio31 smartcard 0 detect general-purpose i/o 31 input bidirectional 4 high C sc0_i/o smartcard 0 data bidirectional (open drain) 6C C sc0_rstn gpio30 smartcard 0 reset general-purpose i/o 30 output bidirectional 4 4 low C sc0_vcc_enn gpio32 smartcard 0 vcc enable general-purpose i/o 32 output bidirectional 4 4 low C sc0_vpp_enn gpio34 smartcard 0 vpp enable general-purpose i/o 34 output bidirectional 4 4 low C sc1_clk gpio38 smartcard 1 clock general-purpose i/o 38 output bidirectional 6 6 CC sc1_detect gpio36 smartcard 1 detect general-purpose i/o 36 input bidirectional C 4 high C sc1_i/o smartcard 1 data bidirectional (open drain) 6C C sc1_rstn gpio35 smartcard 1 reset general-purpose i/o 35 output bidirectional 4 4 low C sc1_vcc_enn gpio37 smartcard 1 vcc enable general-purpose i/o 37 output bidirectional 4 4 low C sc1_vpp_enn gpio39 smartcard 1 vpp enable general-purpose i/o 39 output bidirectional 4 4 low C table 17 pin description summary (cont.) mnemonic description type 1 drive (ma) active 2 pull-up/ down 118bds page 58 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 59 scasn sdram column address strobe output 8 low C scl i 2 c clock bidirectional (open drain) 8C C sclk system clock (27 mhz) input C C C sda i 2 c data bidirectional (open drain) 8C C sdclk sdram master clock output 6 C C sdet sigma-delta control voltage output output (open drain) 6C d sdqmh gpio6 sdram data mask high byte general-purpose i/o 6 output bidirectional 8 8 high C sdqml sdram data mask low byte output 4 C C select/ auxpid[1] gpio27 1284 selection aux packet id [1] output output bidirectional 6 6 6 low C selectinn/ aux_adp/ aux_err gpio28 1284 selection indicator aux adaptation field flag aux error indicator general-purpose i/o 28 input output input bidirectional C 6 C 6 low C srasn sdram row address strobe output 4 low C stroben/ aux_tx gpio29 1284 data strobe aux port direction general-purpose i/o 29 input input bidirectional C C 4 low C swen sdram write enable output 6 low C tclk uart transmit clock (sio 0) input 8 low u tck jtag scan clock input C C C tdi jtag scan in input C C C tdo jtag scan out output (3-state) 4C C tms jtag mode input C C C table 17 pin description summary (cont.) mnemonic description type 1 drive (ma) active 2 pull-up/ down 118bds page 59 wednesday, february 3, 1999 12:37 pm
60 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) trst jtag reset input C high d ttxdata gpio13 teletext data general-purpose i/o 13 output bidirectional 6 6 Cu ttxreq gpio12 teletext request general-purpose i/o 12 input bidirectional C 6 high d txd0 transmit data (sio 0) output 6 C C txd1 ice_tx transmit data (sio 1) transmit data serial iceport output 6 C C txd2 transmit data (sio 2) output 6 C C vdd power C C C C vreqn video data request input C low u vss ground C C C C vvalid video data valid output 6 high C wrn ebus write strobe output 8 low u ztestn test pin input C low u 1. if only one pin type is listed, it applies to all possible pin con?gurations. 2. if only active state (low or high) is listed, it applies to all possible pin con?gurations. 3. the internal pull-up resistor value is from 50C100 k w 4. the internal pull-down resistor value is from 50C100 k w table 17 pin description summary (cont.) mnemonic description type 1 drive (ma) active 2 pull-up/ down 118bds page 60 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 61 packaging and pinouts figure 6 shows the signal solder balls of the L64118. this diagram shows the location, ball number, and signal for each solder ball on the 256-pin plastic ball grid array (pbga) package (package code if). this pinout drawing is followed by: a listing of the solder balls in numerical order for the L64118 (table 18) a listing of the solder balls in alphabetic order for the L64118 (table 19) mechanical drawings that provide the dimensions of the L64118 (figure 7) note: all drawings in this section use the same origin. in other words, solder ball a1 in figure 6 and figure 7 are the same. 118bds page 61 wednesday, february 3, 1999 12:37 pm
62 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) figure 6 L64118 256-pin pbga pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 abcdefghjklmnprtu vw y vss aclk irtx irbl gpio48 gpio45/ rclk cdata[4] trst gpio43 cdata[0] sdet avd[6] avd[5] avd[3] tdi rxd2 nc nc averrn sc0_vpp_ enn nc nc pllvdd iref sa[1] sa[4] sa[6] sa[9] sba[1] sdqmh sdqml sbd[13] sbd[9] sbd[6] sbd[3] ttxreq ctsn0 nc rtsn0 rxd0 nc avdd ztestn sa[2] sa[5] sa[8] sba[0] swen sbd[14] sbd[12] sbd[8] sbd[5] sbd[2] ttxdata dtrn0 tclk ctsn1 pdata_ dir/op_ mode[2] irrx0 nc nc avss sdclk sa[3] sa[7] sa[11] scasn sbd[15] sbd[11] sbd[7] sbd[4] sbd[0] dsrn0 nc nc nc rtsn1 gpio42 nc vss vdd sa[0] sa[10] srasn vdd sbd[10] pllvss vss vss sbd[1] vdd txd0 vss nc nc txd1 cerrn eclk cvalid cdata[6] cdata[7] cdata[1] cdata[5] cdata[2] cdata[3] vdd cclk gpio46 vss gpio49 iddtn nc sclk vdd txd2 tck op_ mode[0] avd[7] tms avd[4] tdo avd[2] vss op_ mode[1] avd[0] vvalid avd[1] avalid vdd vreqn areqn nc nc nc nc nc sc0_ rstn sc0_ clk sc0_ detect sc0_c4 sc0_c8 rxd1 nc faultn busy vdd select ackn pdata[1] perror pdata[0] pdata[2] pdata[3] pdata[4] pdata[5] pdata[6] vss pdata[7] select- inn initn autofdn stroben sda scl intn4 vdd intn2 intn1 intn3 csn2 intn0 csn1 csn0 csn4 csn3 vss csn5/ mem- stbn cpu_clk ben2 ben3 resetn vdd wrn ben0 ben1 ad[30] eackn ale rdn ad[31] vss nc nc nc nc nc nc nc nc nc nc ad[26] ad[28] nc nc vss sc0_ enn vcc_ vdd sc1_io vss ad[8] vdd addr[1] addr[5] vss ad[23] vdd ad[29] sc0_io sc1_ enn vpp_ sc1_clk ad[14] ad[11] ad[7] ad[3] ad[13] ad[12] ad[10] ad[9] ad[5] ad[6] ad[4] ad[2] ad[1] ad[0] addr[0] addr[4] addr[3] addr[2] addr[6] addr[7] ad[16] ad[20] ad[18] ad[17] ad[24] ad[21] ad[19] ad[27] ad[25] ad[22] sc1_ rstn sc1_ detect sc1_ enn vcc_ ad[15] irrx1 118bds page 62 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 63 table 18 L64118 solder ball matrix list u18 nc v18 nc w18 nc y18 ad[28] a19 rtsn0 b19 ctsn1 c19 nc d19 nc e19 faultn f19 ackn g19 pdata[2] h19 pdata[5] j19 initn k19 scl l19 intn1 m19 csn0 n19 csn4 p19 ben3 r19 ben0 t19 ale u19 nc v19 nc w19 nc y19 nc a20 rxd0 b20 pdata_dir/ op_mode[2] c20 rtsn1 d20 txd1 e20 busy f20 pdata[1] g20 pdata[3] h20 pdata[6] j20 autofdn k20 intn4 l20 intn3 m20 intn0 n20 csn3 p20 resetn r20 ben1 t20 rdn u20 ad[31] v20 nc w20 nc y20 nc solder signal ball solder signal ball a1 vss b1 aclk c1 gpio43 d1 irtx e1 irbl f1 gpio48 g1 gpio45/rclk h1 cdata[0] j1 cdata[4] k1 trst l1 sdet m1 avd[6] n1 avd[5] p1 avd[3] r1 tdi t1 rxd2 u1 nc v1 nc w1 averrn y1 sc0_vpp_enn a2 nc b2 nc c2 irrx0 d2 gpio42 e2 cerrn f2 cdata[6] g2 cdata[7] h2 cdata[1] j2 cdata[5] k2 nc l2 txd2 m2 avd[7] n2 tdo p2 op_mode[1] r2 avd[1] t2 irrx1 u2 nc v2 nc w2 nc y2 sc0_detect a3 pllvdd b3 nc c3 nc d3 nc e3 eclk f3 cdata[3] g3 cdata[2] h3 gpio46 j3 gpio49 k3 sclk l3 tck m3 tms n3 avd[2] p3 avd[0] r3 avalid t3 vreqn u3 nc v3 nc w3 sc0_rstn y3 sc0_c4 a4 iref b4 avdd c4 nc d4 vss e4 cvalid f4 vdd g4 cclk h4 vss j4 iddtn k4 vdd l4 op_mode[0] m4 avd[4] n4 vss p4 vvalid r4 vdd t4 areqn u4 vss v4 sc0_io w4 sc0_clk y4 sc0_c8 a5 sa[1] b5 ztestn c5 avss d5 pllvss u5 sc0_vcc_enn v5 sc1_vpp_enn w5 sc1_rstn y5 sc1_detect a6 sa[4] b6 sa[2] c6 sdclk d6 vdd u6 vdd v6 sc1_clk w6 sc1_vcc_enn y6 ad[15] a7 sa[6] b7 sa[5] c7 sa[3] d7 sa[0] u7 sc1_io v7 ad[14] w7 ad[13] y7 ad[12] a8 sa[9] b8 sa[8] c8 sa[7] d8 vss u8 vss v8 ad[11] w8 ad[10] y8 ad[9] a9 sba[1] b9 sba[0] c9 sa[11] d9 sa[10] u9 ad[8] v9 ad[7] w9 ad[6] y9 ad[5] a10 sdqmh b10 swen c10 scasn d10 srasn u10 vdd v10 ad[3] w10 ad[4] y10 ad[2] a11 sdqml b11 sbd[14] c11 sbd[15] d11 vdd u11 addr[1] v11 addr[0] w11 ad[0] y11 ad[1] a12 sbd[13] b12 sbd[12] c12 sbd[11] c12 sbd[10] u12 addr[5] v12 addr[4] w12 addr[3] y12 addr[2] a13 sbd[9] b13 sbd[8] c13 sbd[7] d13 vss u13 vss v13 ad[16] w13 addr[7] y13 addr[6] a14 sbd[6] b14 sbd[5] c14 sbd[4] d14 sbd[1] u14 ad[23] v14 ad[20] w14 ad[18] y14 ad[17] a15 sbd[3] b15 sbd[2] c15 sbd[0] d15 vdd u15 vdd v15 ad[24] w15 ad[21] y15 ad[19] a16 ttxreq b16 ttxdata c16 dsrn0 d16 txd0 u16 ad[29] v16 ad[27] w16 ad[25] y16 ad[22] a17 ctsn0 b17 dtrn0 c17 nc d17 vss e17 rxd1 f17 vdd g17 perror h17 vss j17 pdata[7] k17 stroben l17 vdd m17 csn2 n17 vss p17 cpu_clk r17 vdd t17 ad[30] u17 vss v17 nc w17 nc y17 ad[26] a18 nc b18 tclk c18 nc d18 nc e18 nc f18 select g18 pdata[0] h18 pdata[4] j18 selectinn k18 sda l18 intn2 m18 csn1 n18 csn5/memstbn p18 ben2 r18 wrn t18 eackn solder signal ball solder signal ball solder signal ball 118bds page 63 wednesday, february 3, 1999 12:37 pm
64 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) table 19 L64118 alphabetical signal list select f18 selectinn j18 srasn d10 stroben k17 swen b10 tck l3 tclk b18 tdi r1 tdo n2 tms m3 trst k1 ttxdata b16 ttxreq a16 txd0 d16 txd1 d20 txd2 l2 vdd f4 vdd k4 vdd r4 vdd d6 vdd u6 vdd u10 vdd d11 vdd d15 vdd u15 vdd f17 vdd l17 vdd r17 vreqn t3 vss a1 vss d4 vss h4 vss n4 vss u4 vss d8 vss u8 vss d13 vss u13 vss d17 vss h17 vss n17 vss u17 vvalid p4 wrn r18 ztestn b5 signal solder ball signal solder ball ackn f19 aclk b1 ad[0] w11 ad[10] w8 ad[11] v8 ad[12] y7 ad[13] w7 ad[14] v7 ad[15] y6 ad[16] v13 ad[17] y14 ad[18] w14 ad[19] y15 ad[1] y11 ad[20] v14 ad[21] w15 ad[22] y16 ad[23] u14 ad[24] v15 ad[25] w16 ad[26] y17 ad[27] v16 ad[28] y18 ad[29] u16 ad[2] y10 ad[30] t17 ad[31] u20 ad[3] v10 ad[4] w10 ad[5] y9 ad[6] w9 ad[7] v9 ad[8] u9 ad[9] y8 addr[0] v11 addr[1] u11 addr[2] y12 addr[3] w12 addr[4] v12 addr[5] u12 addr[6] y13 addr[7] w13 ale t19 areqn t4 autofdn j20 avalid r3 avd[0] p3 avd[1] r2 avd[2] n3 avd[3] p1 avd[4] m4 avd[5] n1 avd[6] m1 avd[7] m2 avdd b4 averrn w1 avss c5 ben0 r19 ben1 r20 ben2 p18 ben3 p19 busy e20 cclk g4 cdata[0] h1 cdata[1] h2 cdata[2] g3 cdata[3] f3 cdata[4] j1 cdata[5] j2 cdata[6] f2 cdata[7] g2 cerrn e2 cpu_clk p17 csn0 m19 csn1 m18 csn2 m17 csn3 n20 csn4 n19 csn5/memstbn n18 ctsn0 a17 ctsn1 b19 cvalid e4 dsrn0 c16 dtrn0 b17 eackn t18 eclk e3 faultn e19 gpio42 d2 gpio43 c1 gpio45/rclk g1 gpio46 h3 gpio48 f1 gpio49 j3 iddtn j4 initn j19 intn0 m20 intn1 l19 intn2 l18 intn3 l20 intn4 k20 irbl e1 iref a4 irrx0 c2 irrx1 t2 irtx d1 nc u1 nc v1 nc a2 nc b2 nc k2 nc u2 nc v2 nc w2 nc b3 nc c3 nc d3 nc u3 nc v3 nc c4 nc c17 nc v17 nc w17 nc a18 nc c18 nc d18 nc e18 nc u18 nc v18 nc w18 nc c19 nc d19 nc u19 nc v19 nc w19 nc y19 nc v20 nc w20 nc y20 op_mode[0] l4 op_mode[1] p2 pdata[0] g18 pdata[1] f20 pdata[2] g19 pdata[3] g20 pdata[4] h18 pdata[5] h19 pdata[6] h20 pdata[7] j17 pdata_dir/ op_mode[2] b20 perror g17 pllvdd a3 pllvss d5 rdn t20 resetn p20 rtsn0 a19 rtsn1 c20 rxd0 a20 rxd1 e17 rxd2 t1 sa[0] d7 sa[10] d9 sa[11] c9 sa[1] a5 sa[2] b6 sa[3] c7 sa[4] a6 sa[5] b7 sa[6] a7 sa[7] c8 sa[8] b8 sa[9] a8 sba[0] b9 sba[1] a9 sbd[0] c15 sbd[10] c12 sbd[11] c12 sbd[12] b12 sbd[13] a12 sbd[14] b11 sbd[15] c11 sbd[1] d14 sbd[2] b15 sbd[3] a15 sbd[4] c14 sbd[5] b14 sbd[6] a14 sbd[7] c13 sbd[8] b13 sbd[9] a13 sc0_c4 y3 sc0_c8 y4 sc0_clk w4 sc0_detect y2 sc0_io v4 sc0_rstn w3 sc0_vcc_enn u5 sc0_vpp_enn y1 sc1_clk v6 sc1_detect y5 sc1_io u7 sc1_rstn w5 sc1_vcc_enn w6 sc1_vpp_enn v5 scasn c10 scl k19 sclk k3 sda k18 sdclk c6 sdet l1 sdqmh a10 sdqml a11 signal solder ball signal solder ball signal solder ball 118bds page 64 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 65 figure 7. 256-pin pbga package (if) mechanical drawing md98.if impor tant: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code if. 118bds page 65 wednesday, february 3, 1999 12:37 pm
66 L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) notes 118bds page 66 wednesday, february 3, 1999 12:37 pm
L64118 mpeg-2 transport controller with embedded mips cpu (tr4101) 67 notes 118bds page 67 wednesday, february 3, 1999 12:37 pm
to receive product literature, call us at 1-800-574-4286 (u.s. and canada); +32.11.300.531 (europe); 408.433.7700 (outside u.s., canada, and europe) and ask for department jds; or visit us at http://www.lsilogic.com lsi logic corporation reserves the right to make changes to any products and services herein at any time without notice. lsi logic does not assume any responsibility or lia- bility arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase, lease, or use of a product or service from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or of third parties. this document is preliminary. as such, it contains data derived from functional simulations and performance estimates. lsi logic has not veri?ed the functional descriptions or electrical and mechanical speci?cations using production parts. lsi logic logo design, g10, and coreware are registered trademarks and tinyrisc is a trademark of lsi logic corporation. all other brand and product names may be trademarks of their respective companies. printed in usa order no. i15038 doc. no. db08-000109-01 printed on recycled paper iso 9000 certified sales of?ces and design resource centers lsi logic corporation corporate headquarters tel: 408.433.8000 fax: 408.433.8989 north america california irvine tel: 714.553.5600 fax: 714.474.8101 san diego tel: 619.613.8300 fax: 619.613.8350 wireless design center tel: 619.350.5560 fax: 619.350.0171 silicon valley tel: 408.433.8000 fax: 408.954.3353 colorado boulder tel: 303.447.3800 fax: 303.541.0641 florida boca raton tel: 561.989.3236 fax: 561.989.3237 illinois schaumburg tel: 847.995.1600 fax: 847.995.1622 kentucky bowling green tel: 502.793.0010 fax: 502.793.0040 maryland bethesda tel: 301.897.5800 fax: 301.897.8389 massachusetts waltham tel: 781.890.0180 fax: 781.890.6158 minnesota minneapolis tel: 612.921.8300 fax: 612.921.8399 new jersey edison tel: 732.549.4500 fax: 732.549.4802 new york new york tel: 716.223.8820 fax: 716.223.8822 north carolina raleigh tel: 919.785.4520 fax: 919.783.8909 oregon beaverton tel: 503.645.0589 fax: 503.645.6612 texas austin tel: 512.388.7294 fax: 512.388.4171 dallas tel: 972.509.0350 fax: 972.509.0349 houston tel: 281.379.7800 fax: 281.379.7818 washington issaquah tel: 425.837.1733 fax: 425.837.1734 canada ontario ottawa tel: 613.592.1263 fax: 613.592.3253 toronto tel: 416.620.7400 fax: 416.620.5005 quebec montreal tel: 514.694.2417 fax: 514.694.2699 international australia new south wales reptechnic pty ltd tel: 612.9953.9844 fax: 612.9953.9683 china beijing lsi logic international services inc tel: 86.10.6804.2534.40 fax: 86.10.6804.2521 denmark ballerup lsi logic development centre tel: 45.44.86.55.55 fax: 45.44.86.55.56 france paris lsi logic s.a. immeuble europa tel: 33.1.34.63.13.13 fax: 33.1.34.63.13.19 germany munich lsi logic gmbh tel: 49.89.4.58.33.0 fax: 49.89.4.58.33.108 stuttgart tel: 49.711.13.96.90 fax: 49.711.86.61.428 hong kong hong kong avt industrial ltd tel: 852.2428.0008 fax: 852.2401.2105 india bangalore logicad india private ltd tel: 91.80.526.2500 fax: 91.80.338.6591 israel ramat hasharon lsi logic tel: 972.3.5.480480 fax: 972.3.5.403747 netanya vlsi development centre tel: 972.9.657190 fax: 972.9.657194 italy milano lsi logic s.p.a. tel: 39.039.687371 fax: 39.039.6057867 japan tokyo lsi logic k.k. tel: 81.3.5463.7821 fax: 81.3.5463.7820 osaka tel: 81.6.947.5281 fax: 81.6.947.5287 korea seoul lsi logic corporation of korea ltd tel: 82.2.528.3400 fax: 82.2.528.2250 the netherlands eindhoven lsi logic europe ltd tel: 31.40.265.3580 fax: 31.40.296.2109 singapore singapore lsi logic pte ltd tel: 65.334.9061 fax: 65.334.4749 sweden stockholm lsi logic ab tel: 46.8.444.15.00 fax: 46.8.750.66.47 switzerland brugg/biel lsi logic sulzer ag tel: 41.32.536363 fax: 41.32.536367 taiwan taipei lsi logic asia-paci?c tel: 886.2.2718.7828 fax: 886.2.2718.8869 avnet-mercuries corporation, ltd tel: 886.2.2503.1111 fax: 886.2.2503.1449 jeilin technology corporation, ltd tel: 886.2.2248.4828 fax: 886.2.2242.4397 lumax international corporation, ltd tel: 886.2.2788.3656 fax: 886.2.2788.3568 united kingdom bracknell lsi logic europe ltd tel: 44.1344.426544 fax: 44.1344.481039 sales of?ces with design resource centers 118bds page 68 wednesday, february 3, 1999 12:37 pm

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