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universal synchronous epld cy7c335 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-03017 rev. ** revised march 26, 1997 features ? 100-mhz output registered operation twelve i/o macrocells, each having: ? registered, three-state i/o pins ? input and output register clock select multiplexer ? feed back multiplexer ? output enable (oe ) multiplexer bypass on input and output registers all twelve macrocell state registers can be hidden user configurable i/o macrocells to implement jk or rs flip-flops and t or d registers input multiplexer per pair of i/o macrocells allows i/o pin associated with a hidden macrocell state register to be saved for use as an input four dedicated hidden registers twelve dedicated registered inputs with individually programmable bypass option three separate clocks?two input clocks, two output clocks common (pin 14-controlled) or product term-controlled output enable for each i/o pin 256 product terms?32 per pair of macrocells, variable distribution global, synchronous, product term-controlled, state register set and reset?inputs to product term are clocked by input clock ? 2-ns input set-up and 9-ns output register clock to output ? 10-ns input register clock to state register clock 28-pin, 300-mil dip, lcc, plcc erasable and reprogrammable programmable security bit functional description the cy7c335 is a high-performance, erasable, programma- ble logic device (epld) whose architecture has been opti- mized to enable the user to easily and efficiently construct very high performance state machines. the architecture of the cy7c335, consisting of the user-con- figurable output macrocell, bidirectional i/o capability, input registers, and three separate clocks, enables the user to de- sign high-performance state machines that can communicate either with each other or with microprocessors over bidirec- tional parallel buses of user-definable widths. the four clocks permit independent, synchronous state ma- chines to be synchronized to each other. the user-configurable macrocells enable the designer to des- ignate jk-, rs-, t-, or d-type devices so that the number of product terms required to implement the logic is minimized. the cy7c335 is available in a wide variety of packages includ- ing 28-pin, 300-mil plastic and ceramic dips, plccs, and lccs. logic block diagram c335 ? 1 14 13 12 11 10 9 7 6 5 4 3 2 1 8 15 16 17 18 19 20 23 24 25 26 27 28 22 21 v ss v cc programmable and array (258x68) 17 11 15 13 19 9 11 17 9 19 13 15 13 17 11 19 i/o 11 i/o 10 i/o 9 i/o 8 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 v ss i 5 oe /i 11 i 10 i 9 i 8 i 7 i 6 i 4 i 3 i 2 i 1 /clk3 i 0 /clk2 clk1 node 43 node 42 node 41
cy7c335 document #: 38-03017 rev. ** page 2 of 18 architecture configuration bits the architecture configuration bits are used to program the multiplexers. the function of the architecture bits is outlined in table 1. pin configurations 10 top view plcc lcc top view 5 6 7 8 9 10 11 4 3 2 282726 12131415161718 25 24 23 22 21 20 19 25 24 23 22 21 20 19 5 6 7 8 9 10 11 121314 1516 1718 4 3 2 2827 26 i i i/o i/o 0 1 9 8 i/o i/o i i 1 1 clk1 c335 ? 2 c335 ? 3 2 1 /clk3 i 0 /clk2 i/o 2 i i i/o i/o 0 1 clk1 2 1 /clk3 i 0 /clk2 i/o 2 i 3 i 4 i 5 i 6 i 7 i 8 v ss i 3 i 4 i 5 i 6 i 7 i 8 v ss i/o 3 i/o 4 i/o 5 v cc v ss i/o 6 i/o 7 i/o 3 i/o 4 i/o 5 v cc v ss i/o 6 i/o 7 10 i/o 11 i/o 11 oe /i 9 10 9 8 i/o i/o i i 10 i/o 11 i/o 11 oe /i 9 selection guide cy7c335 ? 100 cy7c335 ? 83 cy7c335 ? 66 cy7c335 ? 50 maximum operating frequency (mhz) commercial 100 83.3 66.6 50 military 83.3 66.6 50 i cc1 (ma) commercial 140 140 140 140 military 160 160 160 table 1. architecture configuration bits architecture configuration bit number of bits value function c0 output enable select mux 12 bits, 1 per i/o macrocell 0 ? virgin state output enable controlled by product term 1 ? programmed output enable controlled by pin 14 c1 state register feed back mux 12 bits, 1 per i/o macrocell 0 ? virgin state state register output is fed back to input array 1 ? programmed i/o macrocell is configured as an input and output of input path is fed to array c2 i/o macrocell input register clock select mux 12 bits, 1 per i/o macrocell 0 ? virgin state iclk1 controls the input register i/o macrocell input register clock input 1 ? programmed iclk2 controls the input register i/o macrocell input register clock input c3 input register bypass mux ? i/o macrocell 12 bits, 1 per i/o macrocell 0 ? virgin state selects input to feedback mux from input register 1 ? programmed selects input to feedback mux from i/o pin c4 output register bypass mux 12 bits, 1 per i/o macrocell 0 ? virgin state selects output from the state register 1 ? programmed selects output from the array, bypassing the state register c5 state clock mux 16 bits, 1 per i/o macrocell and 1 per hidden macrocell 0 ? virgin state state clock 1 controls the state register 1 ? programmed state clock 2 controls the state register
cy7c335 document #: 38-03017 rev. ** page 3 of 18 c6 dedicated input register clock select mux 12 bits, 1 per dedicated input cell 0 ? virgin state iclk1 controls the input register i/o macrocell dedicated input register clock input 1 ? programmed iclk2 controls the input register i/o macrocell dedicated input register clock input c7 input register bypass mux ? input cell 12 bits, 1 per dedicated input cell 0 ? virgin state selects input to array from input register 1 ? programmed selects input to array from input pin c8 iclk2 select mux 1 bit 0 ? virgin state input clock 2 controlled by pin 2 1 ? programmed input clock 2 controlled by pin 3 c9 iclk1 select mux 1 bit 0 ? virgin state input clock 1 controlled by pin 2 1 ? programmed input clock 1 controlled by pin 1 c10 sclk2 select mux 1 bit 0 ? virgin state state clock 2 grounded 1 ? programmed state clock 2 controlled by pin 3 cx (11 ? 16) i/o macrocell pair input select mux 6 bits, 1 per i/o macrocell pair 0 ? virgin state selects data from i/o macrocell input path of macrocell a of macrocell pair 1 ? programmed selects data from i/o macrocell input path of macrocell b of macrocell pair table 1. architecture configuration bits (continued) architecture configuration bit number of bits value function figure 1. cy7c335 input macrocell c335 ? 4 iclk1 iclk2 q d c6 1 0 inputregister input clock mux to array input pin c7 1 0 input reg bypass mux
cy7c335 document #: 38-03017 rev. ** page 4 of 18 figure 2. cy7c335 input/output macrocell pin 14: o e c0 output enable mux 1 0 i/o pin s q d q r c1 1 0 output reg bypass mux feed back mux to array c335 ? 5 output enable product term set product ter m c4 1 0 ex or product term resetproductter m c5 1 0 state clk mux sclk1 sclk2 c2 1 0 input clock mux iclk1 iclk2 c3 1 0 input reg bypass mux q d input registe r cx (11 ? 16) 1 0 shared input mux to arra y from adjacent macrocell
cy7c335 document #: 38-03017 rev. ** page 5 of 18 figure 3. cy7c335 hidden macrocell s q d q r to array set product term reset product term 1 0 state clk mux sclk1 sclk2 c5 c335 ? 6 figure 4. cy7c335 input clocking scheme c335 ? 7 0 1 0 1 iclk1 iclk2 sclk2 to output macrocells and hidden macrocells sclk1 to output macrocells and hidden 0 1 c9 1 0 c8 0 1 0 1 0 1 c10 pin 1 pin 2 pin 3 mux mux mux mux mux mux mux to array to array macrocells
cy7c335 document #: 38-03017 rev. ** page 6 of 18 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................... ? 65 c to +150 c ambient temperature with power applied............................................... ? 55 c to +125 c supply voltage to ground potential (pin 22 to pins 8 and 21) ............................... ? 0.5v to +7.0v dc voltage applied to outputs in high z state ............................................... ? 0.5v to +7.0v dc input voltage............................................ ? 3.0v to +7.0v output current into outputs (low)...............................12 ma static discharge voltage ........................................... >2001v (per mil-std-883, method 3015) latch-up current..................................................... >200 ma dc programming voltage............................................. 13.0v operating range range ambient temperature v cc commercial 0 c to +75 c 5v 10% industrial ? 40 c to +85 c 5v 10% military [1] ? 55 c to +125 c 5v 10% electrical characteristics over the operating range [2] parameter description test conditions min. max. unit v oh output high voltage v cc = min., v in = v ih or v il i oh = ? 3.2 ma com ? l 2.4 v mil/ind v ol output low voltage v cc = min., v in = v ih or v il i ol = 12 ma com ? l 0.5 v mil/ind v ih input high level guaranteed input logical high voltage for all inputs [3] 2.2 v v il input low level guaranteed input logical low voltage for all inputs [3] 0.8 v i ix input leakage current v ss v in v cc , v cc = max. ? 10 10 a i oz output leakage current v cc = max., v ss v out v cc ? 40 40 a i sc output short circuit current v cc = max., v out = 0.5v [4, 5] ? 30 ? 90 ma i cc1 standby power supply current v cc = max., v in = gnd outputs open com ? l 140 ma mil/ind 160 ma i cc2 power supply current at frequency [5] v cc = max., outputs disabled (in high z state), device operating at f max external (f max5 ) com ? l 180 ma mil/ind 200 ma capacitance [5] parameter description test conditions min. max. unit c in input capacitance v in = 2.0v @ f = 1 mhz 10 pf c out output capacitance v out = 2.0v @ f = 1 mhz 10 pf notes: 1. t a is the ? instant on ? case temperature. 2. see the last page of this specification for group a subgroup testing information. 3. these are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 4. not more than one output should be tested at a time. duration of the short circuit should not be more than one second. v out = 0.5v has been chosen to avoid test problems caused by ground degradation. 5. tested initially and after any design or process changes that may affect these parameters.
cy7c335 document #: 38-03017 rev. ** page 7 of 18 ac test loads and waveforms (commercial) 5v output including jig and scope 50pf (a) 90% 10% 3.0v gnd 90% 10% all input pulses 3ns 3ns (b) c335 ? 8 c335 ? 9 c335 ? 10 output (c) th venin equivalent (load 1) v th =2.00v (2.02vmil) c = 50 pf r=125 ? (190 ? mil) output (d) three-state delay load (load2) v x c= 5pf 0v 0v c335 ? 11 r1 313 ? (470 ? mil/ind) r2 208 ? (319 ? mil/ind) r=125 ? (190 ? mil) 0v 0v figure 5. test waveforms parameter v x output waveform measurement level t pxz ( ? ) 1.5v v oh 0.5v v x 0.5v t pxz (+) 2.6v v ol v x t pzx (+) v th 0.5v t pzx ( ? )v th v x v ol 0.5v v x v oh c335 ? 12 c335 ? 13 c335 ? 14 c335 ? 15 0.5v 0.5v 0.5v 0.5v t cer ( ? )1.5v v oh v x t cer (+) 2.6v v ol v x t cea (+) v th t cea ( ? )v th v x v ol v x v oh c335 ? 16 c335 ? 17 c335 ? 18 c335 ? 19
cy7c335 document #: 38-03017 rev. ** page 8 of 18 commercial ac characteristics 7c335 ? 100 7c335 ? 83 7c335 ? 66 7c335 ? 50 parameter description min. max. min. max. min. max. min. max. unit combinatorial mode parameters t pd input to output propagation delay 15 15 20 25 ns t ea input to output enable 15 15 20 25 ns t er input to output disable 15 15 20 25 ns input registered mode parameters t wh input and output clock width high [5] 4 5 6 8 ns t wl input and output clock width low [5] 4 5 6 8 ns t is input or feedback set-up time to input clock 2 2 2 3 ns t ih input register hold time from input clock 2 2 2 3 ns t ico input register clock to output delay 18 18 20 25 ns t ioh output data stable time from input clock 3 3 3 3 ns t ioh ? t ih 33x output data stable from input clock minus input register hold time for 7c335 [6] 0 0 0 0 ns t pzx pin 14 enable to output enabled 12 12 15 20 ns t pxz pin 14 disable to output disabled 12 12 15 20 ns f max1 maximum frequency of (2) cy7c335s in input reg- istered mode (lowest of 1/(t ico +t is ) & 1/(t wl +t wh )) [5] 50 50 45.4 35.7 mhz f max2 maximum frequency data path in input registered mode (lowest of (1/(t ico ), 1/(t wh +t wl ), 1/(t is +t ih )) [5] 55.5 55.5 50 40 mhz t icea input clock to output enabled 17 17 20 25 ns t icer input clock to output disabled 15 15 20 25 ns output registered mode parameters t cea output clock to output enabled [5] 17 17 20 25 ns t cer output clock to output disabled [5] 15 15 20 25 ns t s output register input set-up time from output clock 8 9 12 15 ns t h output register input hold time from output clock 0 0 0 0 ns t co output register clock to output delay 9 10 12 15 ns t co2 input output register clock or latch enable to combinatorial output delay (through logic array) [5] 17 18 23 30 ns t oh output data stable time from output clock 2 2 2 2 ns t oh2 output data stable time from output clock (through memory array) [5] 3 3 3 3 ns t oh2 ? t ih output data clock stable time from output clock minus input register hold time [5] 0 0 0 0 ns f max3 maximum frequency with internal feedback in out- put registered mode [5] 100 83.3 66.6 50 mhz f max4 maximum frequency of (2) cy7c335s in output registered mode (lowest of 1/(t co + t s ) & 1/(t wl + t wh )) [5] 58.8 50 41.6 33.3 mhz f max5 maximum frequency data path in output regis- tered mode (lowest of 1/(t co ), 1/(t wl + t wh ), 1/(t s + t h )) [5] 111 100 83.3 62.5 mhz t oh ? t ih 33x output data stable from output clock minus input register hold time for 7c335 [6] 0 0 0 0 ns
cy7c335 document #: 38-03017 rev. ** page 9 of 18 pipelined mode parameters t cos input clock to output clock 10 12 15 20 ns f max6 maximum frequency pipelined mode (lowest of 1/(t cos ), 1/(t co ), 1/(t wl + t wh )), 1/(t is + t ih ) [5] 100 83.3 66.6 50 mhz f max7 maximum frequency of (2) cy7c335s in pipelined mode (lowest of 1/(t co + t is ) or 1/t cos ) 90.9 83.3 66.6 50 mhz power-up reset parameters t por power-up reset time [5, 7] 1 1 1 1 s commercial ac characteristics (continued) 7c335 ? 100 7c335 ? 83 7c335 ? 66 7c335 ? 50 parameter description min. max. min. max. min. max. min. max. unit military/industrial ac characteristics 7c335 ? 83 7c335 ? 66 parameter description min. max. min. max. unit combinatorial mode parameters t pd input to output propagation delay 20 20 ns t ea input to output enable 20 20 ns t er input to output disable 20 20 ns input registered mode parameters t wh input and output clock width high [5] 5 6 ns t wl input and output clock width low [5] 5 6 ns t is input or feedback set-up time to input clock 3 3 ns t ih input register hold time from input clock 3 3 ns t ico input register clock to output delay 23 23 ns t ioh output data stable time from input clock 3 3 ns t ioh ? t ih 33x output data stable from input clock minus input register hold time for 7c335 [6] 0 0 ns t pzx pin 14 enable to output enabled 15 15 ns t pxz pin 14 disable to output disabled 15 15 ns f max1 maximum frequency of (2) cy7c335s in input registered mode (lowest of 1/(t ico +t is ) & 1/(t wl +t wh )) [5] 38.4 38.4 mhz f max2 maximum frequency data path in input registered mode (lowest of (1/(t ico ), 1/(t wh +t wl ), 1/(t is +t ih )) [5] 43.4 43.4 mhz t icea input clock to output enabled 20 20 ns t icer input clock to output disabled 20 20 ns output registered mode parameters t cea output clock to output enabled [5] 20 20 ns t cer output clock to output disabled [5] 20 20 ns t s output register input set-up time to output clock 10 12 ns t h output register input hold time from output clock 0 0 ns t co output register clock to output delay 11 12 ns t co2 output register clock or latch enable to combinatorial output delay (through logic array) [5] 22 23 ns notes: 6. this specification is intended to guarantee interface compatibility of the other members of the cy7c330 family with the cy7c3 35. this specification is met for the devices operating at the same ambient temperature and at the same power supply voltage. 7. this part has been designed with the capability to reset during system power-up. following power-up, the input and output reg isters will be reset to a logic low state. the output state will depend on how the array is programmed.
cy7c335 document #: 38-03017 rev. ** page 10 of 18 military/industrial ac characteristics (continued) 7c335 ? 83 7c335 ? 66 parameter description min. max. min. max. unit t oh output data stable time from output clock 2 2 ns t oh2 output data stable time from output clock (through memory array) [5] 3 3 ns t oh2 ? t ih output data clock stable time from output clock minus input register hold time [5] 0 0 ns f max3 maximum frequency with internal feedback in output reg- istered mode [5] 83.3 66.6 mhz f max4 maximum frequency of (2) cy7c335s in output registered mode (lower of 1/(t co + t s ) & 1/(t wl + t wh )) [5] 47.6 41.6 mhz f max5 maximum frequency data path in output registered mode (lowest of 1/(t co ), 1/(t wl + t wh ), 1/(t s + t h )) [5] 90.9 83.3 mhz t oh ? t ih 33x output data stable from output clock minus input register hold time for 7c335 [6] 0 0 ns pipelined mode parameters t cos input clock to output clock 12 15 ns f max6 maximum frequency pipelined mode (lowest of 1/(t cos ), 1/(t is ), or 1/(t co )), 1/(t is + t ih ) [5] 83.3 66.6 mhz f max7 maximum frequency of (2) cy7c335s in pipelined mode (lowest of 1/(t co + t is ) or 1/t cos ) 71.4 66.6 mhz power-up reset parameters t por power-up reset time [5, 7] 1 1 s
cy7c335 document #: 38-03017 rev. ** page 11 of 18 switching waveform inputor i/o pin input reg. clock output reg. clock output pin 14 as oe t ih t is t h t s t wh t wl t cos t wh t wl t ico t ioh t co t oh t pd t ea t icea t icer t er t pzx t pxz c335 ? 20 power-up reset waveform [7] 90% t por c335 ? 21 t wl t cos clock output v cc
cy7c335 document #: 38-03017 rev. ** page 12 of 18 block diagram (page 1 of 2) node=40 28 27 26 node=39 25 24 node=38 23 node=34 node=33 11 19 15 13 17 11 19 9 1 2 3 4 5 6 7 40 48 56 64 reset node=29 0 8 16 24 32 (c9) (c6,7) (c8) (c6,7) (c10) (c6,7) (c6,7) (c6,7) (c6,7) to lower section sclk2 sclk1 iclk1 iclk2
cy7c335 document #: 38-03017 rev. ** page 13 of 18 block diagram (page 2 of 2) 9 19 11 17 13 17 13 15 20 node=37 19 node=32 node=31 18 node=36 17 16 node=35 15 14 13 12 11 10 9 c335 ? 23 to upper section (c4,5) (c4,5) (c4,5) (c4,5) (c4,5) 0 oe (c4,5) 8 16 24 32 40 node=30 48 56 64 set oe
cy7c335 document #: 38-03017 rev. ** page 14 of 18 military specifications group a subgroup testing ordering information f max (mhz) i cc1 (ma) ordering code package name package type operating range 100 140 cy7c335 ? 100wc w22 28-lead (300-mil) windowed cerdip commercial 83.3 160 cy7c335 ? 83lmb l64 28-square leadless chip carrier military cy7c335 ? 83qmb q64 28-pin windowed leadless chip carrier cy7c335 ? 83wmb w22 28-lead (300-mil) windowed cerdip 140 cy7c335 ? 83hc h64 28-pin windowed leaded chip carrier commercial cy7c335 ? 83jc j64 28-lead plastic leaded chip carrier cy7c335 ? 83wc w22 28-lead (300-mil) windowed cerdip 66.6 160 cy7c335 ? 66qmb q64 28-pin windowed leadless chip carrier military 140 cy7c335 ? 66hc h64 28-pin windowed leaded chip carrier commercial cy7c335 ? 66jc j64 28-lead plastic leaded chip carrier cy7c335 ? 66pc p21 28-lead (300-mil) molded dip cy7c335 ? 66wc w22 28-lead (300-mil) windowed cerdip 50 140 cy7c335 ? 50jc j64 28-lead plastic leaded chip carrier cy7c335 ? 50pc p21 28-lead (300-mil) molded dip dc characteristics parameter subgroups v oh 1, 2, 3 v ol 1, 2, 3 v ih 1, 2, 3 v il 1, 2, 3 i ix 1, 2, 3 i oz 1, 2, 3 i cc 1, 2, 3 switching characteristics parameter subgroups t pd 9, 10, 11 t ico 9, 10, 11 t is 9, 10, 11 t co 9, 10, 11 t s 9, 10, 11 t h 9, 10, 11 t cos 9, 10, 11
cy7c335 document #: 38-03017 rev. ** page 15 of 18 package diagrams 28-lead (300-mil) cerdip d22 mil-std-1835 d ? 15 config.a 28-lead plastic leaded chip carrier j64 28-square leadless chip carrier l64 mil-std-1835 c ? 4 28-pin windowed leadless chip carrier q64 mil-std-1835 c ? 4
cy7c335 document #: 38-03017 rev. ** page 16 of 18 package diagrams (continued) 28-pin windowed leaded chip carrier h64
cy7c335 document #: 38-03017 rev. ** page 17 of 18 ? cypress semiconductor corporation, 1997. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagrams (continued) 28-lead (300-mil) molded dip p21 28-lead (300-mil) windowed cerdip w22 mil-std-1835 d ? 15config.a
cy7c335 document #: 38-03017 rev. ** page 18 of 18 document title: cy7c335 universal synchronous epld document number: 38-03017 rev. ecn no. issue date orig. of change description of change ** 106317 04/30/01 szv change from spec number: 38-00186 to 38-03017

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