1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com hv66 features hvcmos ? technology 32 push-pull cmos output up to 60v low power level shifting shift register speed 5.0mhz latched data outputs bidirectional shift register (dir) backplane output ? ? ? ? ? ? ? functional block diagram 32-channel lcd driver with separate backplane output general description the hv66 is a low voltage serial to high voltage parallel converter with push-pull outputs. this device has been designed for use as a driver circuit for lcd displays. it can also be used in any appli - cation requiring multiple output high voltage current sourcing and sinking capabilities. the inputs are fully cmos compatible. the device consists of a 32-bit shift register, 32 latches, and con - trol logic to perform blanking and polarity control of the outputs. hv out 1 is connected to the ?rst stage of the shift register. data is shifted through the shift register on the logic rising transition of the clock. a dir pin causes data shifting clockwise when grounded and counter clockwise when connected to vdd. a data output buffer is provided for cascading devices. this output re?ects the current status of the last bit of the shift register. operation of the shift register is not affected by the le (latch enable), bl (blank) or the pol (polarity) inputs. transfer of data from the shift register to the latch occurs when the le (latch enable) input is high. the data in the latch is stored after le transitions from high to low. hv ou t 1 hv ou t 2 hv ou t 31 hv ou t 32 (outputs 3 to 30 not shown) pol bl le data in cl k data out 32-bit shift register latch latch latch latch vpp bp ou t vdd di r gn d
2 hv66 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com ordering information device package options 44-lead pqfp 10.00x10.00mm body 2.35mm height (max) 0.80mm pitch 44-lead plcc . 653x.653in body .180in height (max) .050in pitch hv66 hv66pg-g hv66pj-g -g indicates package is rohs compliant (green) absolute maximum ratings 1 parameter value supply voltage, v dd 2 -0.5v to +7.0v supply voltage, v pp 2 -0.5v to +70v logic input levels -0.5v to v dd +0.5v ground current 3 1.5a continuous total power dissipation 4 1200mw operating temperature range -40c to +85c storage temperature range -65c to +125c lead temperature ( 1.6mm (1/16 inch) from case for 10 seconds) 260c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to gnd. notes: device will survive (but operation may not be speci?ed or guaranteed) at these extremes all voltages are referenced to gnd duty cycle is limited by the total power dissipated in the package for operation above 25c ambient derate linearly to 85c at 20mw/c 1. 2. 3. 4. recommended operating conditions sym parameter min max units v dd logic supply voltage 4.5 5.5 v v pp high voltage supply 12 60 v v ih high-level input voltage 2.4 v dd v v il low-level input voltage 0 0.8 v f clk clock frequency 0 5.0 mhz t a operating free-air temperature -40 +85 c i od allowable current through output diodes - 200 ma pin con?gurations 1 44 product marking yy = year sealed ww = week sealed l = lot number c = country of origin* a = assembler id* = green packagin g *may be part of top markin g top marking bottom marking y y w w hv66pg l l l l l l l l l cccccccc aa a 44-lead pqfp (pg) 44-lead pqfp (pg) (top view) 1 44 6 40 44-lead plcc (pj) (top view) yy = year sealed ww = week sealed a = assembler id l = lot number c = country of origin* = green packagin g *may be part of top markin g top marking bottom marking yyww aaa hv66p j l l l l l l l l l l ccccccccccc 44-lead plcc (pj) package may or may not include the following marks: si or package may or may not include the following marks: si or
3 hv66 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com sym parameter min max units conditions i dd v dd supply current - 15 ma v dd = 5.5v, f clk = 5.0mhz i ppq quiescent v pp supply current - 0.5 ma outputs high - 0.5 ma outputs low i ddq quiescent v dd supply current - 0.5 ma all v in = gnd or v dd v oh high-level output hv out 50 - v i o = -5.0ma, v pp = +60v data out 4.6 - i o = -100 a v ol low-level output hv out - 8.0 v i o = +5.0ma, v pp = +60v data out - 0.4 i o = +100 a i ih high-level input current - 1.0 a v ih = v dd i il low-level input current - -1.0 a v il = 0v v olbp low-level output voltage, backplane - 3.0 v i o = +10ma v ohbp high-level output voltage, backplane 57 - v i o = -10ma ac characteristics (v dd = 5.0v, v pp = 60v, t a = 25 o c, logic input rise/fall time = 10ns.) f clk clock frequency - 5.0 mhz --- t wl, t wh clock width high or low 100 - ns --- t su data set-up time before clock rises 25 - ns --- t h data hold time after clock rises 50 - ns --- t hon , t hoff time from latch enable or pol to hv out - 500 ns c l = 20pf t bon , t boff time from pol to bp out - 500 ns c l = 20pf t dhl delay time clock to data high to low - 200 ns c l = 10pf t dlh delay time clock to data low to high - 200 ns c l = 10pf t dle delay time clock to le low to high 50 - ns --- t wle width of le pulse 100 - ns --- t sle le set-up time before clock rises 50 - ns --- t br , t bf bp out rise/fall time 10 1000 s c l = 350pf |t br - t bf | bp out rise and fall difference - 100 s c l = 350pf power-up sequence should be the following: connect ground. apply v dd . set all inputs (data, clk, enable, etc.) to a known state. apply v pp . the v pp should not drop below v dd during operation. power-down sequence should be the reverse of the above. 1. 2. 3. 4. electrical characteristics (over recommended operating conditions unless otherwise noted) dc characteristics (v dd = 5.0v, v pp = 60v)
4 hv66 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com function table function inputs outputs data clk le bl pol dir shift reg 1, 2, ... 32 hv out 1, 2, ... 32 data out bp out load s/r, r/l shift l or h l ignore ignore h data q 1 ... q 32 ignore q 32 ignore l or h l ignore ignore l q 1 ...q 32 data ignore q 1 ignore load latches x h or l h h h x *...* /*...* no change h x h or l h h l x *...* *...* no change l transparent mode l or h h h h h data q 1 ... q 32 /*...* q 32 h l or h h h l h data q 1 ... q 32 *...* q 32 l l or h h h h l q 1 ...q 32 data /*...* q 1 h l or h h h l l q 1 ...q 32 data *...* q 1 l blank control x x x l l x x l...l ignore l x x x l h x x h...h ignore h le hv out w/ s/r low data vali d 50% 5 0% data in clk data out 50% 5 0% 50 % t su t h t wl t wh 50 % 50 % t dlh t dhl 50 % t wle t dle t sl e 50 % 50 % t hoff v ih v il v ih v il v oh v ol v oh v ol v ih v il v oh v ol v oh v ol 50 % t hon t br po l (asynch w/ clock) bp out v ohbp v olbp 50 % t bf t bon 50% 50% t boff 50 % 10 % 90 % 50 % hv out w/ s/r high v ih v il switching waveforms notes: h - high level l - low level x - dont care ignore - the state of the speci?c input or output is irrelevant to demonstrate the occurred event - low to high transition * - dependent on previous stages state before the last clk or last le high
5 hv66 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com 44-lead pqfp pin description (pg) pin # function 1 hv out 11 2 hv out 12 3 hv out 13 4 hv out 14 5 hv out 15 6 hv out 16 7 hv out 17 8 hv out 18 9 hv out 19 10 hv out 20 11 hv out 21 12 hv out 22 13 hv out 23 14 hv out 24 15 hv out 25 pin # function 16 hv out 26 17 hv out 27 18 hv out 28 19 hv out 29 20 hv out 30 21 hv out 31 22 hv out 32 23 data out 24 gnd 25 n/c 26 bl 27 pol 28 le 29 vdd 30 clk pin # function 31 dir 32 data in 33 vpp 34 bp out 35 hv out 1 36 hv out 2 37 hv out 3 38 hv out 4 39 hv out 5 40 hv out 6 41 hv out 7 42 hv out 8 43 hv out 9 44 hv out 10 pin function 1 hv out 16 2 hv out 17 3 hv out 18 4 hv out 19 5 hv out 20 6 hv out 21 7 hv out 22 8 hv out 23 9 hv out 24 10 hv out 25 11 hv out 26 12 hv out 27 13 hv out 28 14 hv out 29 15 hv out 30 pin function 16 hv out 31 17 hv out 32 18 data out 19 gnd 20 n/c 21 bl 22 pol 23 le 24 vdd 25 clk 26 dir 27 data in 28 vpp 29 bp out 30 hv out 1 pin function 31 hv out 2 32 hv out 3 33 hv out 4 34 hv out 5 35 hv out 6 36 hv out 7 37 hv out 8 38 hv out 9 39 hv out 10 40 hv out 11 41 hv out 12 42 hv out 13 43 hv out 14 44 hv out 15 44-lead plcc pin description (pj)
6 hv66 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com 44-lead pqfp package outline (pg) 10.00x10.00mm body, 2.35mm height (max), 0.80mm pitch symbol a a1 a2 b d d1 e e1 e l l1 l2 dimension (mm) min 1.95* 0.00 1.95 0.30 13.65* 9.80* 13.65* 9.80* 0.80 bsc 0.73 1.95 ref 0.25 bsc 0 o nom - - 2.00 - 13.90 10.00 13.90 10.00 0.88 3.5 o max 2.35 0.25 2.10 0.45 14.15* 10.20* 14.15* 10.20* 1.03 7 o jedec registration mo-112, variation aa-2, issue b, sep.1995. * this dimension is not speci?ed in the jedec drawing. drawings not to scale. supertex doc. #: dspd-44pqfppg, version c041309. 1 52 seating plane gauge plane l l1 l2 vi ew b vi ew b seating plane top view d d1 e e1 b e side view a2 a a1 note 1 (index area d1/4 x e1/4) note: a pin 1 identi?er must be located in the index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. 1.
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate product liability indemnification insurance agreement. supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry an d specifications are subject to change without notice. for the latest product specifications refer to the supertex inc . (website: http//ww w. supertex.com ) ?2009 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 te l: 408-222-8888 www .supertex.com 7 hv66 (the package drawing(s) in this data sheet may not re?ect the most current speci?cations. for the latest package outline information go to http://www.supertex.com/packaging.htm l .) doc.# dsfp-hv66 a010610 44-lead plcc package outline (pj) .653x.653in body, .180in height (max), .050in pitch symbol a a1 a2 b b1 d d1 e e1 e dimension (inches) min .165 .090 .062 .013 .026 .685 .650 .685 .650 .050 bsc nom .172 .105 - - - .690 .653 .690 .653 max .180 .120 .083 .021 .036 ? .695 .656 .695 .656 jedec registration ms-018, variation ac, issue a, june, 1993. ? this dimension differs from the jedec drawing. drawings not to scale. supertex doc. #: dspd-44plccpj, version e041309. .150 ma x .048/.042 x 45 o 1 .075 ma x 6 40 d d1 e1 e to p v iew horizontal side v iew v iew b a a2 a1 seating plane e b note 1 (index area) .056/.042 x 45 o .020max (3 places) .020 min ve rtical side v iew v iew b note 2 44 b1 base plane notes: a pin 1 identi?er must be located in the index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. actual shape of this feature may vary. 1. 2.
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