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hd74hc series common information september 2000 customer service division semiconductor & integrated circuits hitachi, ltd. disclaimer 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products.
outline of hitachi high-speed cmos logic 1 outline of hitachi high-speed cmos logic features of high-speed cmos logic hitachi? hs-cmos logics?he hd74hc series?nd the hct series based on the eia/jedec specification. their specification are shown in the maximum ratings and the electrical characteristics tables. the hs-cmos has the characteristics of both standard cmos logic series and ls-ttl series. the features of this logic are: high-speed equivalent to the ls-ttl? capable of driving 10ls-ttl loads (capable of driving 15ls-ttl loads in bus drivers) maximum input current of 1 m a at 6 v power supply wide supply voltage range: hc series 2 to 6 v hct series 4.5 to 5.5 v wide noise margin v cc assurance of electrical characteristics at 2.0, 4.5 and 6.0 v low static power consumption 1/2 of eia/jedec type name of high-speed cmos logic the jedec has divided the hs-cmos? into two types: hc and hct. the hc type has the cmos logic level for inputs and outputs with buffers. the hct type has the ttl logic level for inputs and the outputs have buffers. the industry-standarized maximum ratings and recommended operating range are shown below. limits for the static characteristics are shown below (right): table 1 is in the industry-standard and table 2 is the hitachi specifications. the hitachi specifications is used throughout this data book. additional specification are shown in the individual data sheets. switching characteristics are specified under the following conditions: input pulse voltage: + v cc load capacitance: 50 pf input pulse rise/fall time: 6 ns switching times measured from 50% point of input voltage to 50% point of output voltage three different supply voltages: 2.0, 4.5 and 6.0 v
outline of hitachi high-speed cmos logic 2 input levels of each series type (v cc = 5 v) input level type v ih v il remarks hc series 3.5 v 1.5 v hct series 2.0 v 0.8 v ttl logic level for inputs type name of hs-cmos logic package code (p : plastic dip,fp:small outline package (eiaj type), rp : small outline package (jedec type)) individual device code 2 or 3-digit:same pin connection and function with its corresponding device in ls-ttl 4?igit:same pin connection and function with the 14000b series cmos) type code (hc,hct) hd74 absolute maximum ratings (voltages referenced to gnd) item symbol rating unit supply voltage v cc ?.5 to +7 v i/o voltage v in , v out ?.5 to v cc +0.5 v i/o diode current i ik , i ok 20 ma output current i o 25 ma v cc , gnd current i cc , i gnd 50 ma power dissipation p t 500 mw storage temperature range tstg ?5 to +150 ?c additional specification values are shown on the individual data sheets.
outline of hitachi high-speed cmos logic 3 recommended operating range hd74hc item symbol rating unit condition supply voltage v cc 2 to 6 v i/o voltage v in , v out 0 to v cc v operating temperature ta ?0 to +85 ?c input rise/fall time tr, tf 0 to 1000 ns v cc = 2.0 v 0 to 500 v cc = 4.5 v 0 to 400 v cc = 6.0 v hd74hct item symbol rating unit condition supply voltage v cc 4.5 to 5.5 v i/o voltage v in , v out 0 to v cc v operating temperature ta ?0 to +85 ?c input rise/fall time tr, tf 0 to 1000 ns v cc = 2.0 v 0 to 500 v cc = 4.5 v 0 to 400 v cc = 6.0 v hd74hc14, hc132 item symbol rating unit condition input rise/fall time tr, tf 0 to unlimited ns v cc = 2.0 v 0 to unlimited v cc = 4.5 v 0 to unlimited v cc = 6.0 v hd74hc123a, hc221, hc423a item symbol rating unit condition a, b input rise/fall time tr, tf 0 to unlimited ns v cc = 2.0 v 0 to unlimited v cc = 4.5 v 0 to unlimited v cc = 6.0 v clr input rise/fall time tr, tf 0 to 1000 ns v cc = 2.0 v 0 to 500 v cc = 4.5 v 0 to 400 v cc = 6.0 v
outline of hitachi high-speed cmos logic 4 hd74hc4538 item symbol rating unit condition a, b input rise/fall time tr, tf 0 to unlimited ns v cc = 2.0 v 0 to unlimited v cc = 4.5 v 0 to unlimited v cc = 6.0 v cd input rise/fall time tr, tf 0 to 1000 ns v cc = 2.0 v 0 to 500 v cc = 4.5 v 0 to 400 v cc = 6.0 v hd74hc540, hc541 item symbol rating unit condition a input rise/fall time tr, tf 0 to unlimited ns v cc = 2.0 v 0 to unlimited v cc = 4.5 v 0 to unlimited v cc = 6.0 v g input rise/fall time tr, tf 0 to 1000 ns v cc = 2.0 v 0 to 500 v cc = 4.5 v 0 to 400 v cc = 6.0 v
outline of hitachi high-speed cmos logic 5 table 1 eia/jedec format for high-speed cmos specifications limits +25?c ?0 to +85?c parameters symbol v cc (v) min max min max unit test conditions input voltage hc series v ih 2.0 1.5 1.5 v 4.5 3.15 3.15 6.0 4.2 4.2 hct series 4.5 to 5.5 2.0 2.0 hc series v il 2.0 0.3 0.3 v 4.5 0.9 0.9 6.0 1.2 1.2 hct series 4.5 to 5.5 0.8 0.8 output hc standard v oh 2.0 1.9 1.9 v vin = v ih or v il iout = ?0 m a voltage series type 4.5 4.4 4.4 6.0 5.9 5.9 4.5 3.98 3.84 iout = ?.0 ma 6.0 5.48 5.34 iout = ?.2 ma bus driver 2.0 1.9 1.9 vin = v ih or v il iout = ?0 m a type 4.5 4.4 4.4 6.0 5.9 5.9 4.5 3.98 3.84 iout = ?.0 ma 6.0 5.48 5.34 iout = ?.8 ma hct standard 4.5 4.4 4.4 vin = v ih or v il iout = ?0 m a series type 4.5 3.98 3.84 iout = ?.0 ma bus driver 4.5 4.4 4.4 vin = v ih or v il iout = ?0 m a type 4.5 3.98 3.84 iout = ?.0 ma hc standard v ol 2.0 0.1 0.1 v vin = v ih or v il iout = 20 m a series type 4.5 0.1 0.1 6.0 0.1 0.1 4.5 0.26 0.33 iout = 4.0 ma 6.0 0.26 0.33 iout = 5.2 ma bus driver 2.0 0.1 0.1 vin = v ih or v il iout = 20 m a type 4.5 0.1 0.1 6.0 0.1 0.1
outline of hitachi high-speed cmos logic 6 limits +25?c ?0 to +85?c parameters symbol v cc (v) min max min max unit test conditions output hc bus driver 4.5 0.26 0.33 v vin = v ih or v il iout = 6.0 ma voltage series type 6.0 0.26 0.33 iout = 7.8 ma hct standard 4.5 0.1 0.1 vin = v ih or v il iout = 20 m a series type 4.5 0.26 0.33 iout = 4.0 ma bus driver 4.5 0.1 0.1 vin = v ih or v il iout = 20 m a type 4.5 0.26 0.33 iout = 6.0 ma input leakage hc series i i 6.0 0.1 1.0 m a vin = v cc or gnd current hct series 5.5 0.1 1.0 analog switch off- hc series i s(off) 6.0 0.1 1.0 m a vin = v ih or v il state current hct series 5.5 0.1 1.0 |v s | = v cc or v cc ?v ee 3-state output off- hc series i oz 6.0 0.5 5.0 m a vin = v ih or v il state current hct series 5.5 0.5 5.0 vout = v cc or gnd quiescent hc ssi i cc 6.0 2.0 20 m a vin = v cc or gnd supply series ff 6.0 4.0 40 iout = 0 m a current msi 6.0 8.0 80 hct ssi 5.5 2.0 20 series ff 5.5 4.0 40 msi 5.5 8.0 80
outline of hitachi high-speed cmos logic 7 table 2 hitachi high-speed cmos series specifications limits +25?c ?0 to +85?c parameters symbol v cc (v) min max min max unit test conditions input voltage hc series v ih 2.0 1.5 1.5 v 4.5 3.15 3.15 6.0 4.2 4.2 hct series 4.5 to 5.5 2.0 2.0 hc series v il 2.0 0.5 0.5 v 4.5 1.35 1.35 6.0 1.8 1.8 hct series 4.5 to 5.5 0.8 0.8 output hc standard v oh 2.0 1.9 1.9 v vin = v ih or v il i oh = ?0 m a voltage series type 4.5 4.4 4.4 6.0 5.9 5.9 4.5 4.18 4.13 i oh = ?.0 ma 6.0 5.68 5.63 i oh = ?.2 ma bus driver 2.0 1.9 1.9 vin = v ih or v il i oh = ?0 m a type 4.5 4.4 4.4 6.0 5.9 5.9 4.5 4.18 4.13 i oh = ?.0 ma 6.0 5.68 5.63 i oh = ?.8 ma hct standard 4.5 4.4 4.4 vin = v ih or v il i oh = ?0 m a series type 4.5 4.18 4.13 i oh = ?.0 ma bus driver 4.5 4.4 4.4 vin = v ih or v il i oh = ?0 m a type 4.5 4.18 4.13 i oh = ?.0 ma hc standard v ol 2.0 0.1 0.1 v vin = v ih or v il i ol = 20 m a series type 4.5 0.1 0.1 6.0 0.1 0.1 4.5 0.26 0.33 v vin = v ih or v il i ol = 4.0 ma 6.0 0.26 0.33 i ol = 5.2 ma bus driver 2.0 0.1 0.1 vin = v ih or v il i ol = 20 m a type 4.5 0.1 0.1 6.0 0.1 0.1
outline of hitachi high-speed cmos logic 8 limits +25?c ?0 to +85?c parameters symbol v cc (v) min max min max unit test conditions output hc bus driver v ol 4.5 0.26 0.33 v vin = v ih or v il i ol = 6.0 ma voltage series type 6.0 0.26 0.33 i ol = 7.8 ma hct standard 4.5 0.1 0.1 vin = v ih or v il i ol = 20 m a series type 4.5 0.26 0.33 i ol = 4.0 ma bus driver 4.5 0.1 0.1 vin = v ih or v il i ol = 20 m a type 4.5 0.26 0.33 i ol = 6.0 ma input leakage hc series i i 6.0 0.1 1.0 m a vin = v cc or gnd current hct series 5.5 0.1 1.0 analog switch hc series i s (off) 6.0 0.1 1.0 m a vin = v ih or v il off-state current hct series 5.5 0.1 1.0 |v s | = v cc or v cc ?v ee 3-state output off- hc series i oz 6.0 0.5 5.0 m a vin = v ih or v il state current hct series 5.5 0.5 5.0 vout = v cc or gnd quiescent hc ssi i cc 6.0 1.0 10 m a vin = v cc or gnd supply series ff 6.0 2.0 20 iout = 0 m a current msi 6.0 4.0 40 hct ssi 5.5 1.0 10 series ff 5.5 2.0 20 msi 5.5 4.0 40
outline of hitachi high-speed cmos logic 9 symbols and terms defined for hd74hc series 1. explanation of symbols used in electrical characteristics and recommended operating conditions 1.1 dc characteristics symbol term description v ih ??level input voltage ??level input voltage to ensure that a logic element operates under some constraint. v il ??level input voltage ??level input voltage to ensure that a logic element operates under some constraint. v ol ??level output voltage output voltage in effect when, under the input condition for bringing the output low, the rated output current is allowed to flow to the output terminal. v oh ??level output voltage output voltage in effect when, under the input condition for bringing the output high, the rated output current is allowed to flow to the output terminal. v t + forward input threshold voltage input voltage in effect when the operation of a logic element varies as the input is allowed to go up from a voltage level lower than the forward input threshold voltage v t - . v t - reverse input threshold voltage input voltage in effect when the operation of a logic element varies as the input is allowed to go up from a voltage level lower than the reverse input threshold voltage v t + . v h hysteresis voltage differnce between forward input threshold voltage v t + and reverse threshold voltage v t - . i oh ??level output current output current that flows out when, under the condition for bringing the output high, the rated output voltage vout is applied to the output terminal. i ol ??level output current output current that flows out when, under the condition for bringing the output high, the rated output voltage v ou t is applied to the output terminal. i in input leakage current input current that flows in when the rated maximum input voltage is applied to the input terminal. i ih ??level input current input current that flows in when the rated ??level voltage is applied to the input. i il ??level input current input current that flows out when the rated ??level voltage is applied to the input. i oz off-state output current (high impedance) current that flows to the 3-state output of an element under the input condition for briging the output to high impedance. is(off) analog switch off-state current current that flows to the analog switch of an element under the input condition for bringing the switch to off-state. i cc quiescent supply current current that flows to the supply terminal (v cc ) under the rated input condition.
outline of hitachi high-speed cmos logic 10 1.2 ac characteristics symbol term description f max maximum clock frequency maximum clock frequency that maintains the stable changes in output logic level in the rated sequence under the i/o condition allowing clock pulses to change the output state. t tlh rise (transient) time rated time from ??level to ??level of a waveform during the defined transient period changing from ??level to ??level. t thl fall (transient) time rated time from ??level to ??level of a waveform during the defined transient period changing from ??level to ??level. t plh output rise propagation delay time delay time between the rated voltage levels of an i/o voltage waveform under a defined load condition, with the output changing from ??level to ??level. t phl output fall propagation delay time delay time between the rated voltage levels of an i/o voltage waveform under a defined load condition, with the output changing from ??level to ??level. t hz 3-state output disable time (? level) delay time between the rated voltage levels of an i/o voltage waveform under a defined load condition, with the 3-state output changing from ??level to the high impedance state. t lz 3-state output disable time (? level) delay time between the rated voltatge levels of an i/o voltage waveform under a defined load condition, with the 3-state output changing from ??level to the high impedance state t zh 3-state output enable time (? level) delay time between the rated voltage levels of an i/o voltage waveform under a defined load condition, with the 3-state output changing from the high impedance state to ??level. t zl 3-state output enable time (? level) delay time between the rated voltage levels of an i/o voltage waveform under a defined load condition, with the 3-state output changing from the high impedance state to ??level. t w pulse width duration of time between the rated levels from a leading edge to a trailing edge of a pulse waveform. t h hold time time in which to hold date at the specified input terminal after a change at another related input terminal (e.g., clock input). t su setup time time in which to set up and keep data at the specified input terminal before a change at another related input terminal (e.g., clock input). t rm removal time time period between the time when data at the specified input terminal is released and the time when another related input terminal (e.g., clock input) can be changed. c in input capacitance capacitance between gnd terminal and an input terminal to which 0 v is applied.
outline of hitachi high-speed cmos logic 11 2. explanation of symbols used in function table symbol description h high level (in steady state; noted "h" or ??level in sentences) l low level (in steady state; noted "l" or ??level in sentences) transition from l level to h level transition from h level to l level x either h or l z 3-state output off (high impedance) a? input level of steady state for each of inputs a-h q 0 q level immediately before the indicated input condition is established q 0 complement of q q n q level immediately before the latest active change ( or ) occurs single h level pulse single l level pulse toggle each output is changed to the complement of the preceding state by an active input change ( or ) measuring method of ac characteristics loading circuit output output output measuring point measuring point measuring point v cc c l s1 r l r l v cc r l c l c l (a) cmos output (b) open drain output (c) 3-state output notes: 1. c l includes the floating capacitance of probe and jig. 2. r l = 1 k w (except for a particular specification)
outline of hitachi high-speed cmos logic 12 waveforms (mutual relationship of waveforms) pulse width (t w ) 74hc series v cc v cc t r = 6ns t f = 6ns t f = 6ns t r = 6ns 90% 90% 90% 90% 50% 50% 10% 10% 50% 50% 10% 10% t w t w gnd gnd h-level pulse l-level pulse 74hct series 3.0v 3.0v t r = 6ns t f = 6ns t f = 6ns t r = 6ns 2.7v 2.7v 2.7v 2.7v 1.3v 1.3v 0.3v 0.3v 1.3v 1.3v 0.3v 0.3v t w t w gnd gnd h-level pulse l-level pulse
outline of hitachi high-speed cmos logic 13 setup time and hold time 74hc series 50% 50% 90% 10% 50% 50% 50% t r v cc gnd v oh v ol v oh v ol t su t h t su t h clock or latch enable input * 1 positive data input negative data input 74hct series 1.3v 1.3v 90% 10% 1.3v 1.3v 1.3v t r 3.0v gnd 3.0v gnd 3.0v gnd t su t h t su t h clock or latch enable input * 1 positive data input negative data input note: waveform for negative edge sensitive circuits will be inverted.
outline of hitachi high-speed cmos logic 14 removal time 74hc series 50% 90% 90% 50% 10% 50% 10% 10% 90% t r v cc gnd v cc gnd v cc gnd clock input * 1 active low clear or enable active high clear or enable t f t rem t r t rem 74hct series 1.3v 90% 90% 1.3v 10% 1.3v 10% 10% 90% t r 3.0v gnd 3.0v gnd 3.0v gnd clock input * 1 active low clear or enable active high clear or enable t f t rem t r note: waveform for negative edge sensitive circuits will be inverted.
outline of hitachi high-speed cmos logic 15 waveforms (mutual relationship of waveforms) propagation delay time, output rise time and output fall time 74hc series 90% 50% 10% 90% 50% 10% 90% 90% 90% 50% 50% 50% 10% 90% 50% 10% 10% 10% t r = 6ns t f = 6ns t tlh t tlh t thl t thl t phl t plh t plh t phl v cc gnd v oh v ol v oh v ol input same-phase output inverse-phase output
outline of hitachi high-speed cmos logic 16 74 hct series 90% 1.3v 10% 2.7v 1.3v 0.3v 90% 90% 90% 1.3v 1.3v 1.3v 10% 2.7v 1.3v 0.3v 10% 10% t r = 6ns t f = 6ns t tlh t tlh t thl t thl t phl t plh t plh t phl 3.0v gnd v oh v ol v oh v ol input same-phase output inverse-phase output
outline of hitachi high-speed cmos logic 17 waveforms (mutual relationship of waveforms) three-state output, enable time and disable time 74hc series 10% 10% 50% 90% 10% 50% 90% 90% t lz t hz s1 : v cc s1 : v cc s1 : gnd s1 : gnd t zl t zh 50% 50% t f = 6ns t r = 6ns output control (l-level enable) waveform 1 waveform 2 v cc gnd v oh v ol v oh v ol 74hct series 10% 0.3v 1.3v 2.7v 0.3v 1.3v 2.7v 90% t lz t hz s1 : v cc s1 : v cc s1 : gnd s1 : gnd t zl t zh 1.3v 1.3v t f = 6ns t r = 6ns output control (l-level enable) waveform 1 waveform 2 3.0v gnd v oh v ol v oh v ol notes: 1. waveform 1 is an output under the internal condition like ??except for the output disabled by the output control. 2. waveform 2 is an output under the internal condition like ??except for the output disabled by the output control.
precautions in system design 18 precautions in system design in the system design, the problems to be considered are described in the following items: 1. transfer characteristics since the transfer characteristics of gate circuit varies with the number of working inputs, care must be taken to the noise margin. in the multiple input nor gate, the p channel mos is connected to v cc in series and the n channel mos is connected to gnd in parallel. in the nand gate, the connection is reverse. the output voltage v out in the transition area becomes a value obtained by distributing the supply voltage at a split ratio according to the on resistance of p channel mos and n channel mos. in the multiple input nor and nand gates, the fall of transfer characteristic, that is, v in (voltage noise margin) that enters in the transition area changes according to the number of inputs as shown in figure 1. number of inputs 1 2 3 4 v in v out number of inputs 1 2 3 4 v in v out figure 1 as seen from the above, it becomes clear that: in the nor gate, ??level noise margin v nl decreases, and ??level noise margin v nh increases according to the number of working inputs. in the nand gate, the noise margins are fully reversed.
precautions in system design 19 2. output impedance the output impedance of cmos logic gate is influenced by the circuit configuration, the number of working inputs, logical state and supply voltage. there are two regions of output impedance depending on the operation: constant impedance area in which p and n channel mos?operate in the nonsaturated state. constant current area in which p and n channel mos?operate in the pinch-off state. in designing a system including an interface circuit, the above must be considered. 3. output short-circuit because no protective circuitry is provided to limit the output current, an output inadvertently shorted to v cc or gnd on the hs-cmos logic ic is limited to the current value determined by the pinch-off effect of the p-channel mos and n-channel mos for the output. notice that such output short-circuit current, if allowed to flow for a long time, could result in increased power dissipation or in a melted wire due to excessive current density through metalization or other performance failures. for operating stability and reliability, the maximum output current should remain within the maximum rating. 4. unused inputs as shown in figure 2, unused inputs must be: (1) directly connected to v cc for nand gate circuits. (2) directly connected to gnd for nor gate circuits. (3) connected to v cc or gnd through a proper resistor (10 k w or 100 k w .). this is required because the extremely high input impedance of cmos logic makes it subject to noise. this noise causes the output logic level to be unstable. furthermore, in some cases, if a gate is not used or a flip-flop is not used, both p-channel mos and n-channel mos may conduct, causing i cc to flow. v cc v cc v cc 100 k w 100 k w gnd gnd v out v out v in v in figure 2 examples of handling unused inputs
precautions in system design 20 5. input impedance since all the input protective diodes are biased reversely in the ordinary operations, the input impedance of cmos logic ic is extremely high. when converted into a leak current, it is about several tens (pa) at a temperature of 25?c or about one (na) even at 100?c. thus, the matching for operating the cmos logic ic has only to be considered at a voltage level. in the actual interface to other ic?, however, remember that fan-out is limited according to a capacitance value because inputs measured in capacity. 6. parallel connection of gate circuits if it is necessary to increase source or sinking current, the same type gate circuits can be connected in parallel as shown in figure 3. i os0 i os0 i os1 i os1 i os1 i os1 increase of source current increase of sinking current increase of sinking current figure 3 examples of parallel connection the switching speed improved at the same time. the source and sinking current capacities also increase in proportion to the number of inputs. 7. wired or connection the wired or connection is unrecommendable and shall not be used in cmos logic ic?. the reason is that if the two gate outputs are connected with a = b = 0 and c = d = 1 as shown in figure 4, the output voltage is a value with which the supply voltage is divided by each of the resistance values of active p and n channel mos? on an about half level (v cc - gnd). a b c d y figure 4 wired or connection
precautions in system design 21 8. input capacitance in the cmos logic ic, there is capacitance between the input and the gnd. in addition to the major capacitance between the gate and the substrate, the capacitance of package, leads and input protection circuit are also included. the change input capacitance depending on the input voltage results mainly from the capacitance between the gate and the substrate. this input capacitance has an advantage of temporarily storing date in it by opening/closing the transmission gate. on the other hand, however, remember that the input capacitance may slow down switching speed of mutually connected gate and also may increase the power dissipation. the input capacitance is usually about 5 (pf) as specified in the standard. 9. output capacitance the whole output capacitance of cmos logic ic is the sum of the drain capacitance of output mos and the external load capacitance. it may be considered that the former is about 10 (pf) per output. the propagation delay time increases linealy in proportion to the increase of external load capacitance as described previously. the power dissipation also increases according to it. especially, be careful in attaching a large capacity of around 1 (1 m f) outside. the peak current at the gate transition, as described previously, is limited by the output characteristics of p and n channel mos? in the buffer circuit, the peak current may increase (to 100 ma or more). pay sufficient attention to the fact that the rise of temperature in the chip may cause metal migration on the metal wiring layer. if the peak current for gate circuit is set to about 50 ma and the one for buffer circuit is set to about 100 ma, no consideration is required.
precautions in system design 22 10. features of 3-state output circuit in a system that requires bus configuration, the 3-state output element is brought from the necessity to place unnecessary circuits in the high output impedance state through control input to operate necessary circuit selectively when tow or more circuit is connected to one bus line. figure 5 shows the typical 3-state circuit. when the disable input of control terminal is at ??level, the output is at low impedance by the switch operation. when at ??level, the output is at extremely high impedance of 10 4 (m w ) at a room temperature. remember that the number of 3-state elements connectable to one bus line is limited by the switching speed and supply voltage. disable in v cc out gnd figure 5 3-state output circuit
precautions in system design 23 11. static power dissipation in the cmos logic ic, the p channel mos and n channel mos are mutually connected each other. therefore, either p channel or n channel is cut off in the input potential level static state. there is no path in which the current from the power supply flows. actually, the reverse bias leak current in all the p-n junction in the chip including parasitic p-n junction flows only. the supply current in this state is referred to as static current consumption, and the power dissipation as static power dissipation. the static current consumption is a total of leak currents, and its values are extremely small as listed in table 1. thus, the static current consumption is almost proportional to the supply voltage and increases exponentially in proportion to temperature. table 1 static current consumption i cc(max) type v cc +25?c ?0 to +85?c hc series ssi 6.0 v 1.0 m a 10 m a ff 2.0 m a 20 m a msi 4.0 m a 40 m a hct series ssi 5.5 v 1.0 m a 10 m a ff 2.0 m a 20 m a msi 4.0 m a 40 m a 12. dynamic power dissipation assuming that the square pulse waves (tr = t f = 0) as shown in figure 7 are applied to the input of the inverter shown in figure 6, the output steps from ??level to ??level in response to the input fall from ??level to ??level. v cc v out v in c l gnd i cc(p) i cc(n) figure 6 inveter circuit
precautions in system design 24 t v in v out i cc(p) i cc(n) figure 7 operating voltage and current of inverter circuit actually, v out is not converted into square waveforms. the reason is that the sum total c l of the outputs such as external load capacitance and drain capacitance are inverted by charging them from 0 to v cc . for charging, supply current i cc(p) flows through the active p channel mos from v cc . contrary to this, when the input goes from ??level to ??level, c l discharges and i cc(n) flows into gnd through the n channel mos. the supply current caused by the charge/discharge is dynamic current dissipation, and the power dissipation is dynamic power dissipation. if the average power dissipation is taken as p t , it is obtained theoritically as follows: the power dissipation when i cc(p) flows into the p channel mos in figure 6 is i cc(p) (v cc - v out ). if an average is taken by the one cycle of input pulse, the average power dissipation p tp of p channel mos is: p = 1/t i (v - v ) dt tp cc(p) cc out 0 t i cc (p) = c l ?d(v cc - v out )/dt in the same manner, the average power dissipation of n channel mos is: p = 1/t i (v - gnd) dt tn cc(n) out 0 t i cc(n) = c l ?d(v out - gnd)/dt thus, the average dynamic power dissipation p t is: p t = p tp + p tn = 1/t ?c l ?v cc 2 = f ?c l ?v cc 2 f : input pulse frequency it is clear that the dynamic power dissipation varies with the frequency, load capacitance and supply voltage. figure 8 shows the aspect.
precautions in system design 25 power dissipation p t (mw) operating frequency f (hz) 1 k 10 k 100 k 1 m 10 m 100 m 0.0001 0.001 0.01 0.1 1.0 10 100 c l = 150 pf c l = 50 pf c l = 15 pf c l = open figure 8 power dissipation vs. operating frequency this relation shows a case where the square wave input with tr = tf = 0 is assumed. in an actual case, the input pulse is considered a trapezoidal waveform. thus, remember that the transition state in which both p channel mos and n channel mos are simultaneously activate and dc current flows from v cc into gnd during this time. if input is used at an intermediate level, such as crystal oscillator circuit and a linear amplifier, and if the circuits such as a differentiation circuit, an integration circuit and an oscillation circuit process gentle waveforms, pay attention to the increase of power dissipation. 13. caution of supply voltage to decouple noises, the capacitance of 0.01 to 0.1 ( m f) should be attached externally between v cc and gnd. 14. caution of fan-out the number of fan-outs of cmos logic ic is virtually unlimited in terms of dc. the reason is that the input current is the p-n junction leak current of input protection circuit at most and its value is actually approximate to 0 because the input is connected to the gate electrodes and insulated from the substrate. therefore, the number of fan-outs is not a problem in terms of dc. in ac, there is a slightly different circumstance. since the input has a capacity of about 5 (pf), the output capacitance increases if the input is connected to the output. if the input capacitance is taken as 5 (pf), for example, the whole load capacitance c l (pf) at the time the number of fan-outs is n and load capacitance is c o (pf) is: c l = 5 ?n + c o (pf) on the other hand, the propagation delay time increases in proportion to the output load capacitance c l . the operating speed decreases according to the number of inputs (fan-outs) connected to the output. therefore, remember that the number of fan-outs is fairly limited if a high-speed operation is required.
precautions in system design 26 15. cautions on actual operation (1) the rise time and fall time of input waveforms should be 500 ns or less. since the voltage gain is very high near the threshold, the slightest ripples on the input voltage may cause the output to produce a corresponding waveform, making the output operation unstable. (2) the power line should be sufficiently filtered for the device. the input threshold voltage of the ic varies with the supply voltage. a ripple on the power line may change the input threshold, causing the same malfunction as noted in (1) above. (3) beware of a ringing (waveform distortion). because the switching from ??level to ??level on vice versa is very fast, the load capacitance plus the wiring inductance may cause a ringing. care should be taken to arrange the circuit configuration, pcb layout and wiring appropriately.
application note 27 application note 1. input protection circuit an si-gate process is applied to hitachi? high-speed cmos logic ics.they have a thinner gate oxide compared to conventional al-gate cmos logic ics and are composed into finer patterns. therefore, an input protection circuit is necessary for the gate to be protected from surges at the input pins. since al-gate cmos logic ics use a diffusion resistor as the input protection resistor (as shown in figure 1a), input over-current flows directly to the power supply and the destruction of the protection diode may occur. on the other hand, using polysilicone as its input protection resistor (shown in figure 1b), high-speed cmos logic ics take the role of a current limiter to counter input over voltage. gnd poly-si resistor input input v cc gnd v cc gnd gnd p well p well (a) al-gate cmos logic (b) si-gate cmos logic n + diffusion resistor n + p + diffusion resistor p + diffusion resistor p + poly-si resistor input internal logic circuit input internal logic circuit n + diffusion resistor internal logic circuit internal logic circuit n sub v cc n sub v cc figure 1 input protection deevice and equivalent circuit
application note 28 2. electric static discharge immunity (esd immunity) esd immunity is evaluated by the capacitor discharge method shown in the test circuit of figure 2. the capacitor is 200 pf, accounting for the electrostatic capacitance of human bodies. figure 3 shows an example of esd immunity of integrated circuits for each products series. the esd for high-speed cmos logic is over 200 v, which is the same level or better than ls-ttl. c = 200 pf test pin gnd figure 2 esd immunity test circuit 0 200 400 100 300 500 applied voltage (v) 1 2 10 20 30 40 50 60 70 80 90 95 3 4 5 accumulated failure rate hd74hc/hct series (hs-cmos) hd74s series (s-ttl) hd74ls series (ls-ttl) hd14000b series (cmos logic) hd17000 series (industrial linear) 8-bit microcomputer (cmos) 256k dram (nmos) figure 3 esd immunity for each series
application note 29 3. latch-up 3.1 latch-up latch-up is an inevitable phenomenon occurring from the basical structure of cmos logic ics. since cmos has pmos and nmos on one chip, npn and pnp transistors are made. these two types of transistors are combined into a pnpn structure, in which a parasitic thyristor is formed (see figure 4). if excessive noise is applied to the input or output pins when the ic is operating, the parasitic thyristor will turn on and the abnormal current will flow through the power supply pin to ground. if the power supply is turned off, the ic will be restored to its normal state, however, the internal ai wiring of the ic may melt thus causing the ic to be destroyed. there are countermeasures to prevent latch-up as listed below (1) separate pmos from nmos. (2) shut down electrical paths between pnp and npn transistors which form parasitic thyristors by its layout pattern. (3) isolate each mos transistor with an insulator to prevent the formation of parasitic thyristors. hitachi? high-speed cmos logic utilizes method (2) v cc v cc in out n-sub (a) parasitic pnp, npn transistor (b) equivalent circuit r 1 r 1 r 2 q 1 q 2 q 2 q 1 g b2 g b1 p + p + p + n + n + p + figure 4 parasitic thyristor
application note 30 3.2 latch-up immunity latch-up immunity is evaluated by the test circuit shown in figure 5. table 1 lists the test results of latch-up immunity of hitachi? high-speed cmos logic. the starting voltage of high-speed cmos logic is over 300 v which causes almost no problems for practical use. a all other input pins are conne- cted to either v cc or gnd. test pin v cc gnd c = 200pf v cc = 7v i cc figure 5 latch-up immunity test circuit table 1 latch-up starting voltage test results latch-up starting voltage positive over 300 v negative over 300 v measured samples hd74hc00 hd74hc02 hd74hc04 hd74hc08 hd74hc14 hd74hc32 hd74hc74
application note 31 hd74hc138 hd74hc139 hd74hc157 hd74hc158 hd74hc175 hd74hc273 hd74hc373 hd74hc533 5 pieces per type 4. electrical characteristics 4.1 dc characteristics (1) logic threshold voltage (v th ) the logic threshold voltage (v th ) of hitachi? high-speed cmos logic ics (hd74hc series) is at half the level of v cc in order to set up the widest noise margin possible. (2) output current characteristics hitachi? high-speed cmos logic ics have symmetrical characteristics between i oh and i ol . thus, the balance between t plh and t phl is mostly kept even when connecting with a comparatively large load capacitance. figures 7 and 8 show the output current characteristics.
application note 32 0 2 4 6 246 input voltage v in (v) output voltage v out (v) v cc = 6 v v cc = 4.5 v v cc = 2 v figure 6 output voltage vs input voltage 0246 low output voltage v ol (v) 20 40 60 80 100 120 low output current i ol (ma) v cc = 6 v 4.5 v 2 v (b) standard output (hd74hc00) 0246 low output voltage v ol (v) 20 40 60 80 100 120 low output current i ol (ma) v cc = 6 v 4.5 v 2 v (b) bus driver output (hd74hc244) figure 7 output current vs voltage (low level)
application note 33 06 4 2 high output voltage v oh (v) ?00 ?0 ?0 ?0 0 ?0 high output voltage i oh (ma) v cc = 2 v 4.5 v 6 v (a) standard output (hd74hc00) 06 4 2 high output voltage v oh (v) (b) bus driver output (hd74hc244) ?00 ?0 ?0 ?0 0 ?0 high output voltage i oh (ma) v cc = 2 v 4.5 v 6 v figure 8 output current vs voltage (high level) 4.2 ac characteristics t plh and t phl of hitachi? high-speed cmos logic ics are set up to be about the same to simplify system timing design. (1) propagation delay time, output rise and fall time vs supply voltage characteristics. 0246 supply voltage v cc (v) 5 10 20 50 ta = 25 c c l = 50 pf propagation delay time t plh, t phl (ns) t plh t phl (a) standard output (hd74hc00) 0246 supply voltage v cc (v) 5 ta = 25 c c l = 50 pf 5 10 20 50 propagation delay time t plh, t phl (ns) t phl t plh (b) bus driver output (hd74hc244) figure 9 propagation delay time vs supply voltage
application note 34 ta = 25 c c l = 50 pf 0246 supply voltage v cc (v) 2 5 10 20 output rise and fall time t tlh, t thl (ns) t thl t tlh ta = 25 c c l = 50 pf 0246 supply voltage v cc (v) 2 5 10 20 output rise and fall time t tlh, t thl (ns) t thl t tlh figure 10 output rise and fall time vs supply voltage (2) propagation delay time, output rise and fall time vs load capacitance characteristics. 0 50 200 100 150 load capacitance c l (pf) 5 10 15 20 v cc = 4.5 v ta = 25 c propagation delay time t plh, t phl (ns) t phl t plh (a) standard output (hd74hc00) 0 50 200 100 150 load capacitance c l (pf) 5 10 15 20 v cc = 4.5 v ta = 25 c propagation delay time t plh, t phl (ns) t phl t plh (b) bus driver output (hd74hc244) figure 11 propagation delay time vs load capacitance
application note 35 5 10 15 20 25 v cc = 4.5 v ta = 25 c 0 50 200 100 150 load capacitance c l (pf) output rise and fall time t tlh, t thl (ns) t thl t tlh 5 10 15 20 25 v cc = 4.5 v ta = 25 c 0 50 200 100 150 load capacitance c l (pf) output rise and fall time t tlh, t thl (ns) t thl t tlh (b) bus driver output (hd74hc244) (a) standard output (hd74hc00) figure 12 output rise and fall time vs load capacitance
application note 36 5. power dissipation 5.1 calculating the power dissipation the power dissipation p t of high-speed cmos logic can be calculated by (1). from this equation, the power dissipation depends on the load capacitance, frequency and supply voltage. p t = (c l + c pd )?f ?v cc 2 (1) figure 13 shows examples of the operating frequency with the power supply current. 010 1.0 operating frequency f (mhz) 0.01 0.1 1.0 ls-ttl hd74ls74 power supply current (per circuit) (ma) high-speed cmos logic hd74hc74 c l = 50 pf c l = 0 pf c l = 50 pf c l = 0 pf figure 13 operating frequency vs power supply current
application note 37 5.2 power dissipation capacitance power dissipation capacitance (c pd ) can be calculated by the following equations, p t1 = c pd ?v cc 2 ?f 1 = i cc1 ?v cc (2) p t2 = c pd ?v cc 2 ?f 2 = i cc2 ?v cc (3) therefore, c= p p v(ff) = ii v(ff) pd t2 t1 cc 2 21 cc 2 cc 1 cc 2 1 (4) then, i cc1 : supply current at frequency f 1 i cc2 : supply current at frequency f 2 table 2 lists the power dissipation capacitance of hitachi? high-speed cmos logic. furthermore, the power dissipation capacitance differs according to the input conditions. table 3 shows typical examples. table 2 power dissipation capacitance of high-speed cmos function product part no. note 1 power dissipation capacitance typ. (pf) gate hd74hc00 * 27 hd74hc04 * 24 flip-flop d-type hd74hc74 * 41 j-k-type hd74hc76 * 49 comparator hd74hc85 p 48 decorder hd74hc138 p 90 counter hd74hc161 p 57 buffer hd74hc240 * 42 multiplexer hd74hc258 p 78 latch hd74hc373 p 57 notes: 1. *:per circuit; p:per package. 2. measurement circuit is shown in figure 14.
application note 38 v cc v cc y a a p.g. y p.g. a hd74hc00 hd74hc04 v cc p.g.1 p.g.2 a pr clr ck d q q f pg1 f pg2 f pg2 =1/2 pg1 hd74hc74 v cc p.g. a j ck clr q q hd74hc76 pr v cc v cc a a = b a p.g. a < b a < b a > b a > b a = b other inputs p.g. g1 a b c y 0 y 1 y 2 y 3 y 4 y 5 y 6 y 7 g2a g2b hd74hc85 hd74hc138 a b figure 14 measurement circuits for dynamic power supply current
application note 39 a v cc v cc y a p.g. p.g. ep et clr ld q a q b q c q d carry ck a b c d g a hd74hc161 hd74hc240 v cc v cc a a p.g. 1b s other inputs 1y 2y 3y 4y p.g. 1q 2q 3q 4q 5q 6q 7q 8q 1d 2d 3d 4d 5d 6d 7d 8d oc eg hd74hc258 hd74hc373 measurement conditions ta = 25 c v cc = 6v f1 = 1mhz f2 = 5mhz duty = 50% t r = t f = 6ns t r t r 90% 10% 10% 90% figure 14 measurement circuits for dynamic power supply current (cont)
application note 40 table 3 power dissipation capacitance by input conditions product part no. input conditions power dissipation capacitance (pf) hd74hc00 single input v cc a p.g. a b 27 double input v cc a p.g. a b 27 hd74hc161 counting operation v cc a p.g. ep et clr ld q a q b q c q d carry ck a b c d 57 preset operation v cc a p.g.1 p.g.2 ep et clr q a q b q c q d carry ck a b c d ld 113
application note 41 6. decoupling cmos logic ics have current spikes when switching. these spikes are produced by the repeated charging and discharging of the output capacitance when charging the output level from low to high or high to low. because of the current spikes the potentials of v cc and gnd change, and large current spikes flow when switching. therefore ringing is produced at the output. (see figure 15 a.) to prevent this, decoupling capacitors must be provided externally between v cc and gnd. this is proven to be useful in instantly absorbing the current and ringing at the output as shown in figure 15 b. output voltage waveform v cc current waveform gnd current waveform (a) no decoupling capacitor (b) decoupling capacitor (0.1 m f) vertical horizontal 20 ma/div 100 ns/div vertical horizontal 2 v/div 100 ns/div gnd 0 0 figure 15 hd74hc00 spike current waveform 7. precautions on board design high-speed cmos logic has different electrical characteristics, such as switching speed and output current drivability, from the conventional standard logics (al-gate cmos, ls-ttl). the system design requires an application technique for high-speed cmos logic. here an interfacing technique between high-speed cmos logic and ls-ttl will be explained. 7.1 transmission line reflection (1) analysis of transmission signals by the bergeron diagram the bergeron diagram is commonly used for the analysis of transmission signals in high-speed digital systems. figure 17 is the analysis result of an actual transmission model which is shown in figure 16.
application note 42 as for the analysis conditions, z 0 = 125 w considering the standard system board, and the wiring length (l) is 1.5 m. the output impedance of the hd74hc04, which operates as a driver becomes the i oh - v oh characteristic curve when the output is high, and the input impedance of the hd74ls04 which operates as a receiver becomes the i ih - v ih characteristic curve. on the other hand, when the output level of the hd74hc04 is low, the output impedance becomes the i ol - v ol characteristic curve and the input impedance becomes the i f - v f characteristic curve. the drawing of load line z 0 as these input/output impedance curves enables the reflection of the transmission signal to be analyzed. the intersection coordinates in figure 17 shows the voltage and current values at the drive end of 2t (t being the propagation delay from the driver end to the receiver end) intervals when the coordinates are even numbers (2t, 4t) or zero, or the voltage and current values at the receiver end when the coordinates are odd numbers (t, 3t, 5t). figure 18 shows the analysis result of the voltage waveform at the receiver end.
application note 43 0 ? p1 ? p2 +v p2 +v p1 voltage (v) time t (b) receiver waveform model driver receiver hd74ls04 hd74hc240 z 0 l : 1.5 m : 125 w 50 w (a) digiral signal transmission model circuit l z 0 note: the model circuit above (figure 16a) is used for analysis when the high-speed cmos logic hd74hc240 is connected as a driver, and the ls-ttl hd74ls04 as a receiver the waveform model for overshoot and undershoot at the receiver end is shown in figure 16b. figure 16 digital signal transmission
application note 44 v (v) 8 7 6 3 2 1 ? ? ?00 ?0 ?0 ?0 40 60 80 100 20 2t 3t 3t 3t 4t 2t 0 5t 4 5 t hd74ls04 i f ?v f characteristics hd74hc240 i ol ?v ol characteristics hd74hc240 i oh ?v oh characteristics z 0 load line i (ma) l z 0 ta : 1.5 m : 125 w : 25 c e20 figure 17 bergeron diagram analysis of the transmission model 500 8 7 6 5 4 3 2 1 0 ? voltage (v) +v p2 0 100 200 300 time t (ns) 400 600 700 800 figure 18 analysis results of the waveform at the receiver end (2) an example for measuring the reflection on the transmission line figure 19 shows the measured results of the reflection of the transmission line using three types of transmission line media such as 1) coaxial cable (z 0 = 50 w ), 2) twisted pair cable (z 0 = 120 w ), and 3) single lead wire (z 0 = 150 to 200 w ). figure 19 shows that the drivers and receivers operate normally with a wiring length of up to 2 m. however, careful precautions should be taken when considering impedance in practical system designing.
application note 45 transmission line midium waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd receiver hd74hc240 driver hd74hc240 receiver hd74hc240 driver hd74hc240 coaxial cable ( l = 2m) twisted pair cable ( l = 2m) single lead wire ( l = 2m) pg 50 w waveform waveform waveform waveform , , vertical horizontal 5 v/div 100 ns/div hd74hc240 hd74ls04 receiver driver hd74hc240 wiring length l = 2 m driving pulse for all inputs ( ) c l = 50 pf r l = 1 k w v cc measurement conditions v cc = 5 v ta = 25 c f = 1 mhz duty = 50% t r = t f = 6 ns note:the load circuit shown on the right is used when the hd74ls04 is used as a receiver. figure 19 reflection ringing waveforms (driver: hd74hc240)
application note 46 7.2 crosstalk crosstalk is the capacitative coupling of signals from one line to another. figure 20 shows an example of crosstalk noise levels using a twisted pair cable. figure 20 also shows that the wiring length beyond 1 m causes malfunction. careful precautions should be taken especially when the spacing between circuits is narrow.
application note 47 waveform waveform3 waveform2 driver and receiver : hd74hc240 wiring length l pg 50 w c l = 50 pf c l = 50 pf vin measurement conditions v cc = 5 v ta = 25 c f = 1 mhz duty = 50% t r = t f = 6 ns waveform vertical horizontal 5 v/div 100 ns/div waveform , vertical horizontal 2 v/div 100 ns/div waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd waveform gnd wiring lenght l = 2m l = 1m l = 0.5m vin = low vin = high figure 20 crosstalk noise waveform (driver: hd74hc240)
application note 48 8. multivibrator the output pulse width (t wq ) of a multivibrator is determined by the external capacitance (c ext ) and external resistor (r ext ), and calculated by the equation t wq = k ?r ext ?c ext . the value of constant k determines the part number according to the jedec committee as listed in table 4. hitachi has 4 types of high-speed cmos logic, hd74hc123a, 221, 423a, 4538. constant k changes from the values of table 4 when c ext is less than 0.01 m f. figure 21 and 22 graph the output pulse width vs external capacitance, constant k vs power supply voltage characteristics of the hd74hc123a. table 4 jedec sp of multivibrators product part no. output pulse width 74hc123 t wq = 0.45 ?(rext) ?(cext) 123a* t wq = 1.0 ?(rext) ?(cext) 74hc221* t wq = 0.7 ?(rext) ?(cext) 221a t wq = 1.0 ?(rext) ?(cext) 74hc423 t wq = 0.45 ?(rext) ?(cext) 423a* t wq = 1.0 ?(rext) ?(cext) 74hc4538* t wq = 0.7 ?(rext) ?(cext) note: *presently under mass production at hitachi.
application note 49 output pulse width t wq (s) 0.001 m 0.01 m 0.1 m 1.0 m external capacitance c ext (f) 0.0001 m 0.00001 m 100 n 1 m 10 m 100 m 1 m 10 m 100 m ta = 25 c v cc = 5 v r ext = 1000 k w 100 k w 10 k w 1 k w figure 21 output pulse width vs external capacitance and resistance constant k 6 4 supply voltage v cc (v) 2 0 0.8 1.0 1.2 1.4 c ext = 0.001 m f r ext = 10 k w c ext = 1 m f note: in order to prevent any malfunctions due to noise, connect a high-frequency performance capacitor between v cc and gnd, and keep the wiring between the external components and cext, rext/cext pins as short as possible. figure 22 constant k vs supply voltage
application note 50 9. interfacing hitachi? high-speed cmos logic has two types of input voltage levels, 74hc and 74hct. the 74hc has a cmos-type input level and the 74hct has a ttl-type input level. interfacing from high-speed cmos logic to ls-ttl since the output level of high-speed cmos logic is of cmos, the use of an interfacing circuit is not necessary. this is the same case for a microcomputer and memory ic with ttl input levels. v oh = 4.13v min > v ih = 2.0v min v ol = 0.37v max < v il = 0.8v max v cc gnd ls ttl 74hc or 74hct figure 23 interfacing hs-cmos to ls-ttl interfacing from ls-ttl to high-speed cmos logic (74hct type) an interfacing circuit is not necessary. this is the same case for a microcomputer and memory ic with ttl output levels. v oh = 2.7v min > v ih = 2.0v min v ol = 0.4v max < v il = 0.8v max v cc gnd ls ttl 74hct figure 24 interfacing ls-ttl to 74hct interfacing from ls-ttl to high-speed cmos logic (74hc type) a pull-up resistor should be added as shown in figure 25. the output voltage of ls-ttl (v oh ) is 2.7 v (min), where as the input voltage of 74hc (v ih ) is 3.15 v (min.).
application note 51 this implies that ls-ttl cannot drive 74hc types directly. this is the same case for a microcomputer and memory ics with ttl output levels. v oh = 2.7v min < v ih = 3.15v min v ol = 0.4v max < v il = 1.35v max v cc gnd ls ttl 74hc r pull-up resistor figure 25 interfacing ls-ttl to 74hc interfacing from ls-ttl with 3-state output to high-speed cmos logic. a pull-up or pull-down resistor should be added as shown in figure 26. when the output of a ls-ttl is in the high-impedance state, the input of the high-speed cmos becomes unstable. this is the same case for all devices with a tri-state output structure. v cc gnd ls ttl with 3-state output 74hc 74hct figure 26 interfacing ls-ttl with 3-state output to 74hc or 74hct
application note 52 10. surface mount package 10.1 mounting small outline packages (sop, tssop) the explanation on the mounting of sops describes the characteristics and reliabilities of the small ic package. (1) dip soldering initially, the package is temporarily fixed on to the board by an adhesive. adhesive agent applied adhesive agent cured residual flux removed sop attached adhesive agent pcb sop direction of movement finished product wave solder (solder vessel for surface mounting) dip soldering assembly completed electrode figure 27 process flow for dip soldering sop with the component side of the board downward, the package is then passed through molten solder. figure 27 depicts the process flow for dip soldering sop. as compared with reflow methods, this method exerts an extremely high thermal stress on the semiconductor chips. the adverse effects from this thermal should be avoided by providing a preheating zone to lessen the thermal shock and by minimizing the soldering time. figure 28 shows a typical temperature profile for dip soldering. the dip soldering temperature is 260?c maximum at a period of 10 seconds maximum (2 to 4 seconds is recommended).
application note 53 natural or forced air cooling solder melting point time pcb surface temperature cooling dipping preheating 1 to 3 min 2 to 4 sec 80 to 150 c t(max) = 260 c temperature figure 28 temperature profile of dip soldering (2) reflow soldering reflow soldering is the basic method of mounting the sop on to a board. the solder composition to be used is sn63/pb37 or sn62/pb36/ag2 with a melting point of 183?c to 193?c. a recommended pasty flux is solder cream sp210-2 by tamura kaken. a pasty flux and organic solvent are also used during the process. be careful to reflow solder at a low temperature for short periods of time. the recommended conditions are shown below. the allowable board temperature is 230?c maximum and the maximum heating time is 15 sec. (3) footprint dimension vs solderability the failure rate of soldering is affected by footprint dimensions. figure 29 shows the soldering failure with the footprint dimension. the recommended dimensions are within the safety zone of this figure. when reflow sordering sops, the recommended thickness of a footprint is 0.2 mm min.
application note 54 displacement safety bridge formed by solder lack of solder width of footprint w (mm) length of footprint l (mm) 0.1 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 w l e 1 sop foot print notes: 1. pin pitch = 1.27 mm 2. recommended spacings between footprint centers. e 1 = 7.62 mm (sop-14, 16) e 1 = 9.53 mm (sop-20) 3. both w and l are footprint dimensions based on the lead direction of the sop. figure 29 recommended dimension of footprint (4) thermal resistance of sop figure 30 shows the derating curves for sops of high-speed cmos logic, and table 6 lists the thermal resistance ( q j-a ) for sops.
application note 55 25 30 35 40 45 50 55 60 65 70 75 80 85 operating ambient temperature ta ( c) maximnm continuous dissipation pt (mw) derating curve of 14/16-pin sop 1136 1000 961 785 681 576 500 468 at t j (max) = 150 c at t j (max) = 100 c no. (1) (2) (3) wind velocity derating factor 0m/s 1m/s 3m/s 6.3mw/ c 7.7mw/ c 9.1mw/ c no. (1) (2) (3) wind velocity derating factor 0m/s 1m/s 3m/s 6.7mw/ c 9.1mw/ c 10.5mw/ c 25 30 35 40 45 50 55 60 65 70 75 80 85 operatin g ambient temperature ta ( c ) maximnm continuous dissipation pt (mw) derating curve of 20-pin sop 1312 1000 1137 835 767 682 500 502 at t j (max) = 150 c at t j (max) = 100 c (3) (1) (2) (2) (3) (3) (1) (2) (3) (2) (1) (1) note: when ta is below 25?c, p t becomes the same value as at ta = 25?c being independent of ta. the data above was measured by using the d v be method on a glass-epoxy board (40 40 1.0 mm) with wiring density of 10%. careful considerations are required for input and load conditions, ta, cooling, etc., during actual use. figure 30 derating curves of sop
application note 56 table 6 thermal resistance of sops maximum continuous dissipation ta = 25?c number of pins wind velocity derating factor thermal resistance t j (max) = 150?c t j (max) = 100?c 14 0 m/s 6.3 mw/?c 160 ?c/w 785 mw 468 mw 16 1 m/s 7.7 mw/?c 130 ?c/w 961 mw 576 mw 3 m/s 9.1 mw/?c 110 ?c/w 1136 mw 681 mw 20 0 m/s 6.7 mw/?c 150 ?c/w 835 mw 502 mw 1 m/s 9.1 mw/?c 110 ?c/w 1137 mw 682 mw 3 m/s 10.5 mw/?c 95 ?c/w 1312 mw 787 mw (5) thermal resistance of tssop figure 31 shows the derating curve of tssop with hd74bc/ac/hc devices, table 7 shows the thermal resistance ( q j-a ) and figure 32 shows the mounting method. derating curves of thin small outline package (14, 16, 20 and 24 pins) at tj (max) = 100 c 1000 500 300 25 30 35 40 45 50 55 60 65 70 75 80 85 operatin g temperature ta ( c ) operatin g temperature ta ( c ) 1000 500 757 862 25 30 35 40 45 50 55 60 65 70 75 80 85 tolerable power dissipation p t (mw) tolerable power dissipation p t (mw) 24 pin 20 pin derating curves of thin small outline package (14, 16, 20 and 24 pins) at tj (max) = 150 c 0 454 517 24 pin 20 pin 14/16 pin 14/16 pin 0 note: fore the ambient temperature less than 25?c, the power dissipation at 25?c is applied. the data above are measured by d v be method mounting on glass epoxy board (40 40 1.6 mm) with 10% of wiring density. in the actual application, using conditions, ambient temperature and forced air-cooling conditions should be sufficiently examined. figure 31 derating curve of tssop
application note 57 table 7 thermal resistance of tssop package tolerable power dissipation number of pins wind velocity derating factor thermal resistance at t j (max) = 150?c at t j (max) = 100?c 14 0 m/s 4.0 mw/?c 250?c/w 500 mw 300 mw 16 20 0 m/s 6.1 mw/?c 165?c/w 757 mw 454 mw 24 0 m/s 6.9 mw/?c 145?c/w 862 mw 517 mw (6) tssop solder mounting 235 c max 10sec max 140 to 160 c @ 60sec 1 to 4 c/sec 1 to 5 c/sec surface temperature of package time infrared-ray reflow recommended conditions 215 c 30sec max 140 to 160 c @ 60sec 1 to 5 c/sec surface temperature of package time vapor-phase reflow recommended conditions recommended:for the whole heating on solder mounting, infrared-ray reflow and vapor-phase reflow are recommended. (solder-dipping is not recommended.) figure 32 mounting method of tssop
application note 58 (7) marking on package (a) small outline package (eiaj) 14, 16, 20 pins ymwc bc a hd74bc series ymwc ac hd74ac series ymwc hc hd74hc series lot no. type no. (b) small outline package (jedec) 14, 16, 20 pins ymwc bc a hd74bc series ymwc ac hd74ac series ymwc hc hd74hc series lot no. type no. note: meaning of marking on package example device name: hd74bc245at y: year code (the last digit of year) m: month code w: week code c: control code type no.: delete hd74 and package code (t) from device name (c) thin shrink small outline package 14, 16, 20 pins ymwc a bc hd74bc series ymwc c a hd74ac series ymwc hc hd74hc series lot no. type no. ?14, 16, 20 pins note: meaning of marking on package example device name: hd74bc245at y: year code (the last digit of year) m: month code w: week code c: control code type no.: delete hd74 and package code (t) from device name

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