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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a lc 2 mos complete, dual 12-bit mdacs AD7837/ad7847 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 functional block diagrams general description the AD7837/ad7847 is a complete, dual, 12-bit multiplying digital-to-analog converter with output amplifiers on a mono- lithic cmos chip. no external user trims are required to achieve full specified performance. both parts are microprocessor compatible, with high speed data latches and interface logic. the ad7847 accepts 12-bit parallel data which is loaded into the respective dac latch using the wr input and a separate chip select input for each dac. the AD7837 has a double-buffered 8-bit bus interface structure with data loaded to the respective input latch in two write op- erations. an asynchronous ldac signal on the AD7837 up- dates the dac latches and analog outputs. the output amplifiers are capable of developing 10 v across a 2 k w load. they are internally compensated with low input off- set voltage due to laser trimming at wafer level. the amplifier feedback resistors are internally connected to v out on the ad7847. the AD7837/ad7847 is fabricated in l inear compatible cmos (lc 2 mos), an advanced, mixed technology process that com- bines precision bipolar circuits with low power cmos logic. a novel low leakage configuration (u.s. patent no. 4,590,456) ensures low offset errors over the specified temperature range. product highlights 1. the AD7837/ad7847 is a dual, 12-bit, voltage-out mdac on a single chip. this single chip design offers considerable space saving and increased reliability over multichip designs. 2. the AD7837 and the ad7847 provide a fast versatile inter- face to 8-bit or 16-bit data bus structures. features two 12-bit mdacs with output amplifiers 4-quadrant multiplication space-saving 0.3", 24-pin dip and 24-terminal soic package parallel loading structure: ad7847 (8 + 4) loading structure: AD7837 applications automatic test equipment function generation waveform reconstruction programmable power supplies synchro applications
rev. 0 C2C AD7837/ad7847Cspecifications 1 (v dd = +15 v 6 5%, v ss = C15 v 6 5%, agnda = agndb = dgnd = o v. v refa = v refb = +10 v, r l = 2 k v , c l = 100 pf [v out connected to r fb AD7837]. all spe cifications t min to t max unless otherwise noted.) parameter a version b version s version units test conditions/comments static performance resolution 12 12 12 bits relative accuracy 2 1 1/2 1 lsb max differential nonlinearity 2 1 1 1 lsb max guaranteed monotonic zero code offset error 2 @ +25 c 2 2 2 mv max dac latch loaded with all 0s t min to t max 4 3 5 mv max temperature coefficient = 5 m v/ c typ gain error 2 @ +25 c 5 2 5 lsb max dac latch loaded with all 1s t min to t max 7 4 7 lsb max temperature coefficient = 2 ppm of fsr/ c typ reference inputs v ref input resistance 8/13 8/13 8/13 k w min/max typical input resistance = 10 k w v refa , v refb resistance matching 3 3 3 % max typically 0.5% digital inputs input high voltage, v inh 2.4 2.4 2.4 v min input low voltage, v inl 0.8 0.8 0.8 v max input current 1 1 1 m a max digital inputs at 0 v and v dd input capacitance 3 8 8 8 pf max analog outputs dc output impedance 0.2 0.2 0.2 w typ short circuit current 15 15 15 ma typ v out connected to agnd power requirements 4 v dd range 14.25/15.75 14.25/15.75 14.25/15.75 v min/max v ss range C14.25/C15.75 C14.25/C15.75 C14.25/C15.75 v min/max power supply rejection d gain/ d v dd 0.1 0.1 0.1 % per % max v dd = 15 v 5%, v ref = C10 v d gain/ d v ss 0.1 0.1 0.1 % per % max v ss = C15 v 5%, v ref = +10 v i dd 10 10 10 ma max output unloaded. typically 5 ma i ss 6 6 6 ma max output unloaded. typically 4 ma ac characteristics 2, 3 voltage output settling time 4 4 4 m s typ settling time to within 1/2 lsb of final value. dac latch alternately loaded with all 0s and all 1s slew rate 7 7 7 v/ m s typ digital-to-analog glitch impulse 175 175 175 nv secs typ dac latch alternately loaded with 01 . . . 11 and 10 . . . 00 channel-to-channel isolation v refa to v outb C95 C95 C95 db typ v refa = 20 v p-p, 10 khz sine wave. dac latches loaded with all 0s v refb to v outa C95 C95 C95 db typ v refb = 20 v p-p, 10 khz sine wave. dac latches loaded with all 0s multiplying feedthrough error C90 C90 C90 db typ v ref = 20 v p-p, 10 khz sine wave. dac latch loaded with all 0s unity gain small signal bw 600 600 600 khz typ v ref = 100 mv p-p sine wave. dac latch loaded with all 1s full power bw 110 110 90 khz typ v ref = 20 v p-p sine wave. dac latch loaded with all 1s total harmonic distortion C88 C88 C88 db typ v ref = 6 v rms, 1 khz. dac latch loaded with all 1s digital crosstalk 10 10 10 nv secs typ code transition from all 0s to all 1s output noise voltage @ +25 c see typical performance graphs (0.1 hz to 10 hz) 2 2 2 m v rms typ amplifier noise and johnson noise of r fb notes 1 temperature ranges are as follows: a, b versions, C40 c to +85 c; s version, C55 c to +125 c. 2 see terminology. 3 sample tested @ +25 c to ensure compliance. 4 the devices are functional with v dd /v ss = 12 v (see typical performance graphs.) specifications subject to change without notice.
AD7837/ad7847 rev. 0 C3C timing characteristics 1, 2 limit at t min , t max limit at t min , t max parameter (a, b versions) (s version) units conditions/comments t 1 0 0 ns min cs to wr setup time t 2 0 0 ns min cs to wr hold time t 3 80 100 ns min wr pulse width t 4 80 80 ns min data valid to wr setup time t 5 10 10 ns min data valid to wr hold time t 6 3 15 15 ns min address to wr setup time t 7 3 15 15 ns min address to wr hold time t 8 3 80 100 ns min ldac pulse width notes 1 sample tested @ +25 c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. 2 see figures 3 and 5. 3 AD7837 only. absolute maximum ratings* (t a = +25 c unless otherwise noted) v dd to dgnd, agnda, agndb . . . . . . . . C0.3 v to +17 v v ss 1 to dgnd, agnda, agndb . . . . . . . +0.3 v to C17 v v refa , v refb to agnda, agndb . . . . . . . . . . . . . . . . . . . . . . . . . . v ss C 0.3 v to v dd + 0.3 v agnda, agndb to dgnd . . . . . . . C0.3 v to v dd + 0.3 v v outa 2 , v outb 2 to agnda, agndb . . . . . . . . . . . . . . . . . . . . . . . . . . v ss C 0.3 v to v dd + 0.3 v r fba 3 , r fbb 3 to agnda, agndb . . . . . . . . . . . . . . . . . . . . . . . . . . v ss C 0.3 v to v dd + 0.3 v digital inputs to dgnd . . . . . . . . . . . C0.3 v to v dd + 0.3 v operating temperature range commercial/industrial (a, b versions) . . . C40 c to +85 c extended (s version) . . . . . . . . . . . . . . . . C55 c to +125 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 secs) . . . . . . . . . . . +300 c power dissipation (any package) to +75 c . . . . . . . 1000 mw derates above +75 c by . . . . . . . . . . . . . . . . . . . . 10 mw/ c notes 1 if v ss is open circuited with v dd and either agnd applied, the v ss pin will float positive, exceeding the absolute maximum ratings. if this possibility exists, a schottky diode connected between v ss and agnd (cathode to agnd) ensures the maximum ratings will be observed. 2 the outputs may be shorted to voltages in this range provided the power dissipation of the package is not exceeded. 3 AD7837 only. *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. ordering guide temperature relative package model 1 range accuracy option 2 AD7837an C40 c to +85 c 1 lsb n-24 AD7837bn C40 c to +85 c 1/2 lsb n-24 AD7837ar C40 c to +85 c 1 lsb r-24 AD7837br C40 c to +85 c 1/2 lsb r-24 AD7837aq C40 c to +85 c 1 lsb q-24 AD7837bq C40 c to +85 c 1/2 lsb q-24 AD7837sq C55 c to +125 c 1 lsb q-24 ad7847an C40 c to +85 c 1 lsb n-24 ad7847bn C40 c to +85 c 1/2 lsb n-24 ad7847ar C40 c to +85 c 1 lsb r-24 ad7847br C40 c to +85 c 1/2 lsb r-24 ad7847aq C40 c to +85 c 1 lsb q-24 ad7847bq C40 c to +85 c 1/2 lsb q-24 ad7847sq C55 c to +125 c 1 lsb q-24 notes 1 to order mil-std-883, class b processed parts, add /883b to part number. 2 n = plastic dip; q = cerdip; r = soic. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although these devices feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. (v dd = +15 v 6 5%, v ss = C15 v 6 5%, agnda = agndb = dgnd = o v)
AD7837/ad7847 rev. 0 C4C terminology relative accuracy (linearity) relative accuracy, or endpoint linearity, is a measure of the maximum deviation of the dac transfer function from a straight line passing through the endpoints. it is measured after allowing for zero and full-scale errors and is expressed in lsbs or as a percentage of full-scale reading. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb or less over the operating temperature range ensures monotonicity. zero code offset error zero code offset error is the error in output voltage from v outa or v outb with all 0s loaded into the dac latches. it is due to a combination of the dac leakage current and offset errors in the output amplifier. gain error gain error is a measure of the output error between an ideal dac and the actual device output with all 1s loaded. it does not include offset error. total harmonic distortion this is the ratio of the root-mean-square (rms) sum of the har- monics to the fundamental, expressed in dbs. multiplying feedthrough error this is an ac error due to capacitive feedthrough from the v ref input to v out of the same dac when the dac latch is loaded with all 0s. channel-to-channel isolation this is an ac error due to capacitive feedthrough from the v ref input on one dac to v out on the other dac. it is measured with the dac latches loaded with all 0s. digital feedthrough digital feedthrough is the glitch impulse injected from the digi- tal inputs to the analog output when the data inputs change state, but the data in the dac latches is not changed. for the AD7837, it is measured with ldac held high. for the ad7847, it is measured with csa and csb held high. digital crosstalk digital crosstalk is the glitch impulse transferred to the output of one converter due to a change in digital code on the dac latch of the other converter. it is specified in nv secs. digital-to-analog glitch impulse this is the voltage spike that appears at the output of the dac when the digital code changes, before the output settles to its fi- nal value. the energy in the glitch is specified in nv secs and is measured for a 1 lsb change around the major carry transition (0111 1111 1111 to 1000 0000 0000). unity gain small signal bandwidth this is the frequency at which the small signal voltage output from the output amplifier is 3 db below its dc level. it is mea- sured with the dac latch loaded with all 1s. full power bandwidth this is the maximum frequency for which a sinusoidal input signal will produce full output at rated load with a distortion less than 3%. it is measured with the dac latch loaded with all 1s. AD7837 pin function description (dip & soic pin numbers) pin mnemonic description 1 cs chip select. active low logic input. the device is selected when this input is active. 2r fba amplifier feedback resistor for dac a. 3v refa reference input voltage for dac a. this may be an ac or dc signal. 4v outa analog output voltage from dac a. 5 agnda analog ground for dac a. 6v dd positive power supply. 7v ss negative power supply. 8 agndb analog ground for dac b. 9v outb analog output voltage from dac b. 10 v refb reference input voltage for dac b. this may be an ac or dc signal. 11 dgnd digital ground. ground reference for digital circuitry. 12 r fbb amplifier feedback resistor for dac b. 13 wr write input. wr is an active low logic input which is used in conjunction with cs , a0 and a1 to write data to the input latches. 14 ldac dac update logic input. data is transferred from the input latches to the dac latches when ldac is taken low. 15 a1 address input. most significant address input for input latches (see table ii). 16 a0 address input. least significant address input for input latches (see table ii). 17C20 db7Cdb4 data bit 7 to data bit 4. 21C24 db3Cdb0 data bit 3 to data bit 0 (lsb) or data bit 11 (msb) to data bit 8.
AD7837/ad7847 rev. 0 C5C ad7847 pin function description (dip & soic pin numbers) pin mnemonic description 1 1 csa chip select input for dac a. active low logic input. dac a is selected when this input is low. 1 2 csb chip select input for dac b. active low logic input. dac b is selected when this input is low. 1 3v refa reference input voltage for dac a. this may be an ac or dc signal. 1 4v outa analog output voltage from dac a. 1 5 agnda analog ground for dac a. 1 6v dd positive power supply. 1 7v ss negative power supply. 1 8 agndb analog ground for dac b. 1 9v outb analog output voltage from dac b. 10 v refb reference input voltage for dac b. this may be an ac or dc signal. 11 dgnd digital ground. 12 db11 data bit 11 (msb). 13 wr write input. wr is a positive edge triggered input which is used in conjunction with csa and csb to write data to the dac latches. 14C24 db10Cdb0 data bit 10 to data bit 0 (lsb). AD7837 pin configuration dip & soic 1 2 3 4 5 6 7 8 9 10 11 24 23 22 21 20 19 18 17 16 15 14 12 13 top view (not to scale) AD7837 cs r fba v refa v outa agnda v dd v ss agndb v outb v refb dgnd r fbb wr ldac a1 a0 db7 db6 db5 db4 db3 db2 db1 db0 ad7847 pin configuration dip & soic 1 2 3 4 5 6 7 8 9 10 11 24 23 22 21 20 19 18 17 16 15 14 12 13 top view (not to scale) ad7847 csa v refa v outa agnda v dd v ss agndb v outb v refb dgnd wr db7 db6 db5 db4 db3 db2 db1 db0 csb db11 db8 db9 db10
AD7837/ad7847Ctypical performance graphs rev. 0 C6C 10 0 ?0 ?0 ?0 10 4 10 5 10 6 10 7 frequency ?hz gain ?db v dd = +15v v ss = ?5v v ref = +20vp? dac code = 111...111 frequency response 0.5 0.4 0.3 0.2 0.1 0.0 9 11 13 15 17 error ?lsb inl dnl v ref = 7.5v v dd /v ss ?volts linearity vs. power supply 0.1 1 10 100 frequency ?khz feedthrough ?db ?0 ?0 1000 ?0 ?0 ?0 ?00 v dd = +15v v ss = ?5v v ref = 20v p? dac code = 000...000 multiplying feedthrough error vs. frequency dac to dac linearity matching 0.1 1 10 100 frequency ?khz ?0 ?0 ?0 ?0 ?0 ?0 ?00 thd ?db v dd = +15v v ss = ?5v v ref = 6v rms dac code = 111...111 thd vs. frequency small signal pulse response 10 100 1000 10000 0 10 20 load resistance ?ohms v out ?volts p? v dd = +15v v ss = ?5v v ref = +20v p? @ 1khz dac code = 111...111 output voltage swing vs. resistive load 400 300 200 100 0 .01 .1 1 10 100 frequency ?khz noise spectral density ?nv/ hz v dd = +15v v ss = ?5v v ref = 0v dac code = 111...111 noise spectral density vs. frequency large signal pulse response
AD7837/ad7847 rev. 0 C7C circuit information d/a section a simplified circuit diagram for one of the d/a converters and output amplifier is shown in figure 1. a segmented scheme is used whereby the 2 msbs of the 12-bit data word are decoded to drive the three switches a-c. the re- maining 10 bits drive the switches (s0Cs9) in a standard r-2r ladder configuration. each of the switches aCc steers 1/4 of the total reference cur- rent with the remaining 1/4 passing through the r-2r section. the output amplifier and feedback resistor perform the current to voltage conversion giving v out = C d v ref where d is the fractional representation of the digital word. ( d can be set from 0 to 4095/4096.) the output amplifier can maintain 10 v across a 2 k w load. it is internally compensated and settles to 0.01% fsr (1/2 lsb) in less than 5 m s. note that on the AD7837, v out must be con- nected externally to r fb . r r r 2r 2r 2r 2r 2r 2r ba s9 2r c v ref s8 s0 r/2 agnd shown for all 1s on dac v out figure 1. d/a simplified circuit diagram interface logic informationad7847 the input control logic for the ad7847 is shown in figure 2. the part contains a 12-bit latch for each dac. it can be treated as two independent dacs, each with its own cs input and a common wr input. csa and wr control the loading of data to the dac a latch, while csb and wr control the loading of the dac b latch. the latches are edge triggered so that input data is latched to the respective latch on the rising edge of wr . if csa and csb are both low and wr is taken high, the same data will be latched to both dac latches. the control logic truth table is shown in table i, while the write cycle timing dia- gram for the part is shown in figure 3. dac a latch dac b latch csa wr csb figure 2. ad7847 input control logic table i. ad7847 truth table c sa csb wr function x x 1 no data transfer 1 1 x no data transfer 01 g data latched to dac a 10 g data latched to dac b 00 g data latched to both dacs g 1 0 data latched to dac a 1 g 0 data latched to dac b gg 0 data latched to both dacs x = dont care. g = rising edge triggered. csa, csb wr data valid data t 1 t 3 t 2 t 4 t 5 figure 3. ad7847 write cycle timing diagram interface logic informationAD7837 the input loading structure on the AD7837 is configured for in- terfacing to microprocessors with an 8-bit-wide data bus. the part contains two 12-bit latches per dacan input latch and a dac latch. each input latch is further subdivided into a least- significant 8-bit latch and a most-significant 4-bit latch. only the data held in the dac latches determines the outputs from the part. the input control logic for the AD7837 is shown in figure 4, while the write cycle timing diagram is shown in figure 5. dac a latch dac a ms input latch dac a ls input latch dac b latch dac b ms input latch dac b ls input latch 12 12 44 88 8 db7 db0 ldac cs wr a0 a1 figure 4. AD7837 input control logic
AD7837/ad7847 rev. 0 C8C address valid a0/a1 cs t 1 wr data valid data ldac t 6 t 7 t 3 t 2 t 4 t 5 t 8 figure 5. AD7837 write cycle timing diagram cs , wr , a0 and a1 control the loading of data to the input latches. the eight data inputs accept right-justified data. data can be loaded to the input latches in any sequence. provided that ldac is held high, there is no analog output change as a result of loading data to the input latches. address lines a0 and a1 determine which latch data is loaded to when cs and wr are low. the control logic truth table for the part is shown in table ii. table ii. AD7837 truth table cs wr a1 a0 ldac function 1 x x x 1 no data transfer x 1 x x 1 no data transfer 0 0 0 0 1 dac a ls input latch transparent 0 0 0 1 1 dac a ms input latch transparent 0 0 1 0 1 dac b ls input latch transparent 0 0 1 1 1 dac b ms input latch transparent 1 1 x x 0 dac a and dac b dac latches updated simultaneously from the respective input latches x = dont care. the ldac input controls the transfer of 12-bit data from the input latches to the dac latches. when ldac is taken low, both dac latches, and hence both analog outputs, are updated at the same time. the data in the dac latches is held on the rising edge of ldac . the ldac input is asynchronous and in- dependent of wr . this is useful in many applications especially in the simultaneous updating of multiple AD7837s. however, care must be taken while exercising ldac during a write cycle. if an ldac operation overlaps a cs and wr operation, there is a possibility of invalid data being latched to the output. to avoid this, ldac must remain low after cs or wr return high for a period equal to or greater than t 8 , the minimum ldac pulse width. unipolar binary operation figure 6 shows dac a on the AD7837/ad7847 connected for unipolar binary operation. similar connections apply for dac b. when v in is an ac signal, the circuit performs 2-quadrant multiplication. the code table for this circuit is shown in table iii. note that on the ad7847 the feedback resistor r fb is internally connected to v out . dac a v ss * agnda dgnd * internally connected on ad7847 AD7837 ad7847 v ss v outa v out r fba v dd v refa v dd v in figure 6. unipolar binary operation table iii. unipolar code table dac latch contents msb lsb analog output, v out 1111 1111 1111 v in 4095 4096 ? ? ? ? 1000 0000 0000 v in 2048 4096 ? ? ? ? = 1/2 v in 0000 0000 0001 v in 1 4096 ? ? ? ? 0000 0000 0000 0 v note 1 lsb = v in 4096 .
AD7837/ad7847 rev. 0 C9C applications programmable gain amplifier (pga) the dual dac/amplifier combination along with access to r fb make the AD7837 ideal as a programmable gain amplifier. in this application, the dac functions as a programmable resistor in the amplifier feedback loop. this type of configuration is shown in figure 8 and is suitable for ac gain control. the cir- cuit consists of two pgas in series. use of a dual configuration provides greater accuracy over a wider dynamic range than a single pga solution. the overall system gain is the product of the individual gain stages. the effective gains for each stage are controlled by the dac codes. as the code decreases, the effec- tive dac resistance increases, and so the gain also increases. dac a dac b 2 5 10 8 9 3 4 12 r fba agnda AD7837 v refb v outb v out v in v refa v outa r fbb agndb figure 8. dual pga circuit the transfer function is given by v out v in = r eqa r fba r eqb r fbb (1) where r eqa , r eqb are the effective dac resistances controlled by the digital input code: r eq = 2 12 r in n (2) where r in is the dac input resistance and is equal to r fb and n = dac input code in decimal. the transfer function in (1) thus simplifies to v out v in = 2 12 n a 2 12 n b (3) where n a = dac a input code in decimal and n b = dac b input code in decimal. n a , n b may be programmed between 1 and (2 12 C1). the zero code is not allowed as it results in an open loop amplifier re- sponse. to minimize errors, the digital codes n a and n b should be chosen to be equal to or as close as possible to each other to achieve the required gain. bipolar operation (4-quadrant multiplication) figure 7 shows the AD7837/ad7847 connected for bipolar op- eration. the coding is offset binary as shown in table iv. when v in is an ac signal, the circuit performs 4-quadrant multiplica- tion. to maintain the gain error specifications, resistors r1, r2 and r3 should be ratio matched to 0.01%. note that on the ad7847 the feedback resistor r fb is internally connected to v out . AD7837 ad7847 ad711 r1 20k w dac a * agnda dgnd * internally connected on ad7847 v ss v outa v out r fba v dd v refa v dd v in v ss r2 20k w r3 10k w figure 7. bipolar offset binary operation table iv. bipolar code table dac latch contents msb lsb analog output, v out 1111 1111 1111 + v in 2047 2048 ? ? ? ? 1000 0000 0001 + v in 1 2048 ? ? ? ? 1000 0000 0000 0 v 0111 1111 1111 v in 1 2048 ? ? ? ? 0000 0000 0000 v in 2048 2048 ? ? ? ? = v in note 1 lsb = v in 2048 .
AD7837/ad7847 rev. 0 C10C analog panning circuit in audio applications it is often necessary to digitally pan or split a single signal source into a two-channel signal while main- taining the total power delivered to both channels constant. this may be done very simply by feeding the signal into the v ref in- put of both dacs. the digital codes are chosen such that the code applied to dac b is the 2s complement of that applied to dac a. in this way the signal may be panned between both channels as the digital code is changed. the total power varia- tion with this arrangement is 3 db. for applications which require more precise power control the circuit shown in figure 9 may be used. this circuit requires the AD7837/ad7847, an ad712 dual op amp and 8 equal value resistors. again both channels are driven with 2s complementary data. the maximum power variation using this circuit is only 0.5 dbs. 1/2 ad712 1/2 ad712 rr rr rr rr v in v outa v outb rl a rl b v refa v outa v outb v refb ad7847 figure 9. analog panning circuit the voltage output expressions for the two channels are as follows: v outa = v in n a 2 12 + n a ? ? ? ? v out b = v in n b 2 12 + n b ? ? ? ? where n a = dac a input code in decimal (1 n a 4095) and n b = dac b input code in decimal (1 n b 4095) with n b = 2s complement of n a . the 2s complement relationship between n a and n b causes n b to increase as n a decreases and vice versa. hence n a + n b = 4096. with n a = 2048, then n b = 2048 also; this gives the balanced condition where the power is split equally between both chan- nels. the total power variation as the signal is fully panned from channel b to channel a is shown in figure 10. 0.6 0.5 0.4 0.3 0.2 0.1 0.0 1 512 1024 1536 2048 2560 3072 3584 4095 total power variation ?db digital input code n a figure 10. power variation for circuit in figure 9 applying the AD7837/ad7847 general ground management ac or transient voltages between the analog and digital grounds i.e., between agnda/agndb and dgnd can cause noise in- jection into the analog output. the best method of ensuring that both agnds and dgnd are equal is to connect them together at the AD7837/ad7847 on the circuit board. in more complex systems where the agnd and dgnd intertie is on the back- plane, it is recommended that two diodes be connected in in- verse parallel between the agnd and dgnd pins (1n914 or equivalent). power supply decoupling in order to minimize noise it is recommended that the v dd and the v ss lines on the AD7837/ad7847 be decoupled to dgnd using a 10 m f in parallel with a 0.1 m f ceramic capacitor. operation with reduced power supply voltages the AD7837/ad7847 is specified for operation with v dd /v ss = 15 v 5%. the part may be operated down to v dd /v ss = 10 v without significant linearity degradation. see typical per- formance graphs. the output amplifier however requires ap- proximately 3 v of headroom so the v ref input should not approach within 3 v of either power supply voltages in order to maintain accuracy. microprocessor interfacingCad7847 figures 11 to 13 show interfaces between the ad7847 and three popular 16-bit microprocessor systems, the 8086, mc68000 and the tms320c10. in all interfaces, the ad7847 is memory- mapped with a separate memory address for each dac latch. ad7847C8086 interface figure 11 shows an interface between the ad7847 and the 8086 microprocessor. a single mov instruction loads the 12-bit word into the selected dac latch and the output responds on the ris- ing edge of wr .
AD7837/ad7847 rev. 0 C11C address bus addr decode csa csb 16-bit latch wr db11 db0 address/data bus ad7847* *additional pins omitted for clarity ale wr ad15 ad0 8086 figure 11. ad7847 to 8086 interface ad7847Cmc68000 interface figure 12 shows an interface between the ad7847 and the mc68000. once again a single move instruction loads the 12-bit word into the selected dac latch. csa and csb are and- gated to pro vide a dtack signal when either dac latch is selected. address bus csa csb wr db11 db0 data bus ad7847* * additional pins omitted for clarity d15 d0 mc68000 addr decode en a23 a1 dtack lds r/w as figure 12. ad7847 to mc68000 interface ad7847Ctms320c10 interface figure 13 shows an interface between the ad7847 and the tms320c10 dsp processor. a single out instruction loads the 12-bit word into the selected dac latch. address bus csa csb wr db11 db0 data bus ad7847* * additional pins omitted for clarity d15 d0 tms320c10 addr decode en a11 a0 men we figure 13. ad7847 to tms320c10 interface microprocessor interfacingCAD7837 figures 14 to 16 show the AD7837 configured for interfacing to microprocessors with 8-bit data bus systems. in all cases, data is right-justified and the AD7837 is memory-mapped with the two lowest address lines of the microprocessor address bus driving the a0 and a1 inputs of the AD7837. five separate memory ad- dresses are required, one for the each ms latch and one for each ls latch and one for the common ldac input. data is written to the respective input latch in two write operations. either high byte or low byte data can be written first to the input latch. a write to the AD7837 ldac address transfers the data from the input latches to the respective dac latches and updates both analog outputs. alternatively, the ldac input can be asynchro- nous and can be common to a several AD7837s for simulta- neous updating of a number of voltage channels. AD7837C8051/8088 interface figure 14 shows the connection diagram for interfacing the AD7837 to both the 8051 and the 8088. on the 8051, the signal psen is used to enable the address decoder while den is used on the 8088. address bus addr decode octal latch wr db7 db0 address/data bus AD7837* * additional pins omitted for clarity ale wr ad7 ad0 8051/8088 a0 a1 en psen or den cs ldac a15 a8 figure 14. AD7837 to 8051/8088 interface AD7837C68008 interface an interface between the AD7837 and the mc68008 is shown in figure 15. in the diagram shown, the ldac signal is derived from an asynchronous timer but this can be derived from the address decoder as in the previous interface diagram. address bus wr db7 db0 data bus AD7837* * additional pins omitted for clarity d7 d0 mc68008 addr decode en a19 a0 dtack ds r/w as cs ldac timer a0 a1 figure 15. AD7837 to 68008 interface
AD7837/ad7847 rev. 0 C12C c1362C10C3/90 printed in u.s.a. AD7837C6502/6809 interface figure 16 shows an interface between the AD7837 and the 6502 or 6809 microprocessor. for the 6502 microprocessor, the f 2 clock is used to generate the wr , while for the 6809 the e sig- nal is used. address bus wr db7 db0 data bus AD7837* * additional pins omitted for clarity d7 d0 6502/6809 addr decode en a15 a0 cs ldac a0 a1 r/w f 2 or e figure 16. AD7837 to 6502/6809 interface 24-pin cerdip (q-24) 0.012 (0.305) 0.008 (0.203) typ 0.320 (8.13) 0.290 (7.37) 15 0 1.290 (32.77) max 0.225 (5.715) max 0.021 (0.533) 0.015 (0.381) typ 0.125 (3.175) min 0.065 (1.651) 0.055 (1.397) 0.110 (2.794) 0.090 (2.286) typ 0.180 (4.572) max seating plane 1 24 0.295 (7.493) max 12 13 0.070 (1.778) 0.020 (0.508) 1. lead no. 1 identified by dot or notch. 2. cerdip leads will be either tin plated or solder dipped in accordance with mil-m-38510 requirements. 24-pin plastic dip (n-24) 0.11 (2.79) 0.09 (2.28) 0.02 (0.5) 0.016 (0.41) 0.32 (8.128) 0.30 (7.62) 0.011 (0.28) 0.009 (0.23) 0.07 (1.78) 0.05 (1.27) seating plane 1.228 (31.19) 1.226 (31.14) 0.260 ?0.001 (6.61 ?0.03) 24 1 13 12 notes 1. lead no. 1 identified by dot or notch. 2. plastic leads will be either solder dipped or tin lead plated in accordance with mil-m-38510 requirements. 0.130 (3.30) 0.128 (3.25) 15 0 outline dimensions dimensions shown in inches and (mm). 24-lead soic (r-24) 0.299 (7.6) 0.291 (7.39) 0.414 (10.52) 0.398 (10.10) 13 12 1 24 0.019 (0.49) 0.014 (0.35) 0.05 (1.27) 0.096 (2.44) 0.089 (2.26) 0.608 (15.45) 0.596 (15.13) 0.01 (0.254) 0.006 (0.15) 0.013 (0.32) 0.009 (0.23) 0.042 (1.067) 0.018 (0.457) 6 0 0.03 (0.76) 0.02 (0.51) 1. lead no. 1 identified by a dot. 2. soic leads will be either tin plated or solder dipped in accordance with mil-m-38510 requirements.

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