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? 1997 microchip technology inc. preliminary ds40150b-page 1 m SCS152 features iso 7816-3:1989 ?nswer to reset compatible for synchronous cards industry standard 4406 command set compatible extended commands: - combined write and erase-with-carry function - cryptographic signature of the eeprom contents and challenge 40-bit user programmable area with lock bit 64-bit cryptographic key 64-bit transport code 33352 token units (78888 8 ) internal protection against token counter value corruption (anti-tearing) description the SCS152 is a third generation token card integrated circuit intended for prepaid applications. typical appli- cations of the SCS152 include disposable telephone cards, vending machine cards, low value debit cards, access control, and authentication. the SCS152 incorporates several security features, including an internal signature function and a long transport code. the SCS152 has two modes ?issuer mode and user mode. during wafer testing, it is placed in issuer mode for card manufacturing and transporta- tion to the issuer. in issuer mode, the transport code is needed to program the device and, thus, is protected from unauthorized use before personalization by the issuer. during personalization, a cryptographic key, unique to the card, is programmed into eeprom. this key can not be read. the system using the card must be able to determine what key was programmed from examining the memory map (i.e., not the token counter) containing the issuer and serial number information. the signature function computes an 8-bit value based on a system supplied value (challenge) and the visible memory map. because of the nature of the signature function and the fact that the key is not known outside the system, it is practically impossible to predict the value which the signature will compute. die layout block diagram a correct signature indicates that the memory contents have not been altered. it can therefore be used to check the serial number, or that changes to the token counter have actually occurred. programming the token counter uses a special circuit to ensure that the programming will either be complete or will not happen at all, if the external supply is suddenly removed.* this is called fail safe programming , and, when used in conjunction with the extended write and erase command, removes the need for special ?ear-out protection to be performed by the reader. note: the fail safe feature only works in the token counter area. gnd sdio v dd sci sck i/o sci sck sdio v dd gnd address generation eeprom signature calculator controller token card chip k ee l oq is a registered trademark of microchip technology inc. *patents applied for.
SCS152 ds40150b -page 2 preliminary ? 1997 microchip technology inc. 1.0 pin definitions 2.0 device opera tion dur ing the lif e of the SCS152 , it goes through the f ol- lo wing stages: man uf acture and w af er probing w af e pac k and tr anspor tation p ersonalization and nal application . v ar ious elds in the memor y map m ust be initializ ed. these include the rst 24 bits in the memor y map , the tr anspor t code , and the mode bits . the rst 24 bits in the memor y map typically identi es the de vice in its nal application. the de vice has tw o pr inciple modes: issuer mode and user mode . in issuer mode , all access to the de vice (e xcept one eld) is b loc k ed bef ore a cor- rect tr anspor t code has been presented to the de vice . thus , the tr anspor t code protects the de vice against theft, bef ore it is personaliz ed. dur ing personalization, all elds , e xcept (chip identi cation data ( cid ), are initializ ed f or the intended application: the de vice ser ial n umber is prog r ammed, the tok en counter is set to its proper v alue , the user data eld is initializ ed, and the tr anspor t code is er ased and replaced with a cr yptog r aphic k e y . after po w er has been applied to the de vice , the i/o pin is dr iv en lo w . once the reset per iod ( t por ) has e xpired, the SCS152 is ready to accept commands . these com- mands typically read the memor y content ser ially . the rst bit at address 0 is initially dr iv en on the i/o line . each read cloc k pulse increments the inter nal address counter and reads the resulting bit from eepr om. this ser ial data stream is composed of v ar ious elds pre- sented in t ab le 2- 1 . 2.1 c id field the de vice cid eld contains a de vice identi cation code , which is prog r ammed dur ing w af er probe and cannot be changed later . these bits typically identify the type of the de vice to the system in the application. 2.2 ser field the ser eld contains the de vice ser ial n umber which identi es the individual de vice . it is prog r ammed while the de vice is in issuer mode dur ing the personalization stage . 2.3 iss field the iss eld indicates whether the de vice is in issuer mode as deter mined b y the cfg eld. this is purely an e xter nal vie w of the cfg eld and e xists as such f or compatibility reasons . iso pin name i/o t ype description c1 v dd p o w er p o w er connection c2 sci input command input to the de vice controller c3 sck input command e x ecution cloc k input c5 gnd p o w er p o w er connection c7 sdio bidir (o .d .) open dr ain ser ial data i/o line t able 2- 1: external representation of the internal memor y map field name ad dress siz e description cid 0?3 24 chip identi cation data ser 24?3 40 ser ial n umber iss 64 1 issuer mode status d4 65?1 7 digit 4 d3 72?9 8 digit 3 d2 80?7 8 digit 2 d1 88?5 8 digit 1 d0 96?03 8 digit 0 cfg 104?07 4 con gur ation data user0 108?47 40 user area ukey0 148?11 64 k e y area 0 which also acts as the tr anspor t code in issuer mode 212?75 64 unde ned
SCS152 ? 1997 microchip technology inc. preliminary ds40150b -page 3 2.4 digit fields 2.4.1 digit field v alue each digit eld, d4 to d0, represents a n umber equal to the n umber of ? bits in the eld. t ab le 2- 2 sho ws the v alue of the digit eld f or each legal digit v alue . t able 2- 2: digit field v alues 2.4.2 t ok en counter v alu e t he f ollo wing f or m ula sho ws ho w the digit elds combine to f or m the tok en counter v alue: t his is , in f act , an octal representation of a v alue and can be wr itten as: suppose the 5-digit eld contain the v alues: (d4=3), (d3=0), (d2=7), (d1=1), (d0=3). the tok en counter v alue is then 30713 8 in octal or in decimal : a digit needs to be set to eight to handle the borro w from the ne xt higher stage . this also implies that each counter v alue does not ha v e a unique representation. f or e xample , 00500 8 = 5 x 64 = 320 10 or 00480 8 or 00478 8 . digit v alue field v alue 0 0000 0000 1 10 00 000 0 2 110 0 0 000 3 1110 0000 4 1111 0000 5 1111 1000 6 111 1 11 00 7 11 11 111 0 8 1111 1111 note: the bits are sho wn, r ight to left, in the order in which the y are read out. note: the v alue digit d4 is sho wn in the f or m ulas as |d4| indicating the n umber of 1 bits in the digit d4 eld. similar ly |d3| indicates the n umber of 1 bits in the digit d3 eld, and so on. t o k e n s d 4 4096 d 3 512 d 2 64 d 1 8 d 0 + + + + = t o k e n s d 4 8 4 d 3 8 3 d 2 8 2 d 1 8 1 d 0 8 0 + + + + = t o k e n s 3 4096 0 512 7 64 1 8 3 + + + + 12747 10 = =
SCS152 ds40150b -page 4 preliminary ? 1997 microchip technology inc. 2.5 cfg field the cfg eld is fur ther divided into f our sub elds: with pc0 = 0 and pc1 = 1 ? the de vice is in issuer mode ; with pc0 = 1 and pc1 = 0 ? the de vice is in user mode . some commands can only be used in issuer mode . 2.6 user0 field the user area can be reprog r ammed to an y state b y the user in user mode . it also can be loc k ed using the lock0 bit. in issuer mode , this eld typically contains the pac kaging status of the de vice . in user mode , this eld can be used f or application dependent data. 2.7 ukey0 field in issuer mode , this eld contains the tr anspor t code ; in user mode , the ukey0 eld contains the k e y used in the signature function. the tr anspor t code is prog r ammed dur ing w af er probe and is completely reprog r ammed dur ing personalization to the v alue of the k e y . 3.0 command interface the SCS152 accepts the f ollo wing basic commands: reset , rdbit/putbit , bitpr og and erase. the e xtended commands are decr-erase and initiate signature function. the de vice inter prets v e diff erent sci/sck sequences f or all its commands: a) an o v er lap of sci and sck f or reset b) a single pulse on sck f or rdbit or putbit c) a single pulse on sci f ollo w ed b y a pulse on sck f or bitpr og d) a repeat of c) f or erase e) a doub le pulse on sci f ollo w ed b y a pulse on sck f or e xtended commands nor mally , an y one of these sequences can be f ollo w ed b y another ; ho w e v er , once the signature function has been star ted, a x ed sequence of commands m ust f ol- lo w . the e xtended functions are accessed b y doub le pulse on sci in the correct address r ange . depending on the current address , the same sequence of e v ents on sci and sck will perf or m diff erent functions . name ad dress description pc0 104 first bit of the issuer mode/user mode indicator pc1 105 second bit of the issuer mode/ user mode indicator n.u . 106 un used lock0 107 unloc k ed status of user0 area in user mode: ? means loc k ed t able 3- 1: extended functions field extended function accessed b y doub le sci pulse cid t est modes ser bitpr og d4?0 decr-erase cfg t est modes user0 bitpr og ukey0 address 163: test mode address 259: initiate signature oper ation other addresses perf or m bitpr og
SCS152 ? 1997 microchip technology inc. preliminary ds40150b -page 5 3.1 access condition s the condition codes are: note 1: if the access condition does not allo w a command that modi es the eepr om (i.e ., bitpr og, erase or decr-erase), it will be con v er ted into a rdbit command. 2: the commands that can potentially change the eepr om (e v en if it is con v er ted into a rdbit command) do not increment the i/o address counter . 3: an y command that modi es the eepr om chec ks the inter nal high v oltage sensor dur ing the prog r amming and goes into the standb y state if the sensor indicates the inter nal high v oltage w as not high enough. p o w er m ust be remo v ed to clear this condition. 4: if the de vice is not in issuer mode and not in user mode , only bitpr og access is allo w ed to the cfg eld. t able 3- 2: access conditions in issuer mode field rdbit bitpr og erase extended commands cid y f and tc n test modes ser y tc n bitpr og o4?1 y tc and z tc and b decr-erase: tc and z o0 y tc and z n n cfg y tc n test modes user0 y y y bitpr og ukey0 ? tc tc bitpr og test modes sign: y t able 3- 3: access conditions in user mode field rdbit bitpr og erase extended commands cid y n n test modes ser y n n bitpr og o4?1 y z b decr-erase: z o0 y z n n cfg y y n test modes user0 y l l bitpr og ukey0 ? n n bitpr og test modes sign: y y command alw a ys allo w ed n no access allo w ed and it is con v er ted into a rdbit command tc t r anspor t code m ust be submitted bef ore the oper ation is allo w ed ? output alw a ys logic high in this eld f command allo w ed if the fuse is not b lo wn z the digit code is nonz ero b command allo w ed if pre vious oper ation w as bitpr og and w as successfully l command allo w ed if lock0 bit in the cfg eld is ? bitpr og the bitpr og condition is chec k ed and e x ecuted
SCS152 ds40150b -page 6 preliminary ? 1997 microchip technology inc. 3.2 reset the reset command sets the inter nal state of the de vice as f ollo ws: 1. the inter nal address counter is set to ? . 2. the inter nal test modes are cleared . 3. the result of the last compared tr anspor t code is cleared. figure 3- 1 sho ws the reset command f ollo wing the application of po w er . figure 3- 1: p o wer on and reset v dd sci sck sdio iomap(0) t por t r t ox t ox t d 1
SCS152 ? 1997 microchip technology inc. preliminary ds40150b -page 7 3.3 rdbit/putbit th e rdbit command increments the inter nal address counter on the leading edge of the sck pulse and reads the resulting bit in eepr om. this sdio line is updated on the f alling edge of the sck pulse . if the ne w address is in the ukey0 area, the sdio line will be tr i- stated immediately in prepar ation of tr anspor t code entr y , e v en if the de vice is in user mode . figure 3- 2 sho ws tw o consecutiv e rdbit commands . the putbit command mirrors a rdbit command, b ut data is tr ansmitted to the chip instead of tr ansmitting data from the chip . it also increments the inter nal address counter . putbit is used to enter the tr anspor t code in issuer mode and the challenge bits , dur ing signature computation. figure 3- 3 sho ws data entr y , typically dur ing tr anspor t code entr y . figure 3- 2: rdbit figure 3- 3: data entr y (t ranspor t code detail) sci sck sdio t h t l iomap(n) iomap(n-1) t d 2 t h sci sck sdio t h tl iomap(147) t d 3 t c tc(0) tc(1) t h
SCS152 ds40150b -page 8 preliminary ? 1997 microchip technology inc. 3.4 bitpr og the bitpr og command modi es one bit in the eepr om. in the digit area , this command decrements the current digit or i n the cfg eld it prog r ams the bits to ad (0) xor fuse-blo wn state: pc0 is er ased to a ?? pc1 is wr itten to a ?? lock0 is wr itten to a ?? when the fuse is in b lo wn state . ev er ywhere else in the memor y map , the current bit is wr itten to a ?? figure 3- 4 diag r ams the bitpr og command. this command is signaled b y pulsing sci high. if the oper ation is allo w ed, the sdio line goes high. the actual eepr om modi cation is initiated b y pulsing sck high. when the prog r amming oper ation has been completed, and sck is lo w , the output goes lo w , indi- cating that the command has completed. 3.5 erase the w a v ef or ms f or erase are the same as bitpr og; the command is implicitly coded b y the repetition of the sequence of e v ents . the erase command e x ecutes diff erent functions , depending on the current address as sho wn in t ab le 3- 5 : figure 3- 4: bitpr og t able 3- 4: bitpr og functions field description cid wr ites current bit to ? ser wr ites current bit to ? d4?0 decrements the current digit cfg prog r am the current bit to the v alue of ( ad (0) xor fuse-blo wn ) user0 wr ites current bit to ? ukey0 wr ites current bit to ? t able 3- 5: erase functions field description cid ser o4?1 sets the ne xt digit to the maxim um digit v alue cfg user0 0x6c?x73: er ases current nib b le to all ? state 0x74?x93: er ases the current b yte to all ? state ukey0 er ases the current b yte to all ? state sci sck sdio t h t s t c t c t prog
SCS152 ? 1997 microchip technology inc. preliminary ds40150b -page 9 3.6 decr-erase the decr-erase command combines bitpr og and erase in the digit area into one oper ation. it is only allo w ed if both of these oper ations are allo w ed at the current address . figure 3- 5 sho ws the typical w a v ef or ms f or the decr-erase command. figure 3- 5: extended functions modifying eepr om sci sck sdio t h t s t c t c t s t c t prog
SCS152 ds40150b -page 10 preliminary ? 1997 microchip technology inc. 4.0 signature function the signature function combines a system - supplied v alue with the contents of the memor y map to f or m an 8-bit v alue . because ukey0 is not kno wn and the w a y in which these v alues are combined , it is v er y dif cult to duplicate . the signature function can , theref ore , be used f or a v ar iety of secur ity related functions , including user/card authentication and protecting against comm unication tamper ing. 4.1 signature pr ocedure the f ollo wing procedure controls the de vice to compute a signature of the eepr om contents: 1. issue a reset command. 2. issue 259 rdbit commands . 3. pulse sci high twice . 4. issue 16 putbit commands to enter the rst 16 bits of the challenge . 5. issue 128 rdbit commands . note: the bits read are the rst 128 bits in the eepr om without an y output mapping ; these bits m ust be used in chec king the result of the signature function. 6. issue 16 putbit commands to enter the sec- ond 16 bits of the challenge . 7. w ait f or the signature computation to complete . 8. issue 8 rdbit command to read the result of the signature computation. 9. updating the tok en counter . 4.2 subtraction pr ocedure the f ollo wing procedure can be used to subtr act a n umber of tok ens: 1. read the tok en counter v alue . 2. con v er t the tok en counter v alue into an octal f or- mat. 3. con v er t the n umber of tok ens to subtr act into an octal f or mat. 4. do the subtr action using ?ong subtr action mak- ing note of the borro ws . note: if the subtr action gener ated a borro w from digit 4, the tok en counter is smaller than the n umber subtr acted. 5. t o update each digit in the order the y are read out (i.e . , d4, then d3, then d2, etc.) : a) calculate b y ho w m uch this digit m ust be decremented. if , dur ing subtr action, a borro w w as gener ated from this digit to the ne xt higher digit, the decrement amount is eight min us this digit s nal v alue , else it is its initial v alue min us its nal v alue . b) read to the rst ? bit in the eld. c) if the f ollo wing digit gener ated a borro w from this digit, issue a bitpr og command, f ol- lo w ed b y an erase command. (see section 5.1 on f ail saf e counter updating.) d) decrement this digit as man y times as cal- culated in step 5 a , taking into account that step 5 c ma y already ha v e decremented this digit. each decrement is done b y reading the ne xt bit in the eld and issuing a bitpr og command. example 4-1: subtract example suppose the tok en counter contains 30713 8 , and 20 10 (24 8 ) tok ens m ust be deducted from the counter . using ?ong subtr action to do the calculation the result is 30677 8 . note the borro ws from digits d2 and d1. digits 4 and 3 do not change . the sequence of com- mands to update digit 2 is: read the second bit in the eld to eld d2, bitpr og, and erase. the erase command is required because of the borro w . updating digit 1 requires the f ollo wing sequence of commands: read the rst bit to eld d1, bitpr og, erase, rdbit , and bitpr og. once again , the erase command is required because of the borro w . updating digit 0 requires the sequence of commands: read the rst bit to eld d0 and bitpr og. example 4-2: decrementing 320: updating this tok en counter goes through the f ollo wing v alues: 00 4 0 0 8 , after the rst bitpr og; 00480 8 , after the erase; 00470 8 ,after bitpr og; 0047 8 8 ,after the erase; 00477 8 , after the nal bitpr og. note: the nal bitpr og actually decrements the v alue . 30713 8 00024 8 30667 8 - - - - - - - - - - - - - - - - - 00500 8 00001 8 00477 8 - - - - - - - - - - - - - - - - -
SCS152 ? 1997 microchip technology inc. preliminary ds40150b -page 11 5.0 c ompatibility with industr y standar d de vices the reset and rdbit commands meets the require- ments of iso 7816-3 f or the ?ns w er-to-reset sequence f or sync hr onous chip cards . the basic counter modi cation commands bitpr og and erase correspond with the write and erase- with- carr y commands of industr y standard de vices . ho w e v er , industr y standard de vices use eight bits to represent each digit, and a write command will prog r am the current bit to ?? the application can, theref ore , decrement a digit b y prog r amming an y of the eight bits to ?? whereas with the SCS152 , an y bitpr og command will alw a ys decrement the current digit v alue . if the application decrements each digit as descr ibed abo v e , the write command will appear to prog r am the current bit to ?? thus , while the SCS152 will accept and inter pret the commands correctly , the changes to the memor y map will only correspond to that of the other cards , if the rst ? in a digit eld is alw a ys prog r ammed ? with a write command. f or e xample , if digit eld d3 contains the v alue ?? it will be read out as 00111111. if a bitpr og command is issued an ywhere in d3, its v alue will be decremented to ?? and it will alw a ys read out as 00011111 , regardless of which address in the digit the bitpr og command w as issued. the iss is only an e xter nal vie w of the cfg eld and cannot be changed. a bitpr og command at this address will actually decrement digit d4. it should also be noted that the address counter appears to wr ap from 275 bac k to 0 , which diff ers from other similar de vices . 5.1 f ail saf e counter update the carr y is perf or med b y a bitpr og, f ollo w ed b y an erase. this process rst deducts a n umber of tok ens (the bitpr og command) and then adds some again (with the erase command), b ut ne v er more than pre- viously deducted with the bitpr og command. if the de vice is pulled from the reader betw een the bitpr og and erase commands , the user ma y lose man y tok ens . this situation can be a v oided b y substituting the decr- erase command whene v er a sequence of bitpr og and erase commands are needed to update the tok en counter (step 5 c in section 4.2 ). this will modify the contents of the eepr om in one indivis- ib le oper ation that will either complete or not modify the eepr om in an y w a y , if e xter nal po w er is remo v ed ear ly on dur ing the eepr om prog r amming.
SCS152 ds40150b -page 12 preliminary ? 1997 microchip technology inc. 6.0 p er sonalization dur ing the typical lif e of the de vice , it m ust be person- aliz ed. the f ollo wing procedure personaliz es the de vice: 1. issue a reset command. 2. issue 147 rdbit commands . 3. issue 64 putbit commands to present the tr anspor t code . 4. issue 88 rdbit commands . 5. prog r am the ser eld b y issuing bitpr og commands at the appropr iate addresses . 6. decrement each digit in the tok en counter to the proper v alue b y issuing bitpr og and rdbit commands as needed. 7. prog r am the user area. 8. prog r am the ukey0 area b y cloc king to the rst bit of each b yte (i.e ., addresses 148, 156, 164, ? issuing bitpr og and erase com- mands , and then prog r amming the b yte with bitpr og commands . 9. chec k the contents via the signature function. 10. set the de vice to user mode b y issuing a bitpr og commands at addresses 104 and 105. 7.0 memor y contents 7.1 shipped de vices 7.2 after p er sonalization note: the inter nal tr anspor t code ok status bit is reset b y the reset command or when the de vice is no longer in issuer mode (which happens when pc0 and pc1 are pro- g r ammed). field name contents cid chip identi cation data ser all 1 iss 1 d4 all 1 d3 all 1 d2 all 1 d1 all 1 d0 all 1 cfg pc0 = 0, pc1 = 1, lock0 = 1 user0 all 1 ukey0 t r anspor t code field name contents cid chip identi cation data ser de vice ser ial n umber iss 0 d4 digit 4 of counter d3 digit 3 of counter d2 digit 2 of counter d1 digit 1 of counter d0 digit 0 of counter cfg pc0 = 1, pc1 = 0, lock0 = 1/0 depending on application user0 all 1 ukey0 t r anspor t code
SCS152 ? 1997 microchip technology inc. preliminary ds40150b -page 13 8.0 device chara cteristics t able 8- 1: absolute maxim um ratings description symbol min. max. units supply v oltage , with respect to gnd v dd -0.3 6.0 v input v oltage , with respect to gnd v i -0.3 6.0 v stor age temper ature t s -55 +85 c esd protection on all pins (hbm) v esd 4000 v t able 8- 2: dc characteristics v dd : 5.0 v 10% t a : -40 c to + 85 c description symbol min. t yp. max. units condition current when reading i ddr 300 600 m a sdio = v dd current when prog r amming i ddp 1.2 1.6 ma sdio = v dd input lo w v oltage v il 0.8 v input high v oltage v ih 3.0 v output lo w v oltage v ol 0.4 v sinking current, io = 1 ma t able 8- 3: a c c haracteristics v dd : 5 v 10% t a : -40 c to + 85 c r pu = 10k description symbol min. t yp. max. units time from v dd high until de vice accepts com- mands t por 3.5 ms ov er lap of sci with sck dur ing reset t ox 2.0 m s ov er lap per iod of sci and sck dur ing reset t r 35.0 m s sck high t h 10.0 m s sck lo w t l 10.0 m s sck/sci f alling to sci changing f or bitpr og, erase, etc. t c 5.0 m s sci high pulse dur ing bitpr o t , erase, etc. t s 2.0 m s sdio changing from f alling edge of sci/sck dur ing reset t d 1 1.8 m s sdio changing from f alling edge of sck dur ing rdbit t d 2 1.8 4.7 m s sdio tr i-state after r ising edge of sck t d 3 4.5 m s time to prog r am eepr om dur ing bitpr og, erase, decr-erase, etc. t prog 1.4 3.4 ms time to compute signature from f alling edge of sck where last challenge bit is entered t sign 2.5 ms
SCS152 ds40150b -page 14 preliminary ? 1997 microchip technology inc. notes:
SCS152 ? 1997 microchip technology inc. preliminary ds40150b -page 15 SCS152 pr oduct identification system t o order or obtain inf or mation, e .g., on pr icing or deliv er y , ref er to the f actor y or the listed sales of ce . sales and suppor t p ac ka g e: s = die in w af e f or m w = die in w af er f or m wf = die in w af er or f r ame f or m t emperature rang e: i = ?0 ? c to +85 ? c de vice: SCS152 t ok en card chip SCS152 / s data sheets products suppor ted b y a preliminar y data sheet ma y ha v e an err ata sheet descr ibing minor oper ational diff erences and recom- mended w or karounds . t o deter mine if an err ata sheet e xists f or a par ticular de vice , please contact one of the f ollo wing: 1. y our local microchip sales of ce . 2. the microchip cor por ate liter ature center u .s . f ax: (602) 786-7277. 3. the microchip s bulletin board, via y our local compuser v e n umber (compuser v e membership no t required) .
information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchips products as critical components in life sup port systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the m icrochip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. ds40150b-page 16 preliminary ? 1997 microchip technology inc. americas corporate of?e microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 602-786-7200 fax: 602-786-7277 technical support: 602 786-7627 web: www.microchip.com atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508-480-9990 fax: 508-480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas microchip technology inc. 14651 dallas parkway, suite 816 dallas, tx 75240-8809 tel: 972-991-7177 fax: 972-991-8588 dayton microchip technology inc. two prestige place, suite 150 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 los angeles microchip technology inc. 18201 von karman, suite 1090 irvine, ca 92612 tel: 714-263-1888 fax: 714-263-1338 new york microchip technology inc. 150 motor parkway, suite 416 hauppauge, ny 11788 tel: 516-273-5305 fax: 516-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto microchip technology inc. 5925 airport road, suite 200 mississauga, ontario l4v 1w1, canada tel: 905-405-6279 fax: 905-405-6253 asia/pacific hong kong microchip asia paci? rm 3801b, tower two metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2-401-1200 fax: 852-2-401-3431 india microchip technology india no. 6, legacy, convent road bangalore 560 025, india tel: 91-80-229-0061 fax: 91-80-229-0062 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 shanghai microchip technology rm 406 shanghai golden bridge bldg. 2077 yan?n road west, hongiao district shanghai, prc 200335 tel: 86-21-6275-5700 fax: 86 21-6275-5060 singapore microchip technology taiwan singapore branch 200 middle road #10-03 prime centre singapore 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan, r.o.c microchip technology taiwan 10f-1c 207 tung hua north road taipei, taiwan, roc tel: 886 2-717-7175 fax: 886-2-545-0139 europe united kingdom arizona microchip technology ltd. unit 6, the courtyard meadow bank, furlong road bourne end, buckinghamshire sl8 5aj tel: 44-1628-851077 fax: 44-1628-850259 france arizona microchip technology sarl zone industrielle de la bonde 2 rue du buisson aux fraises 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 m?chen, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy arizona microchip technology srl centro direzionale colleone palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-39-6899939 fax: 39-39-6899883 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shin yokohama kohoku-ku, yokohama kanagawa 222 japan tel: 81-4-5471- 6166 fax: 81-4-5471-6122 06/16/97 printed on recycled paper. all rights reserved. ?997, microchip technology incorporated, usa. 6/97 m w orldwide s ales & s ervice

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