View 7025E_1073326.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 memory all data sheets are subject to change without notice (619) 503-3300- fax: (619) 503-3301- www.maxwell.com (8k x 16-bit) dual port ram 7025E ?2002 maxwell technologies all rights reserved. high-speed cmos 08.15.02 rev 2 f eatures : ? 8k x 16-bit dual port ram - stand alone - master slave ?r ad -p ak ? radiation-hardened agai nst natural space radiation ? total dose hardness: - > 100 krad (si), depending upon space mission ? excellent single event effects: -sel th let = >100 mev/mg/cm 2 -seu th let = 7 mev/mg/cm 2 ? package: -84 pin r ad -p ak ? quad flat pack ? separate upper byte and lower byte control for multiplexed bus compatibility ? high speed access time: 35/45 ns ? expandable to 32 bits or more using master/slave select when cascading ? high speed cmos technology -ttl compatible, single 5v power supply -interrupt flag for port-to-port communication -on chip port arbitration logic -asynchronous operation from either port d escription : maxwell technologies? 7025E dual port ram high speed cmos? microcircuit features a greater than 100 krad (si) total dose tolerance, depending upon space mission. the 7025E is designed to be used as a stand-alone 128k-bit dual port ram or as a combination master/slave dual-port ram for 32- bit or more word systems. this design results in full-speed, error-free operation without t he need for additional discrete logic. the 7025E provides two independent ports with sepa- rate control, address, and i/o pins that permit independent, asynchronous access for reads or writes to any location in memory. an automatic power down feature controlled by cs permits the on-chip circuitry of each port to enter a very low standby power mode. maxwell technologies' patented r ad -p ak ? packaging technol- ogy incorporates radiation shie lding in the microcircuit pack- age. it eliminates the need for box shielding while providing the required radiation shielding fo r a lifetime in orbit or space mission. in a geo orbit, r ad -p ak provides greater than 100 krad (si) radiation dose toleranc e. this product is available with screening up to class s. logic diagram
memory 2 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. (8k x 16-bit) dual port ram high-speed cmos 7025E 08.15.02 rev 2 t able 1. 7025E p inout d escription n ames l eft p ort r ight p ort chip select cs l cs r read/write select r/w l r/w r output select os l os r address ao l -a12 l ao r -a12 r data input/output i/oo l -i/o15 l i/oo r -i/o15 r semaphore select sem l sem r upper byte select ub l ub r lower byte select lb l lb r interrupt flag int l int r busy flag busy l busy r m/s master or slave select v cc power gnd ground t able 2. 7025E a bsolute m aximum r atings p arameter s ymbol m in m ax u nits supply voltage (relative to v ss )v cc -0.3 7.0 v operating temperature range t a -55 125 c input or output voltage applied -- gnd -0.3v v cc + 0.3 v storage temperature range t stg -65 150 c t able 3. d elta l imits p arameter v ariation i ccop 10% a s s tated i t able 6 i ccop1 10% a s s tated i t able 6 i ccsb 10% a s s tated i t able 6 i ccsb1 10% a s s tated i t able 6 t able 4. 7025E r ecommended o perating c onditions p arameter s ymbol m in m ax u nits supply voltage positive v cc 4.5 5.5 v input voltage v il v ih -0.5 2.2 0.8 6.0 v
memory 3 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. (8k x 16-bit) dual port ram high-speed cmos 7025E 08.15.02 rev 2 thermal impedance jc -- 1.02 c/w operating temperature range t a -55 125 c t able 5. 7025E c apacitance p arameter s ymbol m in m ax u nits input capacitance: v in = 0v 1 1. guaranteed by design. c in -- 5 pf output capacitance: v out = 0v 1 c out -- 7 pf t able 6. 7025E dc e lectrical c haracteristics (v cc = 5v 10%, t a = -55 to 125 c unless otherwise ) p arameter s ymbol s ubgroups m in m ax u nits input leakage current 1 1. vcc = 5.5v, vin = gnd to vcc, cs = vih, vout = 0 to vcc. i li 1, 2, 3 -- 10 a output leakage current 2 2. vcc=5.5v; vout = gnd to vcc i lo 1, 2, 3 -- 10 a standby supply current, both ports ttl level inputs -35 -45 i ccsb 1, 2, 3 -- -- 50 50 ma standby supply current, both ports cmos level inputs -35 -45 i ccsb1 1, 2, 3 -- -- 5 5 ma operating supply current, both ports active -35 -45 i ccop 1, 2, 3 -- -- 320 280 ma operating supply current, one port active, one port standby -35 -45 i ccop1 1, 2, 3 -- -- 190 180 ma input low voltage 3 input high voltage 3. vih max = vcc + 0.3v, vil min = -0.3v or -1v pulse width 50 ns v il v ih 1, 2, 3 -- 2.2 0.8 -- v output low voltage 4 output high voltage 4. v cc min, i ol = 4 ma, i oh = -4 ma. v ol v oh 1, 2, 3 -- 2.4 0.4 -- v t able 4. 7025E r ecommended o perating c onditions p arameter s ymbol m in m ax u nits
memory 4 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. (8k x 16-bit) dual port ram high-speed cmos 7025E 08.15.02 rev 2 t able 7. 7025E ac e lectrical c haracteristics for r ead c ycle (v cc = 5v 10%, v ss = 0v, t a = -55 to 125 c) p arameter s ymbol s ubgroups m in m ax u nit read cycle time -35 -45 t rc 9, 10, 11 35 45 -- -- ns address access time -35 -45 t aa 9, 10, 11 -- -- 35 45 ns chip select access time 1 -35 -45 1. to access ram, cs = v il , ub or lb = v il , sem = v ih . to access semaphore, cs = v in and sem = v il . either condition must be valid for the entire t ew time. t acs 9, 10, 11 -- -- 35 45 ns byte select access time 1 -35 -45 t abe 9, 10, 11 -- -- 35 45 ns output select to output valid -35 -45 t aoe 9, 10, 11 -- -- 20 25 ns output low z time 2,3 -35 -45 2. guaranteed by design. 3. transition is measured 500 mv from low or high impedance voltage with load. t lz 9, 10, 11 3 3 -- -- ns output high z time 2,3 -35 -45 t hz 9, 10, 11 -- -- 20 20 ns chip enable to power up time 2 t pu 9, 10, 11 0 -- ns chip disable to power up time 2 t pd 9, 10, 11 -- 50 ns semaphore flag update pulse (oe or sem )t sop 9, 10, 11 15 -- ns t able 8. 7025E ac e lectrical c haracteristics for w rite c ycle (v cc = 5v 10%, v ss = 0v, t a = -55 to 125 c) p arameter s ymbol s ubgroups m in m ax u nit write cycle time -35 -45 t wc 9, 10, 11 35 45 -- -- ns address valid to end of write -35 -45 t aw 9, 10, 11 30 40 -- -- ns
memory 5 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. (8k x 16-bit) dual port ram high-speed cmos 7025E 08.15.02 rev 2 chip select to end of write 1 -35 -45 t sw 9, 10, 11 30 40 -- -- ns address setup time -35 -45 t as 9, 10, 11 0 0 -- -- ns write pulse width -35 -45 t wp 9, 10, 11 30 35 -- -- ns write recovery time -35 -45 t wr 9, 10, 11 0 0 -- -- ns data valid to end of write -35 -45 t dw 9, 10, 11 25 25 -- -- ns output high z time 2,3 -35 -45 t hz 9, 10, 11 -- -- 20 20 ns data hold time -35 -45 t dh 9, 10, 11 0 0 -- -- ns write select to output in high z 2,3 -35 -45 t wz 9, 10, 11 -- -- 20 20 ns output active from end of write 2,3,4 -35 -45 t ow 9, 10, 11 0 0 -- -- ns sem flag write to read time -35 -45 t swrd 10 10 -- -- ns sem flag contention window -35 -45 t sps 10 10 -- -- ns 1. to access ram, cs = v il , ub or lb = v il , sem = v ih . to access semaphore, cs = v in and sem = v il . either condition must be valid for the entire t ew time. 2. guaranteed by design. 3. transition is measured 500 mv from low or high impedance voltage with load. 4. the specification for t dh must be met by the device supplying write data to the ram under all operating conditions. although t dh and t dw . t able 8. 7025E ac e lectrical c haracteristics for w rite c ycle (v cc = 5v 10%, v ss = 0v, t a = -55 to 125 c) p arameter s ymbol s ubgroups m in m ax u nit
memory 6 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. (8k x 16-bit) dual port ram high-speed cmos 7025E 08.15.02 rev 2 t able 9. 7025E ac e lectrical c haracteristics for w rite m aster /s lave c onfiguration (v cc = 5v 10%, v ss = 0v, t a = -55 to 125 c) p arameter s ymbol m in m ax u nit for master only busy access time to address match -35 -45 t baa -- -- 35 35 ns busy disable time to address not matched -35 -45 t bda -- -- 30 30 ns busy access time to chip select low -35 -45 t bac -- -- 30 30 ns busy disable time to chip select high -35 -45 t bdc -- -- 25 25 ns write pulse to data delay 1 -35 -45 1. port to port timing delay through ram cells from writing port to reading port. t wdd -- -- 60 70 ns write data valid to read data delay 1 -35 -45 t ddd -- -- 45 55 ns arbitration priority setup time 2 -35 -45 2. to ensure that the earlier of the two ports wins. t aps 5 5 -- -- ns busy disable to valid data -35 -45 t bdd -- -- 3 3 3. t bdd is a calculated parameter and is the greater of 0, t wdd - t wp (actual) or t ddd - t wd (actual). ns for slave only write to busy input 4 4. to ensure that the write cycl e is inhibited during contention. t wb 0--ns write hold after busy 5 5. to ensure that a write cycle is completed after contention. t wh 25 -- ns write pulse to data delay 1 -35 -45 t wdd -- -- 60 70 ns write data valid to read data delay 1 -35 -45 t ddd -- -- 45 55 ns
memory 7 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. (8k x 16-bit) dual port ram high-speed cmos 7025E 08.15.02 rev 2 t able 10. 7025E ac p arameters for i nterrupt t iming (v cc = 5v 10%, t a = -55 to 125 c, f = 1 mh z ) p arameter s ymbol m in m ax u nits address setup time t as 0--ns write recovery time t wr 0--ns interrupt set time -35 -45 t ins -- -- 30 35 ns interrupt reset time -35 -45 t inr -- -- 30 35 ns t able 11. 7025E t ruth t able for i nterrupt f lag c ontrol 1 1. assumes busy l = busy r = h. f unction r/w cs os a 0 -a 12 int left port set right int l flag l l x 1fff x reset right int l flag xxxxx set left int l flag xxxxl 2 2. if busy r = l, then no change. reset left int l flag x l l 1ffe h 3 3. if busy l = l, then no change. right port set right int r flag xxxxl 3 reset right int r flag x l l 1fff h 2 set left int r flag l l x 1ffe x reset left int r flag xxxxx
memory 8 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. (8k x 16-bit) dual port ram high-speed cmos 7025E 08.15.02 rev 2 t able 12. 7025E t ruth t able for a rbitration o ptions o ptions i nputs o utputs cs ub lb m/s sem busy int busy logic master l l x l l x h h h h output signal -- busy logic slave l l x l l x l l h h input signal -- interrupt logic l l x l l x x x h h -- output signal semaphore logic h h x x x x h l l l h hi-z -- t able 13. 7025E n on -c ontention r ead /w rite c ontrol i nputs 1 1. ao l - a12 l = ao r -a12 r . o utputs m ode cs r/w oe ub lb sem i/o8-i/o15 i/o0-i/o7 hxxxxhhi-z hi-zdeselected power down x x x h h h hi-z hi-z both bytes deselected: power down l l x l h h datain hi-z write to upper byte only l l x h l h hi-z datain write to lower byte only l l x l l h datain datain write to both bytes l h l l h h dataout hi-z read upper byte only l h l h l h hi-z dataout read lower byte only l h l l l h dataout dataout read both bytes x x h x x x hi-z hi-z outputs disabled
memory 9 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. (8k x 16-bit) dual port ram high-speed cmos 7025E 08.15.02 rev 2 t able 14. 7025E s emaphore r ead /w rite c ontrol 1 1. ao l - a12 l = ao r -a12 r . i nputs o utputs m ode cs r/w oe ub lb sem i/o8-i/o15 i/o0-i/o7 h h l x x l dataout dataout read data in semaphore flag x h l h h l dataout dataout read data in semaphore flag h x x x l datain datain write dino into semaphore flagf x x h h l datain datain write dino into semaphore flag lxxlxl -- --not allowed l x x x l l -- -- not allowed
memory 10 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. (8k x 16-bit) dual port ram high-speed cmos 7025E 08.15.02 rev 2 f igure 1. t iming w aveform of r ead c ycle n o . 1, e ither s ide 1,2,3 f igure 2. t iming w aveform of r ead c ycle n o . 2, e ither s ide 1,4,5 1. f/w is high for read cycles. 2. device is continuously enabled, cs = v il , ub or lb = v l . this waveform cannot be used for semaphore reads. 3. ce = v il . 4. addresses valid prior to or coincident with cs transition. 5. to access ram, cs = v l , ub or lb = v il , sem = v ih . to access semaphore, cs = v ih , sem = v il .
memory 11 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. (8k x 16-bit) dual port ram high-speed cmos 7025E 08.15.02 rev 2 f igure 3. t iming w aveform of r ead c ycle n o . 3, e ither s ide 1,3,4,5 f igure 4. t iming w aveform of r ead with busy 2,3,4 ( for master ) 1. to ensure math, the earlier of the two ports wins. 2. write cycle parameters should be adhered to, to ensure proper writing. 3. device is continuously enable for both ports. 4. oe = l for the reading port.
memory 12 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. (8k x 16-bit) dual port ram high-speed cmos 7025E 08.15.02 rev 2 f igure 5. t iming w aveform of w rite with p ort - to -p ort 1,2,3 ( for slave only ) 1. assume busy input = h or the writing port, and oe = l for the reading port. 2. write cycle parameters should be adhered to, to ensure proper writing. 3. device is continuously enable for both ports. f igure 6. t iming w aveform of w rite c ycle n o . 1, r/w c ontrolled t iming 1,2,3,7
memory 13 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. (8k x 16-bit) dual port ram high-speed cmos 7025E 08.15.02 rev 2 f igure 7. t iming w aveform of w rite c ycle n o . 2, cs c ontrolled t iming 1,2,3,5 f igure 8. t iming w aveform of w rite with busy ( for slave ) 1. r/w must be high during all address transitions. 2. a write occurs during the overlap (t sw to t wf ) of a low cs or sem and a low r/w . 3. t. wf is measured from the earlier of cs or r/w (or sem or r/w ) going high to the end of write cycle. 4. during this period, the i/o pins are in the output state, and input signals must not be applied. 5. if the cs or sem low transition occurs simultaneously with or after the r/w low transition, the outputs remain in the high impedance state. 6. transitions measured = 500 mv from steady state with a 5 pf load (including scope and ji g). this parameter is sam- ple and not 100% tested. 7. if oe is low during a r/w controlled write cycle, the write pulse width must be the larger of two or (t wz +t dw ) to allow the i/o driver to turn off and data to be placed on the bus for the required t dw . if oe is high during an r/w controlled write cycle, this requirement does not apply and the wr ite pulse can be as short as the specified t wp . 8. to access ram, cs = v il , sem = v ih . 9. to access upper byte, cs = v il , ub = v il , sem = v ih . to access lower byte, cs = v il , lb = v il , sem = v ih .
memory 14 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. (8k x 16-bit) dual port ram high-speed cmos 7025E 08.15.02 rev 2 f igure 9. t iming w aveform of c ontention c ycle n o . 1, cs a rbitration ( for master ) f igure 10. t iming w aveform of c ontention c ycle n o . 2, a ddress v alid a rbitration ( for master only ) 1 l eft a ddress v alid f irst
memory 15 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. (8k x 16-bit) dual port ram high-speed cmos 7025E 08.15.02 rev 2 r ight a ddress v alid f irst 1. cs l = cs r = v il . f igure 11. w aveform of i nterrupt t iming 1 s et a ddress c lear a ddress 1. all timing is the same for left and right ports. port ?a? may be either the left or right port. port ?b? is the port opposite from ?a?. 2. see interrupt truth table. 3. timing depends on which enable signal is asserted last. 4. timing depends on which enable si gnal is de-asserted first.
memory 16 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. (8k x 16-bit) dual port ram high-speed cmos 7025E 08.15.02 rev 2 f igure 12. 32- bit m aster /s lave d ual -p ort m emory s ystems 1. no arbitration in master/slave. busy - in inhibits write in master/slave. f igure 13. t iming w aveform of s emaphore r ead after w rite t iming , e ither s ide 1 1. cs = v ih for the duration of the above timing (both write and read cycle).
memory 17 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. (8k x 16-bit) dual port ram high-speed cmos 7025E 08.15.02 rev 2 f igure 14. t iming w aveform of s emaphore c ontention 1,3,4 1. d or = d ol = v il , cs r = cs l = v ih , semaphore flag is released from both sides (reads as ones from both sides) at cycle start. 2. either side ?a? = left and side ?b? = right, or side ?a? = right and side ?b? = left. 3. this parameter is measured from the point where r/w a or sem a goes high until r/w b or sem b goes high. 4. if t sps is violated, the semaphore will fall positively to one si de or the other, but there is no guaranty which side will obtain the flag.
memory 18 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. (8k x 16-bit) dual port ram high-speed cmos 7025E 08.15.02 rev 2 84 p in r ad -p ak ? f lat p ackage s ymbol d imension m in n om m ax a 0.163 0.176 0.189 a1 0.113 0.123 0.133 b 0.006 0.010 0.014 c 0.004 0.006 0.010 d 0.635 0.650 0.665 d1 0.500 bsc e 0.025 bsc s1 0.013 0.070 -- f1 0.540 0.545 0.550 f2 0.415 0.420 0.425 f3 0.412 0.415 0.418 f4 0.560 0.565 0.570 l -- 1.620 1.635 l1 1.595 1.600 1.615 l2 0.940 0.950 0.960 n84
memory 19 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. (8k x 16-bit) dual port ram high-speed cmos 7025E 08.15.02 rev 2 q84-01 note: all dimensions in inches important notice: these data sheets are created using the chip manufacturer s published specifications. maxwell technologies verifies functionality by testing key parameters either by 100% testing, sample test ing or characterization. the specifications presented within these data sheets represent the latest and most accurate information available to date. however, these specifications are subject to change without notice and maxwell technologies assumes no responsibility for the us e of this information. maxwell technologies? products are not authorized for use as critical components in li fe support devices or systems without express written approval from maxwell technologies. any claim against maxwell technologies must be made within 90 days from the date of shipment from maxwell tech- nologies. maxwell technologies? liability shall be limited to replacement of defective parts.

▲Up To Search▲

Price & Availability of 7025E

	To Download 7025E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .