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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. 1998 bicmos integrated circuit m m m m pc1934 dc-dc converter control ic data sheet document no. g13567ej3v0ds00 (3rd edition) date published april 2000 ns cp (k) printed in japan the mark h shows major revised points. description the m pc1934 is an ic that controls a low-voltage input dc-dc converter. this ic is suitable for an operation with 3-v, 3.3-v input or a lithium ion secondary battery input, because the minimum operation supply voltage is 2.5 v. because of its wide operating voltage range, it can also be used to control dc-dc converters that use an ac adapter for input. features low supply voltage: 2.5 v (min.) operating voltage range: 2.5 to 20 v (breakdown voltage: 30 v) timer latch circuit for short-circuit protection. ceramic capacitor with low capacitance (0.1 m f) can be used for short-circuit protection. open drain outputs (each of the outputs can be used to control a step-down converter, a step-up converter and an inverted converter.) can control two output channels. ordering information part number package m pc1934gr-1jg 16-pin plastic ssop (5.72 mm (225)) m pc1934gr-pjg 16-pin plastic tssop (5.72 mm (225))
data sheet g13567ej3v0ds00 2 m m m m pc1934 block diagram dly i n2 v ref e/a 2 e/a 1 pwm 1 pwm 2 i i2 out 2 v cc dtc 2 fb 2 + C C timer latch for short-circuit protection section reference voltage section oscillation section gnd out 1 fb 1 r t c t i i1 i n1 dtc 1 C + C mos input mos output mos input mos output channel 1 channel 2 + C C + 12 34 56 78 16 15 14 13 12 11 10 9
data sheet g13567ej3v0ds00 3 m m m m pc1934 pin configuration (top view) 16-pin plastic ssop (5.72 mm (225)) m m m m pc1934gr-1jg 16-pin plastic tssop (5.72 mm (225)) m m m m pc1934gr-pjg pin functions pin no. symbol function pin no. symbol function 1c t frequency setting capacitor connection 9 v cc power supply 2r t frequency setting resistor connection 10 out 2 channel 2 open drain output 3i n1 channel 1 error amplifier non-inverted input 11 dtc 2 channel 2 dead time setting 4i i1 channel 1 error amplifier inverted input 12 fb 2 channel 2 error amplifier output 5fb 1 channel 1 error amplifier output 13 i i2 channel 2 error amplifier inverted input 6dtc 1 channel 1 dead time setting 14 i n2 channel 2 error amplifier non-inverted input 7out 1 channel 1 open drain output 15 dly delay capacitor connection of short- circuit protection 8 gnd ground 16 v ref reference voltage output 1 2 3 4 16 15 14 13 512 611 710 89 v ref dly i n2 i i2 out 2 v cc dtc 2 fb 2 c t r t i n1 i i1 fb 1 dtc 1 out 1 gnd
data sheet g13567ej3v0ds00 4 m m m m pc1934 contents 1. electrical specifications ................................................................................................... ............. 5 2. configuration and operation of each block.................................................................... 10 2.1 reference voltage generator ................................................................................................. ..........................10 2.2 oscillator .................................................................................................................. .........................................10 2.3 under voltage lock-out circuit .............................................................................................. ..........................11 2.4 error amplifiers............................................................................................................ .....................................11 2.5 pwm comparators............................................................................................................. ...............................11 2.6 timer latch-method short circuit protection circuit ......................................................................... ...........11 2.7 output circuit.............................................................................................................. ......................................11 3. notes on use............................................................................................................... ......................... 12 3.1 setting the output voltage .................................................................................................. .............................12 3.2 setting the oscillation frequency ........................................................................................... ........................13 3.3 preventing malfunction of the timer latch-method short circuit protection circuit..................................13 3.4 connecting unused error amplifiers .......................................................................................... ....................13 3.5 on/off control.............................................................................................................. ...................................14 3.6 notes on actual pattern wiring.............................................................................................. ..........................14 4. application example ......................................................................................................... ................ 15 4.1 application example......................................................................................................... ................................15 4.2 list of external parts ...................................................................................................... ..................................15 5. package drawings............................................................................................................ .................. 16 6. recommended soldering conditions ....................................................................................... 18
data sheet g13567ej3v0ds00 5 m m m m pc1934 1. electrical specifications absolute maximum ratings (unless otherwise specified, t a = = = = 25 c) parameter symbol m pc1934gr-1jg m pc1934gr-pjg unit supply voltage v cc 30 v output voltage v o 30 v output current (open drain output) i o 21 ma total power dissipation p t 417 400 mw operating ambient temperature t a C20 to + 85 c storage temperature t stg C55 to + 150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating conditions parameter symbol min. typ. max. unit supply voltage v cc 2.5 20 v output voltage v o 020v output current i o 20 ma operating temperature t a - 20 + 85 c oscillation frequency f osc 20 1000 khz caution the recommended operating range may be exceeded without causing any problems provided that the absolute maximum ratings are not exceeded. however, if the device is operated in a way that exceeds the recommended operating conditions, the margin between the actual conditions of use and the absolute maximum ratings is small, and therefore thorough evaluation is necessary. the recommended operating conditions do not imply that the device can be used with all values at their maximum values.
data sheet g13567ej3v0ds00 6 m m m m pc1934 electrical characteristics (unless otherwise specified, t a = 25 c, v cc = = = = 3 v, f osc = 100 khz) block parameter symbol conditions min. typ. max. unit start-up voltage v cc (l-h) i ref = 0.1 ma 1.57 v operation stop voltage v cc (h-l) i ref = 0.1 ma 1.5 v hysteresis voltage v h i ref = 0.1 ma 30 70 mv under voltage lock-out section reset voltage (timer latch) v ccr i ref = 0.1 ma 1.0 v reference voltage v ref i ref = 1 ma 2.0 2.1 2.2 v line regulation reg in 2.5 v v cc 20 v 2 12.5 mv load regulation reg l 0.1 ma i ref 1 ma 2 7.5 mv reference voltage section temperature coefficient d v ref / d t - 20 c t a + 85 c, i ref = 0 a 0.5 % f osc setting accuracy d f osc r t = 11 k w , c t = 330 pf - 15 + 15 % oscillation section f osc total stability d f osc - 20 c t a + 85 c, 2.5 v v cc 20 v - 30 + 30 % input bias current i bd 0.4 1.0 m a low-level threshold voltage v th (l) duty = 100 % 1.2 v dead time control section high-level threshold voltage v th (h) duty = 0 % 1.6 v input offset voltage v io - 10 + 10 mv input offset current i io - 100 + 100 na input bias current i b - 100 + 100 na common mode input voltage range v imc 00.4v open loop gain a v v o = 0.3 v 70 80 db unity gain f unity v o = 0.3 v 1.5 mhz maximum output voltage ( + ) v om + i o = - 45 m a1.62v maximum output voltage ( - ) v om - i o = 45 m a 0.02 0.5 v output sink current i osink v fb = 0.5 v 0.8 1.4 ma error amplifier section output source current i osource v fb = 1.6 v - 70 - 45 m a drain cutoff current i leak v o = 30 v 100 m a output on voltage v ol r l = 150 w 0.2 0.6 v rise time t r r l = 150 w 50 ns output section fall time t f r l = 150 w 60 ns input sense voltage v th 0.5 0.63 0.75 v uv sense voltage v uv 0.6 0.8 0.95 v source current on short-circuiting i ouv 1.0 1.6 2.5 m a short-circuit protection section delay time t dly c dly = 0.1 m f50ms overall circuit operation current i cc v cc = 3 v 1.4 2.2 3.7 ma caution connect a capacitor of 0.01 to 10 m m m m f to the v ref pin. c ref = 0.01 to 10 f m m pc1934 16 8
data sheet g13567ej3v0ds00 7 m m m m pc1934 channel 1 channel 1 soft start normal operation out 1 short-load stop output off on dtc 1 fb 1 c t v th channel 2 out 2 dly off on dtc 2 fb 2 c t v uv remark these timings are an example when the channel 1 output has been a short- load. the outputs of channel 1 and 2 are also stoppe d when a short- circuit protection circuit starts operation by detecting a short- load of channel 2. timing charts
data sheet g13567ej3v0ds00 8 m m m m pc1934 typical characteristic curves (unless otherwise specified, v cc = 3 v, f osc = 100 khz, t a = 25 c) (nominal) v ref vs v cc 2.5 2.0 1.5 1.0 0.5 012345 supply voltage v cc (v) reference voltage v ref (v) i ref = 0 a p t vs t a 0.5 0.4 0.3 0.2 0.1 0 25 50 75 100 125 150 operating ambient temperature t a ( c) total power dissipation p t (w) 300 c/w pc1934gr-1jg m 312.5 c/w pc1934gr-pjg m v ref vs t a 2.13 2.12 2.11 2.10 2.08 2.07 2.09 C25 0 25 50 75 100 i ref = 0 a operating ambient temperature t a ( c) reference voltage v ref (v) f osc vs r t 1000 100 10 1 10 1000 100 timing resistance r t (k w) oscillation frequency f osc (khz) c t = 150 pf c t = 1500 pf c t = 330 pf d f osc vs t a 6 4 2 0 C2 C4 C6 0 C25 25 50 75 100 r t = 10 k w c t = 330 pf operating ambient temperature t a ( c) oscillation frequency accuracy d f osc (%) v ol vs t a 0.5 0.4 0.3 0.2 0.1 0 0 C25 25 75 50 100 output on voltage v ol (v) operating ambient temperature t a ( c) i o = 20 ma
data sheet g13567ej3v0ds00 9 m m m m pc1934 v ol vs i o 0.5 0.4 0.3 0 0.1 0.2 4 8 12 16 20 output current i o (ma) output on voltage v ol (v) t dly vs c dly 600 500 400 300 200 100 0 1.0 0.8 0.6 0.4 0.2 dly pin capacitor capacitance c dly ( f) short-circuit protection circuit delay time t dly (ms) m 100 60 80 40 20 0 C20 100 10 k 1 k 10 m C90 C20 0 45 90 135 180 1 m 100 k frequency f (hz) gain a v (db) a v , vs f f a v f f phase (deg) i cc vs v cc 4 3 2 1 0 5 10 15 20 25 30 supply voltage v cc (v) circuit operation i cc (ma)
data sheet g13567ej3v0ds00 10 m m m m pc1934 2. configuration and operation of each block figure 2-1 block diagram 2.1 reference voltage generator the reference voltage generator is comprised of a band-gap reference circuit, and outputs a temperature-compensated reference voltage (2.1 v). the reference voltage can be used as the power supply for internal circuits, or as a reference voltage, and can also be accessed externally via the v ref pin (pin 16). 2.2 oscillator the oscillator self-oscillates if a timing resistor is attached to the r t pin (pin 2). also, the oscillator outputs the symmetrical triangular waveform if a timing capacitor is attached to the c t pin (pin 1). this oscillator waveform is input to the non-inverted input pins of the two pwm comparators to determine the oscillation frequency. 8 10 error amplifier output section pwm comparator scp comparator out 2 dtc 2 fb 2 i i2 7 error amplifier output section pwm comparator out 1 dtc 1 fb 1 i i1 1 c t 2 r t oscillation section sq q gnd dly c dly 15 0.63 v 9 v cc 11 12 13 6 5 4 16 v ref q 2 q 1 reference voltage section under voltage lock-out section i n1 3 i n2 14 timer latch for short-circuit protection section
data sheet g13567ej3v0ds00 11 m m m m pc1934 2.3 under voltage lock-out circuit the under voltage lock-out circuit prevents malfunctioning of the internal circuits when the supply voltage is low, such as when the supply voltage is first applied, or when the power supply is interrupted. when the voltage is low, the two output transistors are cut off at the same time. 2.4 error amplifiers the circuits of the error amplifiers e/a 1 and e/a 2 are exactly the same. the first stage of the error amplifier is a p- channel mos transistor input. be careful of the input voltage ranges (the common mode input voltage ranges are all 0 to 0.4 v (typ.)). 2.5 pwm comparators the output on duty is controlled according to the outputs of the error amplifiers and the voltage input to the dead time control pin. a triangular waveform is input to the non-inverted pin, and the error amplifier output and dead time control pin voltage are input to the inverted pins of the pwm comparators. therefore, the output transistor on period is the period when the triangular waveform is higher than the error amplifier output and dead time control pin voltage (refer to timing charts ). 2.6 timer latch-method short circuit protection circuit when the converter outputs either a channel or both channels drop, the fb outputs of the error amplifiers of those outputs go low. if the fb output goes lower than the timer latch input detection voltage (v th = 0.63 v)), then the output of the scp comparator goes low, and q 1 goes off. when q 1 turns off, the constant-current supply charges c dly via the dly pin. the dly pin is internally connected to a flip-flop. when the dly pin voltage reaches the uv detection voltage (v uv = 0.8 v (typ.)), the output q of the flip-flop goes low, and the output stage of each channel is latched to off (refer to figure 2-1 block diagram ). make the power supply voltage briefly less than the reset voltage (v ccr , 1.0 v typ.) to reset the latch circuit when the short-circuit protection circuit has operated. 2.7 output circuit the output circuit has an n-channel open-drain output providing an output withstand voltage of 30 v (absolute maximum rating), and an output current of 21 ma (absolute maximum rating).
data sheet g13567ej3v0ds00 12 m m m m pc1934 3. notes on use 3.1 setting the output voltage figure 3-1 illustrates the method of setting the output voltage. the output voltage is obtained using the formula shown in the figure. the common mode input voltage range of the error amplifier is 0 to 0.4 v (typ.) for both the error amplifiers, e/a 1 and e/a 2 . therefore, select a resistor value that gives this voltage range. figure 3-1 setting the output voltage (1) when setting a positive output voltage using error amplifier e/a 1 . (2) when setting a negative output voltage using error amplifier e/a 2 . 16 4 3 5 r nf c nf r 4 r 3 r 2 r 1 v ref v ref v out (positive voltage) v out = 1 + r 1 r 2 r 4 r 3 + r 4 e/a 1 16 13 14 12 r nf c nf r 4 r 3 r 2 r 1 v ref v ref v out (negative voltage) v out = r 1 r 4 - r 2 r 3 r 1 (r 3 +r 4 ) e/a 2
data sheet g13567ej3v0ds00 13 m m m m pc1934 3.2 setting the oscillation frequency choose r t according to the oscillation frequency (f osc ) vs timing resistor (c t , r t ) characteristics (refer to typical characteristics curves f osc vs c t , r t ). the formula below (3-1) gives an approximation of f osc . however, the result of formula 3-1 is only an approximation, and the value must be confirmed in actual operation, especially for high-frequency operation. f osc [hz] @ 0.375/(c t [f] x r t [ w ]) (3-1) 3.3 preventing malfunction of the timer latch-method short circuit protection circuit the timer latch short-circuit protection circuit operates when the error amplifier outputs (pin 5 and 12) goes below approximately 0.63 v, and cuts off the output. however, if the rise of the power supply voltage is fast, or if there is noise on the dly pin (pin 15), the latch circuit may malfunction and cut the output off. to prevent this, lower the wiring impedance between the dly pin and the gnd pin (pin 8), and avoid applying noise to the dly pin. 3.4 connecting unused error amplifiers when one of the two control circuits is used, connect the circuit so that the output of the error amplifier of unused circuit is high. figure 3-2 shows examples of how to connect unused error amplifiers. figure 3-2 examples of connecting unused error amplifiers (1) error amplifier e/a 1 (2) error amplifier e/a 2 16 3 4 5 6 v ref dtc 1 e/a 1 16 14 13 12 11 v ref dtc 2 e/a 2
data sheet g13567ej3v0ds00 14 m m m m pc1934 3.5 on/off control the on/off control method of the output oscillation is to input the on/off signal from on as shown in figure 3-3. the pwm converter can be turned on/off by controlling the level of the dtc pin. however, it is necessary to keep the level of the fb output high so that the timer latch does not start when the pwm converter is off. in this circuit example, the fb output level is controlled by controlling the level of the i i pin. figure 3-3 on/off control (1) when on is high: off status q 1 : on ? q 2 : on ? dtc pin: high level ? output duty of pwm comparator: 0 % q 3 : on ? i i pin: low level ? fb output: high level ? scp comparator output: high level ? q is on. ? timer latch stops. (2) when on 3 is low: on status q 1 : off ? q 2 is off. ? c 1 is charged in the sequence of [v ref ? c 1 ? r 4 ] ? dtc pin voltage drops. ? soft start q 3 : off ? i i pin: high level ? fb output: low level ? scp comparator output: low level ? q: off ? charging c dly starts (timer latch start). caution keep the high-level voltage of the dtc pin at 1.6 v or higher and the low-level voltage of the i i pin within (r6/(r5+r6)) v ref . the maximum voltage that is applied to the i i pin must be equal to or lower than v ref . 3.6 notes on actual pattern wiring when actually carrying out the pattern wiring, it is necessary to separate control-related grounds and power-related grounds, and make sure that they do not share impedances as far as possible. in addition, make sure the high-frequency impedance is lowered using capacitors and other components to prevent noise input to the v ref pin. C C + + C C + on q 1 q 2 q 3 q pwm comparator dtc r 2 v ref c dly c 1 fb dly r 1 v o r 5 r 6 v ref r 4 r 3 i i i n 0.3 v 0.63 v error amplifier to output stage oscillation section (common to each channel) scp comparator (common to each channel)
data sheet g13567ej3v0ds00 15 m m m m pc1934 4. application example 4.1 application example figure 4-1 shows an example circuit for obtaining 5 v/50 ma from a +3 v power supply. figure 4-1 chopper-method step-up/inverting-type switching regulator 4.2 list of external parts the list below shows the external parts. table 4-1 list of external parts symbol parameter function part number maker remark c 2 10 m f input stable capacitor 25sc10m sanyo os-con, sc series c 14 68 m f output capacitor 20sa68m sanyo os-con, sa series d 11 schottkey diode d1fs4 shindengen l 11 100 m h choke inductor 636fy-101m toko d73f series q 11 , q 12 buffer transistor m pa609t nec transistor array q 13 switching transistor 2sb1572 nec c 21 68 m f output capacitor 20sa68m sanyo os-con, sa series d 21 schottkey diode d1fs4 shindengen l 21 100 m h choke inductor 636fy-101m toko d73f series q 21 , q 22 buffer transistor m pa609t nec transistor array q 23 switching transistor 2sd2403 nec remarks 1. the capacitors that are not specified in the above list are multilayer ceramic capacitors. 2. the resistors that are not specified in the above list are 1/4w resistors. 4 123 8 567 13 16 15 14 9 12 11 10 m f ch2 v o = +5.0 v i o = 50 ma ch1 v o = - 5.0 v i o = 50 ma gnd gnd r 21 47 k w c 24 68 m h m f c 14 68 r 22 5 k w r 214 10 k w r 12 20 k w r 11 5.1 k w r 111 470 w r 111 10 w r 212 10 w r 210 470 w r 211 24 k w r 24 2 k w r 23 12 k w r 18 12 k w r 18 2 k w r 18 12 k w r 16 10 k w r 17 5 k w r 19 80 w r 29 510 w r t r 111 100 w c 23 100 pf c t 100 pf c 11 1 c 11 c 23 3300 pf c 23 3300 pf 5.1 k w r 25 12 k w r 15 12 k w r 26 10 k w r 27 5 k w r 28 15 k w c 2 10 c 1 1 r 113 10 k w r 112 20 w d 21 q 23 q 23 q 23 q 11 q 13 q 12 d 11 c 113 100 pf l 11 100 m h l 11 100 m f m f m f m f m pc1934 0.1 c 21 m f 1 c dly m f 0.1 i i1 c t r t i n1 gnd fb 1 dtc 1 out 1 ii 2 v ref dly in 2 v cc fb 2 dtc 2 out 2 v in = 3 v com
data sheet g13567ej3v0ds00 16 m m m m pc1934 5. package drawings 16 9 18 s n s detail of lead end c m m a h k l p j i g e f d b item b c h l m 16-pin plastic ssop (5.72 mm (225)) a j d e f g i n millimeters 0.65 (t.p.) 0.475 max. 0.5 0.2 6.2 0.3 0.10 5.2 0.3 0.9 0.2 0.22 0.8 0.125 0.075 1.44 1.565 0.235 4.4 0.2 0.10 5 5 p note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. k 0.17 + 0.08 - 0.07 p16gm-65-225b-4
data sheet g13567ej3v0ds00 17 m m m m pc1934 b detail of lead end k d j m m c 16 9 1 8 s s a a' n r f g e p l s h i item b c j 16-pin plastic tssop (5.72 mm (225)) d g h i p millimeters 0.65 (t.p.) 0.375 max. 1.0 0.2 0.24 0.92 4.4 0.1 6.4 0.2 + 0.06 - 0.04 3 + 5 - 3 note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. e 0.09 + 0.06 - 0.04 f 1.01 + 0.09 - 0.06 a a' 5.0 0.1 5.15 0.15 k l m n 0.5 0.145 0.10 0.10 + 0.055 - 0.045 r s 0.25 0.6 0.15 s16gr-65-pjg-1
data sheet g13567ej3v0ds00 18 m m m m pc1934 6. recommended soldering conditions recommended solder conditions for this product are described below. for details on recommended soldering conditions, refer to information document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended, consult nec. surface mount type m m m m pc1934gr-1jg: 16-pin plastic ssop (5.72 mm (225)) m m m m pc1934gr-pjg: 16-pin plastic tssop (5.72 mm (225)) soldering method soldering conditions symbol of recommended conditions infrared reflow package peak temperature: 235 c, time: 30 seconds max. (210 c min.), number of times: 3 max. ir35-00-3 vps package peak temperature: 215 c, time: 40 seconds max. (200 c min.), number of times: 3 max. vp15-00-3 wave soldering soldering bath temperature: 260 c max., time: 10 seconds max., number of times: 1, preheating temperature: 120 c max. (package surface temperature) ws60-00-1 caution do not use two or more soldering methods in combination.
data sheet g13567ej3v0ds00 19 m m m m pc1934 notes for bicmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins note: no connection for device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. input levels of devices must be fixed high or low by using a pull-up or pull- down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of bicmos devices note: power-on does not necessarily define initial status of device. production process of bicmos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m m m m pc1934 [memo] the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8

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