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intel ? 830 chipset family: 82830 graphics and memory controller hub (gmch-m) datasheet january 2002 order number: 298338-003 r
intel ? 830 chipset family 2 datasheet 298338-003 r information in this document is provided in connection with intel products. no license, express or implied, by estoppel or oth erwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. the information provided in this report, and related materials and presentations, are intended to illustrate the effects of cer tain design variables as determined by modeling, and are neither a recommendation nor endorsement of any specific system-level design practices or ta rgets. the model results are based on a simulated notebook configuration, and do not describe or characterize the properties of any specif ic, existing system design. a detailed description of the simulated notebook configuration is available upon request. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the 830 graphics-memory controller hub- mobile (gmch-m) product may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. current characterized errata are available on request. i2c is a two-wire communications bus/protocol developed by philips*. smbus is a subset of the i2c bus/protocol and was develope d by intel. implementations of the i2c bus/protocol or the smbus bus/protocol may require licenses from various entities, including philips electronics n.v. and north american philips corporation. intel? , pentium?, celeron?, and speedstep? are registered trademarks or trademarks of intel corporation and its subsidiaries i n the united states and other countries. *other brands and names are the property of their respective owners. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copyright ? intel corporation 2002
intel ? 830 chipset family 298338-003 datasheet 3 r contents 1 introduction ................................................................................................................... ............. 24 1.1 document references................................................................................................... 24 2 overview ....................................................................................................................... ............. 25 2.1 terminology................................................................................................................... 2 8 2.2 intel 830 chipset family system architecture .............................................................. 29 2.2.1 intel 830mp chipset.................................................................................... 29 2.2.2 intel 830m chipset ...................................................................................... 29 2.2.3 intel 830mg chipset ................................................................................... 29 2.3 intel 830 chipset family host interface ........................................................................ 30 2.4 intel 830 chipset family system memory interface ..................................................... 30 2.5 intel 830m / 830mp discrete agp interface ................................................................. 30 2.6 intel 830m / 830mg internal graphics introduction ...................................................... 31 2.7 intel 830m / 830mg internal graphics display interface .............................................. 31 2.7.1 intel 830m and 830mg analog display port............................................... 31 2.7.2 intel 830m and 830mg dvo interfaces ...................................................... 31 2.7.2.1 intel 830m and 830mg dedicated dvoa interface ....................... 32 2.7.2.2 intel 830m and 830mg dvob and dvoc interfaces .................... 32 3 signal description ............................................................................................................. ......... 33 3.1 common signals for the intel 830 chipset family........................................................ 35 3.1.1 host interface signals ................................................................................. 35 3.1.2 system memory interface ........................................................................... 37 3.1.3 hub interface signals.................................................................................. 38 3.1.4 clocking and reset ..................................................................................... 38 3.1.5 reserved signals ........................................................................................ 39 3.2 common signals for 830m and 830mp chipset discrete agp graphics implementation .............................................................................................................. 40 3.2.1 agp addressing signals............................................................................. 40 3.2.2 agp flow control signals........................................................................... 41 3.2.3 agp status signals..................................................................................... 41 3.2.4 agp clocking signals ? strobes ................................................................ 42 3.2.5 pci signals - agp semantics.................................................................... 43 3.2.6 pci pins during pci transactions on agp interface ................................. 44 3.3 common signals for 830m and 830mg chipset internal graphics implementation .... 45 3.3.1 dedicated digital video port (dvoa) ......................................................... 46 3.3.2 multiplexed digital video port b (dvob) .................................................... 48 3.3.3 multiplexed digital video port (dvoc) ....................................................... 50 3.3.3.1 dvobc to agp pin mapping ......................................................... 51 3.3.3.2 dvo miscellaneous signals ........................................................... 51 3.3.4 analog display ............................................................................................ 52 3.3.5 display control signals ............................................................................... 53 3.3.5.1 dvo display control signals ......................................................... 54 3.3.5.2 display control signals to agp pin mapping ................................ 54 3.4 intel 830 chipset family voltage references, pll power ........................................... 55 3.5 intel 830 chipset family strap signals ......................................................................... 56 4 register description........................................................................................................... ........ 57 4.1 conceptual overview of the platform configuration structure ..................................... 57 4.2 routing configuration accesses to pci0 or agp/pci .................................................. 59
intel ? 830 chipset family 4 datasheet 298338-003 r 4.2.1 intel 830 chipset family gmch-m configuration cycle flow charts.........60 4.2.2 pci bus configuration mechanism..............................................................60 4.2.3 pci bus #0 configuration mechanism.........................................................61 4.2.4 primary pci and downstream configuration mechanism ...........................61 4.2.5 intel 830m and 830mp chipset agp/pci1 bus configuration mechanism 62 4.2.6 intel 830 chipset family internal gmch-m configuration register access mechanism ..................................................................................................64 4.3 intel 830 chipset family gmch-m register introduction .............................................64 4.4 intel 830 chipset family i/o mapped registers ............................................................65 4.4.1 config_address - configuration address register..............................66 4.4.2 config_data - configuration data register ...........................................68 4.5 intel 830 chipset family gmch-m internal device registers ......................................68 4.5.1 sdram controller/host-hub interface device registers - device #0.........69 4.5.1.1 vid - vendor identification register - device #0 ............................71 4.5.1.2 did - device identification register - device #0.............................71 4.5.1.3 pcicmd - pci command register - device #0 .............................72 4.5.1.4 pcists - pci status register - device #0.....................................73 4.5.1.5 rid - revision identification register - device #0..........................74 4.5.1.6 subc - sub-class code register - device #0...............................74 4.5.1.7 bcc - base class code register - device #0................................75 4.5.1.8 mlt - master latency timer register - device #0 .........................75 4.5.1.9 hdr - header type register - device #0 ......................................75 4.5.1.10 apbase - aperture base configuration register - device #0 ......76 4.5.1.11 svid - subsystem vendor id - device #0 .....................................77 4.5.1.12 sid - subsystem id - device #0 ....................................................77 4.5.1.13 capptr - capabilities pointer - device #0...................................77 4.5.1.14 rrbar - register range base address register - device #0......78 4.5.1.15 gcc0 - gmch control register #0 - device #0 ............................79 4.5.1.16 gcc1-?gmch control register #1 - device #0 ............................81 4.5.1.17 fdhc - fixed dram hole control register - device #0 ...............84 4.5.1.18 pam(6:0) - programmable attribute map registers - device #0....85 4.5.1.19 drb ? dram row boundary register - device #0......................88 4.5.1.20 dra ? dram row attribute register - device #0........................89 4.5.1.21 drt?dram timing register - device #0.....................................90 4.5.1.22 drc - dram controller mode register - device #0 ......................92 4.5.1.23 dtc - dram throttling control register - device #0. ...................94 4.5.1.24 smram - system management ram control register ? device #0 ........................................................................................96 4.5.1.25 esmramc - extended system management ram control register - device #0 .......................................................................97 4.5.1.26 errsts ? error status register ? device #0................................98 4.5.1.27 errcmd - error command register - device #0..........................99 4.5.1.28 acapid - agp capability identifier register - device #0 ............101 4.5.1.29 agpstat - agp status register - device #0 .............................102 4.5.1.30 agpcmd - agp command register - device #0 ........................103 4.5.1.31 agpctrl - agp control register - device #0............................104 4.5.1.32 aft ? agp functional test register ? device #0 .......................104 4.5.1.33 apsize ? aperture size - device #0 ...........................................105 4.5.1.34 attbase ? aperture translation table base register ? device #0 ......................................................................................106 4.5.1.35 amtt ? agp interface multi-transaction timer register - device #0 .................................................................................................106 4.5.1.36 lptt ? low priority transaction timer register - device #0.......107
intel ? 830 chipset family 298338-003 datasheet 5 r 4.5.1.37 buff_sc ? system memory buffer strength control register - device #0...................................................................................... 108 4.5.1.37.1 sdr drive strength register description .................. 108 4.5.2 830m and 830mp chipset host-agp bridge registers - device #1 ..... 111 4.5.2.1 vid1 - vendor identification register - device #1........................ 112 4.5.2.2 did1 - device identification register - device #1 ........................ 112 4.5.2.3 pcicmd1 - pci-pci command register - device #1 ................. 113 4.5.2.4 pcists1 - pci-pci status register - device #1 ......................... 114 4.5.2.5 rid1 - revision identification register - device #1 ..................... 115 4.5.2.6 subc1 - sub-class code register - device #1 .......................... 115 4.5.2.7 bcc1 - base class code register - device #1 ........................... 116 4.5.2.8 mlt1 - master latency timer register - device #1 .................... 116 4.5.2.9 hdr1 - header type register - device #1 .................................. 117 4.5.2.10 pbusn - primary bus number register - device #1................... 117 4.5.2.11 sbusn - secondary bus number register - device #1............. 117 4.5.2.12 subusn - subordinate bus number register - device #1 ......... 118 4.5.2.13 smlt - secondary master latency timer register - device #1.. 118 4.5.2.14 iobase - i/o base address register - device #1....................... 119 4.5.2.15 iolimit - i/o limit address register - device #1........................ 119 4.5.2.16 ssts - secondary pci-pci status register - device #1 ........... 120 4.5.2.17 mbase - memory base address register - device #1 ............... 121 4.5.2.18 mlimit - memory limit address register - device #1 ................ 121 4.5.2.19 pmbase - prefetchable memory base address register - device #1 ................................................................................................ 122 4.5.2.20 pmlimit - prefetchable memory limit address register - device #1 ................................................................................................ 123 4.5.2.21 bctrl - pci-pci bridge control register - device #1 ............... 124 4.5.2.22 errcmd1 - error command register - device #1 .................... 125 4.5.3 830m and 830mg chipset integrated graphics device registers ? device #2 .................................................................................................. 126 4.5.3.1 vid2 - vendor identification register ? device #2....................... 127 4.5.3.2 did2 - device identification register - device #2 ........................ 128 4.5.3.3 pcicmd2 - pci command register - device #2......................... 128 4.5.3.4 pcists2 - pci status register - device #2 ................................ 130 4.5.3.5 rid2 - revision identification register - device #2 ..................... 131 4.5.3.6 cc - class code register - device #2......................................... 131 4.5.3.7 cls - cache line size register - device #2 ............................... 132 4.5.3.8 mlt2 - master latency timer register - device #2 .................... 132 4.5.3.9 hdr2 - header type register - device #2 .................................. 132 4.5.3.10 gmadr - graphics memory range address register ? device #2 ................................................................................................ 133 4.5.3.11 mmadr - memory mapped range address register ? device #2 ................................................................................................ 134 4.5.3.12 svid2 - subsystem vendor identification register - device #2 .. 134 4.5.3.13 sid2 - subsystem identification register - device #2 ................. 134 4.5.3.14 romadr - video bios rom base address registers ? device #2 ................................................................................................ 135 4.5.3.15 cappoint - capabilities pointer register - device #2 ............... 135 4.5.3.16 intrline - interrupt line register - device #2........................... 135 4.5.3.17 intrpin - interrupt pin register - device #2 .............................. 136 4.5.3.18 mingnt - minimum grant register - device #2.......................... 136 4.5.3.19 maxlat - maximum latency register - device #2..................... 136 4.5.3.20 pmcapid - power management capabilities id register - device #2 ................................................................................................ 137
intel ? 830 chipset family 6 datasheet 298338-003 r 4.5.3.21 pmcap - power management capabilities register - device #2 .................................................................................................137 4.5.3.22 pmcs - power management control/status register - device #2 ......................................................................................138 5 functional description ......................................................................................................... .....139 5.1 system address map...................................................................................................139 5.1.1 system memory address ranges .............................................................139 5.1.2 compatibility area......................................................................................141 5.1.2.1 dos area (00000h-9ffffh) ........................................................142 5.1.2.2 legacy vga ranges (a0000h-bffffh) ......................................142 5.1.2.3 compatible smram address range (a0000h-bffffh) .............142 5.1.2.4 monochrome adapter (mda) range (b0000h - b7fffh) ............143 5.1.2.5 expansion area (c0000h-dffffh) ..............................................143 5.1.2.6 extended system bios area (e0000h-effffh) .........................143 5.1.2.7 system bios area (f0000h-fffffh)..........................................143 5.1.3 extended memory area .............................................................................143 5.1.3.1 main system sdram address range (0010_0000h to top of main memory) ........................................................................................143 5.1.3.1.1 15 mb-16 mb window ................................................144 5.1.3.1.2 pre-allocated memory.................................................144 5.1.3.2 extended smram address range (hseg and tseg) ...............144 5.1.3.2.1 hseg ..........................................................................144 5.1.3.2.2 tseg ..........................................................................144 5.1.3.3 intel dynamic video memory technology (dvmt).......................144 5.1.3.4 pci memory address range (top of main memory to 4 gb) ......145 5.1.3.5 configuration space (fec0_0000h -fecf_ffffh, fee0_0000h- feef_ffffh) ...............................................................................145 5.1.3.6 high bios area (ffe0_0000h -ffff_ffffh) ............................145 5.1.4 agp memory address ranges .................................................................146 5.2 intel 830 chipset family host interface.......................................................................146 5.2.1 overview....................................................................................................146 5.2.2 processor unique psb activity .................................................................147 5.2.3 host addresses above 4 gb.....................................................................149 5.2.4 host bus cycles ........................................................................................150 5.2.4.1 partial reads.................................................................................150 5.2.4.2 part-line read and write transactions........................................150 5.2.4.3 cache line reads ........................................................................150 5.2.4.4 partial writes.................................................................................150 5.2.4.5 cache line writes.........................................................................150 5.2.4.6 memory read and invalidate (length > 0) ...................................150 5.2.4.7 memory read and invalidate (length = 0) ...................................150 5.2.4.8 memory read (length = 0) ...........................................................151 5.2.4.9 host initiated zero-length r/w cycles ........................................151 5.2.4.10 cache coherency cycles .............................................................151 5.2.4.11 interrupt acknowledge cycles ......................................................152 5.2.4.12 locked cycles...............................................................................152 5.2.4.12.1 cpu<->system sdram locked cycles ....................152 5.2.4.12.2 cpu<->hub interface locked cycles.........................152 5.2.4.12.3 cpu<->agp/pci locked cycles ................................152 5.2.4.12.4 cpu<->igd (graphics memory).................................152 5.2.4.13 branch trace cycles.....................................................................152 5.2.4.14 special cycles ..............................................................................153 5.2.5 in-order queue pipelining .........................................................................154
intel ? 830 chipset family 298338-003 datasheet 7 r 5.2.6 write combining........................................................................................ 154 5.3 intel 830 chipset family system memory interface ................................................... 155 5.3.1 sdram interface overview ...................................................................... 155 5.3.2 sdram organization and configuration .................................................. 155 5.3.2.1 configuration mechanism for so-dimms..................................... 156 5.3.2.1.1 memory detection and initialization ........................... 156 5.3.2.1.2 sdram register programming ................................. 156 5.3.3 sdram address translation and decoding............................................. 157 5.3.4 sdram performance description ............................................................ 157 5.4 intel 830m and 830mg chipset internal graphics description................................... 157 5.4.1 3d/2d instruction processing ................................................................... 158 5.4.2 3d engine.................................................................................................. 158 5.4.2.1 setup engine ................................................................................ 159 5.4.2.2 viewport transform and perspective divide ................................ 159 5.4.2.3 3d primitives and data formats support..................................... 159 5.4.2.4 pixel accurate fast scissoring and clipping operation............... 159 5.4.2.5 backface culling........................................................................... 159 5.4.2.6 scan converter............................................................................. 159 5.4.2.7 texture engine ............................................................................. 160 5.4.2.8 perspective correct texture support ........................................... 160 5.4.2.8.1 texture decompression ............................................. 160 5.4.2.9 texture colorkey and chromakey .............................................. 160 5.4.2.10 anti-aliasing .................................................................................. 160 5.4.2.11 texture map filtering.................................................................... 161 5.4.2.12 multiple texture composition....................................................... 161 5.4.2.13 cubic environment mapping ........................................................ 162 5.4.2.14 bump mapping ............................................................................. 162 5.4.3 raster engine ........................................................................................... 162 5.4.3.1 texture map blending .................................................................. 162 5.4.3.2 combining intrinsic and specular color components ................. 162 5.4.3.3 color shading modes ................................................................... 163 5.4.3.4 color dithering.............................................................................. 163 5.4.3.5 vertex and per pixel fogging....................................................... 163 5.4.3.6 alpha blending (frame buffer)..................................................... 163 5.4.3.7 color buffer formats: (destination alpha) ................................... 164 5.4.3.8 depth buffer ................................................................................. 164 5.4.3.9 stencil buffer ................................................................................ 164 5.4.3.10 projective textures....................................................................... 165 5.4.4 2d engine.................................................................................................. 165 5.4.4.1 gmch-m vga registers and enhancements ............................. 165 5.4.4.2 256-bit pattern fill and blt engine ............................................. 165 5.4.4.3 alpha stretch blt ........................................................................ 166 5.4.5 planes and engines .................................................................................. 166 5.4.5.1 dual display functionality ............................................................ 166 5.4.6 hardware cursor plane............................................................................. 167 5.4.6.1 cursor color formats ................................................................... 167 5.4.6.2 cursor hot spot............................................................................ 167 5.4.6.3 popup plane ................................................................................. 167 5.4.6.4 popup color formats ................................................................... 168 5.4.7 overlay plane............................................................................................ 168 5.4.7.1 multiple overlays .......................................................................... 168 5.4.7.2 source/destination color-/chroma-keying .................................. 168 5.4.7.3 gamma correction ....................................................................... 168 5.4.7.4 yuv to rgb conversion .............................................................. 168
intel ? 830 chipset family 8 datasheet 298338-003 r 5.4.7.5 color control .................................................................................168 5.4.7.6 x/y mirroring .................................................................................168 5.4.7.7 dynamic bob and weave .............................................................169 5.4.8 video functionality ....................................................................................169 5.4.8.1 mpeg-2 decoding ........................................................................169 5.4.8.2 hardware motion compensation ..................................................169 5.5 intel 830m and 830mg chipset internal graphics display interface ..........................169 5.5.1 analog display port characteristics ..........................................................170 5.5.1.1 integrated ramdac .....................................................................170 5.5.1.2 ddc (display data channel) ........................................................170 5.5.2 dvo display interface ...............................................................................170 5.5.2.1 dedicated digital display channel - dvoa ..................................170 5.5.2.2 multiplexed digital display channels ? dvob and dvoc...........171 5.5.2.2.1 optional high speed (dual channel) interface ..........171 5.5.2.3 ddc (display data channel) ........................................................171 5.5.2.4 third party tmds/lvds support capabilities .............................171 5.5.2.5 tv encoder capabilities ...............................................................171 5.5.2.5.1 flicker filter and overscan compensation.................172 5.5.2.5.2 direct yuv from overlay ...........................................172 5.5.2.5.3 analog content protection ..........................................172 5.5.2.5.4 support of progressive scan sdtv tvs ....................172 5.5.3 concurrent and simultaneous display ......................................................172 5.6 intel 830m and 830mp discrete agp interface...........................................................173 5.6.1 agp target operations .............................................................................173 5.6.2 agp transaction ordering ........................................................................174 5.6.3 agp electricals..........................................................................................174 5.6.4 support for pci-66 devices .......................................................................174 5.6.5 4x agp protocol ........................................................................................174 5.6.6 fast writes.................................................................................................175 5.6.7 agp-to-memory read coherency mechanism .........................................175 5.6.8 pci semantic transactions on agp .........................................................175 5.6.8.1 pci read snoop-ahead and buffering.........................................175 5.6.8.2 intel 830m and 830mp chipset gmch-m initiator and target operations.....................................................................................175 5.6.8.3 gmch-m retry/disconnect conditions ........................................179 5.6.8.4 delayed transaction .....................................................................179 5.7 intel 830 chipset family gmch-m power and thermal management .......................179 5.7.1 acpi 2.0 support.......................................................................................180 5.7.2 acpi states supported .............................................................................180 5.7.2.1 intel 830m and 830mp chipset acpi supported states ..............180 5.7.2.2 intel 830m and 830mg chipset acpi supported states..............181 5.7.3 intel 830 chipset family system and cpu states ....................................182 5.7.4 intel 830 chipset family cpu ?c? states ..................................................182 5.7.4.1 full-on (c0) ..................................................................................182 5.7.4.2 auto-halt (c1) ...............................................................................182 5.7.4.3 quickstart (c2) ..............................................................................182 5.7.4.4 deep sleep (c3) ...........................................................................183 5.7.5 intel 830mp and 830m chipset agp_busy# protocol with external graphics ....................................................................................................183 5.7.6 intel 830m and 830mg internal graphics device agp_busy# protocol.183 5.7.7 enhanced intel speedstep ? technology (applicable with mobile intel corporation pentium iii processor-m only) ...............................................183 5.7.8 intel 830 chipset family system ?s? states ..............................................184 5.7.8.1 powered-on-suspend (pos) (s1) ..............................................184
intel ? 830 chipset family 298338-003 datasheet 9 r 5.7.8.2 suspend-to-ram (str) (s3) ...................................................... 184 5.7.8.3 s4 (suspend to disk), s5 (soft off) state ............................. 185 5.7.9 intel 830m and 830mg chipset internal graphics ?d? states .................. 185 5.7.9.1 d0 graphics adapter state ? active state ................................... 185 5.7.9.2 the d1 graphics adapter state ................................................... 185 5.7.9.3 the d3 graphics adapter state ................................................... 185 5.7.9.4 monitor [analog crt] states........................................................ 185 5.7.9.5 dpms clock signaling in s1 (d1) state....................................... 186 5.7.10 system memory dynamic cke support.................................................... 186 5.7.11 intel 830 chipset family gmch-m thermal management....................... 186 5.7.11.1 thermal sensor ............................................................................ 187 5.7.11.2 graphic thermal throttling........................................................... 187 5.7.11.3 system and graphics memory bandwidth monitoring and throttling....................................................................................... 187 5.8 clocking....................................................................................................................... 187 5.9 xor test chains ........................................................................................................ 188 5.9.1.1 test mode entry ........................................................................... 188 5.9.1.2 rac chain initialization................................................................ 189 5.9.1.3 xor chain test pattern consideration for differential pairs ...... 191 5.9.1.4 xor chain exclusion list ............................................................ 192 5.9.1.5 nc balls........................................................................................ 193 5.9.1.6 xor chain connectivity/ordering................................................ 194 6 intel 830 chipset family performance..................................................................................... 207 7 mechanical specification ....................................................................................................... .. 208 7.1 intel 830mp chipset gmch-m ballout diagram ......................................................... 208 7.2 intel 830m chipset gmch-m ballout diagram ........................................................... 211 7.3 intel 830mg gmch-m ballout diagram...................................................................... 214 7.4 intel 830mp gmch-m signal list ............................................................................... 217 7.5 intel 830m gmch-m signal list.................................................................................. 227 7.6 intel 830mg gmch-m signal list............................................................................... 237 7.7 intel 830 chipset family chipset package dimensions ............................................. 245
intel ? 830 chipset family 10 datasheet 298338-003 r figures figure 1. intel 830mp chipset interface block diagram ............................................................25 figure 2. intel 830m chipset interface block diagram...............................................................26 figure 3. intel 830mg chipset interface block diagram............................................................27 figure 4. intel 830mp chipset logical bus structure during pci configuration .......................58 figure 5. intel 830m chipset logical bus structure during pci configuration..........................58 figure 6. 830mg chipset logical bus structure during pci configuration...............................59 figure 7. configuration cycle flow chart ..................................................................................60 figure 8. hub interface type 0 configuration address translation ...........................................61 figure 9. hub interface type 1 configuration address translation ...........................................62 figure 10. mechanism #1 type 0 configuration address to pci address mapping..................62 figure 11. mechanism #1 type 1 configuration address to pci address mapping..................63 figure 12. pam registers ....................................................................................................... ...86 figure 13. memory system address map ................................................................................140 figure 14. detailed memory system address map..................................................................141 figure 15. intel 830m and 830mg chipset gmch-m graphics block diagram ......................158 figure 16. xor chain test mode entry events diagram........................................................189 figure 17. rac chain timing diagram....................................................................................190 figure 18. intel 830mp ballout diagram (left) .........................................................................209 figure 19. intel 830mp ballout (right) .....................................................................................210 figure 20. intel 830m chipset ballout diagram (left) ..............................................................212 figure 21. intel 830m chipset ballout diagram (right)............................................................213 figure 22. intel 830mg chipset ballout diagram (left) ...........................................................215 figure 23. intel 830mg chipset ballout diagram (right).........................................................216 figure 24. intel 830 chipset family gmch-m package dimensions ......................................245
intel ? 830 chipset family 298338-003 datasheet 11 r tables table 1. signal voltage levels ................................................................................................. .34 table 2. host interface signal descriptions............................................................................... 35 table 3. system memory interface signal descriptions ............................................................ 37 table 4. hub interface signal descriptions ............................................................................... 38 table 5. clocking and reset signal descriptions...................................................................... 38 table 6. intel reserved signals ................................................................................................ .39 table 7. agp addressing signal descriptions .......................................................................... 40 table 8. agp flow control signal descriptions ........................................................................ 41 table 9. agp status signal descriptions .................................................................................. 41 table 10. agp clock signal-strobe descriptions...................................................................... 42 table 11. pci signals ? agp semantics signal descriptions................................................... 43 table 12. internal graphics status signal descriptions ............................................................ 45 table 13. dedicated digital video port (dvoa) signal descriptions ........................................ 46 table 14. multiplexed dvob (dvob) signal descriptions ........................................................ 48 table 15. multiplexed digital video port c (dvoc) signal descriptions................................... 50 table 16. multiplexed dvobc to agp pin mapping information .............................................. 51 table 17. analog display signal descriptions ........................................................................... 52 table 18. display control signal descriptions........................................................................... 53 table 19. dvo display control signals descriptions ................................................................ 54 table 20. display signals to agp pin mapping signal descriptions......................................... 54 table 21. voltage references, pll power signal descriptions................................................ 55 table 22. bootup strap signal descriptions .............................................................................. 56 table 23. agp/pci1 config address remapping ..................................................................... 63 table 24. nomenclature for access attributes .......................................................................... 68 table 25. host-hub i/f bridge/sdram controller configuration space (device #0) ............... 69 table 26. attribute bit assignment............................................................................................. 85 table 27. pam registers and associated memory segments.................................................. 87 table 28. summary of gmch-m error sources, enables and status flags........................... 100 table 29. host-agp bridge configuration space (device #1) ................................................ 111 table 30. integrated graphics device configuration space (device #2) ................................ 126 table 31. memory segments and attributes ........................................................................... 142 table 32. host bus transactions supported by gmch-m ...................................................... 148 table 33. host bus responses supported by gmch-m......................................................... 149 table 34. intel 830 chipset family gmch-m responses to host initiated special cycles .... 153 table 35. system memory so-dimm configurations.............................................................. 155 table 36. data bytes on so-dimm used for programming sdram registers ..................... 156 table 37. address translation and decoding.......................................................................... 157 table 38. dual display usage model ...................................................................................... 167 table 39. dvo usage model ................................................................................................... 172 table 40. agp commands supported by gmch-m when acting as an agp target............ 173 table 41. pci commands supported by gmch-m when acting as a pci target................. 176 table 42. pci commands supported by gmch-m when acting as an agp/pci1 initiator... 178 table 43. intel 830 chipset family system and cpu states .................................................. 182 table 44. combinations of crt and graphics power down states ....................................... 186 table 45. rac chain timing descriptions .............................................................................. 190 table 46. xor chain differential pairs ................................................................................... 191 table 47. nc ball and associated xor chain........................................................................ 193 table 48. xor chain agp1 .................................................................................................... 194 table 49. xor chain agp2 .................................................................................................... 195 table 50. xor chain dvo ...................................................................................................... 19 6 table 51. xor chain psb1..................................................................................................... 19 7
intel ? 830 chipset family 12 datasheet 298338-003 r table 52. xor chain psb2 .....................................................................................................19 9 table 53. xor chain gpio .....................................................................................................20 1 table 54. xor chain hub.......................................................................................................2 01 table 55. xor chain sm1 .......................................................................................................2 02 table 56. xor chain sm2 .......................................................................................................2 03 table 57. xor chain cmos ...................................................................................................205 table 58. xor chain rac.......................................................................................................2 05 table 59. system bandwidths ..................................................................................................20 7 table 60. intel 830mp chipset ballout signal name list.........................................................217 table 61. intel 830m chipset ballout signal name list ...........................................................227 table 62. intel 830mg chipset ballout signal name list ........................................................237
intel ? 830 chipset family 298338-003 datasheet 13 r revision history rev. description date 001 initial release july 2001 002 updates include: ? added design specifications for 830m and 830mg chipset ? added mobile intel ? celeron ? processors support information october 2001 003 updates include: ? better differentiation between 830 skus (830mp, 830m, and 830mg) ? added ball-out diagrams and signal list for each skus (830mp, 830m, and 830mg) ? updated intel reserved signals ? removed local memory support ? removed sections 5.4.8.3 and 5.4.8.4 january 2002
intel ? 830 chipset family 14 datasheet 298338-003 r intel ? 830mp chipset product features mobile processor/host bus support ? optimized for mobile intel ? pentium ? iii processor-m /mobile intel ? celeron ? processors 1 at 133-mhz host bus frequency ? supports 32-bit host bus addressing ? 1.25 v agtl bus driver technology (gated agtl receivers for reduced power) ? supports dual ended agtl termination system memory sdram controller ? single data rate (sdr) sdram support ? supports pc133 only ? four integrated 133- mhz system memory clocks ? supports 64-mb, 128-mb, 256-mb, and 512-mb technologies ? maximum of 1.0 gb of system memory using 512-mb technology ? supports lvttl signaling interface hub interface proprietary interconnect between gmch- m and ich3-m accelerated graphics port (agp) interface ? supports a single agp or pci-66 device ? agp support ? supports agp 2.0 including 4x agp data transfers ? agp 1.5-v signaling only ? fast writes ? pci support ? 66-mhz pci 2.2 specification compliant with the following exceptions: 1.5v but not 3.3-v safe, agp 2.0 specification electricals power management ? apm rev 1.2 compliant power management ? acpi 1.0b and 2.0 support ? system states: s0, s1, s3, s4, s5 ? cpu states: c0, c1, c2, c3 package ? 625 pbga io device support ? 82801cam (i/o controller hub) 1 the 830 chipset family is optimized for the mobile intel ? pentium ? iii processor-m, the mobile intel ? celeron ? processor (0.13 ) in micro-fcbga and micro-fcpga packages, and the mobile intel ? celeron ? processor (.18 ) in micro-fcbga and micro-fcpga packages (hereafter referred to as mobile intel celeron processors)
intel ? 830 chipset family 298338-003 datasheet 15 r intel 830mp chipset interface block diagram mobile intel pentium iii processor ?m / mobile intel celeron processor gmch-m lpc i/f lan hub interface pci bus super i/o docking ich3-m ext. gc lpc flash ide keyboard, sp, ir usb agp sdram system memory mouse, pp processor side bus
intel ? 830 chipset family 16 datasheet 298338-003 r intel ? 830m chipset product features mobile processor/host bus support ? optimized for mobile intel ? pentium ? iii processor-m /mobile intel ? celeron ? processors 2 at 133- mhz host bus frequency ? supports 32-bit host bus addressing ? 1.25-v agtl bus driver technology (gated agtl receivers for reduced power) ? supports dual ended agtl termination system memory sdram controller ? single data rate (sdr) sdram support ? supports pc133 only ? four integrated 133- mhz system memory clocks ? supports 64-mb, 128-mb, 256-mb, and 512-mb technologies ? maximum of 1.0 gb of system memory using 512-mb technology ? supports lvttl signaling interface accelerated graphics port (agp) interface ? supports a single agp or pci-66 device ? agp support ? supports agp 2.0 including 4x agp data transfers ? agp 1.5-v signaling only ? fast writes ? pci support ? 66-mhz pci 2.2 specification compliant with the following exceptions: 1.5-v but not 3.3-v safe, agp specification electricals. hub interface ? proprietary interconnect between gmch-m and ich3-m graphics features ? core frequency up to 166 mhz ? high performance 3d setup and render engine ? setup capable of delivering mobile intel pentium iii processor-m / mobile celeron processors performance ? triangles list, strips, and fans support ? d3d vertex formats ? pixel accurate fast scissoring and clipping operation ? backface culling support ? support d3d and ogl pixelization rules ? sprite points support ? high quality / performance texture engine ? per pixel perspective corrected texture mapping 2 the 830 chipset family is optimized for the mobile intel ? pentium ? iii processor-m, the mobile intel ? celeron ? processor (0.13) in micro-fcbga and micro-fcpga packages, and the mobile intel ? celeron ? processor (.18) in micro-fcbga and micro-fcpga packages (hereafter referred to as mobile intel celeron processors)
intel ? 830 chipset family 298338-003 datasheet 17 r ? single pass texture compositing ? 12 level of details mip map sizes from 1x1 to 2kx2k ? all texture formats including 32-bit rgba and 8-bit paletted ? alpha and luminance maps ? texture colorkeying / chromakeying ? bilinear, trilinear, and anisotropic mip-mapped filtering ? cubic environment reflection mapping ? embossed and environment reflection mapping ? embossed and environment bump-mapping ? d3d (dxtn) texture decompression ? 3d graphics rasterization enhancements ? flat & gouraud shading ? color alpha blending for transparency ? vertex and programmable pixel fog and atmospheric effects ? color specular lighting ? line and full-scene anti-aliasing ? 16-bit and 24-bit z buffering ? 16-bit and 24-bit w buffering ? 8-bit stencil buffering ? double and triple render buffer support ? 16-bit and 32-bit color ? destination alpha ? fast clear support ? 2d graphics ? 256-bit pattern fill and blt engine performance ? programmable 3-color transparent cursor ? color space conversion ? gdi+ feature support ? anti-aliased lines ? alpha blended cursor ? anti-aliased text ? alpha stretch blitter ? 8-bit, 16-bit and 32-bit color ? rop support ? video ? dynamic bob and weave support for video streams ? supports 720 x 480 dvd quality encoding ? mpeg2 hwmc decoding support ? video overlay ? single high quality scalable overlay ? multiple overlay functionality provided via stretch blitter ? independent gamma correction ? independent brightness / contrast / saturation ? independent tint / hue support ? destination colorkeying ? source chromakeying display ? analog display support ? 350-mhz integrated 24-bit ramdac ? hardware color cursor support ? ddc2b compliant
intel ? 830 chipset family 18 datasheet 298338-003 r ? dual display options with fp/ digital display ? concurrent: different images and native display timings on each display device ? simultaneous: same images and native display timings on each display device ? dvo support ? 3 dvo interfaces supported ? 165-mhz dot clock with 12-bit interface ? supports hot plug display ? supports a variety of dvo devices ? dedicated dvo (dvoa) interface ? 165-mhz dot clock 12-bit interface ? multiplexed dvo (dvob and dvoc) interface ? two channels multiplexed with agp ? can combine two 12-bits channels to form one 24-bit interface ? supports larger display resolutions ? supports one additional flat panel display and / or one tv power management ? apm rev 1.2 compliant power management ? acpi 1.0b and 2.0 support ? system states: s0, s1, s3, s4, s5 ? cpu states: c0, c1, c2, c3 package ? 625 pbga io device support ? 82801cam (i/o controller hub)
intel ? 830 chipset family 298338-003 datasheet 19 r intel 830m chipset interface block diagram mobile intel pentium iii processor ?m / mobile intel celeron processor gmch-m lpc i/f lan hub interface pci bus super i/o docking ich3-m ext. gc or lpc flash ide keyboard, sp, ir usb agp sdram system memory dvob/dvoc fp display v ga crt mouse, pp processor side bus dac dvo
intel ? 830 chipset family 20 datasheet 298338-003 r intel ? 830mg chipset product features mobile processor/host bus support ? optimized for mobile intel pentium iii processor-m / mobile intel celeron processors 3 at 133- mhz host bus frequency ? supports 32-bit host bus addressing ? 1.25-v agtl bus driver technology (gated agtl receivers for reduced power) ? supports dual ended agtl termination system memory sdram controller ? single data rate (sdr) sdram support ? supports pc133 only ? four integrated 133- mhz system memory clocks ? supports 64-mb, 128-mb, 256-mb, and 512-mb technologies ? maximum of 1.0 gb of system memory using 512-mb technology ? supports lvttl signaling interface hub interface proprietary interconnect between gmch-m and ich3-m graphics features ? core frequency up to 166 mhz ? high performance 3d setup and render engine ? setup capable of delivering mobile intel pentium iii processor-m / mobile celeron processors performance ? triangles list, strips, and fans support ? d3d vertex formats ? pixel accurate fast scissoring and clipping operation ? backface culling support ? support d3d and ogl pixelization rules ? sprite points support ? high quality / performance texture engine ? per pixel perspective corrected texture mapping ? single pass texture compositing ? 12 level of details mip map sizes from 1x1 to 2kx2k ? all texture formats including 32-bit rgba and 8-bit paletted ? alpha and luminance maps ? texture colorkeying / chromakeying ? bilinear, trilinear, and anisotropic mip-mapped filtering ? cubic environment reflection mapping ? embossed and environment reflection mapping ? embossed and environment bump-mapping ? d3d (dxtn) texture decompression ? 3d graphics rasterization enhancements 3 the 830 chipset family is optimized for the mobile intel pentium iii processor-m, the mobile intel celeron ? processor (0.13) in micro-fcbga and micro-fcpga packages, and the mobile intel celeron ? processor (.18) in micro-fcbga and micro-fcpga packages (hereafter referred to as mobile intel celeron processors).
intel ? 830 chipset family 298338-003 datasheet 21 r ? flat & gouraud shading ? color alpha blending for transparency ? vertex and programmable pixel fog and atmospheric effects ? color specular lighting ? line and full-scene anti-aliasing ? 16-bit and 24-bit z buffering ? 16-bit and 24-bit w buffering ? 8-bit stencil buffering ? double and triple render buffer support ? 16-bit and 32-bit color ? destination alpha ? fast clear support ? 2d graphics ? 256-bit pattern fill and blt engine performance ? programmable 3-color transparent cursor ? color space conversion ? gdi+ feature support ? anti-aliased lines ? alpha blended cursor ? anti-aliased text ? alpha stretch blitter ? 8-bit, 16-bit and 32-bit color ? rop support ? video ? dynamic bob and weave support for video streams ? supports 720 x 480 dvd quality encoding ? mpeg2 hwmc decoding support ? video overlay ? single high quality scalable overlay ? multiple overlay functionality provided via stretch blitter ? independent gamma correction ? independent brightness / contrast / saturation ? independent tint / hue support ? destination colorkeying ? source chromakeying display ? analog display support ? 350-mhz integrated 24-bit ramdac ? hardware color cursor support ? ddc2b compliant ? dual display options with fp/ digital display ? concurrent: different images and native display timings on each display device ? simultaneous: same images and native display timings on each display device ? dvo support ? 3 dvo interfaces supported ? 165-mhz dot clock with 12-bit interface ? supports hot plug display ? dedicated dvo (dvoa) interface ? 165-mhz dot clock 12-bit interface ? multiplexed dvo (dvob & dvoc) interface ? two channels multiplexed with agp
intel ? 830 chipset family 22 datasheet 298338-003 r ? can combine two 12-bits channels to form one 24-bit interface ? supports larger display resolutions ? supports one additional flat panel and / or one tv power management ? apm rev 1.2 compliant power management ? acpi 1.0b and 2.0 support ? system states: s0, s1, s3, s4, s5 ? cpu states: c0, c1, c2, c3 package ? 625 pbga io device support ? 82801cam (i/o controller hub)
intel ? 830 chipset family 298338-003 datasheet 23 r intel 830mg chipset interface block diagram mobile intel pentium iii processor ?m / mobile intel celeron processor gmch-m lpc i/f lan hub interface pci bus super i/o docking ich3-m lpc flash ide keyboard, sp, ir usb dvo sdram system memory dvob/dvoc fp display ( dvoa ) v ga crt mouse, pp processor side bus dac dvo
intel ? 830 chipset family 24 datasheet 298338-003 r 1 introduction this document provides the external design specifications for notebook computer manufacturers. 1.1 document references ? mobile intel ? pentium ? iii processor-m datasheet (298340-003): contact http://developer.intel.com/design/mobile/datashts/298340.htm ? mobile intel ? celeron ? processor (0.18) in micro-fcbga and micro-fcpga packages datasheet (298514-001): contact http://developer.intel.com/design/mobile/datashts/298514.htm ? mobile intel ? celeron ? processor (0.13) in micro-fcbga and micro-fcpga packages datasheet (298517-001): contact http://developer.intel.com/design/mobile/datashts/298517.htm ? pci local bus specification 2.2 : contact www.pcisig.com ? intel ? 82801cam i/o controller hub 3 (ich3-m) datasheet (290716-002): contact http://developer.intel.com/design/chipsets/datashts/290716.htm ? intel ? 830 chipset family design guide (298339-003): contact http://developer.intel.com/design/chipsets/designex/298339.htm ? advanced graphic port (agp) 2.0 specification : contact ftp://download.intel.com/technology/agp/downloads/agp20.pdf ? advanced configuration and power management (acpi) specification 1.0b & 2.0 : contact http://www.teleport.com/~acpi/ ? advanced power management (apm) specification 1.2 : contact http://www.microsoft.com/hwdev/busbios/amp_12.htm ? write combing memory implementation guideline : contact http://developer.intel.com/design/pentiumii/applnots/244422.htm ? ia-32 intel architecture software developer manuel volume 3: system programming guide : contact http://developer.intel.com/design/pentium4/manuals/24547203.pdf ? intel graphics software pc 10.0 product requirements: contact you intel field representative.
intel ? 830 chipset family 298338-003 datasheet 25 r 2 overview figure 1. intel 830mp chipset interface block diagram
intel ? 830 chipset family 26 datasheet 298338-003 r figure 2. intel 830m chipset interface block diagram , display interface system memory (single data rate) sm_ma[12:0] sm_ba[1:0] sm_md[63:0] sm_ecc[7:0] sm_dqm[7:0] sm_cs[5:0]# sm_ras# sm_cas# sm_we# sm_cke[5:0] sm_rcomp vsync hsync red green blue refset [red,green,blue# agp interface sba[7:0] pipe# st[2:0] rbf# wbf# ad_stb[1:0], ad_stb[1:0]# sb_stb, sb_stb# agprcomp g_frame# g_irdy# g_trdy# g_stop# g_devsel# g_req# g_gnt# g_ad[31:0] g_c/be[3:0]# g_par host interface ha[31:3]# hd[63:0]# ads# bnr# bpri# dbsy# defer# drdy# hit# hitm# hlock# hreq[4:0]# htrdy# rs[2:0]# cpurst# gtl_rcomp gtl_ref[b:a] ram_ref[b:a] agpref hlref vcca_hpll, vssa_hpll vcca_cpll, vssa_cpll vcca_dpll, vssa_dpll vcccmos vccq_agp vccqsm voltage refernce, pll power multiplexed with agp (either agp or these functions) note: dashed lines indicated multiplexed functions. htclk, htclk# gbout gbin gm_gclk [reserved] drefclk reset# clocks and reset digital video out a (dvoa) dvoa_clk/dvoa_clk dvoa_d[11:0] dvoa_hsync dvoa_vsync dvoa_blank# dvoa_rcomp dvoa_intr# dvoa_clkint dvoa_fld/stl hub interface hl[10:0] hlstrb, hlstrb# hl_rcomp ddc2_data ddc2_clk i2c_data i2c _clk ddc1_data ddc1_clk gpio digital video out c (dvoc) dvoc_clk/dvoc_clk dvoc_d[11:0] dvoc_hsync dvoc_vsync dvoc_blank# dvobc_intr# dvoc_fld/stl mddc_data mddc_clk mi2c_data mi2c_clk multiplexed gpio dq_a[7:0] [reserved] dq_b[7:0] [reserved] rq[7:0] [reserved] ctm, ctm# [reserved] cfm, cfm# [reserved] cmd [reserved] sck [reserved] sio [reserved] graphics direct rdram channel digital video out b (dvob) dvob_clk/dvob_clk dvob_d[11:0] dvob_hsync dvob_vsync dvob_blank# dvobc_clkint dvob_fld/stl sm_oclk sm_rclk vss sm_ref[b:a] gm_rclk [reserved] (reserved)
intel ? 830 chipset family 298338-003 datasheet 27 r figure 3. intel 830mg chipset interface block diagram display interface system memory (single data rate) sm_ma[12:0] sm_ba[1:0] sm_md[63:0] sm_ecc[7:0] sm_dqm[7:0] sm_cs[5:0]# sm_ras# sm_cas# sm_we# sm_cke[5:0] sm_rcomp vsync hsync red green blue refset red,green,blue# host interface ha[31:3]# hd[63:0]# ads# bnr# bpri# dbsy# defer# drdy# hit# hitm# hlock# hreq[4:0]# htrdy# rs[2:0]# cpurst# gtl_rcomp gtl_ref[b:a] ram_ref[b:a] agpref hlref vcca_hpll, vssa_hpll vcca_cpll, vssa_cpll vcca_dpll, vssa_dpll vcccmos vccq_agp vccqsm voltage refernce, pll power digital video out a (dvoa) dvoa_clk/dvoa_clk dvoa_hsync dvoa_vsync dvoa_blank# dvoa_rcomp dvoa_intr# dvoa_clkint dvoa_fld/stl hub interface hl[10:0] hlstrb, hlstrb# hl_rcomp ddc2_data ddc2_clk i2c_data i2c_clk ddc1_data ddc1_clk gpio sm_oclk sm_rclk vss sm_ref[b:a] dvob_clk/dvob_clk dvob_d[11:0] dvob_hsync dvob_vsync dvob_blank# dvobc_clkint dvob_fld/stl digital video outb (dvob) dvoc_clk/dvoc_clk dvoc_d[11:0] dvoc_hsync dvoc_vsync dvoc_blank# dvobc_intr# dvoc_fld/stl digital video outc (dvoc) mddc_data mddc_clk mi2c_data mi2c_clk gpio dq_a[7:0] [reserved] dq_b[7:0] [reserved] rq[7:0] [reserved] ctm, ctm# [reserved] cfm, cfm# [reserved] cmd [reserved] sck [reserved] sio [reserved] graphics direct rdram channel htclk, htclk# gbout gbin gm_gclk [reserved] drefclk reset# clocks and reset gm_rclk [reserved] # dvoa_d[11:0] (reserved)
intel ? 830 chipset family 28 datasheet 298338-003 r 2.1 terminology 82830mp graphics and memory controller hub (gmch-m) the intel 830mp graphics and memory controller hub-mobile component, which contains the cpu interface, system sdram controller and agp interface. it communicates with the ich3-m over a proprietary interconnect called the hub interface. 82830m graphics and memory controller hub (gmch-m) the intel 830m graphics and memory controller hub-mobile component which contains the cpu interface, system sdram controller, agp interface, and integrated graphics device (igd). it communicates with the ich3-m over a proprietary interconnect called the hub interface. 82830mg graphics and memory controller hub (gmch-m) the intel 830mg graphics and memory controller hub-mobile component which contains the cpu interface, system sdram controller, and integrated graphics device (igd). it communicates with the ich3-m over a proprietary interconnect called the hub interface. intel 830 chipset family intel 830 chipset family sku consists of the following 3 defined skus: 82830mp, 82830m, 82830mg and will be referred to as the intel 830 chipset family discrete agp graphics interface the intel 830m and 830mp graphics and memory controller hub-mobile (gmch-m) components which implements an external graphics solution (agp) will be referred to as intel 830m and 830mp discrete agp graphics interface internal graphics device pci device #2 of the intel 830m and 830mg graphics and memory controller hub-mobile (gmch-m) component which implements the intel graphics solution will be referred to as the intel graphics device 82801cam i/o controller hub (ich3-m) the ich3-m is connected to the gmch-m through a proprietary interconnect called the hub interface. this is the i/o controller hub or ich component that contains the primary pci interface, lpc interface, usb1.1, ata-100 and other io functions. hub interface the proprietary interconnect between the gmch-m and the ich3-m. in this document, hub interface cycles originating from or destined for the ich3-m are generally referred to as hub interface cycles. hub cycles originating from or destined for the primary pci interface on the ich3-m are sometimes referred to as hub interface/pci cycles. dvo port digital video out port. refers to the intel 830m and 830mg chipset?s digital display channels. the intel 830m chipset has one dedicated dvo and two dvos that are multiplexed with agp. the intel 830mg chipset has three dedicated dvo. agp accelerated graphics port. refers to the agp/pci interface that is in the intel 830mp and 830m chipset skus. it supports a 1.5v agp 4x component. pipe# and sba cycles are generally referred to as agp transactions. frame# cycles are generally referred to as agp/pci transactions. agp/pci1 the physical bus that is driven directly by the agp/pci1 bridge (device #1) in the 830mp and 830m skus. this is the primary agp bus. primary pci the primary physical pci (pci0) bus that is driven directly by the ich3-m component. it supports a 3.3v interface and is 5.0v tolerant, 33 mhz pci 2.2 compliant components. interaction between pci0 and gmch-m occurs over the hub interface. note that even though the primary pci bus is referred to as pci0 it is not pci bus #0 from a configuration standpoint. secondary pci the secondary physical pci (pci1) interface that is a subset of the agp bus driven directly by the gmch-m. it supports a subset of 1.5v, 66 mhz pci 2.2 compliant components. note that even though the secondary pci bus is referred to as pci1 it may not be configured as pci bus #1. direct agp integrated agp interface. uma unified memory architecture. graphics memory for the igd that is located in system memory igd integrated graphics device. the graphics device that is internal to the gmch-m dvmt direct video memory technology
intel ? 830 chipset family 298338-003 datasheet 29 r 2.2 intel 830 chipset family system architecture the intel 830 chipset family (consists of the three different skus: 82830m, 82830mp, 82830mg) is a highly integrated hub that provides the cpu interface to a mobile intel ? pentium ? iii processor-m / mobile intel celeron processor, the sdram system memory interface, a hub link interface to the 82801cam i/o controller hub ( ich3-m), and is optimized for mobile intel pentium iii processor-m /mobile intel celeron processor configurations at 133-mhz psb. 2.2.1 intel 830mp chipset the intel 830mp chipset supports mobile intel pentium iii processor-m / mobile intel celeron processors with an external agp 4x graphics solution. ? 1.25-v agtl host bus supporting 32-bit host addressing ? system sdram supports pc133 (lvttl) sdram ? supports up to 1.0 gb of system sdram ? agp interface with 1x/2x/4x sba/data transfer and 2x/4x fast write capability ? hub interface to ich3-m 2.2.2 intel 830m chipset the intel 830m chipset has integrated graphics capabilities as well as external agp support. its dedicated multimedia engines deliver high performance 3d, 2d, video, and display capabilities. the intel 830m chipset provides the flexibility of an external graphics solution with the agp port. ? 1.25-v agtl host bus supporting 32-bit host addressing ? system sdram supports pc133 (lvttl) sdram ? supports up to 1.0 gb of system sdram ? agp interface with 1x/2x/4x sba/data transfer and 2x/4x fast write capability ? hub interface to ich3-m ? integrated graphics capabilities, including 3d rendering acceleration and 2d hardware acceleration ? integrated 350-mhz ramdac ? a variety of display device protocols (tv, dvi, lvds) are supported through digital video out ports (one dedicated and two muxed with agp) connected to external devices 2.2.3 intel 830mg chipset the intel 830mg chipset has integrated graphics capabilities. its dedicated multimedia engines deliver high performance 3d, 2d, video, and display capabilities. 1.25-v agtl host bus supporting 32-bit host addressing: ? 1.25-v agtl host bus supporting 32-bit host addressing ? system sdram supports pc133 (lvttl) sdram ? supports up to 1.0 gb of system sdram ? hub interface to ich3-m
intel ? 830 chipset family 30 datasheet 298338-003 r ? integrated graphics capabilities, including 3d rendering acceleration and 2d hardware acceleration ? integrated 350-mhz ramdac ? a variety of display device protocols (tv, dvi, lvds) are supported through three digital video out ports (dvos) connected to external devices 2.3 intel 830 chipset family host interface 1 the intel 830 chipset family is optimized for the mobile intel pentium iii processor-m /mobile intel celeron processors. each member of the intel 830 chipset family supports a psb frequency of 133 mhz using 1.25-v agtl signaling. dual ended termination agtl is supported for single processor configurations. it supports 32-bit host addressing, decoding up to 4 gb of the cpu?s memory address space. host initiated i/o cycles are decoded to agp/pci1, hub interface, or gmch-m configuration space. host initiated memory cycles are decoded to agp/pci1, hub interface, or system sdram. all memory accesses from the host interface that hit the graphics aperture are translated using an agp address translation table. gmch-m accesses to graphics memory and agp/pci1 device accesses to non-cacheable system memory are not snooped on the host bus. memory accesses initiated from agp/pci1 using pci semantics and from hub interface to system sdram will be snooped on the host bus. note: discrete agp support is available only with the intel 830mp and 830m chipset. 2.4 intel 830 chipset family system memory interface the intel 830 chipset family integrates a system memory sdram controller with a 64-bit wide interface. the intel 830 chipset family supports single data rate (sdr) sdram for system memory. consequently, the gmch-m system memory buffers support lvttl signal interfaces. configured for sdram, the gmch-m memory interface includes support for the following: ? up to 1.0 gb of 133-mhz sdr sdram using 512-mb technology ? pc133 so-dimms ? maximum of two so-dimms, single-sided and/or double-sided ? the intel 830m chipset only supports four bank memory technologies. ? four integrated clock buffers 2.5 intel 830m / 830mp discrete agp interface gmch-m has the capability to support a single agp or pci-66 component using the intel 830m and 830mp agp interface via an agp 2.0 interface. high bandwidth access to data is provided through the system memory ports. gmch-m can access agp memory located in system memory with a peak bandwidth of 1.0 gb/s. actual agp throughput may vary depending on application running and system memory throttling mechanism applied. please consult section 5.7.11.2 for a discussion on throttling management. the 830m/830mp agp port supports a 1.5-v interface and is not 3.3-v safe. this mode is compliant with the agp 2.0 spec.
intel ? 830 chipset family 298338-003 datasheet 31 r the agp/pci1 interface supports up to 4x agp signaling and up to 4x fast writes. agp semantic cycles to system sdram are not snooped on the host bus. pci semantic cycles to system sdram are snooped on the host bus. the gmch-m supports pipe# or sba[7:0] agp address mechanisms, but not both simultaneously. either the pipe# or the sba[7:0] mechanism must be selected during system initialization. the gmch-m contains a 32-deep agp request queue. high priority accesses are supported. 2.6 intel 830m / 830mg internal graphics introduction the intel 830m and 830mg chipset igd provide a highly integrated graphics accelerator delivering high performance 3d, 2d, and video capabilities. the gmch-m contains an extensive set of instructions for 3d operations, blt and stretch blt operations, motion compensation, overlay, and display control. gmch-m supports a uma architecture using dvmt configuration. with its interfaces to analog display and flat panel display (through an accompanying lvds transmitter/scaler), the gmch-m provides a complete graphics solution. high bandwidth access to data is provided through the system memory ports. the gmch-m uses tiling architecture to increase memory efficiency and thus maximize effective rendering bandwidth. the gmch-m uses intel?s direct memory execution model to fetch textures from system memory at 1.0 gb/s. gmch-m includes a cache controller to avoid frequent memory fetches of recently used texture data. the gmch-m also provides 2d hardware acceleration for block transfers of data (blts). the blt engine provides the ability to copy a source block of data to a destination and perform raster operations (e.g., rop1, rop2, and rop3) on the data using a pattern, and/or another destination. performing these common tasks in hardware reduces cpu load, and thus improves performance. 2.7 intel 830m / 830mg internal graphics display interface the intel 830m and 830mg igd sku have four display ports, one analog and three digital. this provides support for a progressive scan analog monitor, a dedicated dvo port (dvoa) and dual dvo ports. each port can transmit data according to one or more protocols. the dvo ports are connected to an external device that converts one protocol to another. examples of this are tv encoders, external dacs, lvds transmitters, and tmds transmitters. each display port has control signals that may be used to control, configure and/or determine the capabilities of an external device. the data that is sent out the display port is selected from one of the two possible sources; pipe a or pipe b. 2.7.1 intel 830m and 830mg analog display port the intel 830m and 830mg chipset has an integrated 350-mhz ramdac that can directly drive a progressive scan analog monitor up to a resolution of 1800 x 1440 pixels. 2.7.2 intel 830m and 830mg dvo interfaces the intel 830m and 830mg chipset provides digital display channels that are capable of driving a 165- mhz pixel clock. gmch-m is compliant with dvi specification 1.0. when combined with a dvi compliant external device and connector, the intel 830m and 830mg chipset has a high-speed interface to a digital display (e.g. flat panel or digital crt).
intel ? 830 chipset family 32 datasheet 298338-003 r 2.7.2.1 intel 830m and 830mg dedicated dvoa interface the intel 830m and 830mg supports dvo devices that can drive pixel clocks up to 165 mhz. the dedicated dvoa interface can support a variety of tv-out and tmds transmitters. 2.7.2.2 intel 830m and 830mg dvob and dvoc interfaces the intel 830mg chipset has dedicated interfaces (dvob and dvoc). each interface is capable to drive pixel clocks up to 165 mhz. the dvo interface can support a variety of tv-out and tmds transmitters. the dvob and dvoc interfaces may be used independently or combined to support higher resolutions and refresh rates. similar to the intel 830mg chipset, the intel 830m chipset can use dvob and dvoc interfaces independently or combined for higher resolutions and refresh rates. furthermore, the intel 830m chipset supports a discrete agp graphics device by multiplexing an agp interface with the dvob and dvoc interfaces.
intel ? 830 chipset family 298338-003 datasheet 33 r 3 signal description this section provides a detailed description of the intel 830 chipset family gmch-m signals. the signals are arranged in functional groups according to their associated interface. the ?#? symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. when ?#? is not present after the signal name the signal is asserted when at the high voltage level. when not otherwise specified, ?set? refers to changing a bit to its asserted state (a logical 1). clear refers to changing a bit to its negated state (a logical 0). the following notations are used to describe the signal type: the following notations are used to describe the signal type: i input pin o output pin i/o bi-directional input/output pin s/t/s sustained tristate. this pin is driven to its inactive state prior to tri-stating. as/t/s active sustained tristate. this applies to some of the hub interface signals. this pin is weekly driven to its last driven value. the signal description also includes the type of buffer used for the particular signal: agtl open drain 1.25-v agtl interface signal. refer to the agtl i/o specification for complete details. agtl signals are ?inverted bus? style where a low voltage represents a logical ?1?. agp/1.5v signals used for agp or 1.5v interfaces. agp signals are compatible with agp 2.0 1.5-v signaling environment dc and ac specifications. the buffers are not 3.3-v tolerant. lvttl low voltage ttl compatible signals. these are also 3.3-v outputs. cmos cmos buffers. note that cpu address and data bus signals are logically inverted signals. in other words, the actual values are inverted of what appears on the cpu bus. this must be taken into account and the addresses and data bus signals must be inverted inside the gmch-m. all cpu control signals follow normal convention. a 0 indicates an active level (low voltage) if the signal is followed by # symbol and a 1 indicates an active level (high voltage) if the signal has no # suffix. table 1 shows the vtt/vdd and vref levels for the various interfaces.
intel ? 830 chipset family 34 datasheet 298338-003 r table 1. signal voltage levels interface vtt/vdd (nominal) vref agtl 1.25 v 2/3 * vtt 1.5 v/agp 1.5 v 0.5 * vdd lvttl 3.3 v vddq * 0.5 rsl [reserved] 1.8 v 1.4 v hub interface 1.8 v 0.5 * vdd
intel ? 830 chipset family 298338-003 datasheet 35 r 3.1 common signals for the intel 830 chipset family this section describes the common signals that apply to the entire intel 830 chipset family. the intel 830 chipset family common signals consist of: host interface signals, system memory signals, hub interface signals, and clock and reset signals. 3.1.1 host interface signals table 2. host interface signal descriptions signal name type description cpurst# o agtl cpu reset . the cpurst# pin is an output from the gmch-m. the gmch-m asserts cpurst# while reset# (pcirst# from ich3-m) is asserted and for approximately 1 ms after reset# is deasserted. the cpurst# allows the cpus to begin execution in a known state. note that the ich3-m must provide cpu strap set-up and hold times around cpurst#. this requires strict synchronization between gmch-m cpurst# deassertion and ich3-m driving the straps. ha[31:3]# i/o agtl host address bus : ha[31:3]# connect to the cpu address bus. during cpu cycles the ha[31:3]# are inputs. the gmch-m drives ha[31:3]# during snoop cycles on behalf of hub interface and agp/secondary pci initiators. note that the address bus is inverted on the cpu bus. hd[63:0]# i/o agtl host data : these signals are connected to the cpu data bus. note that the data signals are inverted on the cpu bus. ads# i/o agtl address strobe : the cpu bus owner asserts ads# to indicate the first of two cycles of a request phase. bnr# i/o agtl block next request : used to block the current request bus owner from issuing a new request. this signal is used to dynamically control the cpu bus pipeline depth. bpri# o agtl priority agent bus request : the gmch-m is the only priority agent on the cpu bus. it asserts this signal to obtain the ownership of the address bus. this signal has priority over symmetric bus requests and will cause the current symmetric owner to stop issuing new transactions unless the hlock# signal was asserted. dbsy# i/o agtl data bus busy : used by the data bus owner to hold the data bus for transfers requiring more than one cycle. defer# o agtl defer : gmch-m will generate a deferred response as defined by the rules of the gmch-m?s dynamic defer policy. the gmch-m will also use the defer# signal to indicate a cpu retry response. drdy# i/o agtl data ready : asserted for each cycle that data is transferred. hit# i/o agtl hit : indicates that a caching agent holds an unmodified version of the requested line. also, driven in conjunction with hitm# by the target to extend the snoop window. hitm# i/o agtl hit modified : indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line. also, driven in conjunction with hit# to extend the snoop window. hlock# i agtl host lock : all cpu bus cycles sampled with the assertion of hlock# and ads#, until the negation of hlock# must be atomic, i.e. no hub interface or agp/pci snoopable access to sdram is allowed when hlock# is asserted by the cpu.
intel ? 830 chipset family 36 datasheet 298338-003 r hreq[4:0]# i/o agtl host request command : asserted during both clocks of request phase. in the first clock, the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. in the second clock, the signals carry additional information to define the complete transaction type. the transactions supported by the gmch-m host bridge are defined in the host interface section of this document. htrdy# i/o agtl host target ready : indicates that the target of the cpu transaction is able to enter the data transfer phase. rs[2:0]# i/o agtl response signals : indicates type of response according to the following table: rs[2:0] response type 000 idle state 001 retry response 010 deferred response 011 reserved (not driven by gmch-m) 100 hard failure (not driven by gmch-m) 101 no data response 110 implicit writeback 111 normal data response gtl_rcomp i/o gtl compensation : used to calibrate the gtl interface buffers to match the board. this pin should be connected to an 80- ? simple resistor to ground. total pins for this section: 113.
intel ? 830 chipset family 298338-003 datasheet 37 r 3.1.2 system memory interface table 3. system memory interface signal descriptions signal name type description sm_ma[12:0] o lvttl memory address : sm_ma[12:0] are used to provide the multiplexed row and column address to sdram. sm_ba[1:0] o lvttl memory bank address : these signals define the banks that are selected within each sdram row. the sm_ma and sm_ba signals combine to address every possible location within a sdram device. sm_md[63:0] i/o lvttl memory data : these signals are used to interface to the sdram data bus. sm_dqm[7:0] o lvttl input/output data mask : these pins act as synchronized output enables during read cycles and as byte enables during write cycles. sm_cs[3:0]# o lvttl chip select : for the memory rows configured with sdram, these pins perform the function of selecting the particular sdram components during the active state. note: there is one sm_cs per sdram row. these signals can be toggled on every rising system memory clock edge. sm_ras# o lvttl sdram row address strobe : a table of the sdram commands supported by the intel 830 chipset family is given in the sdram section. sm_ras# may be heavily loaded and requires 2 sdram clock cycles for setup time to the sdrams. sm_cas# o lvttl sdram column address strobe : a table of the sdram commands supported by the intel 830 chipset family is given in the sdram section. sm_cas# may be heavily loaded and requires 2 sdram clock cycles for setup time to the sdrams. sm_we# o lvttl write enable signal : sm_we# is asserted during writes to sdram. refer to truth table of the sdram commands supported by the intel 830 chipset family, given in the sdram section. sm_we# may be heavily loaded and requires 2 sdram clock cycles for setup time to the sdrams. sm_cke[3:0] o lvttl clock enable : these signals are used to signal a self-refresh or power down command to a sdram array when entering system suspend. sm_cke is also used to dynamically power down inactive sdram rows. there is one sm_cke per sdram row. these signals can be toggled on every rising sm_clk clock edge. sm_oclk o lvttl system memory output clock : this signal delivers a synchronized clock to the sm_rclk pin. sm_rclk i lvttl system memory return clock : this signal receives the synchronized clock from sm_oclk. sm_clk [3:0] o lvttl system memory clock : these signals deliver a synchronized clock to the sdrams. sm_rcomp i/o system memory rcomp : used to calibrate the system memory i/o buffers. this pin should be connected to a 27.5- ? resistor tied to vss. total pins for system memory section: 105.
intel ? 830 chipset family 38 datasheet 298338-003 r 3.1.3 hub interface signals table 4. hub interface signal descriptions signal name type description hl[10:0] i/o (as/t/s) cmos hl[10:0] hub interface signals. signals used for the hub interface. hlstrb; hlstrb# i/o (as/t/s) cmos hlstrb; hlstrb# hub interface strobe/complement. the two differential strobe signals used to transmit or receive packet data. hl_rcomp i/o hl_rcomp hub interface compensation: used to calibrate the hub i/o buffers. this signal has an external 55-ohm pull-down resistor. total pins for this section: 14. 3.1.4 clocking and reset table 5. clocking and reset signal descriptions signal name type description htclk; htclk# i cmos host clock in : these pins receive a buffered host clock from the external clock synthesizer. this clock is used by all of the gmch-m. the clock is also the reference clock for the graphics core pll. this is a low voltage differential input. gbout o lvttl agp/hub clock reference output : this clock goes to the external agp/hub/pci buffer. gbin i lvttl agp/hub input clock : 66 mhz, 3.3-v input clock from external buffer agp/hub-link interface. gm_gclk; gm_rclk o cmos graphics memory clock out: (reserved) these signals should leave as nc (?not connected?). dclkref i lvttl display clock input: this pins provides a 48-mhz input clock to the display pll that is used for 2d/video/flat panel and dac. the signal needs pull down if ext graphics solution is implemented. reset# i lvttl reset in : when asserted, this signal will asynchronously reset the gmch-m logic. this signal is connected to the pcirst# output of the ich3-m. the ich3-m drives this to 3.3 v. all agp/pci output and bi-directional signals will also tri-state compliant to pci rev 2.2 specifications. this input should have a schmidt trigger to avoid spurious resets. note that this input needs to be 3.3-v tolerant. total pins for clocks/resets section: 8.
intel ? 830 chipset family 298338-003 datasheet 39 r 3.1.5 reserved signals table 6. intel reserved signals signal name type description dq_a[7:0] intel reserved. should be left nc (?not connected?) dq_b[7:0] intel reserved. should be left nc (?not connected?) rq[7:0] intel reserved. should be left nc (?not connected?) ctm;ctm# intel reserved . requires pull down. cfm;cfm# intel reserved. should be left nc (?not connected?) cmd intel reserved. should be left nc (?not connected?) sck intel reserved. should be left nc (?not connected?) sio intel reserved. should be left nc (?not connected?) total reserved pins: 31.
intel ? 830 chipset family 40 datasheet 298338-003 r 3.2 common signals for 830m and 830mp chipset discrete agp graphics implementation the intel 830m and 830mp chipset support an external agp graphics solution. the following signals apply only when an external agp graphics solution is implemented. please consult section 3.3 for internal graphics implementation with the intel 830m and 830mg chipset. for signal multiplexing information between agp and dvo/display signals, please refer to sections 3.3.3.1and 3.3.5.2. please see intel ? 830 chipset family design guide for design recommendations required for pins where no functionality is defined for the chosen sku. 3.2.1 agp addressing signals table 7. agp addressing signal descriptions signal name type description pipe# i agp pipelined read : this signal is asserted by the current master to indicate a full width address is to be queued by the target. the master queues one request each rising clock edge while pipe# is asserted. when pipe# is deasserted no new requests are queued across the ad bus. pipe# is a sustained tri-state signal from the master (graphics controller) and is an input to the gmch-m. sba[7:0] i agp sideband address : this bus provides an additional bus to pass address and command to the gmch-m from the agp master. the above table contains two mechanisms to queue requests by the agp master. note that the master can only use one mechanism. when pipe# is used to queue addresses, the master is not allowed to queue addresses using the sba bus. for example, during configuration time, if the master indicates that it can use either mechanism, the configuration software will indicate which mechanism the master will use. once this choice has been made, the master will continue to use the mechanism selected until the master is reset (and reprogrammed) to use the other mode. this change of modes is not a dynamic mechanism but rather a static decision when the device is first being configured after reset.
intel ? 830 chipset family 298338-003 datasheet 41 r 3.2.2 agp flow control signals table 8. agp flow control signal descriptions signal name type description rbf# i agp read buffer full : indicates if the master is ready to accept previously requested low priority read data. when rbf# is asserted, the gmch-m is not allowed to return low priority read data to the agp master on the first block. rbf# is only sampled at the beginning of a cycle. if the agp master is always ready to accept return read data, it is not required to implement this signal. wbf# i agp write buffer full : indicates if the master is ready to accept fast write data from the gmch-m. when wbf# is asserted, the gmch-m is not allowed to drive fast write data to the agp master. wbf# is only sampled at the beginning of a cycle. if the agp master is always ready to accept fast write data, it is not required to implement this signal. 3.2.3 agp status signals table 9. agp status signal descriptions signal name type description st[2:0] o agp status : provides information from the arbiter to the agp master on what it may do. st[2:0] only have meaning to the master when its gnt# is asserted. when gnt# is deasserted these signals have no meaning and must be ignored. 000 indicates that previously requested low priority read data is being returned. 001 indicates that previously requested high priority read data is being returned. 010 indicates that the master is to provide low priority write data for a previously queued write command. 011 indicates that the master is to provide high priority write data for a previously queued write command. 100 reserved 101 reserved 110 reserved 111 indicates that the master has been given permission to start a bus transaction. the master may queue agp requests by asserting pipe# or start a pci transaction by asserting frame#. st[2:0] are always an output from the gmch-m and an input to the master. agp_rcomp i/o agp rcomp : used to calibrate agp i/o buffers for 830m and 830mp discrete agp interface please refer to the intel ? 830 chipset family design guide for pull down resistor value.
intel ? 830 chipset family 42 datasheet 298338-003 r 3.2.4 agp clocking signals ? strobes table 10. agp clock signal-strobe descriptions signal name type description ad_stb0 i/o (s/t/s) agp ad bus strobe-0 : provides timing for 2x and 4x clocked data on ad[15:0] and c/be[1:0]#. the agent that is providing data drives this signal. ad_stb0# i/o (s/t/s) agp ad bus strobe-0 complement : the differential complement to the ad_stb0 signal. it is used to provide timing for 4x clocked data. ad_stb1 i/o (s/t/s) agp ad bus strobe-1 : provides timing for 2x and 4x clocked data on ad[31:16] and c/be[3:2]#. the agent that is providing data drives this signal. ad_stb1# i/o (s/t/s) agp ad bus strobe-1 complement : the differential complement to the ad_stb1 signal. it is used to provide timing for 4x clocked data. sb_stb i agp sideband strobe : provides timing for 2x and 4x clocked data on the sba[7:0] bus. the agp master drives it after the system has been configured for 2x or 4x clocked sideband address delivery. sb_stb# i agp sideband strobe complement : the differential complement to the sb_stb signal. it is used to provide timing for 4x clocked data.
intel ? 830 chipset family 298338-003 datasheet 43 r 3.2.5 pci signals - agp semantics pci signals are redefined when used in agp transactions that are carried using agp protocol extension. for transactions on the agp interface that are carried using pci protocol, these signals completely preserve pci 2.2 semantics. the exact roles of all pci signals during agp transactions are defined below. table 11. pci signals ? agp semantics signal descriptions signal name type description g_frame# i/o s/t/s agp not used during an agp pipelined transaction. g_frame# is an output from the gmch-m during fast writes. g_irdy# i/o s/t/s agp g_irdy# indicates the agp compliant master is ready to provide all write data for the current transaction. once irdy# is asserted for a write operation, the master is not allowed to insert wait states. the assertion of irdy# for reads indicates that the master is ready to transfer to a subsequent block (32 bytes) of read data. the master is never allowed to insert a wait state during the initial data transfer (32 bytes) of a read transaction. however, it may insert wait states after each 32-byte block is transferred. (there is no g_frame# -- g_irdy# relationship for agp transactions.) for fast write transactions, g_irdy# is driven by the gmch-m to indicate when the write data is valid on the bus. the gmch-m deasserts this signal to insert wait states on block boundaries. g_trdy# i/o s/t/s agp g_trdy# indicates the agp compliant target is ready to provide read data for the entire transaction (when the transfer size is less than or equal to 32 bytes) or is ready to transfer the initial or subsequent block (32 bytes) of data when the transfer size is greater than 32 bytes. the target is allowed to insert wait states after each block (32 bytes) is transferred on both read and write transactions. for fast write transactions, the agp master uses this signal to indicate when it is willing to transfer a subsequent block. g_stop# i/o s/t/s agp g_stop# not used during an agp transaction. for fast write transactions g_stop# is used to signal disconnect or target abort terminations. g_devsel# i/o s/t/s agp g_devsel# not used during an agp transaction. for fast write transactions, it is used when the transaction cannot complete during the block. g_req# i agp g_req# used to request access to the bus to initiate a pci or agp request. g_gnt# o agp g_gnt# same meaning as pci but additional information is provided on st[2:0]. the additional information indicates that the selected master ? is the recipient of previously requested read data (high or normal priority) ? is to provide write data (high or normal priority), for a previously queued write command or ? has been given permission to start a bus transaction (agp or pci). g_ad[31:0] i/o g_ad[31:0] same as pci.
intel ? 830 chipset family 44 datasheet 298338-003 r agp g_c/be[3:0]# i/o agp g_c/be[3:0]# slightly different meaning. ? provides command information (different commands than pci) when requests are being queued when using pipe#. ? provide valid byte information during agp write transactions and are not used during the return of read data. g_par i/o agp g_par same as pci. not used on agp transactions but used during pci transactions as defined by the pci specification. notes: 1. pcirst# from the ich3-m is connected to reset# and is used to reset agp interface logic within the gmch- m. the agp agent will also use pcirst# provided by the as an input to reset its internal logic. 2. lock# signal is not supported on the agp interface (even for pci operations). 3. the serr# and perr# signals are not supported on the agp interface. total pins for agp section: 66. 3.2.6 pci pins during pci transactions on agp interface pci signals described in a previous table behave according to pci 2.2 specifications when used to perform pci transactions on the agp interface.
intel ? 830 chipset family 298338-003 datasheet 45 r 3.3 common signals for 830m and 830mg chipset internal graphics implementation an internal graphics device is available with the intel 830m and 830mg chipset. the following signals apply when the internal graphics device is chosen. the internal graphics device has support for dedicated digital video port (dvoa), dual dvob and dvoc ports, and analog display. please consult section 3.2 for discrete agp implementation with 830m or 830mp chipset. also see sections 3.3.3.1 and 3.3.5.2 for signal mapping information between discrete agp and dvo/display signals for the 830m sku. please refer to the intel ? 830 chipset family design guide regarding design recommendations for pins where no functionality is defined for the chosen sku. table 12. internal graphics status signal descriptions signal name type description agp_busy# od agp_busy#: output of the intel 830m or 830mg gmch-m graphics controller to the ich3-m, which indicates that certain internal graphics (igd) activity is taking place. assertion indicates to the acpi software to not enter the c3 state. assertion also causes a c3 exit if c3 was being entered, or was already entered when agp_busy# went active. agp_busy# will be inactive when the graphics controller is in any acpi state other than d0. agp_busy# must be pulled up to a voltage rail which turned off in the acpi s3-s5 stages. .
intel ? 830 chipset family 46 datasheet 298338-003 r 3.3.1 dedicated digital video port (dvoa) table 13. dedicated digital video port (dvoa) signal descriptions name type description dvoa_clk; dvoa_clk# o 1.5 v dvo clock output : these pins provide a differential pair reference clock that can run up to 165 mhz. dvoa_clk (dvoclkout0) (aj24) corresponds to the primary clock out. dvoa_clk# (dvoclkout1) (ag24) corresponds to the primary clock out. dvoa_clk and dvoa_clk# need to be pulled up if: i) the signals are not used when using internal graphics device, or ii) discrete agp device is implemented. dvoa_d[11:0] o 1.5 v dvo data : this data bus is used to drive 12-bit rgb data on each edge of dvoa_clkout. this provides 24-bits of data per clock. dvoa_d[11:0] should be left as nc (not connected) if: i) the signals are not used when using internal graphics device, or ii) discrete agp device is implemented. dvoa_hsync o 1.5 v horizontal sync : hsync signal for the dvo interface. the active polarity of the signal is programmable. dvoa_hysnc should be left as nc (not connected) if: i) the signal is not used when using internal graphics device, or ii) discrete agp device is implemented. dvoa_vsync o 1.5v vertical sync : vsync signal for the dvo interface. the active polarity of the signal is programmable. dvoa_vsync should be left as nc (not connected) if: i) the signal is not used when using internal graphics device, or ii) discrete agp device is implemented. dvoa_blank# o 1.5 v flicker blank or border period indication : dvoa_blank# is a programmable output pin driven by the gmch-m. when programmed as a blank period indication, this pin indicates active pixels excluding the border. when programmed as a border period indication, this pin indicates active pixel including the border pixels. dvoa_blank# should be left as nc (not connected) if: i) the signal is not used when using internal graphics device, or ii) discrete agp device is implemented. dvoa_rcomp i/o dvo compensation : used to calibrate the dvoa i/o buffers. this signal needs to be pulled down to ground through an external resistor (resistance is based on board impedance). dvoa_intr# i 1.5 v dvo interrupt : this pin is used to signal an interrupt, typically used to indicate a hot plug or unplug of a digital display. dvoa_intr# needs to be pulled up if: i) the signal is not used when using internal graphics device, or ii) discrete agp device is implemented. dvoa_clkint i 1.5 v dvo pixel clock input/interrupt input pin can be programmed to be either a reference input to a dot clock pll (dpll) or to be a second interrupt input. dvo pixel clock input : when used as a pixel clock input, this signal may be selected as a reference input for an external tv encoder.
intel ? 830 chipset family 298338-003 datasheet 47 r dvo interrupt: when used as an interrupt input, the signal is internally anded with the dvoa_intr# signal inside the gmch-m. dvoa_clkint needs to be pulled up if: i) the signal is not used when using internal graphics device, or ii) discrete agp device is implemented. dvoa_fld/stl i 1.5 v dvoa_fld/stl input pin can be programmed to be either a tv field input from the tv encoder or stall input from the flat panel. dvoa tv field stall signal . when used as a field input, it synchronizes the overlay field with the tv encoder field when the overlay is displaying an interleaved source. dvoa flat panel stall signal . when used as the stall input, it indicates that the pixel pipeline should stall one horizontal line. the signal changes during horizontal blanking. this is used by the panel fitting logic when expanding the image vertically. dvoa_fld/stl needs to be pulled down if: i) the signal is not used when using internal graphics device, or ii) discrete agp device is implemented. total pins for dvoa section: 21.
intel ? 830 chipset family 48 datasheet 298338-003 r 3.3.2 multiplexed digital video port b (dvob) table 14. multiplexed dvob (dvob) signal descriptions name type description dvob_clk; dvob_clk# o agp dvo clock output : these pins provide a differential pair reference clock that can run up to 165 mhz. dvob_clk (dvoclkout0) corresponds to the primary clock out. dvob_clk# (dvoclkout1) corresponds to the primary clock out. dvob_clk and dvob_clk# should be left as nc (?not connected?) if the signals are not used when using internal graphics device. dvob_d[11:0] o agp dvo data : this data bus is used to drive 12-bit rgb data on each edge of dvob_clkout. this provides 24-bits of data per clock. dvob_d[11:0] should be left as left as nc (?not connected?) if the signal are not used when using internal graphics device. dvob_hsync o agp horizontal sync : hsync signal for the dvo interface. the active polarity of the signal is programmable. dvob_hsync should be left as left as nc (?not connected?) if the signal is not used when using internal graphics device. dvob_vsync o agp vertical sync : vsync signal for the dvo interface. the active polarity of the signal is programmable. dvob_vsync should be left as left as nc (?not connected?) if the signal is not used when using internal graphics device. dvob_blank# o agp flicker blank or border period indication : dvob_blnk# is a programmable output pin driven by the gmch-m. when programmed as a blank period indication, this pin indicates active pixels excluding the border. when programmed as a border period indication, this pin indicates active pixel including the border pixels. dvob_blank# should be left as left as nc (?not connected?) if the signal is not used when using internal graphics device. dvobc_clkint i agp dvobc pixel clock input/interrupt: this signal may be selected as the reference input to either dot clock pll (dpll) or may be configured as an interrupt input. dvobc pixel clock input : when selected as the dot clock pll (dpll) reference input, this clock reference input supports ssc clocking for dvo lvds devices. dvobc interrupt : when configured as an interrupt input, this interrupt can support for either of the dvob or dvoc. dvobc_clkint needs to be pulled up if the signal is not used when using internal graphics device. dvob_fld/stl i agp tv field and flat panel stall signal . this input can be programmed to either be a tv field input from the tv encoder or stall input from the flat panel. dvob tv field signal : when used as a field input, it synchronizes the overlay field with the tv encoder field when the overlay is displaying an interleaved source. dvob flat panel stall signal: when used as the stall input, it indicates that the pixel pipeline should stall one horizontal line. the signal changes during horizontal blanking. this is used by the panel fitting logic when expanding the image vertically.
intel ? 830 chipset family 298338-003 datasheet 49 r dvob_fld/stl needs to be pulled down if the signal is not used when using internal graphics device. total multiplexed pins for dvob (and dvoc) section: 19.
intel ? 830 chipset family 50 datasheet 298338-003 r 3.3.3 multiplexed digital video port (dvoc) table 15. multiplexed digital video port c (dvoc) signal descriptions name type description dvoc_clk; dvoc_clk# o agp dvo clock output : these pins provide a differential pair reference clock that can run up to 165 mhz. dvoc_clk (dvoclkout0) corresponds to the primary clock out. dvoc_clk# (dvoclkout1) corresponds to the primary clock out. dvoc_clk and dvoc_clk# should be left as nc (?not connected?) if the signal are not used when using internal graphics device. dvoc_d[11:0] o agp dvo data : this data bus is used to drive 12-bit rgb data on each edge of dvoc_clkout. this provides 24-bits of data per clock. dvoc_d[11:0] should be left as nc (?not connected?) if the signals are not used when using internal graphics device. dvoc_hsync o agp horizontal sync : hsync signal for the dvo interface. the active polarity of the signal is programmable. dvoc_hsync should be left as nc (?not connected?) if the signal is not used when using internal graphics device. dvoc_vsync o agp vertical sync : vsync signal for the dvo interface. the active polarity of the signal is programmable. dvoc_vsync should be left as nc (?not connected?) if the signal is not used when using internal graphics device. dvoc_blank# o agp flicker blank or border period indication : dvoc_blnk# is a programmable output pin driven by the gmch-m . when programmed as a blank period indication, this pin indicates active pixels excluding the border. when programmed as a border period indication, this pin indicates active pixel including the border pixels. dvoc_blank# should be left as nc (?not connected?) if the signal is not used when using internal graphics device. dvobc_intr#/ dpms_clk i agp dvobc interrupt : this pin is used to signal an interrupt, typically used to indicate a hot plug or unplug of a digital display. dmps_clk : when internal graphics is used, this signal is needed to provide the necessary clock source for d1/s1 state support. dvoc_fld/stl i agp tv field and flat panel stall signal . this input can be programmed to either be a tv field input from the tv encoder or stall input from the flat panel. dvoc tv field signal: when used as a field input, it synchronizes the overlay field with the tv encoder field when the overlay is displaying an interleaved source. dvoc flat panel stall signal : when used as the stall input, it indicates that the pixel pipeline should stall one horizontal line. dvoc_fld/stl needs to be pulled down if the signal is not used when using internal graphics device. total multiplexed pins for dvob (and dvoc) section: 19.
intel ? 830 chipset family 298338-003 datasheet 51 r 3.3.3.1 dvobc to agp pin mapping table 16. multiplexed dvobc to agp pin mapping information dvo signal name agp signal name dvo signal name agp signal name dvob_d0 ad3 dvoc_d0 ad19 dvob_d1 ad2 dvoc_d1 ad20 dvob_d2 ad5 dvoc_d2 ad21 dvob_d3 ad4 dvoc_d3 ad22 dvob_d4 ad7 dvoc_d4 ad23 dvob_d5 ad6 dvoc_d5 cbe3# dvob_d6 ad8 dvoc_d6 ad25 dvob_d7 cbe0# dvoc_d7 ad24 dvob_d8 ad10 dvoc_d8 ad27 dvob_d9 ad9 dvoc_d9 ad26 dvob_d10 ad12 dvoc_d10 ad29 dvob_d11 ad11 dvoc_d11 ad28 dvob_clk adstb0 dvoc_clk adstb1 dvob_clk# adstb0# dvoc_clk# adstb1# dvob_hsync ad0 dvoc_hsync ad17 dvob_vsync ad1 dvoc_vsync ad16 dvob_blank# cbe1# dvoc_blank# ad18 dvobc_clkint# ad13 dvobc_intr#/dpms_clk ad30 dvob_fld/stl ad14 dvoc_fld/stl ad31 dvobc_rcomp agp_rcomp 3.3.3.2 dvo miscellaneous signals signal name type description dvobc_rcomp i/o dvobc rcomp: used to calibrate dvobc i/o buffer 830m and 830mg internal graphics device. please refer to the intel 830 chipset family design guide for pull down resistor value. dvo_detect i/o agp dvo_detect used for strapping option for the muxed dvo interface. please see design guide for requirement.
intel ? 830 chipset family 52 datasheet 298338-003 r 3.3.4 analog display table 17. analog display signal descriptions pin name type description vsync o lvttl crt vertical synchronization : this signal is used as the vertical sync (polarity is programmable) or "vsync interval". vsync should be left as nc (?not connected?) if discrete agp device is implemented. hsync o lvttl crt horizontal synchronization : this signal is used as the horizontal sync (polarity is programmable). hsync should be left as nc (?not connected?) if discrete agp device is implemented. red o analog red (analog video output) : this signal is a crt analog video output from the internal color palette dac. the dac is designed for a 37.5 w equivalent load on each pin (e.g., 75-w resistor on the board, in parallel with the 75-w crt load). red can be left as nc (?not connected?) if discrete agp device is implemented. green o analog green (analog video output) : this signal is a crt analog video output from the internal color palette dac. the dac is designed for a 37.5 w equivalent load on each pin (e.g., 75-w resistor on the board, in parallel with the 75-w crt load). green can be left as nc (?not connected?) if discrete agp device is implemented. blue o analog blue (analog video output) : this signal is a crt analog video output from the internal color palette dac. the dac is designed for a 37.5 w equivalent load on each pin (e.g., 75-w resistor on the board, in parallel with the 75-w crt load). blue can be left as nc (?not connected?) if discrete agp device is implemented. refset i na resistor set : set point resistor for the internal color palette dac. a 255-w 1% resistor is required between refset and vssa. reset can be left as nc (?not connected?) if discrete agp device is implemented. red# o analog red#(analog output) : this signal is an analog video output from the internal color palette dac connected to a 37.5-ohm resistor to ground. this is used to provide noise immunity. please refer to the intel ? 830 chipset family design guide. red# can be left as nc (?not connected?) if discrete agp device is implemented. green# o analog green# (analog output): this signal is an analog video output from the internal color palette dac connected to a 37.5-ohm resistor to ground this is used to provide noise immunity. please refer to the intel ? 830 chipset family design guide . green# can be left as nc (?not connected?) if discrete agp device is implemented. blue# o analog blue# (analog output) : this signal is an analog video output from the internal color palette dac connected to a 37.5 ohm resistor to ground. this is used to provide noise immunity. please refer to the intel ? 830 chipset family design guide. blue# can be left as nc (?not connected?) if discrete agp device is implemented. total pins for display section: 9.
intel ? 830 chipset family 298338-003 datasheet 53 r 3.3.5 display control signals table 18. display control signal descriptions pin name type description ddc1_clk i/o lvttl ddc1_clk: the specific function is ddc_clk for crt/analog display. this signal is tri-stated during a hard reset. ddc1_clk needs to be pulled up if: i) the signal is not used when using internal graphics device, or ii) discrete agp device is implemented. ddc1_data i/o lvttl ddc1_data: the specific function is ddc_data for crt/analog display. this signal is tri-stated during a hard reset. ddc1_data needs to be pulled up if: i) the signal is not used when using internal graphics device, or ii) discrete agp device is implemented. i2c_clk i/o lvttl i2c_clk : the specific function is i2c clk. this signal can be used as gmbus bus for dvoa/b/c device. this signal is tri-stated during a hard reset. i2c_clk needs to be pulled up if: i) the signal is not used when using internal graphics device, or ii) discrete agp device is implemented. i2c_data i/o lvttl i2c_data : the specific function is i2c_data. this signal can be used as gmbus bus for dvoa/b/c device. this signal is tri-stated during a hard reset. i2c_data needs to pull up if: i) the signal is not used when using internal graphics device, or ii) discrete agp device is implemented. ddc2_clk i/o lvttl ddc2_clk : the specific function is ddc_clk for digital display, edid info or as gmbus bus for dvoa/b/c device. this signal is tri-stated during a hard reset. ddc2_clk needs to be pull up if: i) the signal is not used when using internal graphics device, or ii) discrete agp device is implemented. ddc2_data i/o lvttl ddc2_data : the specific function is ddc_data for digital display, edid info or as gmbus bus for dvoa/b/c device. this signal is tri-stated during a hard reset. ddc2_data needs to be pull up if: i) the signal is not used when using internal graphics device, or ii) discrete agp device is implemented. total pins for this section: 6.
intel ? 830 chipset family 54 datasheet 298338-003 r 3.3.5.1 dvo display control signals table 19. dvo display control signals descriptions pin name type description m_i2c_clk i/o 1.5 v m_i2c_clk : the specific function is i2c_clk for the muxed dvos. m_i2c_clk needs to be pulled up if: i) the signal is not used when using internal graphics device. m_i2c_data 1.5 v m_i2c_data : the specific function is i2c_data for the muxed dvos. m_i2c_data needs to be pulled up if: i) the signal is not used when using internal graphics device. m_ddc1_clk 1.5 v m_ddc1_clk : the specific function is ddc1_clk for the muxed dvos. m_ddc1_clk needs to be pulled up if: i) the signal is not used when using internal graphics device. m_ddc1_data 1.5 v m_ddc1_data : the specific function is ddc1_data for the muxed dvos. m_ddc1_data needs to be pulled up if: i) the signal is not used when using internal graphics device. total multiplexed pins for this section: 4. 3.3.5.2 display control signals to agp pin mapping table 20. display signals to agp pin mapping signal descriptions gpio signal name agp signal name gpio signal name agp signal name m_i2c_clk irdy# m_ddc1_clk g_trdy# m_i2c_data devsel# m_ddc1_data g_frame#
intel ? 830 chipset family 298338-003 datasheet 55 r 3.4 intel 830 chipset family voltage references, pll power table 21. voltage references, pll power signal descriptions signal name number description gtl_ref[b:a] 2 gtl reference : reference voltage input for the host agtl interface. gtlref is 2/3 * vtt. vtt is nominally 1.25 v. vtt 9 host voltage : vtt is nominally 1.25 v for host signals. agpref/ dvobc_ref 1 agp reference : reference voltage input for the agp interface. agpref is 0.5 * vagpdd when vdd=1.5 v. dvo bc interface : dvobc_ref is 0.5 * vagpdd when vdd=1.5 v. vcc_agp 8 agp voltage : vdd is nominally 1.5 v for agp. vccq_agp 2 agp quiet voltage : quiet voltage for agp interface is also 1.5 v. hlref 1 hub interface reference : reference voltage input for the hub interface. hlref is 0.5 * vdd. vcc_hub 2 hub interface voltage : vcc supplies for the hub interface are 1.8 v. sm_ref[b:a] 2 system memory reference : reference voltage input for system memory is vcc_sm/6 = .55 v. vcc_sm 14 system memory voltage : vcc supplies for system memory are 3.3 v. vccq_sm 5 system memory quiet voltage : quiet vcc for the system memory interface is 3.3 v. vcc_gpio 2 gpio voltage : vcc supplies for general purpose i/o signals are 3.3 v. vcc_dvo 3 dvo voltage : vcc supplies for digital video output signals are 1.5 v. vcca_dac; vssa_dac 21 dac voltage : vcca and vssa supplies for the dac. vcca_dac is 1.8 v. ram_ref[b:a] 2 reserved(rambus* reference) : reference voltage input for the rambus rsl interface. ramref is approximately 1.4 v. rambus no longer supported. vcc_cmos; vss_cmos 43 reserved(graphics memory cmos voltage) : vcc and vss supplies for local memory cmos signals. vcc_cmos is 1.8 v. local memory no longer supported. vcc_lm 9 reserved(vcc graphics memory voltage) : vcc supplies for local memory. vcc_lm is 1.8 v. local memory no longer supported. vdd_lm 7 reserved(vdd graphics memory voltage) : vdd supplies for local memory. vdd_lm is 1.25v. local memory no longer supported. vcca_cpll; vssa_cpll 11 graphics core pll voltage : vcca and vssa supplies for core pll. vcca_cpll is 1.25 v. vcca_hpll; vssa_hpll 11 host/memory/hub/agp pll voltage : vcca and vssa supplies for host pll. vcca_hpll is 1.25 v. vcca_dpll[1:0]; vssa_dpll[1:0] 22 display pll voltage : vcca and vssa supplies for display pll. vcca_dpll is 1.25 v. vcc 24 core vcc : 1.25 v.
intel ? 830 chipset family 56 datasheet 298338-003 r vss 140 ground pins . 3.5 intel 830 chipset family strap signals table 22 indicates the strap options invoked by various intel 830 chipset family gmch-m signal pins. table 22. bootup strap signal descriptions signal name description dvoa_d [5] desktop/mobile selection . the state of this pin on the rising edge of reset# selects whether the gmch-m is desktop or mobile. dvoa_d [5 ] desktop/mobile part 0 = desktop part (default) 1= mobile part dvoa_d[7] xor chain. the state of this pin on the rising edge of reset# select whether to invoke the xor chain test mode for checking the io buffer connectivity. dvoa_d[7] xor chain test mode 0 = default (normal operation; xor chain test mode is not invoked) 1 = xor chain test mode to invoke the xor chain test mode, pull up this signal through an external resistor to 1.5 v. dvoa_d[8] all z. the state of this pin on the rising edge of reset# select whether to tri-states all gmch output when ich3-m is in xor chain mode. dvoa_d[8] all z 0 = default (do not tri-states gmch output) 1 = all z to invoke this strap, pull up this signal through an external resistor to 1.5 v.
intel ? 830 chipset family 298338-003 datasheet 57 r 4 register description this section details register access and provides pci register address maps. 4.1 conceptual overview of the platform configuration structure the intel 830 chipset family gmch-m and the ich3-m are physically connected with the hub interface. from a configuration standpoint the hub interface connecting the gmch-m and the ich3-m is logically pci bus #0. all devices internal to the gmch-m and ich3-m appear to be on pci bus #0. the system?s primary pci expansion bus is physically attached to the ich3-m, and from a configuration standpoint appears as a hierarchical pci bus behind a pci-to-pci bridge. the primary pci expansion bus connected to the ich3-m has a programmable pci bus number. note that even though the primary pci bus is referred to as pci0 in this document it is not pci bus #0 from a configuration standpoint. the gmch-m contains three pci devices within a single physical component. the configuration registers for device 0 and 1 are mapped as devices residing on pci bus #0. ? device 0: host-hub interface bridge/sdram controller . logically, this appears as a pci device residing on pci bus #0. physically, device 0 contains the standard pci registers, agp capabilities registers 1 , sdram registers, the graphics aperture controller, and other gmch-m specific registers. device 0 applies to the entire 830 chipset family. ? device 1: host-agp bridge . logically, this appears as a ?virtual? pci-to-pci bridge residing on pci bus #0. physically, device 1 contains the standard pci-to-pci bridge registers and the standard agp/pci1 configuration registers (including the agp i/o and memory address mapping). device 1 applies to both the intel 830mp and 830m chipset. ? device 2: integrated graphics device (igd). logically, this appears as a pci device residing on pci bus #0. physically, device 2 contains the standard registers of a pci graphics controller device. device 2 applies to both the intel 830m and 830mg chipset. note: 1 agp capabilities registers are applicable when discrete agp graphics solution (intel 830mp/ intel 830m chipset) is used. logically, the ich3-m appears as two pci devices within a single physical component also residing on pci bus #0. one of the ich3-m devices residing on pci bus #0 is a pci-to-pci bridge. logically, the primary side of the bridge resides on pci bus #0 while the secondary side is the standard pci expansion bus (pci0). also within the ich3-m is another pci device, the lan controller, which resides on the standard pci expansion bus (pci0) down from the pci-to-pci bridge. note that a physical pci bus #0 does not exist and that hub interface and the internal devices in the gmch-m and ich3-m logically constitute pci bus #0 to configuration software. this is shown in figure 4, figure 5, and figure 6 for the intel 830mp, intel 830m, and intel 830mg chipsets respectively.
intel ? 830 chipset family 58 datasheet 298338-003 r figure 4. intel 830mp chipset logical bus structure during pci configuration hub i/f bridge dram controller device #0 agp bridge device #1 pci bridge device #30 lpc bridge device #31 intel 830mp chipset gmch-m intel ich3-m pci bus #0 hub interface a gp/pci1 pci0 lan controller device #8 figure 5. intel 830m chipset logical bus structure during pci configuration hub i/f bridge dram controller device #0 agp bridge device #1 integrated graphics device #2 pci bridge device #30 lpc bridge device #31 intel 830m chipset gmch-m intel ich3-m pci bus #0 hub interface a gp/pci1 pci0 lan controller device #8 note: intel 830m chipset can support the use of either the discrete agp interface or the internal graphics device.
intel ? 830 chipset family 298338-003 datasheet 59 r figure 6. 830mg chipset logical bus structure during pci configuration hub i/f bridge dram controller device #0 integrated graphics device #2 pci bridge device #30 lpc bridge device #31 intel 830mg chipset gmch-m intel ich3-m pci bus #0 hub interface pci0 lan controller device #8 4.2 routing configuration accesses to pci0 or agp/pci the intel 830 chipset family gmch-m supports two bus interfaces: hub interface and agp/pci. pci configuration cycles are selectively routed to both interfaces. the gmch-m is responsible for routing pci configuration cycles to the proper interface. pci configuration cycles to ich3-m internal devices and primary pci (including downstream devices) are routed to the ich3-m via hub interface. agp/pci1 configuration cycles are routed to agp. the agp/pci1 interface is treated as a separate pci bus from the configuration point of view. routing of configuration accesses to agp/pci1 is controlled via the standard pci-pci bridge mechanism using information contained within the primary bus number, the secondary bus number, and the subordinate bus number registers of the host-agp/pci1 (device #1). note: agp is only available with 830m and 830mp chipset; internal graphics device is available with 830m and 830mg chipset.
intel ? 830 chipset family 60 datasheet 298338-003 r 4.2.1 intel 830 chipset family gmch-m configuration cycle flow charts figure 7. configuration cycle flow chart dw i/o write to config_address with bit 31=1 i/o read/write to config_data bus#=0 dev#=0, fn#=0 gmch-m claims bus #0 / device #0 / function #0 dev#=1, fn#=0 yes yes yes no gmch-m generates hub i/f type 1 configuration cycle bus#= secondary bus in gmch dev #1 no gmch-m generates type 0 access to agp/pci1 yes bus# > sec bus bus# <= sub bus no gmch-m generates type 1 access to agp/pci1 yes no gmch-m generates hub i/f type 0 configuration cycle dev#=2, fn#=0/1 no no yes gmch-m claims bus #0 / device #1 / function #0 gmch-m claims bus #0 / device #2 / function #0/1 a detailed description of the mechanism for translating cpu i/o bus cycles to configuration cycles on one of the two buses is described in figure 7 above. 4.2.2 pci bus configuration mechanism the pci bus defines a slot based "configuration space" that allows each device to contain up to 8 functions with each function containing up to 256, 8-bit configuration registers. the pci specification defines two bus cycles to access the pci configuration space: configuration read and configuration write. memory and i/o spaces are supported directly by the cpu. configuration space is supported by a mapping mechanism implemented within the gmch-m. the pci specification defines two mechanisms to access configuration space, mechanism #1 and mechanism #2. the gmch-m supports only mechanism #1 for pci configuration accesses. the configuration access mechanism makes use of the config_address register and config_data register. to reference a configuration register, a dword i/o write cycle is used to place a value into config_address that specifies the pci bus, the device on that bus, the function within the device, and a specific configuration register of the device function being accessed. config_address[31] must be first to enable a configuration cycle. config_data then becomes
intel ? 830 chipset family 298338-003 datasheet 61 r a window into the four bytes of configuration space specified by the contents of config_address. any read or write to config_data will result in the intel 830 chipset family gmch-m translating the config_address into the appropriate configuration cycle. the gmch-m is responsible for translating and routing the cpu?s i/o accesses to the config_address and config_data registers to internal gmch-m configuration registers, hub interface, or agp/pci1 (applicable when discrete agp is used with intel 830m and 830mp chipset). 4.2.3 pci bus #0 configuration mechanism the intel 830 chipset family gmch-m decodes the bus number (bits 23:16) and the device number fields of the config_address register. if the bus number field of config_address is 0 the configuration cycle is targeting a pci bus #0 device. the host-hub interface bridge entity within the gmch-m is hardwired as device #0 on pci bus #0 (applicable to the entire 830 chipset family). the host-agp/pci1 bridge entity within the gmch-m is hardwired as device #1 on pci bus #0 (applicable only to the 830m and 830mp chipset). the integrated graphics entity within the gmch-m is hardwired as device #2 on pci bus#0 (applicable to 830m and 830mg chipset). configuration cycles to any of the gmch-m?s internal devices are confined to the gmch-m and not sent over hub interface. accesses to devices #3 to #31 will be forwarded over hub interface as type 0 configuration cycles (see hub interface spec). a[1:0] of the hub interface request packet for the type 0 configuration cycle will be ?00?. bits 15:2 of the config_address register will be translated to the a[15:2] field of the hub interface request packet of the configuration cycle as shown the figure below. the ich3-m decodes the type 0 access and generates a configuration access to the selected internal device. figure 8. hub interface type 0 configuration address translation device number function no. register number 0 0 reserved 0 15 31 16 type 0 x x register number function no. device number 0 reserved 1 config_address hub interface type 0 configuration address extension cfg_hl0.vsd 0 31 4.2.4 primary pci and downstream configuration mechanism if the bus number in the config_address is non-zero, and is less than the value programmed into the intel 830 chipset family gmch-m?s device #1 secondary bus number register or greater than the value programmed into the subordinate bus number register, the gmch-m will generate a type 1 hub interface configuration cycle. a[1:0] of the hub interface request packet for the type 1 configuration cycle will be ?01?. bits 31:2 of the config_address register will be translated to the a[31:2] field of the hub interface request packet of the configuration cycle as shown in the figure below. the ich3-m compares the non-zero bus number with the secondary bus number and subordinate bus number registers of its p2p bridges to determine if the configuration cycle is meant for primary pci, one of the ich3-m?s hub interfaces, or a downstream pci bus.
intel ? 830 chipset family 62 datasheet 298338-003 r figure 9. hub interface type 1 configuration address translation device number function no. register number 0 1 0 15 31 16 type 1 x x register number function no. device number bus number reserved 1 config_address hub interface type 1 configuration address extension cfg_hl1.vsd reserved bus number 31 0 4.2.5 intel 830m and 830mp chipset agp/pci1 bus configuration mechanism from the chipset configuration perspective, agp/pci1 is seen as another pci bus interface residing on a secondary bus side of the ?virtual? pci-pci bridge referred to as the intel 830m and 830mp chipset gmch-m host-agp/pci1 bridge. on the primary bus side, the ?virtual? pci-pci bridge is attached to pci bus #0. therefore, the primary bus number register is hardwired to ?0?. the ?virtual? pci- pci bridge entity converts type #1 pci bus configuration cycles on pci bus #0 into type 0 or type 1 configuration cycles on the agp/pci1 interface. type 1 configuration cycles on pci bus #0 that have a bus number that matches the secondary bus number of the gmch-m?s ?virtual? pci-pci bridge will be translated into type 0 configuration cycles on the agp/pci1 interface. the gmch-m will decode the device number field [15:11] and assert the appropriate gad signal as an idsel in accordance with the pci-to-pci bridge type 0 configuration mechanism. for pci-to-pci bridge translation one of 16 idsels are generated (as opposed to one of 21 for host-to-pci bridges). when bit [15] = 0, bits [14:11] are decoded to assert a single ad[31:16] idsel. if bit [15] = 1, ad[31:16] are 0000h. the remaining address bits will be mapped as described in figure 10. figure 10. mechanism #1 type 0 configuration address to pci address mapping x x register number function no. device number bus number reserved 1 config_address agp/pci1 type 0 configuration cycle cfg_hl1.vsd 31 0 24 23 16 15 11 10 8 7 2 1 0 0 register number function no. reserved = 0 idsel 31 0 24 23 16 15 11 10 8 7 2 1 14 agp gad[31:0] address
intel ? 830 chipset family 298338-003 datasheet 63 r table 23. agp/pci1 config address remapping config address ad[15:11] agp gad[31:16] idsel 00000 0000 0000 0000 0001 00001 0000 0000 0000 0010 00010 0000 0000 0000 0100 00011 0000 0000 0000 1000 00100 0000 0000 0001 0000 00101 0000 0000 0010 0000 00110 0000 0000 0100 0000 00111 0000 0000 1000 0000 01000 0000 0001 0000 0000 01001 0000 0010 0000 0000 01010 0000 0100 0000 0000 01011 0000 1000 0000 0000 01100 0001 0000 0000 0000 01101 0010 0000 0000 0000 01110 0100 0000 0000 0000 01111 1000 0000 0000 0000 1xxxx 0000 0000 0000 0000 if the bus number is non-zero, greater than the value programmed into the secondary bus number register and less than or equal to the value programmed into the subordinate bus number register, the configuration cycle is targeting a pci bus downstream of agp/pci1. the 830m and 830mp gmch-m will generate a type 1 pci configuration cycle on agp/pci1. the address bits will be mapped as described in figure below. figure 11. mechanism #1 type 1 configuration address to pci address mapping reg. index reg. index pci address ad[31:0] 16 15 11 7 0 31 16 15 8 7 0 config_address x x 0 1 1 2 2 1 11 10 device number function number 8 10 bus number 23 31 30 24 reserved 1 function number device number bus number 23 24 0
intel ? 830 chipset family 64 datasheet 298338-003 r to prepare for mapping of the configuration cycles on agp/pci1 the initialization software will go through the following sequence: 1. scan all devices residing on the pci bus #0 using type 0 configuration accesses. 2. for every device residing at bus #0 which implements pci-pci bridge functionality, it will configure the secondary bus of the bridge with the appropriate number and scan further down the hierarchy. this process will include the configuration of the ?virtual? pci-pci bridge within the 830m and 830mp gmch-m used to map the agp address space in a software specific manner. note: although initial agp platform implementations will not support hierarchical buses residing below agp, this specification still must define this capability in order to support pci-66 compatibility. note also that future implementations of the agp devices may support hierarchical pci or agp-like buses coming out of the root agp device. 4.2.6 intel 830 chipset family internal gmch-m configuration register access mechanism accesses decoded as pci bus #0/device #0 (host-hub interface bridge/sdram controller), pci bus #0/device #1 (host-agp bridge 1 ), or pci bus #0/device#2 (integrated graphics device 1 ) are sequenced as type 0 pci configuration cycle accesses on bus #0 to device #0/function #0, device #1/function #0, and device #2/function #0/1. note that since gmch-m device #0 and #1 are not multi-function devices, the function number should always be ?0?. if the function number is not ?0? for accesses to device #0 or #1, the gmch-m will not claim the configuration cycle and it will be forwarded to the hub interface where it should be master aborted (by the ich3-m) in the same way as transactions to other unimplemented pci configuration targets. note: agp is available only with the intel 830mp and 830m chipset. internal graphics device is available only with the intel 830m and 830mg chipset. 4.3 intel 830 chipset family gmch-m register introduction the intel 830 chipset family gmch-m contains two sets of software accessible registers, accessed via the host cpu i/o address space: 1. control registers i/o mapped into the cpu i/o space, which control access to pci and agp configuration space (see section entitled i/o mapped registers). 2. internal configuration registers residing within the gmch-m that are partitioned into three logical device register sets (?logical? since they reside within a single physical device). the first register set is dedicated to host-hub interface bridge functionality (controls pci bus #0 i.e. sdram configuration, other chip-set operating parameters and optional features). the second register block is dedicated to host-agp/pci1 bridge functions (controls agp/pci1 interface configurations and operating parameters). the third register block is dedicated to the integrated graphics device (igd) function. note: agp is only available with 830m and 830mp chipset; internal graphics device is available with 830m and 830mg chipset note: this configuration scheme is necessary to accommodate the existing and future software configuration model supported by microsoft* where the host bridge functionality will be supported and controlled via a dedicated specific driver. virtual pci-pci bridge functionality will be supported via standard pci bus enumeration configuration software. the term ?virtual? is used to designate that no real physical embodiment of the pci-pci bridge functionality exists within the gmch-m, but that gmch-m?s
intel ? 830 chipset family 298338-003 datasheet 65 r internal configuration register sets are organized in this particular manner to create that impression to the standard configuration software. the gmch-m supports pci configuration space accesses using the mechanism denoted as configuration mechanism #1 in the pci specification. the gmch-m internal registers (both i/o mapped and configuration registers) are accessible by the host cpu. the registers can be accessed as byte, word (16-bit), or dword (32-bit) quantities, with the exception of config_address that can only be accessed as a dword. all multi-byte numeric fields use "little-endian" ordering (i.e., lower addresses contain the least significant parts of the field). some of the gmch-m registers described in this section contain reserved bits. these bits are labeled "reserved?. software must deal correctly with fields that are reserved. on reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. on writes, software must ensure that the values of reserved bit positions are preserved. that is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. note the software does not need to perform read, merge, and write operations for the configuration address register. in addition to reserved bits within a register, the gmch-m contains address locations in the configuration space of the host-hub interface bridge entity that are marked either "reserved" or ?intel reserved?. the gmch-m responds to accesses to ?reserved? address locations by completing the host cycle. when a ?reserved? register location is read, a zero value is returned. (?reserved? registers can be 8-, 16-, or 32-bit in size). writes to ?reserved? registers have no effect on the gmch-m. registers that are marked as ?intel reserved? must not be modified by system software. writes to ?intel reserved? registers may cause system failure. reads to ?intel reserved? registers may return a non-zero value. upon reset, the gmch-m sets all of its internal configuration registers to predetermined default states. some register values at reset are determined by external strapping options. the default state represents the minimum functionality feature set required to successfully bring up the system. hence, it does not represent the optimal system configuration. it is the responsibility of the system initialization software (usually bios) to properly determine the sdram configurations, operating parameters and optional system features that are applicable, and to program the gmch-m registers accordingly. 4.4 intel 830 chipset family i/o mapped registers the intel 830 chipset family gmch-m contains a set of registers that reside in the cpu i/o address space - the configuration address (config_address) register and the configuration data (config_data) register. the configuration address register enables/disables the configuration space and determines what portion of configuration space is visible through the configuration data window.
intel ? 830 chipset family 66 datasheet 298338-003 r 4.4.1 config_address - configuration address register i/o address: 0cf8h accessed as a dword default value: 00000000h access: read/write size: 32 bits config_address is a 32-bit register accessed only when referenced as a dword. a byte or word reference will "pass through" the configuration address register and hub interface onto the pci0 bus as an i/o cycle. the config_address register contains the bus number, device number, function number, and register number for which a subsequent configuration access is intended. r 1 0 2 7 8 11 15 16 23 24 30 3 1 10 r 0 0 0 0 0 reserved register number function number device number bus number reserved enable bit default bit descriptions 31 configuration enable (cfge) . when this bit is set to 1, accesses to pci configuration space are enabled. if this bit is reset to 0, accesses to pci configuration space are disabled. 30:24 reserved (these bits are read only and have a value of 0). 23:16 bus number . when the bus number is programmed to 00h the target of the configuration cycle is either the gmch-m or the ich3-m. the configuration cycle is forwarded to hub interface if the bus number is programmed to 00h and no device internal to the gmch-m is the target. if the bus number is non-zero and matches the value programmed into the secondary bus number register of the agp/pci1 bridge, a type 0 pci configuration cycle will be generated on agp/pci1. if the bus number is non-zero, greater than the value in the secondary bus number register of the agp/pci1 bridge, and less than or equal to the value programmed into the subordinate bus number register, a type 1 pci configuration cycle will be generated on agp/pci1. if the bus number is non-zero, and is less than the value programmed into the secondary bus number register of the agp/pci1 bridge, or is greater than the value programmed into the subordinate bus number register, a type 1 hub interface configuration cycle is generated. 15:11 device number . this field selects one agent on the pci bus selected by the bus number. when the bus number field is ?00? the gmch-m decodes the device number field. the gmch-m is always device #0 for the host-hub interface bridge entity, device #1 for the host-agp/pci1 entity, and device #2 for the integrated graphics device entity. therefore, when the bus number = 0 and the device number = 0, 1, or 2, the internal gmch-m devices are selected. if the bus number is non-zero and matches the value programmed into the secondary bus number register of the agp/pci1 bridge, a type 0 pci configuration cycle will be generated on agp/pci1. the device number field is decoded and the gmch-m asserts one and only one gadxx signal as an idsel. gad11 is asserted to access device #0, gad12 for device #1, and so forth up to device #20 for which will assert gad31. all device numbers higher than 20 cause a type 0 configuration access with no idsel asserted, which will result in a master abort reported in the gmch-m?s ?virtual? pci-pci bridge registers.
intel ? 830 chipset family 298338-003 datasheet 67 r for bus numbers resulting in agp/pci1 type 1 configuration cycles, the device number is propagated as gad[15:11]. 10:8 function number . this field is mapped to gad[10:8] during agp/pci1 configuration cycles. this allows the configuration registers of a particular function in a multi-function device to be accessed. the gmch- m ignores configuration cycles to devices 1 if the function number is not equal to 0. 7:2 register number . this field selects one register within a particular bus, device, and function as specified by the other fields in the configuration address register. this field is mapped to gad[7:2] during agp/pci1 configuration cycles. 1:0 reserved
intel ? 830 chipset family 68 datasheet 298338-003 r 4.4.2 config_data - configuration data register i/o address: 0cfch default value: 00000000h access: read/write size: 32 bits config_data is a 32-bit read/write window into configuration space. the portion of configuration space that is referenced by config_data is determined by the contents of config_address. 31 0 bit default 0 configuration data window bit descriptions 31:0 configuration data window (cdw) . if bit 31 of config_address is 1, any i/o access to the config_data register will be mapped to configuration space using the contents of config_address. 4.5 intel 830 chipset family gmch-m internal device registers table 24 below shows the nomenclature of access attributes for the configuration space of each device. table 24. nomenclature for access attributes ro read only . if a register is read only, writes to this register have no effect. r/w read/write . a register with this attribute can be read and written r/wc read/write clear . a register bit with this attribute can be read and written. however, a write of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect. r/wo read/write once . a register bit with this attribute can be written to only once after power up. after the first write, the bit becomes read only. l lock . a register bit with this attribute becomes read only after a lock bit is set.
intel ? 830 chipset family 298338-003 datasheet 69 r 4.5.1 sdram controller/host-hub interface device registers - device #0 table 25 shows the gmch-m configuration space for device #0 (applicable to the entire 830 chipset family). an ?s? in the default value field means that a strap determines the power-up default value for that bit. table 25. host-hub i/f bridge/sdram controller configuration space (device #0) address offset register symbol register name default value access 00-01h vid vendor identification 8086h ro 02-03h did device identification 3575h ro 04-05h pcicmd pci command register 0006h r/w 06-07h pcists pci status register 0010h ro, r/wc 08h rid revision identification 00h ro 09h - intel reserved - - 0ah subc sub-class code 00h ro 0bh bcc base class code 06h ro 0ch - intel reserved - - 0dh mlt master latency timer 00h ro 0eh hdr header type 00h ro 0fh - intel reserved - - 10-13h apbase aperture base configuration 00000008h r/w, ro 14-2bh - intel reserved - - 2c-2dh svid subsystem vendor identification 00h r/wo 2e-2fh sid subsystem identification 00h r/wo 30-33h - intel reserved - - 34h capptr capabilities pointer 40h ro 35-3fh - intel reserved - - 40-44h - intel reserved - - 45-47h - intel reserved - - 48-4bh rrbar register range base address 00000000h r/w, ro 4c-4fh - intel reserved - - 50-51h gcc0 gmch control register 0 a072h r/w, ro 52-53h gcc1 gmch control register 1 0000h r/w 54-55h - intel reserved - - 56-57h - intel reserved - - 58h fdhc fixed dram hole control 00h r/w 59-5fh pam[6:0] programmable attribute map (7 i) 00h r/w
intel ? 830 chipset family 70 datasheet 298338-003 r registers) 60-67h drb[7:0] dram row boundary register 00h r/w/l 68-6fh - intel reserved - - 70-71h dra[1:0] dram row attributes ffh r/w/l 72-77h - intel reserved - - 78-7bh drt dram timing register 00000010h r/w 7c-7fh drc dram control 00000000h r/w 80-8bh - intel reserved - - 8c-8fh dtc dram throttling control register 00000000h r/w/l 90h smram system management ram control reg. 02h r/w/l 91h esmramc extended system management ram control register 38h r/w 92-93h errsts error status register 0000h r/w 94-95h errcmd error command register 0000h r/w 96h - intel reserved - - 97h - intel reserved - - 98-9f - intel reserved - - a0-a3h acapid agp capability identifier 00200002h ro* a4-a7h agpstat agp status register 1f000217h ro* a8-abh agpcmd agp command register 00000000h rw* ac-afh - intel reserved - - b0-b1h agpctrl agp control register 0000h r/w* b2-b3h aft agp functional test register 0000h r/w* b4h apsize agp aperture size 00h r/w* b5-b7h - intel reserved - - b8-bbh attbase aperture translation table 00000000h r/w* bch amtt agp interface multi-transaction timer register 00h r/w* bdh lptt low priority transaction timer register 00h r/w* be-bfh - intel reserved - - c2-ebh - intel reserved - - ec-efh buff_sc system memory buffer strength control register 00000000h r/w f0-ffh - intel reserved - - note: *register is read only (ro) when internal graphics device is used with the intel 830mg chipset is used. register will have no functionality when internal graphics device is used with intel 830m chipset.
intel ? 830 chipset family 298338-003 datasheet 71 r 4.5.1.1 vid - vendor identification register - device #0 address offset: 00 - 01h default value: 8086h attribute: read only size: 16 bits the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 vendor identification number . this is a 16-bit value assigned to intel. intel vid = 8086h. default value=1000/0000/1000/0110. 4.5.1.2 did - device identification register - device #0 address offset: 02 - 03h default value: 3575h attribute: read only size: 16 bits this 16-bit register combined with the vendor identification register uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 device identification number . this is a 16-bit value assigned to the gmch-m host-hub interface bridge, device #0. default value=0011/0101/0111/0101.
intel ? 830 chipset family 72 datasheet 298338-003 r 4.5.1.3 pcicmd - pci command register - device #0 address offset: 04-05h default value: 0006h access: read/write size 16 bits since gmch-m device #0 is the host-to-hub interface bridge, many of the pci specific bits in this register don?t apply. bit description 15:10 reserved 9 fast back-to-back . this bit controls whether or not the master can do fast back-to-back write. since device #0 is strictly a target this bit is not implemented and is hardwired to 0. writes to this bit position have no effect. default value=0. 8 serr enable (serre) . this bit is a global enable bit for device #0 serr messaging. the gmch-m does not have an serr# signal. the gmch-m communicates the serr# condition by sending an serr message to the ich3-m. if this bit is set to a 1, the gmch-m is enabled to generate serr messages over hub interface for specific device #0 error conditions that are individually enabled in the errcmd register. the error status is reported in the errsts and pcists registers. if serre is reset to 0, then the serr message is not generated by the gmch-m for device #0. note : this bit only controls serr messaging for the device #0. device #1 has its own serre bit to control error reporting for error conditions occurring on device #1. the two control bits are used in a logical or manner to enable the serr hub interface message mechanism. default value=0. 7 address/data stepping . address/data stepping is not implemented in the gmch-m, and this bit is hardwired to 0. writes to this bit position have no effect. default value=0. 6 parity error enable (perre) . perr# is not implemented by the gmch-m, and this bit is hardwired to 0. writes to this bit position have no effect. default value=0. 5 vga palette snoop . the gmch-m does not implement this bit and it is hardwired to a 0. writes to this bit position have no effect. default value=0. 4 memory write and invalidate enable . the gmch-m will never use this command and this bit is hardwired to 0. writes to this bit position have no effect. default value=0. 3 special cycle enable . the gmch-m does not implement this bit and it is hardwired to a 0. writes to this bit position have no effect. default value=0. 2 bus master enable (bme) . the gmch-m is always enabled as a master on hub interface. this bit is hardwired to a 1. writes to this bit position have no effect. default value=1. 1 memory access enable (mae) . the gmch-m always allows access to main memory. this bit is not implemented and is hardwired to 1. writes to this bit position have no effect. default value=1. 0 i/o access enable (ioae). this bit is not implemented in the gmch-m and is hardwired to a 0. writes to this bit position have no effect. default value=0.
intel ? 830 chipset family 298338-003 datasheet 73 r 4.5.1.4 pcists - pci status register - device #0 address offset: 06-07h default value: 0010h access: read only, read/write clear size: 16 bits pcists is a 16-bit status register that reports the occurrence of error events on device #0?s hub interface. bit 14 is read/write clear. all other bits are read only. since gmch-m device #0 is the host-to-hub interface bridge, many of the pci specific bits in this register do not apply. bit description 15 detected parity error (dpe) . this bit is hardwired to a 0. writes to this bit position have no effect. default value=0. 14 signaled system error (sse). this bit is set to 1 when gmch-m device #0 generates an serr message over hub interface for any enabled device #0 error condition. device #0 error conditions are enabled in the pcicmd and errcmd registers. device #0 error flags are read/reset from the pcists or errsts registers. software sets sse to 0 by writing a 1 to this bit. default value=0. 13 received master abort status (rmas). this bit is set when the gmch-m generates a hub interface request that receives a master abort completion packet. software clears this bit by writing a 1 to it. default value=0. 12 received target abort status (rtas ). this bit is set when the gmch-m generates a hub interface request that receives a target abort completion packet. software clears this bit by writing a 1 to it. default value=0. 11 signaled target abort status (stas) . the gmch-m will not generate a target abort hub interface completion packet. this bit is not implemented in the gmch-m and is hardwired to a 0. writes to this bit position have no effect. default value=0. 10:9 devsel# timing (devt). hub interface does not comprehend devsel# protocol. these bits are hardwired to ?00?. writes to these bits have no effect. default value=00. 8 data parity detected (dpd) . gmch-m does not support parity on hub interface. this bit is hardwired to a 0. writes to this bit position have no effect. default value=0. 7 fast back-to-back (fb2b). hub interface does not comprehend pci fast back-to-back protocol. this bit is hardwired to 0. writes to this bit position have no effect. default value=0. 6:5 reserved 4 capability list (clist) . this bit is hardwired to 1 to indicate to the configuration software that this device/function implements a list of new capabilities. a list of new capabilities is accessed via register capptr at configuration address offset 34h. register capptr contains an offset pointing to the start address within configuration space of this device where the capabilities linked list begins. default value=1. 3:0 reserved
intel ? 830 chipset family 74 datasheet 298338-003 r 4.5.1.5 rid - revision identification register - device #0 address offset: 08h default value: 03h (a5 silicon) 04h (a6 silicon) access: read only size: 8 bits this register contains the revision number of the gmch-m device #0. these bits are read only and writes to this register have no effect. bit description 7:0 revision identification number . this is an 8-bit value that indicates the revision identification number for the gmch-m device #0. please see spec update for the latest silicon revision. silicon revision default value a5 0000/0011 (03h) a6 0000/0100 (04h) 4.5.1.6 subc - sub-class code register - device #0 address offset: 0ah default value: 00h access: read only size: 8 bits this register contains the sub-class code for the gmch-m device #0. this code is 00h indicating a host bridge device. the register is read only. bit description 7:0 sub-class code (subc). this is an 8-bit value that indicates the category of bridge into which the gmch- m falls. the code is 00h indicating a host bridge. default value=0000/0000.
intel ? 830 chipset family 298338-003 datasheet 75 r 4.5.1.7 bcc - base class code register - device #0 address offset: 0bh default value: 06h access: read only size: 8 bits this register contains the base class code of the gmch-m device #0. this code is 06h indicating a bridge device. this register is read only. bit description 7:0 base class code (basec). this is an 8-bit value that indicates the base class code for the gmch-m. this code has the value 06h. default value=0000/0110. 4.5.1.8 mlt - master latency timer register - device #0 address offset: 0dh default value: 00h access: read only size: 8 bits hub interface does not comprehend the concept of a master latency timer. therefore the functionality of this register is not implemented and the register is hardwired to 0. bit description 7:0 these bits are hardwired to 0. writes have no effect. default value=0000/0000. 4.5.1.9 hdr - header type register - device #0 address offset: 0eh default value: 00h access: read only size: 8 bits this register identifies the header layout of the configuration space. no physical register exists at this location. bit descriptions 7:0 this read only field always returns 0 when read and writes have no effect. default value=0000/0000.
intel ? 830 chipset family 76 datasheet 298338-003 r 4.5.1.10 apbase - aperture base configuration register - device #0 address offset: 10-13h default value: 00000008h access: read/write, read only size: 32 bits the apbase is a standard pci base address register that is used to set the base of the graphics aperture. the standard pci configuration mechanism defines the base address configuration register such that only a fixed amount of space can be requested (dependent on which bits are hardwired to ?0? or behave as hardwired to ?0?). to allow for flexibility (of the aperture) an additional register called apsize is used as a ?back-end? register to control which bits of the apbase will behave as hardwired to ?0?. this register will be programmed by the gmch-m specific bios code that will run before any of the generic configuration software is run. note that bit 9 of the gcc0 register at 51-50h is used to prevent accesses to the aperture range before the configuration software initializes this register and the appropriate translation table structure has been established in the main memory. bit description 31:28 upper programmable base address bits (r/w). these bits are used to locate the range size selected via lower bits 27:4. default value = 0000. 27:25 lower ?hardwired?/programmable base address bits. these bits behave as a ?hardwired? or as a programmable depending on the contents of the apsize register as defined below: 27 26 25 aperture sizer/w r/w r/w r/w 32 mb r/w r/w r/w 64 mb r/w 0 0 128 mb 0 0 0 256 mb the default for apsize[5:3,0]=0000 with forces default apbase[27:25] =000 (i.e. all bits respond as ?hardwired? to 0). this provides a default to the maximum aperture size of 256mb. the gmch-m specific bios is responsible for selecting smaller size (if required) before pci configuration software runs and establishes the system address map. default value=000. 24:4 hardwired to ?0?. this forces minimum aperture size selected by this register to be 32 mb. 3 prefetchable (ro). this bit is hardwired to ?1? to identify the graphics aperture range as a prefetchable, i.e. there are no side effects on reads, the device returns all bytes on reads regardless of the byte enables, and the gmch-m may merge processor writes into this range without causing errors. 2:1 type (ro). these bits determine addressing type and they are hardwired to ?00? to indicate that address range defined by the upper bits of this register can be located anywhere in the 32-bit address space. default value=00. 0 memory space indicator (ro). hardwired to ?0? to identify aperture range as a memory range.
intel ? 830 chipset family 298338-003 datasheet 77 r 4.5.1.11 svid - subsystem vendor id - device #0 address offset: 2c-2dh default value: 0000h access: read/write once size: 16 bits this value is used to identify the vendor of the subsystem. bit description 15:0 subsystem vendor id (r/wo). the default value is 00h. this field should be programmed during boot-up. after this field is written once, it becomes read only. default value=0000/0000/0000/0000. 4.5.1.12 sid - subsystem id - device #0 address offset: 2e-2fh default value: 0000h access: read/write once size: 16 bits this value is used to identify a particular subsystem. bit description 15:0 subsystem id (r/wo). the default value is 00h. this field should be programmed during boot-up. after this field is written once, it becomes read only. default value=0000/0000/0000/0000. 4.5.1.13 capptr - capabilities pointer - device #0 address offset: 34h default value: 40h access: read only size: 8 bits the capptr provides the offset that is the pointer to the location where the first capability register set is located. bit description 7:0 pointer to the start of capabilities register block. the value in this field is 40h. default value=0100/0000.
intel ? 830 chipset family 78 datasheet 298338-003 r 4.5.1.14 rrbar - register range base address register - device #0 address offset: 48-4bh default value: 00000000h access: read/write, read only size: 32 bits this register requests a 256-kb allocation for the device registers. the base address is defined by bits 31 to 18 and can be used to access device configuration registers. only dword aligned writes are allowed to this space. see table below for address map within the 512-kb space. this addressing mechanism may be used to write to registers that modify the device address map (includes all the bars, pams, smm registers, pre-allocated memory registers etc). however, before using or allowing the use of the modified address map the bios must synchronize using an io or read cycle. note that bit 8 of the gcc0 register at 51-50h is used to prevent accesses to this range before the configuration software initializes this register. bit description 31:18 memory base address-r/w . set by the os, these bits correspond to address signals [31:18]. default value=0000/0000/0000/0. 17:15 address mask-ro . hardwired to 0s to indicate 512-kb address range. the minimum size that can be requested by converting all these bits to r/w would be 64 kb. default value=000. 15:8 reserved. hardwired to 00h. 7:0 scratch pad size-ro, hardwired to ?00h?. 00h = 256b ffh = 64 kb default value=0000/0000. address range sub ranges description 00000h to 0003fh read only: maps to 00-3fh of device #0 p&p register space. 00040h to 000ffh read/write: maps to 40-ffh of device #0 p&p register space. 00100h to 3feffh read/write: extended register space. reserved. 00000h to 3ffffhdevice 0 space 3ff00h to 3ffffh scratch pad registers: 256 b, d-word read/write-able.
intel ? 830 chipset family 298338-003 datasheet 79 r 4.5.1.15 gcc0 - gmch control register #0 - device #0 address offset: 50-51h default value: a072h access: read/write, read only size: 16 bits bit descriptions 15 reserved 14:12 low priority grace period . this value is loaded in sdram arbiter when a request is ongoing and a higher priority request is presented to the arbiter. the arbiter continues to grant the first request for this specified number of page hits (1 kb). if the first requester causes a page miss or stops requesting the arbiter will switch to the higher priority requester. (a request equals an oct-word also known as dual-oct byte). 000 = 00 001 = 04 010 = 08 (default) 011 = 16 100 = 24 101 = 32 110 = reserved 111 = reserved default value=010. recommended value with internal graphics = 010 8 recommended value without internal graphics = 011 16 11 scratch pad enable . this bit when set to a ?1?, allows the upper 256 bytes of device #0 rrbar space to be mapped to scratch pad ram in the device. once d_lck is set, this bit becomes read only. note : the bios can use the scratch pad area when devices on the agp bus are inactive (not capable of using the agp pipe or side-band command bus to issue read cycles to main memory). default value=0. 10 reserved. 9 aperture access global enable (r/w ). this bit is used to prevent access to the aperture from any port (cpu, pci0 or agp/pci1) before the aperture range is established by the configuration software and appropriate translation table in the main sdram has been initialized. it must be set after system is fully configured for aperture accesses. default value=0. 8 rrbar access enable . this bit when set to a ?1?, enables the rrbar space. when ?0?, accesses will not decode to register range. default value=0. 7 reserved 6:4 ioq request grant ceiling . this value is loaded in sdram arbiter when an ioq request is granted. it provides a grant for the duration specified for as long as the request is active or until a fixed higher priority request needs to be serviced. 111 = infinite ceiling (default) 110 = 64 101 = 48 100 = 32 011 = 24
intel ? 830 chipset family 80 datasheet 298338-003 r 010 = 16 001 = 08 000 = 04 default value=111. please contact your intel field representative for more information. 3:1 reserved 0 mda present (mdap) (r/w). this bit works with the vga enable bit in the bctrl register of device 1 to control the routing of cpu initiated transactions targeting mda compatible i/o and memory address ranges. this bit should not be set when the vga enable bit is not set. if the vga enable bit is set, then accesses to io address range x3bch-x3bfh are forwarded to hub interface. if the vga enable bit is not set then accesses to io address range x3bch-x3bfh are treated just like any other io accesses i.e. the cycles are forwarded to agp if the address is within iobase and iolimit and isa enable bit is not set, otherwise they are forwarded to hub interface. mda resources are defined as the following: memory: 0b0000h - 0b7fffhi/o: i/o: 3b4h, 3b5h, 3b8h, 3b9h, 3bah, 3bfh, (including isa address aliases, a[15:10] are not used in decode) any i/o reference that includes the i/o locations listed above, or their aliases, will be forwarded to hub interface even if the reference includes i/o locations not listed above. the following table shows the behavior for all combinations of mda and vga: vga mda behavior default 0 0 all references to mda and vga go to hub interface 0 1 illegal combination (do not use) 1 0 all references to vga go to agp/pci. mda-only references (i/o address 3bf and aliases) will go to hub interface. 1 1 vga references go to agp/pci; mda references go to hub interface default value=0.
intel ? 830 chipset family 298338-003 datasheet 81 r 4.5.1.16 gcc1-?gmch control register #1 - device #0 address offset: 52-53h default value: 0000h access: read/write size: 16 bits bit descriptions 15:7 reserved 6:4 graphics mode select (gms ). this field is used to select the amount of main memory that is pre- allocated to support the internal graphics device in vga (non-linear) and native (linear) modes. these 3 bits are valid only when internal graphics is enabled. 000 = no memory pre-allocated (graphics memory disabled) [reserved] 001 = no memory pre-allocated (graphics memory enabled) [reserved] 010 = dvmt (uma) mode, 512k of memory pre-allocated for frame buffer 011 = dvmt (uma) mode, 1m of memory pre-allocated for frame buffer 100 = dvmt (uma) mode, 8m of memory pre-allocated for frame buffer ) *all other combinations reserved. note this register is locked and becomes read only when the d_lck bit in the smram register is set. default value = 000 3 device #2 disable when set to ?1? this bit disables device #2 and all associated spaces. default value = 0 note : device#2(igd) is only available with intel 830m and 830mg chipset. 2 device #2 function 1 enable when set to ?1?, enables the second function within device #2. default value = 0 note: device#2(igd) is only available with intel 830m and 830mg chipset. 1 igd vga disable (ivd). when set to a ?1?, the igd will not claim vga cycles (mem and i/o), and the sub-class code field within device #2 class code register is 80h. when set to a ?0?, the igd will claim vga memory and i/o cycles, the sub-class code within device#2 class code register is 00h default value = 0 note: device#2(igd) is only available with intel 830m and 830mg chipset. 0 device 2: graphics memory aperture size (controls gmadr register in device#2) 0 = 128 mb 1 = 64 mb default value = 0 note: device#2(igd) is only available with intel 830m and 830mg chipset. note: notes on pre-allocated memory for graphics (applicable only when internal graphics is used).
intel ? 830 chipset family 82 datasheet 298338-003 r these register bits control the theft of memory from main memory space for use as graphics memory. the memory for tseg is pre-allocated first and then the graphics memory is pre-allocated. an example of this theft mechanism is: tom equal 64 mb, tseg selected as 512 kb in size, graphics memory selected as 1 mb in size general system ram available in system = 62.5 mb general system ram range 00000000h to 03e7ffffh tseg address range 03f80000h to 03ffffffh tseg pre-allocated from 03f80000h to 03ffffffh graphics memory pre-allocated from 03e80000h to 03f7ffffh vga memory and io space decode priority: integrated graphics device (igd), device #2. pci-pci bridge, device #1. hub interface. vga memory space decode to igd: if ige = ?1? and ivd = ?0? and device # 2 mem_access_en = ?1? and msrb1 = ?1? and additional qualification within igd decode (comprehends mda requirements) mem access gr06(3:2) a0000h - affffh b0000h - b7fffh b8000h-bffffh ?00? igd igd igd ?01? igd p2p bridge or hub interface p2p bridge or hub interface ?10? p2p bridge or hub interface igd p2p bridge or hub interface ?11? p2p bridge or hub interface p2p bridge or hub interface igd else vga mem space legacy decode: if device # 1 mem_access_en = ?1?. vga mem range xa0000 - xbffff mda mem range xb0000 - xb7fff vga_en mdap range destination exceptions/notes 0 0 vga, mda hub interface - 0 1 illegal illegal illegal 1 0 vga, mda agp - 1 1 vgamda agphub interface -
intel ? 830 chipset family 298338-003 datasheet 83 r else defaults to hub interface. vga io space decode to igd: if ige = ?1? and ivd = ?0? and device # 2 io_access_en = ?1? and additional qualification within igd decode (comprehends mda requirements). io access msrb0 3cx 3dx 3b0-3bb 3bc-3bf ?0? igd p2p bridge or hub interface igd p2p bridge or hub interface ?1? igd igd p2p bridge or hub interface p2p bridge or hub interface else vga io space legacy decode: if device # 1 io_access_en = ?1?. vga i/o x3b0 - x3bb & x3c0 - x3df mda i/o x3b4, x3b5, x3b8, x3b9, x3ba, x3bf vga_en mdap range destination exceptions/notes 0 0 vga, mda hub interface x3bc - x3bf goes to agp if isa enabled bit is not set in device #1 0 1 illegal illegal illegal 1 0 vga mda only ( x3bf) agphub interface note : x3bc - x3be will also go to hub interface 1 1 vgamda agphub interface note : x3bc - x3be will also go to hub interface else defaults to hub interface.
intel ? 830 chipset family 84 datasheet 298338-003 r 4.5.1.17 fdhc - fixed dram hole control register - device #0 address offset: 58h default value: 00h access: read/write size: 8 bits this 8-bit register controls a single fixed sdram hole: 15-16 mb. bit description 7 hole enable (hen). this field enables a memory hole in sdram space. host cycles matching an enabled hole are passed on to ich3-m through hub interface. hub interface cycles matching an enabled hole will be ignored by the gmch-m. note that a selected hole is not re-mapped. bit 7 hole enabled 0 none 1 15m-16m (1m bytes) default value=0. 6:0 reserved
intel ? 830 chipset family 298338-003 datasheet 85 r 4.5.1.18 pam(6:0) - programmable attribute map registers - device #0 address offset: 59 - 5fh default value: 00h attribute: read/write size: 4 bits/register, 14 registers the gmch-m allows programmable memory attributes on 13 legacy memory segments of various sizes in the 640-kb to 1-mb address range. seven programmable attribute map (pam) registers are used to support these features. cacheability of these areas is controlled via the mtrr registers in the p6 processor. two bits are used to specify memory attributes for each memory segment. these bits apply to host, agp/pci, and hub interface initiator accesses to the pam areas. note: agp is available only with the intel 830m and 830mp chipset. these attributes are: re - read enable . when re = 1, the cpu read accesses to the corresponding memory segment are claimed by the gmch-m and directed to main memory. conversely, when re = 0, the host read accesses are directed to pci0. we - write enable. when we = 1, the host write accesses to the corresponding memory segment are claimed by the gmch-m and directed to main memory. conversely, when we = 0, the host write accesses are directed to pci0. the re and we attributes permit a memory segment to be read only, write only, read/write, or disabled. for example, if a memory segment has re = 1 and we = 0, the segment is read only. each pam register controls two regions, typically 16 kb in size. each of these regions has a 4-bit field. the 4 bits that control each region have the same encoding and are defined in the following table. table 26. attribute bit assignment bits [7, 3] reserved bits [6, 2] reserved bits [5, 1] we bits [4, 0] re description x x 0 0 disabled . sdram is disabled and all accesses are directed to hub interface. the gmch-m does not respond as an agp/pci or hub interface target for any read or write access to this area. x x 0 1 read only . reads are forwarded to sdram and writes are forwarded to hub interface for termination. this write protects the corresponding memory segment. the gmch-m will respond as an agp/pci or hub interface target for read accesses but not for any write accesses. x x 1 0 write only . writes are forwarded to sdram and reads are forwarded to the hub interface for termination. the gmch-m will respond as an agp/pci or hub interface target for write accesses but not for any read accesses. x x 1 1 read/write . this is the normal operating mode of main memory. both read and write cycles from the host are claimed by the gmch-m and forwarded to sdram. the gmch-m will respond as an agp/pci or hub interface target for both read and write accesses. note: agp is available only with the intel 830m and 830mp chipset.
intel ? 830 chipset family 86 datasheet 298338-003 r as an example, consider a bios that is implemented on the expansion bus. during the initialization process, the bios can be shadowed in main memory to increase the system performance. when bios is shadowed in main memory, it should be copied to the same address location. to shadow the bios, the attributes for that address range should be set to write only. the bios is shadowed by first doing a read of that address. this read is forwarded to the expansion bus. the host then does a write of the same address, which is directed to main memory. after the bios is shadowed, the attributes for that memory area are set to read only so that all writes are forwarded to the expansion bus. figure 12 and table 27 show the pam registers and the associated attribute bits: figure 12. pam registers
intel ? 830 chipset family 298338-003 datasheet 87 r table 27. pam registers and associated memory segments pam reg attribute bits memory segment comments offset pam0[3:0] reserved 59h pam0[7:4] r r we re 0f0000h - 0fffffh bios area 59h pam1[3:0] r r we re 0c0000h - 0c3fffh isa add-on bios 5ah pam1[7:4] r r we re 0c4000h - 0c7fffh isa add-on bios 5ah pam2[3:0] r r we re 0c8000h - 0cbfffh isa add-on bios 5bh pam2[7:4] r r we re 0cc000h- 0cffffh isa add-on bios 5bh pam3[3:0] r r we re 0d0000h- 0d3fffh isa add-on bios 5ch pam3[7:4] r r we re 0d4000h- 0d7fffh isa add-on bios 5ch pam4[3:0] r r we re 0d8000h- 0dbfffh isa add-on bios 5dh pam4[7:4] r r we re 0dc000h- 0dffffh isa add-on bios 5dh pam5[3:0] r r we re 0e0000h- 0e3fffh bios extension 5eh pam5[7:4] r r we re 0e4000h- 0e7fffh bios extension 5eh pam6[3:0] r r we re 0e8000h- 0ebfffh bios extension 5fh pam6[7:4] r r we re 0ec000h- 0effffh bios extension 5fh for details on overall system address mapping scheme see the address decoding section of this document. dos application area (00000h-9fffh) the dos area is 640 kb in size and it is further divided into two parts. the 512-kb area at 0 to 7ffffh is always mapped to the main memory controlled by the gmch-m, while the 128-kb address range from 080000 to 09ffffh can be mapped to pci0 or to main sdram. by default, this range is mapped to main memory and can be declared as a main memory hole (accesses forwarded to pci0) via gmch- m?s fdhc configuration register. video buffer area (a0000h-bffffh) this 128-kb area is not controlled by attribute bits. the host -initiated cycles in this region are always forwarded to either pci0 or agp/pci1 or pci2 unless this range is accessed in smm mode. routing of accesses is controlled by the legacy vga control mechanism of the ?virtual? pci-pci bridge device embedded within the gmch-m . this area can be programmed as smm area via the smram register. when used as an smm space, this range cannot be accessed from hub interface or agp. expansion area (c0000h-dffffh) this 128-kb area is divided into eight 16-kb segments that can be assigned with different attributes via pam control register as defined by table 27. extended system bios area (e0000h-effffh) this 64-kb area is divided into four 16-kb segments that can be assigned with different attributes via pam control register as defined by the table 27.
intel ? 830 chipset family 88 datasheet 298338-003 r system bios area (f0000h-fffffh) this area is a single 64-kb segment that can be assigned with different attributes via pam control register as defined by the table 27. 4.5.1.19 drb ? dram row boundary register - device #0 address offset: 60-67h default value: 00h access: read/write (read_only if d_lck = 1) size: 8 bits row boundary register defines the upper boundary address of each sdram row in 32-mb granularity. each row has its own drb register. contents of these 8-bit registers represent the boundary address in 32-mb granularity. for example, a value of 1 indicates 32 mb. row0: 60h row1: 61h row2: 62h row3: 63h row4: 64h: reserved row5: 65h: reserved row6: 66h: reserved row7: 67h: reserved drb0 = total memory in row0 (in 32 mbytes) drb1 = total memory in row0 + row1 (in 32 mbytes) ---- drb4 = total memory in row0 + row1 + row2 + row3 + (in 32 mbytes) note: the number of drb registers and number of bits per drb register are system dependent. for example, a system that supports 4 rows of sdram and a max memory of 1.0 gb needs only 4 drb registers and 4 bits per drb. gmch-m supports four physical rows of single data rate sdram in 2 so-dimms. the width of a row is 64 bits. each so-dimm/row is represented by a byte. each byte has the following format. gmch-m supported maximum memory size: 1.0 gb. bit description 7:0 sdram row boundary address : this 8-bit value defines the upper and lower addresses for each sdram row. bits 6:0 of this field are compared against the address lines a[31:25] to determine the upper address limit of a particular row. bit 7 must be zero. default value=0000/0000.
intel ? 830 chipset family 298338-003 datasheet 89 r 4.5.1.20 dra ? dram row attribute register - device #0 address offset: 70-71h default value: ffh access: read/write (read_only if d_lck = 1) size: 8 bits row0, 1: 70h row2, 3: 71h row attribute register defines the page size of each row. 7 6 4 3 2 0 r row attribute for row1 r row attribute for row0 7 6 4 3 2 0 r row attribute for row3 r row attribute for row2 bit description 3:0(7:4) row attribute : this 4-bit filed defines the page size of the row. page size is dependent on the technology as shown in the table below. bits 3:0 page size ?0000? 2 kb ?0001? 4 kb ?0010? 8 kb ?0011? 16 kb. ?1111? empty row. all other combinations are reserved. default value=1111.
intel ? 830 chipset family 90 datasheet 298338-003 r 4.5.1.21 drt?dram timing register - device #0 address offset: 78-7bh default value: 00000010h access: read/write size: 32 bits this register controls the timing of the sdram controller. bit description 31:19 reserved 18:16 dram idle timer: this field determines the number of clocks the sdram controller allows a row in the idle state (un-accessed) before pre-charging all pages in that row; or powering down that row based on the settings of bit 28 and bit 14 of drc. bit[18:16 ] idle clocks before action 0 0 0 infinite (counter is disabled and no action is taken) 0 0 1 0 (not supported on gmch-m as this setting requires auto precharge) 0 1 0 8 0 1 1 16 1 0 0 64 1 0 1 256 1 1 0 512 1 1 1 1024 drc 28 drc 14 action on counter expiration. (pwr dwn enbl) (page cls enbl) 0 0 none (counter disabled) 0 1 pre-charge all 1 0 power down and deassert cke, pages open. 1 1 pre-charge all, power down and deassert cke default value=000. recommended settings for drc 28=1, drc 14=1 and drt 18:16 =010. 15:11 reserved 10 activate to precharge delay (tras). this bit controls the number of clks for tras. 0 = tras = 7 clks 1 = tras = 5 clks. default value=0. 9:6 reserved 5:4 cas# latency (tcl). this bit controls the number of clks between when a read command is sampled by the sdram and when gmch-m samples read data from the sdram. 00 = reserved 01 = 3 10 = 2 11 = reserved default value=01. 3 reserved
intel ? 830 chipset family 298338-003 datasheet 91 r bit description 2 dram ras# to cas# delay (trcd). this bit controls the number of clks from a row activate command to a read or write command. 0 = 3 clocks will be inserted between a row activate command and either a read or write command. 1 = 2 clocks will be inserted between a row activate command and either a read or write command. default value=0. 1 reserved 0 dram ras# precharge (trp). this bit controls the number of clks for ras# pre-charge. 0 = 3 clocks of ras# pre-charge are provided. 1 = 2 clocks of ras# pre-charge are provided default value=0.
intel ? 830 chipset family 92 datasheet 298338-003 r 4.5.1.22 drc - dram controller mode register - device #0 address offset: 7c-7fh default value: 00000000h access: read/write size: 32 bits bit description 31:30 specification revision number. hardwired to ? 00 ? on gmch-m. 29 initialization complete (ic): setting this bit to a ?1? enables sdram refreshes. on power up and s3 exit, the bios initializes the sdram array and sets this bit to a ?1?. this bit works in combination with the rms bits in controlling refresh state: ic rms refresh state 0 xxx off x 000 off 1 001 on 1 010 on 1 011 on 1 111 on default value=0. 28 dram row power- mgmt enable: when this bit is set to a 1, a sdram row is powered down (issued a power down command and cke deasserted) after the sdram idle timer (as programmed in drt) expires. during a refresh, rows in the low power state are powered up and refreshed. hence, coming out of a refresh all rows will be powered up. default value=0. 27 reserved. 26:24 active row count: this field determines the number of rows the sdram controller allows in the active state if sdram row power management is enabled (bit 28). all populated rows not in the active state are in power down. an access to a row in power down will cause that row to exit power down, following that the lru row is placed into power down if the number of active rows is greater than that allowed by this register (see bios specification for the latest value. to receive the bios specification, contact your intel field representative). bit[26:24 ] maximum number of active rows 0 0 0 all rows allowed to be in active state. 0 0 1 1 row 0 1 0 2 rows 0 1 1 3 rows 1 0 0 4 rows 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved default value=000. 23:20 reserved 19:15 reserved 14 page close enable: when this bit is set to a 1, sdram row pages are closed after the sdram idle timer (as programmed in drt) expires. default value=0. 13:11 reserved
intel ? 830 chipset family 298338-003 datasheet 93 r bit description 10:8 refresh mode select (rms) : bits determine if refresh is enabled and refresh rate. 000: refresh disabled. 001: refresh enabled. refresh interval 15.6 s. 010: refresh enabled. refresh interval 7.8 s. 011: reserved 111: refresh enabled. refresh interval 128 clocks. (fast refresh mode) all other combinations are reserved. default value=000. 7 reserved 6:4 mode select (sms). these bits select the special operational mode of the gmch-m sdram interface. the special modes are intended for initialization at power up. 000 = self refresh (default): in this mode, ckes are deasserted. all other values cause cke assertion. the exception is in c3/s1/s3 this register is programmed to ?normal operation?, the drams are in self-refresh, and ckes are deasserted. 001 = nop command enable: in this mode all cpu cycles to sdram result in a nop command on the sdram interface. 010 = all banks pre-charge enable: in this mode all cpu cycles to sdram result in an all banks pre-charge command on the sdram interface. 011 = mode register set enable: in this mode all cpu cycles to sdram result in a mode register set command on the sdram interface. the command is driven on the ma[12:0] lines. ma[2:0] must always be driven to 010 for burst of 4 mode. ma3 must be driven to 1 for interleave wrap type. ma[6:4] needs to be driven based on the value programmed in the cas# latency field. cas latency ma[6:4 ] 2 clocks 010 3 clocks 011 ma[12:7] must be driven to 00000. bios must calculate and drive the correct host address for each row of memory such that the correct command is driven on the ma[12:0] lines. 100 = reserved. 101 = reserved. 110 = cbr refresh enable. in this mode all cpu cycles to sdram result in a cbr cycle on the sdram interface. 111 = normal operation. default value=000. 3:2 reserved 1:0 reserved
intel ? 830 chipset family 94 datasheet 298338-003 r 4.5.1.23 dtc - dram throttling control register - device #0. offset address: 8c-8fh default value: 0000_0000h access: read/write/lock size: 32 bits throttling is independent for reads and writes. if the number of oct-words (16 bytes) read/written during this window exceeds the dram bandwidth threshold defined below, then the dram throttling mechanism will be invoked to limit dram reads/writes to a lower bandwidth checked over smaller time windows. the throttling will be active for the remainder of the current gdws and for the next gdsw after which it will return to non-throttling mode. the throttling mechanism accounts for the actual bandwidth consumed during the sampling window, by reducing the allowed bandwidth within the smaller throttling window based on the bandwidth consumed during the sampling period. bits description 31 throttle lock (tlock): this bit secures the sdram throttling control register. once a ?1? is written to this bit, all of the configuration register bits in dtc (including tlock) documented below become read- only. default value=0. 30 intel reserved 29:28 dram throttle mode (tmode): bits mode 0 0 throttling turned off. 0 1 bandwidth counter mechanism is enabled. when bandwidth exceeds threshold set in the r/w ptc field, dram read/write throttling begins. 1 0 thermal sensor based throttling enabled. when the device?s thermal sensor is tripped dram write throttling begins based on settings programmed in wptc. read throttling is disabled. 1 1 with this setting thermal sensor and dram counter mechanisms are both enabled. however, read throttling is bandwidth counter triggered only while write throttling is thermal sensor or counter triggered. both read and write throttling mechanisms use programmed values in the throttle control registers. default value=00 27 : 26 reserved 25:24 read power throttle control. these bits select the power throttle bandwidth limits for read operations to system memory. r/w, ro if throttle lock. bits power throttle bandwidth limit 00 no limit (default) 01 limit at 65% 10 limit at 55% 11 limit at 45% default value=00 23:22 reserved 21:20 write power throttle control. these bits select the power throttle bandwidth limits for write operations to system memory.
intel ? 830 chipset family 298338-003 datasheet 95 r bits description r/w, ro if throttle lock. bits power throttle bandwidth limit 00 no limit (default) 01 limit at 65% 10 limit at 55% 11 limit at 45% default value=00 19:16 reserved 15:8 global dram sampling window (gdsw) : this eight bit value is multiplied by 4 to define the length of time in milliseconds (0-1020) over which the number of octwords (16 bytes) read/written is counted and throttling is imposed. default value=00000000. 7:0 reserved
intel ? 830 chipset family 96 datasheet 298338-003 r 4.5.1.24 smram - system management ram control register - device #0 address offset: 90h default value: 02h access: read/write/lock, read only size: 8 bits the smram register controls how accesses to compatible and extended smram spaces are treated. the open, close, and lock bits function only when g_smrame bit is set to a 1. also, the open bit must be reset before the lock bit is set. bit description 7 reserved 6 smm space open (d_open): when d_open=1 and d_lck=0, the smm space sdram is made visible even when smm decode is not active. this is intended to help bios initialize smm space. software should ensure that d_open=1 and d_cls=1 are not set at the same time. when d_lck is set to a 1, d_open is reset to 0 and becomes read only. default value=0. 5 smm space closed (d_cls) : when d_cls = 1 smm space dram is not accessible to data references, even if smm decode is active. code references may still access smm space sdram. this will allow smm software to reference "through" smm space to update the display even when smm is mapped over the vga range. software should ensure that d_open=1 and d_cls=1 are not set at the same time. default value=0. 4 smm space locked (d_lck): when d_lck is set to 1 then d_open is reset to 0 and d_lck, d_open, g_smrame, c_base_seg, gms, drb, dra, h_smram_en, tseg_sz and tseg_en become read only. gba[15:0] and gar[15:0] associated with the sdram controller also become read only after d_lck is set. d_lck can be set to 1 via a normal configuration space write but can only be cleared by a full reset. the combination of d_lck and d_open provide convenience with security. the bios can use the d_open function to initialize smm space and then use d_lck to "lock down" smm space in the future so that no application software (or bios itself) can violate the integrity of smm space, even if the program has knowledge of the d_open function. default value=0. 3 global smram enable (g_smrame). if set to a 1, then compatible smram functions is enabled, providing 128 kb of sdram accessible at the a0000h address while in smm (ads# with smm decode). to enable extended smram function this bit has be set to 1. refer to the section on smm for more details. once d_lck is set, this bit becomes read only. default value=0. 2:0 compatible smm space base segment (c_base_seg) (ro) . this field indicates the location of smm space. "smm dram" is not remapped. it is simply "made visible" if the conditions are right to access smm space, otherwise the access is forwarded to hub interface. c_base_seg is hardwired to 010 to indicate that the gmch-m supports the smm space at a0000h- bffffh. default value=010.
intel ? 830 chipset family 298338-003 datasheet 97 r 4.5.1.25 esmramc - extended system management ram control register - device #0 address offset: 91h default value: 38h access: read/write size: 8 bits the extended smram register controls the configuration of extended smram space. the extended smram (e_smram) memory provides a write-back cacheable smram memory space that is above 1 mb. bit description 7 h_smram_en (h_smrame): controls the smm memory space location (i.e. above 1 mb or below 1 mb). when g_smrame is 1 and h_smrame this bit is set to 1, the high smram memory space is enabled. smram accesses from 0feda0000h to 0fedbffffh are remapped to sdram address 000a0000h to 000bffffh. once d_lck is set, this bit becomes read only. default value=0. 6 e_smram_err (e_smerr): this bit is set when cpu accesses the defined memory ranges in extended smram (high memory and t-segment) while not in smm space and with the d-open bit = 0. it is software?s responsibility to clear this bit. the software must write a 1 to this bit to clear it default value=0. 5 smram_cache (sm_cache) : this bit is forced to ?1? by the gmch-m . default value=1. 4 smram_l1_en (sm_l1): this bit is forced to ?1? by the gmch-m. default value=1. 3 smram_l2_en (sm_l2): this bit is forced to ?1? by the gmch-m. default value=1. 2 reserved 1 tseg_sz(t_sz): selects the size of the tseg memory block if enabled. this memory is taken from the top of sdram space (i.e. tom - tseg_sz), which is no longer claimed by the memory controller. this field decodes as follows: tseg_sz description 0 (tom-512k) to tom 1 (tom-1m) to tom once d_lck is set, this bit becomes read only. default value=0. 0 tseg_en (t_en): enabling of smram memory (tseg, 512 kbytes or 1 mbytes of additional smram memory) for extended smram space only. when g_smrame =1 and tseg_en = 1, the tseg is enabled to appear in the appropriate physical address space. once d_lck is set, this bit becomes read only . default value=0.
intel ? 830 chipset family 98 datasheet 298338-003 r 4.5.1.26 errsts ? error status register ? device #0 address offset: 92-93h default value: 0000h access: read/write clear size: 16 bits this register is used to report various error conditions via hub interface special cycles. an serr, smi, or sci error hub interface special cycle may be generated on a zero to one transition of any of these flags when enabled in the pcicmd/errcmd, smicmd, or scicmd registers respectively. bit description 15:13 reserved 12 gmch software generated event for smi. this indicates the source of the smi was a device#2 software event for the local memory interface. software must write a ?1? to clear this bit. (local memory no longer supported.) 11 reserved 10 reserved 9 lock to non-dram memory flag (lckf). (r/wc) when this bit is set it indicates that a cpu initiated lock cycle targeting non-dram memory space occurred. software must write a ?1? to clear this status bit. 8 received refresh timeout. this bit is set when 1024 memory core refresh are queued up. software must write a ?1? to clear this status bit. 7 dram throttle flag (dtf) (r/wc). when this bit is set it indicates that the dram throttling condition occurred. software must write a ?1? to clear this status bit. 6 reserved 5 received unimplemented special cycle hub interface completion packet flag (unsc) (r/wc). when this bit is set, it indicates that the gmch initiated a hub interface request that was terminated with an unimplemented special cycle completion packet. software must write a ?1? to clear this status bit. 4 agp access outside of graphics aperture flag (oogf). (r/wc) when this bit is set it indicates that an agp access occurred to an address that is outside of the graphics aperture range. software must write a ?1? to clear this status bit. note: agp is available only with the intel 830m and 830mp chipset. 3 invalid agp access flag (iaaf). (r/wc) when this bit is set to ?1? it indicates that an agp access was attempted outside of the graphics aperture and either to the 640k - 1m range or above the top of memory. software must write a ?1? to clear this status bit. note: agp is available only with the intel 830m and 830mp chipset. 2 invalid graphics aperture translation table entry flag (ittef). (r/wc) when this bit is set to ?1?, it indicates that an invalid translation table entry was returned in response to an agp access to the graphics aperture. software must write a ?1? to clear this status bit. invalid translation table entries include the following: invalid bit set in table entry. translated address hits pam region. translated address hits enabled physical smm space. note: agp is available only with the intel 830m and 830mp chipset. 1-0 reserved
intel ? 830 chipset family 298338-003 datasheet 99 r 4.5.1.27 errcmd - error command register - device #0 address offset: 94-95h default value: 0000h access: read/write size: 16 bits this register enables various errors to generate an serr hub interface special cycle. since the gmch- m does not have an serr# signal, serr messages are passed from the gmch-m to the ich3-m over the hub interface. the actual generation of the serr message is globally enabled for device #0 via the pci command register. note: an error can generate one and only one hub interface error special cycle. the software is responsible to ensure that when an serr error message is enabled for an error condition, smi and sci error messages are disabled for that same error condition. bit description 15:10 reserved 9 serr on lock to non-sdram memory . when this bit is set to ?1?, the gmch-m generates an serr hub interface special cycle when a cpu initiated lock transaction targeting non-sdram memory space occurs. if this bit is ?0? then reporting of this condition is disabled. default value=0. 8 serr on sdram refresh timeout . when this bit is set to ?1?, the gmch-m generates an serr hub interface special cycle when a sdram refresh timeout occurs. if this bit is ?0? then reporting of this condition is disabled. default value=0. 7 serr on sdram throttle condition . when this bit is set to ?1?, the gmch-m generates an serr hub interface special cycle when a sdram read or write throttle condition occurs. if this bit is ?0? then reporting of this condition is disabled. default value=0. 6 serr on receiving target abort on hub interface . when this bit is set to ?1?, the gmch-m generates an serr hub interface special cycle when a gmch-m originated hub interface cycle is terminated with a target abort. if this bit is ?0? then reporting of this condition is disabled. default value=0. 5 serr on receiving unimplemented special cycle hub interface completion packet . when this bit is set to ?1?, the gmch-m generates an serr hub interface special cycle when a gmch-m initiated hub interface request is terminated with a unimplemented special cycle completion packet. if this bit is ?0? then reporting of this condition is disabled. default value=0. 4 serr on agp access outside of graphics aperture . when this bit is set to ?1?, the gmch-m generates an serr hub interface special cycle when an agp access occurs to an address outside of the graphics aperture. if this bit is ?0? then reporting of this condition is disabled. default value=0. note: agp is available only with the intel 830m and 830mp chipset. 3 serr on invalid agp access . when this bit is set to ?1?, the gmch-m generates an serr hub interface special cycle when an agp access occurs to an address outside of the graphics aperture and either to the 640k - 1m range or above the top of memory.
intel ? 830 chipset family 100 datasheet 298338-003 r default value=0. note: agp is available only with the intel 830m and 830mp chipset. 2 serr on access to invalid graphics aperture translation table entry . when this bit is set to ?1?, the gmch-m generates an serr hub interface special cycle when an invalid translation table entry was returned in response to a agp access to the graphics aperture. if this bit is ?0? then reporting of this condition via serr messaging is disabled. default value=0. note: agp is available only with the intel 830m and 830mp chipset. 1-0 reserved table 28. summary of gmch-m error sources, enables and status flags error event hub i/f message enable bits required to be set status flags set sdram refresh timeout serr pcicmd bit 8 errcmd bit 8 pcists bit 14 errsts bit 8 cpu lock to non-sdram memory serr pcicmd bit 8 errcmd bit 9 pcists bit 14 errsts bit 9 sdram throttle serr pcicmd bit 8 errcmd bit 7 pcists bit 14 errsts bit 7 received hub interface target abort serr pcicmd bit 8 errcmd bit 6 pcists bit 14 pcists bit 12 unimplemented special cycle serr pcicmd bit 8 errcmd bit 5 pcists bit 14 errsts bit 5 agp access outside of graphics aperture serr pcicmd bit 8 errcmd bit 4 pcists bit 14 errsts bit 4 invalid agp access serr pcicmd bit 8 errcmd bit 3 pcists bit 14 errsts bit 3 access to invalid gtlb entry serr pcicmd bit 8 errcmd bit 2 pcists bit 14 errsts bit 2 agp pci parity error detected serr pcicmd1 bit 8 bctrl bit 0 pcists1 bit 14 ssts bit 15 agp pci received target abort serr pcicmd1 bit 8 errcmd1 bit 0 pcists1 bit 14 ssts bit 12
intel ? 830 chipset family 298338-003 datasheet 101 r 4.5.1.28 acapid - agp capability identifier register - device #0 address offset: a0-a3h default value: 00200002h access: read only size: 32 bits this register provides standard identifier for agp capability. this register is read only when either the intel 830m or intel 830mg internal graphics device is used. bit description 31:24 reserved 23:20 major agp revision number : these bits provide a major revision number of agp specification to which this version of gmch-m conforms. these bits are set to the value 0010 to indicate agp rev. 2.x. default value=0010. 19:16 minor agp revision number : these bits provide a minor revision number of agp specification to which this version of gmch-m conforms. this number is hardwired to value of 0000 (i.e. implying rev x.0). together with major revision number, this field identifies gmch-m as an agp rev 2.0 compliant device. default value=0000. 15:8 next capability pointer : agp capability is the last capability described via the capability pointer mechanism and therefore these bits are hardwired to 00h to indicate the end of the capability linked list. default value=0000/0000. 7:0 agp capability id : this field identifies the linked list item as containing agp registers. this field has the value 02h as assigned by the pci sig. default value=0000/0010.
intel ? 830 chipset family 102 datasheet 298338-003 r 4.5.1.29 agpstat - agp status register - device #0 address offset: a4-a7h default value: 1f000217h access: read only size: 32 bits this register reports agp device capability/status. this register is read only when either the intel 830m or intel 830mg internal graphics device is used. bit description 31:24 request queue . this field is hardwired to 1fh to indicate a maximum of 32 outstanding agp command requests can be handled by the gmch-m. default =1fh to allow a maximum of 32 outstanding agp command requests. default value=00011111. 23:10 reserved 9 sba . this bit indicates that the gmch-m supports side band addressing. it is hardwired to 1. 8:6 reserved 5 4g . this bit indicates that the gmch-m does not support addresses greater than 4 gb. it is hardwired to 0. 4 fast writes the gmch-m supports fast writes from the cpu to the agp master. fast writes are disabled. default value=1. 3 reserved 2:0 rate . after reset the gmch-m reports its data transfer rate capability. bit 0 identifies if agp device supports 1x data transfer mode bit 1 identifies if agp device supports 2x data transfer mode bit 2 identifies if agp device supports 4x data transfer mode. 1x, 2x, and 4x data transfer modes are supported by the gmch-m. note: the selected data transfer mode applies to both ad bus and sba bus. default value=111.
intel ? 830 chipset family 298338-003 datasheet 103 r 4.5.1.30 agpcmd - agp command register - device #0 address offset: a8-abh default value: 00000000h access: read/write size: 32 bits this register provides control of the agp operational parameters. this register is read only when either the intel 830m or intel 830mg internal graphics device is used. bit description 31:10 reserved 9 sba enable . when this bit is set to 1, the side band addressing mechanism is enabled. default value=0. 8 agp enable . when this bit is reset to 0, the gmch-m will ignore all agp operations, including the sync cycle. any agp operations received while this bit is set to 1 will be serviced even if this bit is reset to 0. if this bit transitions from a 1 to a 0 on a clock edge in the middle of an sba command being delivered in 1x mode the command will be issued. when this bit is set to 1 the gmch-m will respond to agp operations delivered via pipe#, or to operations delivered via sba if the agp side band enable bit is also set to 1. default value=0. 7:6 reserved 5 4g . the gmch-m as an agp target does not support addressing greater than 4 gb. this bit is hardwired to 0. 4 fast write enable when set to ?1? gmch-m agp master supports fast writes. when set to ?0? fast writes are disabled. default value=0. 3 reserved 2:0 data rate : the settings of these bits determine the agp data transfer rate. one (and only one) bit in this field must be set to indicate the desired data transfer rate. 001 = 1x (bit 0) 010 = 2x (bit 1) 100 = 4x (bit 2) the same bit must be set on both master and target. configuration software will update this field by setting only one bit that corresponds to the capability of agp master (after that capability has been verified by accessing the same functional register within the agp masters configuration space.) note that the selected data transfer mode applies to both ad bus and sba bus. default value=000
intel ? 830 chipset family 104 datasheet 298338-003 r 4.5.1.31 agpctrl - agp control register - device #0 address offset: b0-b1h default value: 00000000h access: read/write size: 32 bits this register provides for additional control of the agp interface. this register is read only when either the intel 830m or intel 830mg internal graphics device is used. bit description 31:8 reserved 7 gtlb enable (and gtlb flush control) (r/w): note : this bit can be changed dynamically (i.e. while an access to gtlb occurs). default value=0. 6:0 reserved 4.5.1.32 aft ? agp functional test register ? device #0 address offset: b2-b3h default value: 0000h access: read/write size: 16 bits this register provides for additional control of the agp interface. this register is read only when either the intel 830m or intel 830mg internal graphics device is used. bit description 15:10 reserved 9 pci read buffer disable. (rw) when set to ?1? is disabled. in this mode all data pre-fetched and buffered for a pci-to-dram read will be discarded when that read transaction terminates. this bit defaults to ?0?. 8:4 agp pci1 discard timer time-out count. (rw) these bits control the length of agp/pci1 delayed transaction discard time-out for the purpose of enhancing the system testability. default value is 11111b (31d) for a discard count of 1024d ((value+1)*32). 3:0 reserved
intel ? 830 chipset family 298338-003 datasheet 105 r 4.5.1.33 apsize ? ? ? ? aperture size - device #0 address offset: b4h default value: 00h access: read/write size: 8 bits this register determines the effective size of the graphics aperture. this register can be updated by the gmch-m-specific bios configuration sequence before the pci standard bus enumeration sequence. if the register is not updated then a default value will select an aperture of maximum size (i.e. 256 mb). the size of the table that will correspond to a 256 mb aperture is not practical for most applications and therefore these bits must be programmed to a smaller practical value that will force adequate address range to be requested via apbase register from the pci configuration software. this register is read only when either the intel 830m or intel 830mg internal graphics device is used. bit description 7:6 reserved 5:3 graphics aperture size (apsize) (r/w): each bit in apsize[5:3] operates on similarly ordered bits in apbase[27:25] of the aperture base configuration register. when a particular bit of this field is ?0?, it forces the similarly ordered bit in apbase[27:25] to behave as ?hardwired? to 0. when a particular bit of this field is set to ?1?, it allows the corresponding bit of the apbase[27:25] to be read/write accessible. only the following combinations are allowed when the aperture is enabled: bits[5:3] aperture size 1 1 1 32 mb 1 1 0 64 mb 1 0 0 128 mb 0 0 0 256 mb default for apsize[5:3]=000b forces default apbase[27:25] =000b (i.e. all bits respond as ?hardwired? to 0). this provides maximum aperture size of 256 mb. as another example, programming apsize[5:3]=111b enables apbase[27:25] as read/write programmable. 2:0 reserved
intel ? 830 chipset family 106 datasheet 298338-003 r 4.5.1.34 attbase ? ? ? ? aperture translation table base register - device #0 address offset: b8-bbh default value: 00000000h access: read/write size: 32 bits this register provides the starting address of the graphics aperture translation table base located in the main dram. this value is used by the gmch-m?s graphics aperture address translation logic (including the gtlb logic) to obtain the appropriate address translation entry required during the translation of the aperture address into a corresponding physical dram address. the attbase register may be dynamically changed. this register is read only when either the intel 830m or intel 830mg internal graphics device is used. note: the address provided via attbase is 4-kb aligned. bit description 31: 12 this field contains a pointer to the base of the translation table used to map memory space addresses in the aperture range to addresses in main memory. 11:0 reserved 4.5.1.35 amtt ? ? ? ? agp interface multi-transaction timer register - device #0 address offset: bch default value: 00h access: read/write size: 8 bits amtt is an 8-bit register that controls the amount of time that the gmch-m?s arbiter allows the agp/pci master to perform multiple back-to-back transactions. the gmch-m?s amtt mechanism is used to optimize the performance of the agp master (using pci semantics) that performs multiple back- to-back transactions to fragmented memory ranges (and as a consequence cannot use long burst transfers). the amtt mechanism applies to the cpu-agp/pci transactions as well and it guarantees to the cpu a fair share of the agp/pci interface bandwidth. the number of clocks programmed in the amtt represents the guaranteed time slice (measured in 66- mhz clocks) allotted to the current agent (either agp pci master or host bridge) after which the agp arbiter may grant the bus to another agent. the default value of amtt is 00h and disables this function. the amtt value can be programmed with 8-clock granularity. for example, if the amtt is programmed to 18h, then the selected value corresponds to the time period of 24 agp (66-mhz) clocks. this register is read only when either the intel 830m or intel 830mg internal graphics device is used. bit description 7:3 multi-transaction timer count value . the number programmed in these bits represents the guaranteed time slice (measured in eight 66-mhz clock granularity) allotted to the current agent (either agp pci master or host bridge) after which the agp arbiter may grant the bus to another agent. 2:0 reserved
intel ? 830 chipset family 298338-003 datasheet 107 r 4.5.1.36 lptt ? ? ? ? low priority transaction timer register - device #0 address offset: bdh default value: 00h access: read/write size: 8 bits lptt is an 8-bit register similar in a function to amtt. this register is used to control the minimum tenure on the agp for low priority data transaction (both reads and writes) issued using pipe# or sideband mechanisms. the number of clocks programmed in the lptt represents the guaranteed time slice (measured in 66- mhz clocks) allotted to the current low priority agp transaction data transfer state. this does not necessarily apply to a single transaction but it can span over multiple low-priority transactions of the same type. after this time expires the agp arbiter may grant the bus to another agent if there is a pending request. the lptt does not apply in the case of high-priority request where ownership is transferred directly to the high-priority requesting queue. the default value of lptt is 00h and disables this function. the lptt value can be programmed with 8-clock granularity. for example, if the lptt is programmed to 10h, then the selected value corresponds to the time period of 16 agp (66-mhz) clocks. this register is read only when either the intel 830m or intel 830mg internal graphics device is used. bit description 7:3 low priority transaction timer count value . the number of clocks programmed in these bits represents the guaranteed time slice (measured in eight 66-mhz clock granularity) allotted to the current low priority agp transaction data transfer state. 2:0 reserved
intel ? 830 chipset family 108 datasheet 298338-003 r 4.5.1.37 buff_sc ? system memory buffer strength control register - device #0 address offset: ec-efh default value: 00000000h access: read/write size 32 bits 4.5.1.37.1 sdr drive strength register description the system memory buffer strength control register programs drive strengths and slew rate and for each buffer category based on loading detected by spd. cs#, cke, and clk buffers have independent control for each so-dimm and are programmed to the same strength for front and back side of each so-dimm. if the bios detects different loading on the backside of the so-dimm (i.e. 96 mb), it should ignore the devices on the backside of the so-dimm. bit descriptions 31 reserved 30 clk[3:2] slew rate . this field sets the slew rate of the clk[3:2] pins. 0 = normal slew rate. 1 = fast slew rate for reduced tco. default value=0. 29 clk[1:0] slew rate . this field sets the slew rate of the clk[1:0] pins. 0 = normal slew rate. 1 = fast slew rate for reduced tco. default value=0. 28 reserved 27 cs[3:2]#, cke[3:2] slew rate . this field sets the slew rate of the cs[3:2]#, cke[3:2] pins. 0 = normal slew rate. 1 = fast slew rate for reduced tco. default value=0. 26 cs[1:0]#, cke[1:0] slew rate . this field sets the slew rate of the cs[1:0]#, cke[1:0] pins. 0 = normal slew rate. 1 = fast slew rate for reduced tco. default value=0. 25 dq[63:0], dqm[7:0] slew rate . this field sets the slew rate of the dq[63:0], dqm[7:0] pins. 0 = normal slew rate. 1 = fast slew rate for reduced tco. default value=0. 24 ma[12:0], ba[1:0], ras#, cas#, we# slew rate . this field sets the slew rate of the ma[12:0], ba[1:0], ras#, cas#, we# pins. 0 = normal slew rate. 1 = fast slew rate for reduced tco. default value=0. 23:21 reserved 20:18 clk[3:2] buffer strength . this field sets the buffer strength of the clk[3:2] pins.
intel ? 830 chipset family 298338-003 datasheet 109 r 000 = 0.75x 001 = 1x 010 = 1.25x 011 = 1.5x 100 = 2x 101 = 2.5x 110 = 3x 111 = 4x default value=000. 17:15 clk[1:0] buffer strength . this field sets the buffer strength of the clk[1:0] pins. 000 = 0.75x 001 = 1x 010 = 1.25x 011 = 1.5x 100 = 2x 101 = 2.5x 110 = 3x 111 = 4x default value=000. 14:12 reserved 11:9 cs[3:2]#, cke[3:2] buffer strength . this field sets the buffer strength of the cs[3:2]#, cke[3:2] pins. 000 = 0.75x 001 = 1x 010 = 1.25x 011 = 1.5x 100 = 2x 101 = 2.5x 110 = 3x 111 = invalid default value=000. 8:6 cs[1:0]#, cke[1:0] buffer strength . this field sets the buffer strength of the cs[1:0]#, cke[1:0] pins. 000 = 0.75x 001 = 1x 010 = 1.25x 011 = 1.5x 100 = 2x 101 = 2.5x 110 = 3x 111 = invalid default value=000. 5:3 dq[63:0], dqm[7:0] buffer strength . this field sets the buffer strength of the dq[63:0], dqm[7:0] pins. 000 = 0.75x 001 = 1x 010 = 1.25x
intel ? 830 chipset family 110 datasheet 298338-003 r 011 = 1.5x 100 = 2x 101 = 2.5x 110 = 3x 111 = invalid default value=000. 2:0 ma[12:0], ba[1:0], ras#, cas#, we# buffer strength . this field sets the buffer strength of the ma[12:0], ba[1:0], ras#, cas#, we# pins. 000 = 0.75x 001 = 1x 010 = 1.25x 011 = 1.5x 100 = 2x 101 = 2.5x 110 = 3x 111 = invalid default value=000.
intel ? 830 chipset family 298338-003 datasheet 111 r 4.5.2 830m and 830mp chipset host-agp bridge registers - device #1 table 29 summarizes the gmch-m configuration space for device #1. device 1 applies to both the intel 830mp and 830m chipset. table 29. host-agp bridge configuration space (device #1) address offset register symbol register name default value access 00-01h vid1 vendor identification 8086h ro 02-03h did1 device identification 3576h ro 04-05h pcicmd1 pci command register 0000h ro, r/w 06-07h pcists1 pci status register 0020h ro, r/wc 08 rid1 revision identification 00h ro 09 - intel reserved - - 0ah subc1 sub-class code 04h ro 0bh+ bcc1 base class code 06h ro 0ch - intel reserved - - 0dh mlt1 master latency timer 00h r/w 0eh hdr1 header type 01h ro 0f-17h - intel reserved - - 18h pbusn primary bus number 00h ro 19h sbusn secondary bus number 00h r/w 1ah subusn subordinate bus number 00h r/w 1bh smlt secondary bus master latency timer 00h r/w 1ch iobase i/o base address register f0h r/w 1dh iolimit i/o limit address register 00h r/w 1e-1fh ssts secondary status register 02a0h ro, r/wc 20-21h mbase memory base address register fff0h r/w 22-23h mlimit memory limit address register 0000h r/w 24-25h pmbase prefetchable memory base address reg. fff0h r/w 26-27h pmlimit prefetchable memory limit address reg. 0000h r/w 28-3dh - intel reserved - - 3eh bctrl bridge control register 00h r/w 3fh - intel reserved - - 40h errcmd1 error command 00h r/w 41-ffh - intel reserved - -
intel ? 830 chipset family 112 datasheet 298338-003 r 4.5.2.1 vid1 - vendor identification register - device #1 address offset: 00 - 01h default value: 8086h attribute: read only size: 16 bits the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 vendor identification number . this is a 16-bit value assigned to intel. intel vid = 8086h. default value=1000/0000/1000/0110. 4.5.2.2 did1 - device identification register - device #1 address offset: 02 - 03h default value: 3576h attribute: read only size: 16 bits this 16-bit register combined with the vendor identification register uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 device identification number. this is a 16-bit value assigned to the gmch-m device #1.gmch-m device #1 did =3576h. default value=0011/0101/0111/0110.
intel ? 830 chipset family 298338-003 datasheet 113 r 4.5.2.3 pcicmd1 - pci-pci command register - device #1 address offset: 04-05h default value: 0000h access: read/write, read only size 16 bits bit descriptions 15:10 reserved 9 fast back-to-back: not applicable-hardwired to 0 . default value=0. 8 serr message enable (serre1) . this bit is a global enable bit for device #1 serr messaging. the gmch-m does not have an serr# signal. the gmch-m communicates the serr# condition by sending an serr message to the ich3-m. if this bit is set to a 1, the gmch-m is enabled to generate serr messages over hub interface for specific device #1 error conditions that are individually enabled in the bctrl register. the error status is reported in the pcists1 register. if serre1 is reset to 0, then the serr message is not generated by the gmch-m for device #1. note : this bit only controls serr messaging for the device #1. device #0 has its own serre bit to control error reporting for error conditions occurring on device #0. the two control bits are used in a logical or manner to enable the serr hub interface message mechanism. default value=0. 7 address/data stepping: not applicable. hardwired to 0. 6 parity error enable (perre1) : perr# is not supported on agp/pci1. hardwired to 0. 5 reserved 4 memory write and invalidate enable: (ro) this bit is implemented as read only and returns a value of ?0? when read. default value=0. 3 special cycle enable: (ro) this bit is implemented as read only and returns a value of ?0? when read. default value=0. 2 bus master enable (bme1): (r/w) when the bus master enable is set to ?0? (default), agp master initiated frame# cycles will be ignored by the gmch-m resulting in a master abort. ignoring incoming cycles on the secondary side of the p2p bridge effectively disables the bus master on the primary side. when bus master enable is set to ?1?, agp master initiated frame# cycles will be accepted by the gmch-m if they hit a valid address decode range this bit has no effect on agp master originated sba or pipe# cycles. default value=0. 1 memory access enable (mae1): (r/w) this bit must be set to ?1? to enable the memory and prefetchable memory address ranges defined in the mbase, mlimit, pmbase, and pmlimit registers. when set to ?0?, all of device #1?s memory space is disabled. default value=0. 0 i/o access enable (ioae1): (r/w) this bit must be set to ?1? to enable the i/o address range defined in the iobase, and iolimit registers. when set to ?0? all of device #1?s i/o space is disabled. default value=0.
intel ? 830 chipset family 114 datasheet 298338-003 r 4.5.2.4 pcists1 - pci-pci status register - device #1 address offset: 06-07h default value: 0020h access: read only, read/write clear size: 16 bits pcists1 is a 16-bit status register that reports the occurrence of error conditions associated with primary side of the ?virtual? pci-pci bridge embedded within the gmch-m. since this device does not physically reside on pci0 it reports the optimum operating conditions so that it does not restrict the capability of pci0. bit descriptions 15 detected parity error (dpe1): not applicable - hardwired to ?0?. 14 signaled system error (sse1). this bit is set to 1 when gmch-m device #1 generates an serr message over hub interface for any enabled device #1 error condition. device #1 error conditions are enabled in the pcicmd1 and bctrl registers. device #1 error flags are read/reset from the ssts register. software clears this bit by writing a 1 to it. default value=0. 13 received master abort status (rmas1): not applicable - hardwired to ?0?. 12 received target abort status (rtas1): not applicable - hardwired to ?0?. 11 signaled target abort status (stas1): not applicable - hardwired to ?0?. 10:9 devsel# timing (devt1): not applicable - hardwired to ?00?. 8 data parity detected (dpd1): not applicable - hardwired to ?0?. 7 fast back-to-back (fb2b1): not applicable - hardwired to ?0?. 6 reserved 5 66/60 mhz capability: not applicable - hardwired to ?1?. 4:0 reserved
intel ? 830 chipset family 298338-003 datasheet 115 r 4.5.2.5 rid1 - revision identification register - device #1 address offset: 08h default value: 03h (a5 silicon) 04h (a6 silicon) access: read only size: 8 bits this register contains the revision number of the gmch-m device #1. these bits are read only and writes to this register have no effect. for the a-5 stepping, this value is 03h. bit description 7:0 revision identification number . this is an 8-bit value that indicates the revision identification number for the gmch-m device #1. please see spec update for the latest silicon revision. silicon revision default value a5 0000/0011 (03h) a6 0000/0100 (04h) 4.5.2.6 subc1 - sub-class code register - device #1 address offset: 0ah default value: 04h access: read only size: 8 bits this register contains the sub-class code for the gmch-m device #1. this code is 04h indicating a pci-pci bridge device. the register is read only. bit description 7:0 sub-class code (subc1). this is an 8-bit value that indicates the category of bridge into which the gmch-m falls. the code is 04h indicating a host bridge. default value=0000/0100.
intel ? 830 chipset family 116 datasheet 298338-003 r 4.5.2.7 bcc1 - base class code register - device #1 address offset: 0bh default value: 06h access: read only size: 8 bits this register contains the base class code of the gmch-m device #1. this code is 06h indicating a bridge device. this register is read only. bit description 7:0 base class code (basec). this is an 8-bit value that indicates the base class code for the gmch-m device #1. this code has the value 06h, indicating a bridge device. default value=00000110. 4.5.2.8 mlt1 - master latency timer register - device #1 address offset: 0dh default value: 00h access: read/write size: 8 bits this functionality is not applicable. it is described here since these bits should be implemented as a read/write to prevent standard pci-pci bridge configuration software from getting ?confused?. bit description 7:3 not applicable but support read/write operations. (reads return previously written data.) default value=00000. 2:0 reserved
intel ? 830 chipset family 298338-003 datasheet 117 r 4.5.2.9 hdr1 - header type register - device #1 address offset: 0eh default value: 01h access: read only size: 8 bits this register identifies the header layout of the configuration space. no physical register exists at this location. bit descriptions 7:0 this read only field always returns 01h when read. writes have no effect. default value=00000001. 4.5.2.10 pbusn - primary bus number register - device #1 address offset: 18h default value: 00h access: read only size: 8 bits this register identifies that ?virtual? pci-pci bridge is connected to bus #0. bit descriptions 7:0 bus number. hardwired to ?0?. 4.5.2.11 sbusn - secondary bus number register - device #1 address offset: 19h default value: 00h access: read /write size: 8 bits this register identifies the bus number assigned to the second bus side of the ?virtual? pci-pci bridge i.e. to pci1/agp. this number is programmed by the pci configuration software to allow mapping of configuration cycles to pci1/agp. bit descriptions 7:0 bus number . programmable default value=00000000.
intel ? 830 chipset family 118 datasheet 298338-003 r 4.5.2.12 subusn - subordinate bus number register - device #1 address offset: 1ah default value: 00h access: read /write size: 8 bits this register identifies the subordinate bus (if any) that resides at the level below pci1/agp. this number is programmed by the pci configuration software to allow mapping of configuration cycles to pci1/agp. bit descriptions 7:0 bus number . programmable default value=00000000. 4.5.2.13 smlt - secondary master latency timer register - device #1 address offset: 1bh default value: 00h access: read/write size: 8 bits this register controls the bus tenure of the gmch-m on agp/pci. smlt is an 8-bit register that controls the amount of time the gmch-m, as an agp/pci bus master, can burst data on the agp/pci bus. the count value is an 8-bit quantity, however smlt[2:0] are reserved and assumed to be 0 when determining the count value. the gmch-m?s smlt is used to guarantee to the agp master a minimum amount of the system resources. when the gmch-m begins the first pci bus cycle after being granted the bus, the counter is loaded and enabled to count from the assertion of frame#. if the count expires while the gmch-m?s grant is removed (due to agp master request), then the gmch-m will lose the use of the bus, and the agp master agent may be granted the bus. if gmch-m?s bus grant is not removed, the gmch-m will continue to own the agp/pci bus regardless of the smlt expiration or idle condition. note: the gmch-m must always properly terminate an agp/pci transaction, with frame# negation prior to the final data transfer. the number of clocks programmed in the smlt represents the guaranteed time slice (measured in 66- mhz pci clocks) allotted to the gmch-m, after which it must complete the current data transfer phase and then surrender the bus as soon as its bus grant is removed. for example, if the smlt is programmed to 18h, then the value is 24 agp clocks. the default value of smlt is 00h and disables this function. when the smlt is disabled, the burst time for the gmch-m is unlimited (i.e. the gmch-m can burst forever). bit description 7:3 secondary mlt counter value . default value=00000. 2:0 reserved
intel ? 830 chipset family 298338-003 datasheet 119 r 4.5.2.14 iobase - i/o base address register - device #1 address offset: 1ch default value: f0h access: read/write size: 8 bits this register control the cpu to pci1/agp i/o access routing based on the following formula: io_base =< address =< io_limit only upper 4 bits are programmable. for the purpose of address decode address bits a[11:0] are treated as 0. thus the bottom of the defined i/o address range will be aligned to a 4-kb boundary. note: bios must not set this register to 00h otherwise 0cf8h/0cfch accesses will be forwarded to agp. bit description 7:4 i/o address base . corresponds to a[15:12] of the i/o address. default value=1111. 3:0 i/o addressing capability . hardwired to 0h indicating that only 16 bit i/o addressing is supported. bits [31:16] of the i/o base address is assumed to be 0000h. default value=0000. 4.5.2.15 iolimit - i/o limit address register - device #1 address offset: 1dh default value: 00h access: read/write size: 8 bits this register controls the cpu to pci1/agp i/o access routing based on the following formula: io_base=< address = intel ? 830 chipset family 120 datasheet 298338-003 r 4.5.2.16 ssts - secondary pci-pci status register - device #1 address offset: 1e-1fh default value: 02a0h access: read only, read/write clear size: 16 bits ssts is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (i.e. pci1/agp side) of the ?virtual? pci-pci bridge embedded within gmch-m. bit descriptions 15 detected parity error (dpe1). this bit is set to a 1 to indicate gmch-m?s detection of a parity error in the address or data phase of pci1/agp bus transactions. software sets dpe1 to 0 by writing a 1 to this bit. note that the function of this bit is not affected by the perre1 bit. also note that perr# is not implemented in the gmch-m. default value=0. 14 received system error (sse1) . this bit is hardwired to 0 since the gmch-m does not have an serr# signal pin. default value=0. 13 received master abort status (rmas1). when the gmch-m terminates a host-to-pci1/agp with an unexpected master abort, this bit is set to 1. software resets this bit to 0 by writing a 1 to it. default value=0. 12 received target abort status (rtas1). when a gmch-m-initiated transaction on pci1/agp is terminated with a target abort, rtas1 is set to 1. software resets rtas1 to 0 by writing a 1 to it. default value=0. 11 signaled target abort status (stas1). stas1 is hardwired to a 0, since the gmch-m does not generate target abort on pci1/agp. default value=0. 10:9 devsel# timing (devt1). this 2-bit field indicates the timing of the devsel# signal when the gmch-m responds as a target on pci1/agp, and is hard-wired to the value 01b (medium) to indicate the time when a valid devsel# can be sampled by the initiator of the pci cycle. default value=01. 8 data parity detected (dpd1). hardwired to 0. gmch-m does not implement g_perr# function. however, data parity errors are still detected and reported using serr hub interface special cycles(if enabled by serre1 and the bctrl register, bit 0). default value=0. 7 fast back-to-back (fb2b1). this bit is hardwired to 1 since gmch-m as a target supports fast back- to-back transactions on pci1/agp. default value=1. 6 reserved 5 66/60 mhz capability : hardwired to ?1?. 4:0 reserved
intel ? 830 chipset family 298338-003 datasheet 121 r 4.5.2.17 mbase - memory base address register - device #1 address offset: 20-21h default value: fff0h access: read/write size: 16 bits this register controls the cpu to pci1 non-prefetchable memory access routing based on the following formula: memory_base=< address = intel ? 830 chipset family 122 datasheet 298338-003 r note: memory range covered by mbase and mlimit registers are used to map non-prefetchable pci1/agp address ranges (typically where control/status memory-mapped i/o data structures of the graphics controller will reside). memory range covered by pmbase and pmlimit registers are used to map prefetchable address ranges (typically graphics memory). this segregation allows application of uswc space attribute to be performed in a true plug-and-play manner to the prefetchable address range for improved cpu-agp memory access performance. note: configuration software is responsible for programming all address range registers (prefetchable, non- prefetchable) with the values that provide exclusive address ranges i.e. prevent overlap with each other and/or with the ranges covered with the main memory. there is no provision in the gmch-m hardware to enforce prevention of overlap and operations of the system in the case of overlap are not guaranteed. 4.5.2.19 pmbase - prefetchable memory base address register - device #1 address offset: 24-25h default value: fff0h access: read/write size: 16 bits this register controls the cpu to pci1 prefetchable memory accesses routing based on the following formula: prefetchable_memory_base=< address = intel ? 830 chipset family 298338-003 datasheet 123 r 4.5.2.20 pmlimit - prefetchable memory limit address register - device #1 address offset: 26-27h default value: 0000h access: read/write size: 16 bits this register controls the cpu to pci1 prefetchable memory accesses routing based on the following formula: prefetchable_memory_base=< address = intel ? 830 chipset family 124 datasheet 298338-003 r 4.5.2.21 bctrl - pci-pci bridge control register - device #1 address offset: 3eh default value: 00h access: read/write size 8 bits this register provides extensions to the pcicmd1 register that are specific to pci-pci bridges. the bctrl provides additional control for the secondary interface (i.e. pci1/agp) as well as some bits that affect the overall behavior of the ?virtual? pci-pci bridge embedded within gmch-m, e.g. vga compatible address ranges mapping. bit descriptions 7 fast back-to-back enable : since there is only one target allowed on agp this bit is meaningless. this bit is hardwired to 0. 6 secondary bus reset : gmch-m does not support generation of reset via this bit on the agp and therefore this bit is hardwired to 0. note that the only way to perform a hard reset of the agp is via the system reset either initiated by software or hardware via ich3-m. 5 master abort mode : this bit is hardwired to 0. this means when acting as a master on agp/pci1 the gmch-m will drop writes on the ?floor? and return all 1 during reads when a master abort occurs. default value=0. 4 reserved 3 vga enable . controls the routing of cpu initiated transactions targeting vga compatible i/o and memory address ranges. when this bit is set, the gmch-m will forward the following cpu accesses to the agp: 1) memory accesses in the range 0a0000h to 0bffffh 2) i/o addresses where a[9:0] are in the ranges 3b0h to 3bbh and 3c0h to 3dfh (inclusive of isa address aliases - a[15:10] are not decoded) when this bit is set , forwarding of these accesses issued by the cpu is independent of the i/o address and memory address ranges defined by the previously defined base and limit registers. forwarding of these accesses is also independent of the settings of the bit 2 (isa enable) of this register if this bit is 1. if the vga enable bit is set, then accesses to io address range x3bch-x3bfh are forwarded to hub interface. if the vga enable bit is not set then accesses to io address range x3bch-x3bfh are treated just like any other io accesses, i.e. the cycles are forwarded to agp if the address is within iobase and iolimit and isa enable bit is not set, otherwise they are forwarded to hub interface. if this bit is 0, then vga compatible memory and i/o range accesses are not forwarded to agp but rather they are mapped to primary pci unless they are mapped to agp via i/o and memory range registers defined above (iobase, iolimit, mbase, mlimit, pmbase, pmlimit) the following table shows the behavior for all combinations of mda and vga: vga mda behavior 0 0 all references to mda and vga go to hub interface ( default) 0 1 illegal combination (do not use) 1 0 all references to vga go to agp mda-only references (i/o address 3bf and aliases) will go to hub interface. 1 1 vga references go to agp; mda references go to hub interface default value=0.
intel ? 830 chipset family 298338-003 datasheet 125 r bit descriptions 2 isa enable : modifies the response by the gmch-m to an i/o access issued by the cpu that target isa i/o addresses. this applies only to i/o addresses that are enabled by the iobase and iolimit registers. when this bit is set to 1, gmch-m will not forward to pci1/agp any i/o transactions addressing the last 768 bytes in each 1kb block even if the addresses are within the range defined by the iobase and iolimit registers. instead of going to pci1/agp these cycles will be forwarded to hub interface where they can eventually be subtractive or positively claimed by the isa bridge. if this bit is ?0? (default) then all addresses defined by the iobase and iolimit for cpu i/o transactions will be mapped to pci1/agp. default value=0. 1 serr# enable . this bit normally controls forwarding serr# on the secondary interface to the primary interface. the gmch-m does not support the serr# signal on the agp pci1 bus. hardwired to a ?0?. 0 parity error response enable : controls gmch-m?s response to data phase parity errors on pci1/agp g_perr# is not implemented by the gmch-m. however, when this bit is set to 1, address and data parity errors on pci1 are reported via serr messaging, if enabled by serre1. if this bit is reset to 0, then address and data parity errors on pci1/agp are not reported via the gmch-m serr# signal. other types of error conditions can still be signaled via serr messaging independent of this bit?s state. default value=0. 4.5.2.22 errcmd1 - error command register - device #1 address offset: 40h default value: 00h access: read/write size 8 bits bit descriptions 7:1 reserved . 0 serr on receiving target abort on agp/pci . when this bit is set to 1, the gmch-m generates an serr hub interface special cycle when an gmch-m originated agp/pci cycle is terminated with a target abort. if this bit is 0, then reporting of this condition is disabled. default value=0.
intel ? 830 chipset family 126 datasheet 298338-003 r 4.5.3 830m and 830mg chipset integrated graphics device registers ? device #2 this section contains the pci configuration registers listed in order of ascending offset address. device#2 applies to both the intel 830m and 830mg chipset. device #2 incorporates 2 functions, #0 and #1. table 30. integrated graphics device configuration space (device #2) address offset register symbol register name default value function #0 default value function #1 access regs in func #1* 00-01h vid2 vendor identification 8086h 8086h ro cof0 02-03h did2 device identification 3577h 3577h ro cof0 04-05h pcicmd2 pci command register 0000h 0000h ro,r/w uif1 06-07h pcists2 pci status register 0090h 0090h ro,r/wc uif1 08h rid2 revision identification 00h 00h ro cof0 09-0bh cc class code 030000h 038000h ro uif1 0ch cls cache line size register 00h 00h ro cof0 0dh mlt2 master latency timer 00h 00h ro cof0 0eh hdr2 header type 00h 00h ro uif1 0fh - intel reserved - - - - 10-13h gmadr graphics memory range address 00000008h 00000008h ro,r/w uif1 14-17h mmadr memory mapped range address 00000000h 00000000h ro,r/w uif1 18-2bh - intel reserved - - - - 2c-2dh svid2 subsystem vendor id 0000h 0000h r/wo in f# 0 cof0 2e-2fh sid2 subsystem id 0000h 0000h r/ wo in f# 0 cof0 30-33h romadr video bios rom base address 00000000h 00000000h ro,r/w cof0 34h cappoint capabilities pointer d0h d0h ro cof0 35-3bh - intel reserved - - - - 3ch intrline interrupt line rit 00h 00h r/w, ro in f# 1 -
intel ? 830 chipset family 298338-003 datasheet 127 r register f# 1 3dh intrpin interrupt pin register 01h 00h ro, reserved in f #1 - 3eh mingnt minimum grant register 00h 00h ro cof0 3fh maxlat maximum latency register 00h 00h ro cof0 40-cfh - intel reserved - - - - d0-d1h pmcapid power management capabilities id 0001h 0001h ro cof0 d2-d3h pmcap power management capabilities 0221h 0221h ro cof0 d4-d5h pmcs power management control 0000h 0000h ro,r/w uif1 d6-ffh - intel reserved - - - - notes: 1. cof0: copy of function #0, no hardware implemented for this register in function #1. 2. uif1: unique in function #1, hardware is implemented for this register in function #1, may be ro or r/w. 4.5.3.1 vid2 - vendor identification register ? device #2 address offset: 00h-01h default value: 8086h access: read only size: 16 bits the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 vendor identification number . this is a 16-bit value assigned to intel. default value=1000/0000/1000/0110.
intel ? 830 chipset family 128 datasheet 298338-003 r 4.5.3.2 did2 - device identification register - device #2 address offset: 02h-03h default value: 3577h access: read only size: 16 bits this 16-bit register combined with the vendor identification register uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 device identification number . this is a 16 bit value assigned to the gmch-m igd. default value=0011/0101/0111/0111. 4.5.3.3 pcicmd2 - pci command register - device #2 address offset: 04h-05h default value: 0000h access: read only, read/write size: 16 bits this 16-bit register provides basic control over the igd?s ability to respond to pci cycles. the pcicmd register in the igd disables the igd pci compliant master accesses to main memory. bit description 15:10 reserved 9 fast back-to-back (fb2b) - ro . (not implemented). hardwired to 0. 8 serr# enable (serre) - ro . (not implemented). hardwired to 0. 7 address/data stepping - ro . (not implemented). hardwired to 0. 6 parity error enable (perre) - ro . (not implemented). hardwired to 0. since the igd belongs to the category of devices that does not corrupt programs or data in system memory or hard drives, the igd ignores any parity error that it detects and continues with normal operation. 5 video palette snooping (vps) - ro . this bit is hardwired to 0 to disable snooping. 4 memory write and invalidate enable (mwie) - ro . hardwired to 0. the igd does not support memory write and invalidate commands. 3 special cycle enable (sce) - ro . this bit is hardwired to 0. the igd ignores special cycles. 2 bus master enable (bme) - r/w . set to 1 to enable the igd to function as a pci compliant master. set to 0 to disable igd bus mastering. default value=0. 1 memory access enable (mae) - r/w . this bit controls the igd?s response to memory space accesses. 0 = disable 1 = enable default value=0.
intel ? 830 chipset family 298338-003 datasheet 129 r 0 i/o access enable (ioae) - r/w . this bit controls the igd?s response to i/o space accesses. 0 = disable 1 = enable. default value=0.
intel ? 830 chipset family 130 datasheet 298338-003 r 4.5.3.4 pcists2 - pci status register - device #2 address offset: 06h-07h default value: 0090h access: read only, read/write clear size: 16 bits pcists is a 16-bit status register that reports the occurrence of a pci compliant master abort and pci compliant target abort. pcists also indicates the devsel# timing that has been set by the igd. bit description 15 detected parity error (dpe) - ro . since the igd does not detect parity, this bit is always set to 0. default value=0. 14 signaled system error (sse) - r/wc . the igd never asserts serr#, therefore this bit is hardwired to 0. 13 received master abort status (rmas) - r/wc . the igd never gets a master abort, therefore this bit is hardwired to 0. 12 received target abort status (rtas) - r/wc . the igd never gets a target abort, therefore this bit is hardwired to 0. 11 signaled target abort status (stas) . hardwired to 0. the igd does not use target abort semantics. 10:9 devsel# timing (devt) - ro . na - hardwired to 00. 8 data parity detected (dpd) - r/wc . since parity error response is hardwired to disabled (and the igd does not do any parity detection), this bit is hardwired to 0. 7 fast back-to-back (fb2b). hardwired to 1 . the igd accepts fast back-to-back when the transactions are not to the same agent. 6 user defined format (udf). hardwired to 0. 5 66 mhz pci capable (66c). na - hardwired to 0. 4 cap list - ro . this bit is set to 1 to indicate that the register at 34h provides an offset into the function?s pci configuration space containing a pointer to the location of the first item in the list. default value=1. 3:0 reserved
intel ? 830 chipset family 298338-003 datasheet 131 r 4.5.3.5 rid2 - revision identification register - device #2 address offset: 08h default value: 03h (a5 silicon) 04h (a6 silicon) access: read only size: 8 bits this register contains the revision number of the igd. these bits are read only and writes to this register have no effect. bit description 7:0 revision identification number . this is an 8-bit value that indicates the revision identification number for the igd. please see spec update for the latest silicon revision. silicon revision default value a5 0000/0011 (03h) a6 0000/0100 (04h) 4.5.3.6 cc - class code register - device #2 address offset: 09h-0bh default value: 030000h access: read only size: 24 bits this register contains the device programming interface information related to the sub-class code and base class code definition for the igd. this register also contains the base class code and the function sub-class in relation to the base class code. bit description 23:16 base class code (basec). 03=display controller default value=00000011. 15:8 sub-class code (scc) . function 0: 00h=vga compatible; based on device #0 gcc1 bit 1. function 1: 80h=non vga; default value=00000000. 7:0 programming interface (pi) . 00h=hardwired as a display controller. default value=00000000.
intel ? 830 chipset family 132 datasheet 298338-003 r 4.5.3.7 cls - cache line size register - device #2 address offset: 0ch default value: 00h access: read only size: 8 bits the igd does not support this register as a pci slave. bit description 7:0 cache line size (cls). this field is hardwired to 0?s. the igd as a pci compliant master does not use the memory write and invalidate command and, in general, does not perform operations based on cache line size. default value=00000000. 4.5.3.8 mlt2 - master latency timer register - device #2 address offset: 0dh default value: 00h access: read only size: 8 bits the igd does not support the programmability of the master latency timer because it does not perform bursts. bit description 7:0 master latency timer count value. hardwired to 00000000. 4.5.3.9 hdr2 - header type register - device #2 address offset: 0eh default value: 00h access: read only size: 8 bits this register contains the header type of the igd. bit description 7 multi function status (mfunc). indicates if the device is a multi-function device. the value of this register is determined by gcc1 bit 2. if gcc1 bit 2 is set this bit is a ?1? indicating device #2 to be multi-function. default value=0. 6:0 header code (h ) . this is an 7-bit value that indicates the header code for the igd. this code has the value 00h, indicating a type 0 configuration space format. default value=00000000.
intel ? 830 chipset family 298338-003 datasheet 133 r 4.5.3.10 gmadr - graphics memory range address register - device #2 address offset: 10-13h default value: 00000008h access: read/write, read only size: 32 bits this register requests allocation for the igd graphics memory. the allocation is for either 64 mb or 128 mb and the base address is defined by bits [31:27,26]. bit description 31:27 memory base address - r/w . set by the os, these bits correspond to address signals [31:26]. default value=00000. 26 128 mb address mask ? ro, r/w. the operation of this bit is controlled via device 0 register gccr. if the signal is low this bit is read only with a value of 0, indicating a memory range of 128 mb. if the signal is high, this bit becomes r/w, indicating a memory range of 64mb (where system software will program the bit to the appropriate address bit value. default value=0. 25:4 address mask - ro . hardwired to 0s to indicate (at least) a 32mb address range. 3 prefetchable memory - ro . hardwired to 1 to enable prefetching. 2:1 memory type - ro . hardwired to 0 to indicate 32-bit address. 0 memory/io space - ro . hardwired to 0 to indicate memory space.
intel ? 830 chipset family 134 datasheet 298338-003 r 4.5.3.11 mmadr - memory mapped range address register - device #2 address offset: 14-17h default value: 00000000h access: read/write, read only size: 32 bits this register requests allocation for the igd registers and instruction ports. the allocation is for 512 kb and the base address is defined by bits [31:19]. bit description 31:19 memory base address - r/w. set by the os, these bits correspond to address signals [31:19]. default value=0. 18:4 address mask - ro . hardwired to 0s to indicate 512-kb address range. 3 prefetchable memory - ro . hardwired to 0 to prevent prefetching. 2:1 memory type - ro . hardwired to 0s to indicate 32-bit address. 0 memory / io space - ro. hardwired to 0 to indicate memory space. 4.5.3.12 svid2 - subsystem vendor identification register - device #2 address offset: 2c-2dh default value: 0000h access: read/write once size: 16 bits bit description 15:0 subsystem vendor id . this value is used to identify the vendor of the subsystem. this register should be programmed by bios during boot-up. once written, this register becomes read_only. this register can only be cleared by a reset. default value=0000000000000000. 4.5.3.13 sid2 - subsystem identification register - device #2 address offset: 2e-2fh default value: 0000h access: read/write once size: 16 bits bit description 15:0 subsystem identification . this value is used to identify a particular subsystem. this field should be programmed by bios during boot-up. once written, this register becomes read_only. this register can only be cleared by a reset. default value=0000000000000000.
intel ? 830 chipset family 298338-003 datasheet 135 r 4.5.3.14 romadr - video bios rom base address registers - device #2 address offset: 30-33h default value: 00000000h access: read/write, read only size: 32 bits the igd does not use a separate bios rom, therefore this register is hardwired to 0?s. bit description 31:18 rom base address - r/w . hardwired to 0?s. 17:11 address mask - ro . hardwired to 0s to indicate 256-kb address range. 10:1 reserved . hardwired to 0s. 0 rom bios enable - r/w . 0 = rom not accessible. default value=0. 4.5.3.15 cappoint - capabilities pointer register - device #2 address offset: 34h default value: d0h access: read only size: 8 bits bit description 7:0 capabilities pointer value . this field contains an offset into the function?s pci configuration space for the first item in the new capabilities linked list, the acpi registers at address d0h. default value=11010000. 4.5.3.16 intrline - interrupt line register - device #2 address offset: 3ch default value: 00h access: read/write size: 8 bits bit description 7:0 interrupt connection . used to communicate interrupt line routing information. post software writes the routing information into this register as it initializes and configures the system. the value in this register indicates which input of the system interrupt controller that the device?s interrupt pin is connected to. default value=00000000.
intel ? 830 chipset family 136 datasheet 298338-003 r 4.5.3.17 intrpin - interrupt pin register - device #2 address offset: 3dh default value: 01h, 00h for function #1 access: read only size: 8 bits bit description 7:0 interrupt pin . as a single function device, the igd specifies inta# as its interrupt pin. 01h=inta#. for function #1, this register is set to 00h. default value=00000001. 4.5.3.18 mingnt - minimum grant register - device #2 address offset: 3eh default value: 00h access: read only size: 8 bits bit description 7:0 minimum grant value . the igd does not burst as a pci compliant master. bits[7:0]=00h. default value=00000000. 4.5.3.19 maxlat - maximum latency register - device #2 address offset: 3fh default value: 00h access: read only size: 8 bits bit description 7:0 maximum latency value. the igd has no specific requirements for how often it needs to access the pci bus. bits [7:0]=00h default value=00000000.
intel ? 830 chipset family 298338-003 datasheet 137 r 4.5.3.20 pmcapid - power management capabilities id register - device #2 address offset: d0h-d1h default value: 0001h access: read only size: 16 bits bit description 15:8 next_ptr. this contains a pointer to next item in capabilities list. this is the final capability in the list and must be set to 00h. default value=00000000. 7:0 cap_id. sig defines this id is 01h for power management. default value=00000001. 4.5.3.21 pmcap - power management capabilities register - device #2 address offset: d2h-d3h default value: 0221h access: read only size: 16 bits bit description 15:11 pme support . this field indicates the power states in which the igd may assert pme#. hardwired to 0 to indicate that the igd does not assert the pme# signal. 10 d2 . the d2 power management state is not supported. this bit is hardwired to 0. 9 d1 . hardwired to 1 to indicate that the d1 power management state is supported. 8:6 reserved . read as 0s. 5 device specific initialization (dsi). hardwired to 1 to indicate that special initialization of the igd is required before generic class device driver is to use it. 4 auxiliary power source . hardwired to 0. 3 pme clock . hardwired to 0 to indicate igd does not support pme# generation. 2:0 version. hardwired to 001b to indicate there are 4 bytes of power management registers implemented.
intel ? 830 chipset family 138 datasheet 298338-003 r 4.5.3.22 pmcs - power management control/status register - device #2 address offset: d4h-d5h default value: 0000h access: read/write, read only size: 16 bits bit description 15 pme_status - ro . this bit is 0 to indicate that igd does not support pme# generation from d3 (cold). default value=0. 14:13 reserved default value=0. 12:9 reserved default value=0. 8 pme_en - ro . this bit is 0 to indicate that pme# assertion from d3 (cold) is disabled. default value=0. 7:2 reserved. always returns 0 when read, write operations have no effect. default value=0. 1:0 powerstate - r/w . this field indicates the current power state of the igd and can be used to set the igd into a new power state. if software attempts to write an unsupported state to this field, write operation must complete normally on the bus, but the data is discarded and no state change occurs. on a transition from d3 to d0, the graphics controller is optionally reset to initial values. bits[1:0] power state 00 d0 00 d1 10 d2 not supported 11 d3 default value=00.
intel ? 830 chipset family 298338-003 datasheet 139 r 5 functional description 5.1 system address map a mobile intel pentium iii processor-m / mobile intel celeron processor system based on the intel 830 chipset family gmch-m supports 4 gb of addressable memory space and 64 kb+3 of addressable i/o space. (the p6 bus i/o addressability is 64 kb + 3.) there is a programmable memory address space under the 1 mb region that is divided into regions which can be individually controlled with programmable attributes such as disable, read/write, write only, or read only. the mobile intel pentium iii processor-m / mobile intel celeron processors support addressing of memory ranges larger than 4 gb. the gmch-m claims any cpu access over 4 gb and terminates the transaction without forwarding it to hub interface or agp. simply dropping the data terminates writes and for reads the gmch-m returns all zeros on the host bus. note that the gmch-m does not support the pci dual address cycle mechanism (dac) and therefore does not allow addressing of greater than 4 gb on either the hub interface or agp interface. in the following sections, it is assumed that all of the compatibility memory ranges reside on the hub interface/pci. the exception to this rule is vga ranges, which may be mapped to agp or to igd. in the absence of more specific references, cycle descriptions referencing pci should be interpreted as the hub interface/pci, while cycle descriptions referencing agp are related to the agp bus. note: support for agp is available on both the intel 830mp and 830m chipset. support for internal graphics device (igd) is available on both the intel 830mg and 830m chipset. 5.1.1 system memory address ranges the intel 830 chipset family gmch-m provides a maximum pc133 address decode space of 1.0 gb. the gmch-m does not re-map apic memory space. the gmch-m does not limit sdram space in hardware. it is the bios or system designer?s responsibility to limit sdram population so that adequate pci, agp, high bios, and apic memory space can be allocated . the following figure represents system memory address map in a simplified form. the following figure provides additional details on mapping specific memory regions as defined and supported by the intel 830 chipset family.
intel ? 830 chipset family 140 datasheet 298338-003 r figure 13. memory system address map independently programmable non-overlapping memory windows main memory address range agp* address range pci memory address range 4gb top of the main memory graphics (agp)* aperture 0 830 memory space note: note: support for agp is available on both the intel 830mp and 830m chipset.
intel ? 830 chipset family 298338-003 datasheet 141 r figure 14. detailed memory system address map pre-allocated memory expansion card bios and buffer area (128 kb) 16 kb x 8 standard pci/isa video memory (smm memory) 128 kb dos area optionall y mapped t o agp 768 kb 640 kb 896 kb 960 kb 1 mb lower bios area (64 kb) 16 kb x 4 upper bios area (64 kb) agp window agp window extended p6 memory note: support for agp is available on both the intel 830mp and 830m chipset. 5.1.2 compatibility area this area is divided into the following address regions: ? 0 ? 640 kb dos area ? 640 ? 768 kb video buffer area ? 768 ? 896 kb in 16-kb sections (total of 8 sections) - expansion area ? 896 -960 kb in 16-kb sections (total of 4 sections) - extended system bios area ? 960 kb - 1 mb memory (bios area) - system bios area there are 16 memory segments in the compatibility area. thirteen of the memory ranges can be enabled or disabled independently for both read and write cycles.
intel ? 830 chipset family 142 datasheet 298338-003 r table 31. memory segments and attributes memory segments attributes comments 000000h - 09ffffh fixed - always mapped to main sdram 0 to 640k ? dos region 0a0000h - 0bffffh mapped to hub interface, or agp - configurable as smm space video buffer (physical sdram configurable as smm space) 0c0000h - 0c3fffh we re add-on bios 0c4000h - 0c7fffh we re add-on bios 0c8000h - 0cbfffh we re add-on bios 0cc000h - 0cffffh we re add-on bios 0d0000h - 0d3fffh we re add-on bios 0d4000h - 0d7fffh we re add-on bios 0d8000h - 0dbfffh we re add-on bios 0dc000h - 0dffffh we re add-on bios 0e0000h - 0e3fffh we re bios extension 0e4000h - 0e7fffh we re bios extension 0e8000h - 0ebfffh we re bios extension 0ec000h - 0effffh we re bios extension 0f0000h - 0fffffh we re bios area 5.1.2.1 dos area (00000h-9ffffh) the dos area is 640 kb in size and is always mapped to the main memory controlled by the intel 830 chipset family gmch-m. 5.1.2.2 legacy vga ranges (a0000h-bffffh) the legacy 128-kb vga memory range a0000h-bffffh (frame buffer) can be mapped to agp/pci1 (device #1), to igd (device #2) and/or to the hub interface depending on the programming of the vga steering bits. priority for vga mapping is constant in that the intel 830 chipset family gmch-m always decodes internally mapped devices first. internal to the gmch-m, decode precedence is always given to igd. the gmch-m always positively decodes internally mapped device, namely the igd and agp/pci1. subsequent decoding of regions mapped to agp/pci1 or the hub interface depends on the legacy vga configurations bits (vga enable and mdap). this region is also the default for smm space. 5.1.2.3 compatible smram address range (a0000h-bffffh) when compatible smm space is enabled, smm-mode cpu accesses to this range are routed to physical system sdram at this address. non-smm-mode cpu accesses to this range are considered to be to the video buffer area as described above. agp and hub interface originated cycles to enabled smm space are not allowed and are considered to be to the video buffer area.
intel ? 830 chipset family 298338-003 datasheet 143 r 5.1.2.4 monochrome adapter (mda) range (b0000h - b7fffh) legacy support requires the ability to have a second graphics controller (monochrome) in the system. accesses in the vga range are forwarded to igd, agp/pci1 and the hub interface (depending on configuration bits). since the monochrome adapter may be mapped to anyone of these devices, the gmch-m must decode cycles in the mda range and forward them either to igd, agp/pci1 or to the hub interface. this capability is controlled by a vga steering bits and the legacy configuration bit (mdap bit). in addition to the memory range b0000h to b7fffh, the intel 830 chipset family gmch- m decodes io cycles at 3b4h, 3b5h, 3b8h, 3b9h, 3bah, and 3bfh and forwards them to the either the igd, agp/pci1 and/or the hub interface. 5.1.2.5 expansion area (c0000h-dffffh) this 128-kb isa expansion region is divided into eight 16- kb segments. each segment can be assigned one of four read/write states: read-only, write-only, read/write, or disabled. typically, these blocks are mapped through gmch-m and are subtractively decoded to isa space. memory that is disabled is not remapped. 5.1.2.6 extended system bios area (e0000h-effffh) this 64-kb area is divided into four 16-kb segments. each segment can be assigned independent read and write attributes so it can be mapped either to main sdram or to hub interface. typically, this area is used for ram or rom. memory segments that are disabled are not remapped elsewhere. 5.1.2.7 system bios area (f0000h-fffffh) this area is a single 64-kb segment. this segment can be assigned read and write attributes. it is by default (after reset) read/write disabled and cycles are forwarded to hub interface. by manipulating the read/write attributes, the gmch-m can ?shadow? bios into the main sdram. when disabled, this segment is not remapped. 5.1.3 extended memory area this memory area covers 100000h (1 mb) to ffffffffh (4 gb-1) address range and it is divided into the following regions: ? main system sdram memory from 1 mb to the top of memory; maximum of 1.0 gb. ? agp or pci memory space from the top of memory to 4 gb with two specific ranges: ? apic configuration space from fec0_0000h (4 gb-20 mb) to fecf_ffffh and fee0_0000h to feef_ffffh ? high bios area from 4 gb to 4 gb - 2 mb 5.1.3.1 main system sdram address range (0010_0000h to top of main memory) the address range from 1 mb to the top of main memory is mapped to main sdram address range controlled by the intel 830 chipset family gmch-m. the top of memory (tom) is limited to 1.0 gb. all accesses to addresses within this range will be forwarded by the gmch-m to the sdram unless a hole in this range is created using the fixed hole as controlled by the fdhc register. accesses within this hole are forwarded to hub interface.
intel ? 830 chipset family 144 datasheet 298338-003 r the gmch-m provides a maximum sdram address decode space of 4 gb. the gmch-m does not re-map apic memory space. the gmch-m does not limit sdram address space in hardware. it is the bios or system designer?s responsibility to limit sdram population so that adequate pci, agp, high bios, and apic memory space can be allocated. 5.1.3.1.1 15 mb-16 mb window a hole can be created at 15 mb-16 mb as controlled by the fixed hole enable (fdhc register) in device 0 space. accesses within this hole are forwarded to the hub interface. the range of physical sdram memory disabled by opening the hole is not remapped to the top of the memory ? that physical sdram space is not accessible. this 15 mb-16 mb hole is an optionally enabled isa hole. video accelerators originally used this hole. validation and customer sv teams also use it for some of their test cards. that is why it is being supported. there is no inherent bios request for the 15-16 hole. 5.1.3.1.2 pre-allocated memory physical addresses that are not accessible as general system memory and reside within system memory address range (less than tom) are created for smm-mode and legacy vga graphics compatibility. the intel 830m and 830mg chipsets support an increased amount of pre-allocated memory to support up to 1600 x 1200 x 32 bpp. the pre-allocated memory allows sizes of 512 kb, 1 mb, or 8 mb. . the system bios must properly initialize these regions. 5.1.3.2 extended smram address range (hseg and tseg) the hseg and tseg smm transaction address spaces reside in this extended memory area. 5.1.3.2.1 hseg smm-mode cpu accesses to enabled hseg are remapped to 000a0000h-000bffffh. non-smm- mode cpu accesses to enabled hseg are considered invalid and are terminated immediately on the host interface. the exceptions to this rule are non-smm-mode write back cycles that are remapped to smm space to maintain cache coherency. agp and hub interface originated cycles to enabled smm space are not allowed. physical sdram behind the hseg transaction address is not remapped and is not accessible. 5.1.3.2.2 tseg tseg can be up to 1 mb in size and is at the top of physical memory. smm-mode cpu accesses to enabled tseg access the physical sdram at the same address. non-smm-mode cpu accesses to enabled tseg is considered invalid and are terminated immediately on the host interface. the exceptions to this rule are non-smm-mode write back cycles that are directed to the physical smm space to maintain cache coherency. agp and hub interface originated cycles to enabled smm space are not allowed. the size of the smram space is determined by the usmm value in the smram register. when the extended smram space is enabled, non-smm cpu accesses and all other accesses in this range are forwarded to the hub interface. when smm is enabled, the amount of memory available to the system is equal to the amount of physical sdram minus the value in the tseg register. 5.1.3.3 intel dynamic video memory technology (dvmt) the igd on both 830m and 830mg chipsets supports dvmt in a non-graphics memory configuration. intel's dynamic video memory technology is a mechanism that manages system memory and the
intel ? 830 chipset family 298338-003 datasheet 145 r internal graphics device for optimal graphics performance. dvmt-enabled software drivers, working with the memory arbiter and the operating system, utilize the system memory to support graphics 2d and 3d applications. dvmt dynamically responds to application requirements by allocating the proper amount of display and texturing memory. dvmt is not available when discrete agp device is used. 5.1.3.4 pci memory address range (top of main memory to 4 gb) the address range from the top of main sdram to 4 gb (top of physical memory space supported by the intel 830 chipset family gmch-m is normally mapped via the hub interface to pci. as an internal graphics configuration, there is one exception to this rule. 1. addresses decoded to the memory mapped range of the internal graphics device. these are forwarded to the internal graphics device. as an agp configuration, there are two exceptions to this rule. 1. addresses decoded to the agp memory window defined by the mbase, mlimit, pmbase, and pmlimit registers are mapped to agp. 2. addresses decoded to the graphics aperture range defined by the apbase and apsize registers are mapped to the main sdram. there are two sub-ranges within the pci memory address range defined as apic configuration space and high bios address range. as an igd, the memory mapped range of the igd must not overlap with these two ranges. similarly, as an agp device, the agp memory window and agp graphics aperture window must not overlap with these two ranges. these ranges are described in detail in the following paragraphs. 5.1.3.5 configuration space (fec0_0000h -fecf_ffffh, fee0_0000h- feef_ffffh) this range is reserved for apic configuration space that includes the default i/o apic configuration space. the default local apic configuration space is fee0_0000h to feef_0fffh. cpu accesses to the local apic configuration space do not result in external bus activity since the local apic configuration space is internal to the cpu. however, an mtrr must be programmed to make the local apic range uncacheable (uc). the local apic base address in each cpu should be relocated to the fec0_0000h (4 gb-20 mb) to fecf_ffffh range so that one mtrr can be programmed to 64 kb for the local and i/o apics. the i/o apic(s) usually resides in the ich3-m portion of the chip-set or as a stand-alone component(s). i/o apic units will be located beginning at the default address fec0_0000h. the first i/o apic will be located at fec0_0000h. each i/o apic unit is located at fec0_x000h where x is i/o apic unit number 0 through f(hex). this address range will be normally mapped to hub interface. note: there is no provision to support an i/o apic device on agp. the address range between the apic configuration space and the high bios (fed0_0000h to ffdf_ffffh) is always mapped to the hub interface. 5.1.3.6 high bios area (ffe0_0000h -ffff_ffffh) the top 2 mb of the extended memory region is reserved for system bios (high bios), extended bios for pci devices, and the a20 alias of the system bios. cpu begins execution from the high bios after reset. this region is mapped to hub interface so that the upper subset of this region aliases to
intel ? 830 chipset family 146 datasheet 298338-003 r 16 mb-256 kb range. the actual address space required for the bios is less than 2 mb but the minimum cpu mtrr range for this region is 2 mb so that full 2 mb must be considered. 5.1.4 agp memory address ranges the intel 830mp and 830m gmch-m can be programmed to direct memory accesses to the agp bus interface when addresses are within either of two ranges specified via registers in gmch-m?s device #1 configuration space. the first range is controlled via the memory base register (mbase) and memory limit register (mlimit) registers. the second range is controlled via the prefetchable memory base (pmbase) and prefetchable memory limit (pmlimit) registers. conceptually, address decoding for each range follows the same basic concept. the top 12 bits of the respective memory base and memory limit registers correspond to address bits a[31:20] of a memory address . for the purpose of address decoding, the gmch-m assumes that address bits a[19:0] of the memory base are zero and that address bits a[19:0] of the memory limit address are fffffh. this forces each memory address range to be aligned to 1-mb boundary and to have a size granularity of 1 mb. the gmch-m positively decodes memory accesses to agp memory address space as defined by the following equations: memory_base_address * address * memory_limit_address prefetchable_memory_base_address * address * prefetchable_memory_limit_address the window size is programmed by the plug-and-play configuration software. the window size depends on the size of memory claimed by the agp device. normally these ranges will reside above the top-of-main-sdram and below high bios and apic address ranges. they normally reside above the top of memory (tom) so they do not steal any physical sdram memory space. it is essential to support a separate prefetchable range in order to apply uswc attribute (from the processor point of view) to that range. the uswc attribute is used by the processor for write combining. note that the gmch-m device #1 memory range registers described above are used to allocate memory address space for any devices sitting on agp that requires such a window. these devices would include the agp device, pci-66 mhz/1.5 v agents, and multifunctional agp devices where one or more functions are implemented as pci devices. the pcicmd1 register can override the routing of memory accesses to agp. in other words, the memory access enable bit must be set in the device 1, pcicmd1 register, to enable the memory base/limit and prefetchable base/limit windows. 5.2 intel 830 chipset family host interface 5.2.1 overview the intel 830 chipset family gmch-m is optimized for the mobile intel pentium iii processor-m/ mobile intel celeron processors. the gmch-m supports a psb frequency of 133 mhz using 1.25 v agtl signaling. the agtl buffers support dual-ended termination. the gmch-m supports 32-bit host addressing, decoding up to 4 gb of memory address space for the processor. cpu memory writes to address space above 4 gb will be immediately terminated and discarded. cpu memory reads to address space above 4 gb will be immediately terminated and will return the value of the pulled-up
intel ? 830 chipset family 298338-003 datasheet 147 r gtl host bus. host initiated i/o cycles are decoded to agp/pci1, hub interface, or gmch-m configuration space. host initiated memory cycles are decoded to agp/pci1, hub interface, or system sdram, or graphics memory mapped registers. host cycles to agp/pci, or the integrated graphics device (igd), or hub interface, are subject to dynamic deferring. all memory accesses from the host that hit the graphics aperture are translated using an agp address translation table. gmch-m accesses to agp/pci1 device accesses to non-cacheable system memory are not snooped on the host bus. memory accesses initiated from agp/pci1 using pci semantics, cacheable accesses from the igd and from hub interface to sdram will be snooped on the host bus. note: support for agp is available on both the intel 830mp and 830m chipset. support for internal graphics device (igd) is available on both the intel 830mg and 830m chipset. 5.2.2 processor unique psb activity the intel 830 chipset family gmch-m recognizes and supports a large subset of the transaction types that are defined for the p6 bus interface. however, each of these transaction types has a multitude of response types, some of which are not supported by this controller. all transactions are processed in the order that they are received on the host bus. a summary of transactions supported by the gmch-m is given in the following table.
intel ? 830 chipset family 148 datasheet 298338-003 r table 32. host bus transactions supported by gmch-m transaction reqa[4:0]# reqb[4:0]# gmch-m support deferred reply 0 0 0 0 0 x x x x x the gmch-m will initiate a deferred reply for a previously deferred transaction. reserved 0 0 0 0 1 x x x x x reserved interrupt acknowledge 0 1 0 0 0 0 0 0 0 0 interrupt acknowledge cycles are forwarded to the hub interface bus. special transactions 0 1 0 0 0 0 0 0 0 1 see table 34 in special cycles section. reserved 0 1 0 0 0 0 0 0 1 x reserved reserved 0 1 0 0 0 0 0 1 x x reserved branch trace message 0 1 0 0 1 0 0 0 0 0 the gmch-m will terminate a branch trace message without latching data. reserved 0 1 0 0 1 0 0 0 0 1 reserved reserved 0 1 0 0 1 0 0 0 1 x reserved reserved 0 1 0 0 1 0 0 1 x x reserved i/o read 1 0 0 0 0 0 0 x len# i/o read cycles are forwarded to hub interface or agp/pci unless they target the gmch-m configuration space (this includes the igd). in this case, the gmch- m picks up the transaction. i/o write 1 0 0 0 1 0 0 x len# i/o write cycles are forwarded to hub interface or agp/pci unless they target the gmch-m configuration space (this includes the igd). in this case, the gmch- m picks up the transaction. reserved 1 1 0 0 x 0 0 x x x reserved memory read & invalidate 0 0 0 1 0 0 0 x len# host initiated memory read and invalidate cycles are forwarded to system sdram, hub interface, agp/pci, or graphics memory mapped registers. the gmch- m will initiate an mri (len=0) cycle to snoop a hub interface, agp/pci, or cacheable igd initiated write cycle to system sdram. reserved 0 0 0 1 1 0 0 x len# reserved memory code read 0 0 1 0 0 0 0 x len# memory code read cycles are forwarded to system sdram, hub interface, or agp/pci. memory data read 0 0 1 1 0 0 0 x len# host initiated memory read cycles are forwarded to system sdram, hub interface, agp/pci, or graphics memory mapped registers. the gmch-m will initiate a memory read cycle to snoop a hub interface, agp/pci, or cacheable igd initiated read cycle to system sdram. memory write (no retry) 0 0 1 0 1 0 0 x len# this memory write is a writeback cycle and cannot be retried. the gmch-m will forward the write to system sdram. memory write (can be retried) 0 0 1 1 1 0 0 x len# the memory write cycle will be forwarded to system sdram, hub interface, agp/pci, or graphics memory mapped registers. notes: 1. for memory cycles, reqa[4:3]# = asz#. the gmch-m only supports asz# = 00 (32 bit address). 2. reqb[4:3]# = dsz#. for the pentium pro processor, dsz# = 00 (64 bit data bus size).
intel ? 830 chipset family 298338-003 datasheet 149 r 3. len# = data transfer length as follows: len# data length 00 <= 8 bytes (be[7:0]# specify granularity) 01 length = 16 bytes be[7:0]# all active 10 length = 32 bytes be[7:0]# all active 4. reserved. table 33. host bus responses supported by gmch-m rs2# rs1# rs0# description gmch-m support 0 0 0 idle 0 0 1 retry response this response is generated if an access is to a resource that cannot be accessed by the processor at this time and the logic must avoid deadlock. hub interface directed reads and writes, sdram locked reads, agp/pci, and igd reads and writes can be retried. unless there is an attempt to establish lock, the gmch- m will never retry a cycle that targets system memory. 0 1 0 deferred response this response can be returned for all transactions that can be executed ?out of order.? hub interface directed reads (memory, i/o and interrupt acknowledge) and writes (i/o only), agp/pci directed reads (memory and i/o) and writes (i/o only), and igd directed reads (memory and i/o) and writes (i/o only) can be deferred. unless there is an attempt to establish lock, the gmch- m will never defer a cycle that targets system memory. 0 1 1 reserved reserved 1 0 0 hard failure not supported 1 0 1 no data response this is for transactions where the data has already been transferred or for transactions where no data is transferred. writes and zero length reads receive this response. 1 1 0 implicit writeback this response is given for those transactions where the initial transactions snoop hits on a modified cache line. 1 1 1 normal data response this response is for transactions where data accompanies the response phase. reads receive this response. 5.2.3 host addresses above 4 gb cpu memory writes to address space above 4 gb will be terminated and discarded immediately. cpu memory reads to address space above 4 gb will also be immediately terminated and will return the value of the pulled-up gtl host bus.
intel ? 830 chipset family 150 datasheet 298338-003 r 5.2.4 host bus cycles the following transaction descriptions illustrate the various operations in their most straightforward representation. the diagrams do not attempt to show the transaction phase relationships when multiple transactions are active on the cpu bus. for a full description of the cpu bus functionality please refer to the latest p6 family of processor hardware developer?s manual. 5.2.4.1 partial reads partial read transactions include: i/o reads and memory read operations of less than or equal to eight bytes (four consecutive bytes for i/o) within an aligned 8-byte span. the byte enable signals, be#[7:0], select which bytes in the span to read. 5.2.4.2 part-line read and write transactions the intel 830 chipset family gmch-m does not support a part-line, i.e. 16-byte transactions. 5.2.4.3 cache line reads a read of a full cache line (as indicated by the len[1:0]=10 during request phase) requires 32 bytes of data to be transferred, which translates into four data transfers for a given request. if selected as a target, the intel 830 chipset family gmch-m will determine if the address is directed to system sdram, graphics sdram, hub interface, or agp/pci, and provide the corresponding command and control to complete the transaction. 5.2.4.4 partial writes partial write transactions include: i/o and memory write operations of eight bytes or less (maximum of four bytes for i/o) within an aligned 8-byte span. the byte enable signals, be#[7:0], select which bytes in the span to write. i/o writes crossing a 4-byte boundary are broken into two separate transactions by the cpu. 5.2.4.5 cache line writes a write of a full cache line requires 32 bytes of data to be transferred, which translates into four data transfers for a given request. 5.2.4.6 memory read and invalidate (length > 0) a memory read and invalidate (mri) transaction is functionally equivalent to a cache line read. the purpose this special transaction is to support write allocation (write miss case) of cache lines in the processors. when a processor issues an mri, the cache line is read as in a normal cache line read operation; however, all other caching agents must invalidate this line if they have it in a shared or exclusive state. if a caching agent has this line in the modified state, then it must be written back to memory and invalidated. the intel 830 chipset family gmch-m snarfs the write-back data. 5.2.4.7 memory read and invalidate (length = 0) a memory read and invalidate transaction of length zero, mri(0) does not have an associated data response. executing the transaction will inform other agents in the system that the agent issuing this request wants exclusive ownership of a cache line that is in the shared state (write hit to a shared line).
intel ? 830 chipset family 298338-003 datasheet 151 r agents with this cache line will invalidate the line. if this line is in the modified state an implicit write- back cycle is generated and the intel 830 chipset family gmch-m snarfs the data. the intel 830 chipset family gmch-m generates length=0 memory read and invalidate transactions for hub interface, agp/pci, or igd memory write cycles to system sdram. 5.2.4.8 memory read (length = 0) a memory read of length zero, mr(0), does not have an associated data response. this transaction is used by the gmch-m to snoop for the hub interface to system sdram, agp/pci snoopable system sdram read accesses, and igd snoopable system sdram read accesses. the intel 830 chipset family gmch-m snoop request policy is identical for hub interface and agp/pci, and igd memory read transactions. note that the gmch-m will perform single mr(0) cycles for hub interface reads less than or equal to 32 bytes, for agp/pci master reads or read lines directed to system sdram, and for igd cacheable reads or read lines (which can only be directed to system sdram). the gmch-m will do multiple snoop ahead cycles for hub interface burst reads greater than 32 bytes and for agp/pci master burst reads (i.e. memory read multiple) to sdram. multiple snoop ahead cycles by the gmch-m are not necessary for the igd as burst reads are not supported by the igd. 5.2.4.9 host initiated zero-length r/w cycles streaming simd extension (sse) new instructions can result in zero-length read and write cycles to the chipset. the intel 830 chipset family gmch-m supports a zero-length processor write cycle by executing a 1 qw write cycle to the targeted destination with all 8 byte enables turned off. the following destinations for host initiated zero-length writes are supported: 1. coherent system memory 2. aperture mapped to system memory 3. aperture mapped to graphics memory 4. gmch-m internal memory-mapped i/o registers 5. pci (via hub interface) 6. agp the gmch-m only supports zero-length processor read cycles that target coherent system memory or agp/pci1. when targeting coherent system memory, the gmch-m forwards the cycle as a 1 qw read from system sdram. the data is returned to the gmch-m. the gmch-m then returns a ?no data? response to the host and empties the returned data from its buffer. 5.2.4.10 cache coherency cycles the intel 830 chipset family gmch-m generates an implicit writeback response during host bus read and write transactions when a cpu asserts hitm# during the snoop phase. the cpu initiated write case has two data transfers, the requesting agents data followed by the snooping agents writeback data. the gmch-m will perform a memory read and invalidate cycle of length = 0 (mri[0]) on the cpu bus when a hub interface, agp/pci, or igd snoopable system sdram write cycle occurs. the gmch-m will perform a memory read cycle with length = 0 (mr[0]) on the cpu bus when a hub interface, agp/pci, or igd snoopable system sdram read cycle occurs.
intel ? 830 chipset family 152 datasheet 298338-003 r 5.2.4.11 interrupt acknowledge cycles a processor agent issues an interrupt acknowledge cycle in response to an interrupt from an 8259- compatible interrupt controller. the interrupt acknowledge cycle is similar to a partial read transaction, except that the address bus does not contain a valid address. interrupt acknowledge cycle is always directed to the hub interface (never to agp/pci, or the igd). 5.2.4.12 locked cycles the intel 830 chipset family gmch-m supports resource locking due to the assertion of the lock# line on the cpu bus as follows. 5.2.4.12.1 cpu<->system sdram locked cycles the intel 830 chipset family gmch-m supports cpu to sdram locked cycles. the host bus may not execute any other transactions until the locked cycle is complete. the gmch-m arbiter may grant another hub interface or agp device, but any ?coherent? cycles to sdram will be blocked. cpu lock operations do not block any ?non_coherent? accesses to sdram. 5.2.4.12.2 cpu<->hub interface locked cycles any cpu-to-hub interface locked transaction will initiate a hub interface locked sequence. the p6 bus implements the bus lock mechanism, which means that no change of bus ownership can occur from the time one agent, has established a locked transaction (i.e., the initial read cycle of a locked transaction has completed) until the locked transaction is completed. note that for cpu-to-hub interface lock transactions, a bit in the request packet indicates a lock transaction. any concurrent cycle that requires snooping on the host bus is not processed while a lock transaction is occurring on the host bus. hub interface-to-sdram locked cycles are not supported. 5.2.4.12.3 cpu<->agp/pci locked cycles the agp/pci1 interface does not support locked operations and therefore both cpu locked and non- locked transactions destined to agp/pci1 are propagated in the same manner. however, note that any concurrent cycle that requires snooping on the host bus is not processed while a lock transaction is occurring on the host bus. 5.2.4.12.4 cpu<->igd (graphics memory) the igd does not support locked operations and therefore both cpu locked and non-locked transactions destined to igd graphics memory are propagated in the same manner. note however, that any concurrent cycle that requires snooping on the host bus is not processed while a lock transaction is occurring on the host bus. 5.2.4.13 branch trace cycles an agent issues a branch trace cycle for taken branches if execution tracing is enabled. address aa[35:3]# is reserved and can be driven to any value. d[63:32]# carries the linear address of the instruction causing the branch and d[31:0]# carries the target linear address. the gmch-m will respond
intel ? 830 chipset family 298338-003 datasheet 153 r and retire this transaction but will not latch the value on the data lines or provide any additional support for this type of cycle. 5.2.4.14 special cycles a special cycle is defined when reqa[4:0] = 01000 and reqb[4:0]= xx001. in the first address phase aa[35:3]# is undefined and can be driven to any value. in the second address phase, ab[15:8]# defines the type of special cycle issued by the processor. all host initiated special cycles are routed to hub interface. special cycles are ?posted? into the intel 830 chipset family gmch-m. the host bus transaction is terminated immediately. it does not wait for the cycle to propagate or terminate on hub interface. table 34 specifies the cycle type and definition as well as the action taken by the gmch-m when the corresponding cycles are identified. note that none of the host bus special cycles are propagated to the agp interface. table 34. intel 830 chipset family gmch-m responses to host initiated special cycles be[7:0}# special cycle type action taken 0000 0000 nop this transaction has no side effects. 0000 0001 shutdown this transaction is issued when an agent detects a severe software error that prevents further processing. this cycle is claimed by the gmch-m and propagated as a shutdown special cycle over the hub interface bus. this cycle is retired on the cpu bus after the associated hub interface special cycle request packet is successfully broadcast over hub interface. 0000 0010 flush this transaction is issued when an agent has invalidated its internal caches without writing back any modified lines. the gmch-m claims this cycle and simply retires it. 0000 0011 halt this transaction is issued when an agent executes a hlt instruction and stops program execution. this cycle is claimed by the gmch-m and propagated over hub interface as a halt special cycle. this cycle is retired on the cpu bus after the associated hub interface special cycle request packet is successfully broadcast over hub interface. 0000 0100 sync this transaction is issued when an agent has written back all modified lines and has invalidated its internal caches. the gmch-m claims this cycle and simply retires it. 0000 0101 flush acknowledge this transaction is issued when an agent has completed a cache sync and flush operation in response to an earlier flush# signal assertion. the gmch-m claims this cycle and simply retires it. 0000 0110 stop clock acknowledge this transaction is issued when an agent enters stop clock mode. this cycle is claimed by the gmch-m and propagated over hub interface as a stop grant special cycle. this cycle is retired on the cpu bus after the associated hub interface special cycle request packet is successfully broadcast over hub interface. 0000 0111 smi acknowledge this transaction is first issued when an agent enters the system management mode (smm). ab[7]# is also set at this entry point.
intel ? 830 chipset family 154 datasheet 298338-003 r all subsequent transactions from the cpu with ab[7]# set are treated by the gmch-m as accesses to the smm space. no corresponding cycle is propagated to the hub interface. to exit the system management mode the cpu issues another one of these cycles with the ab[7]# bit deasserted. the smm space access is closed by the gmch-m at this point. all others reserved 5.2.5 in-order queue pipelining all agents on the cpu bus track the number of pipelined bus transaction with an in-order queue (ioq). the gmch-m can support an ioq depth of 8 and uses bnr# to guarantee that limit is not exceeded. 5.2.6 write combining to allow for high speed write capability for graphics, the uswc (uncacheable, speculative, write- combining) memory type provides a write-combining buffering mechanism for write operations. a high percentage of graphics transactions are writes to the memory-mapped graphics region, normally known as the linear frame buffer. reads and writes to uswc are non-cached and can have no side effects. in the case of graphics, current 32-bit drivers (without modifications) would use partial write protocol to update the frame buffer. the highest performance write transaction on the cpu bus is the line write. by combining several back-to-back partial write transactions (internal to the cpu) into a line write transaction on the cpu bus, the performance of frame buffer accesses would be greatly improved. to this end, the cpu supports the uswc memory. writes to uswc memory can be buffered and combined in the processor's write-combining buffers (wcb). the wcb is flushed after executing a serializing, locked, i/o instruction, or the wcb is full (32 bytes). the wcb can be flushed under different situations*. in order to extend this capability to the current drivers, it is necessary to set up the linear frame buffer address range to be uswc memory type. this can be done by programming the mtrr registers in the cpu. if the number of bytes in the wcb is < 32 then a series of <= 8 byte writes are performed upon wcb flushing. the gmch-m further optimizes this by providing write combining for cpu-to-hub interface, cpu-to-agp/pci, and cpu-to-igd write transactions. if the target of cpu writes is hub interface memory, then the data is combined and sent to the hub interface bus as a single write burst. the same concept applies to cpu writes to agp/pci and igd memory. the uswc writes that target system sdram are handled as regular system sdram writes. note that the application of uswc memory attribute is not limited only to the frame buffer support and that the gmch-m implements write combining for any cpu-to-hub interface or cpu-to-agp/pci posted write. *please refer to the following documents on how to implement write combining buffers: intel ? write combining memory implementation guidelines (24422) .
intel ? 830 chipset family 298338-003 datasheet 155 r 5.3 intel 830 chipset family system memory interface 5.3.1 sdram interface overview the intel 830 chipset gmch-m integrates a main memory sdram controller with a 64-bit wide interface. the gmch-m memory buffers support lvttl (sdram) signaling at 133 mhz. ? configured for single data rate sdram, the gmch memory interface includes support for: ? up to 1.0 gb of 133-mhz sdram using 512-mb technology ? pc133 so-dimms ? maximum of 2 so-dimms, single-sided and/or double-sided ? the intel 830mp/830m/830mg chipset only support 4 bank memory technologies. ? four integrated clock buffers the 2-bank select lines sm_ba[1:0] and the 13 address lines sm_ma[12:0] allow each member of the intel 830 chipset family to support 64 bit wide so-dimms using 64-mb, 128-mb, 256-mb, and 512- mb sdram technology. while address lines sm_ma[9:0] determine the starting address for a burst, burst lengths are fixed at 4. six chip selects sm_cs# lines allow maximum of three rows of single-sided so-dimms and six rows of double-sided sdram so-dimms. the intel 830 chipset family gmch-m main memory controller targets cas latencies of 2 and 3 for sdram. each member of the chipset family provides refresh functionality with programmable rate (normal sdram rate is 1 refresh/15.6 ms). for write operations of less than a qword in size, a byte- wise write will be performed. 5.3.2 sdram organization and configuration in the following discussion the term row refers to a set of memory devices that are simultaneously selected by a sm_cs# signal. the intel 830 chipset family will support a maximum of 4 rows of memory. for the purposes of this discussion, a ?side? of a so-dimm is equivalent to a ?row? of sdram devices. the 2-bank select lines sm_ba[1:0] and the 13 address lines sm_ma[12:0] allow the intel 830 chipset family to support 64-bit wide so-dimms using x16 64-mb, 128-mb, 256-mb, and 512-mb sdram technologies. table 35. system memory so-dimm configurations sdram technology( density) device depth device width devices per side capacity per side # of row addr bits # of column addr bits # of bank addr bits page size max capacity sdr(2 so- dimms) 64 mb 4m x16 4 32 mb 12 8 2 2 kb 128 mb 128 mb 8m x16 4 64 mb 12 9 2 4 kb 256 mb 256 mb 16m x16 4 128 mb 13 9 2 4 kb 512 mb 512 mb 32m x16 4 256 mb 13 10 2 8 kb 1.0 gb
intel ? 830 chipset family 156 datasheet 298338-003 r 5.3.2.1 configuration mechanism for so-dimms detection of the type of sdram installed on the so-dimm is supported via serial presence detect mechanism as defined in the jedec so-dimm specification. this uses the scl, sda and sa[2:0] pins on the so-dimms to detect the type and size of the installed so-dimms. no special programmable modes are provided on the intel 830 chipset family for detecting the size and type of memory installed. type and size detection must be done via the serial presence detection pins. 5.3.2.1.1 memory detection and initialization before any cycles to the memory interface can be supported, the intel 830 chipset family sdram registers must be initialized. the intel 830 chipset family must be configured for operation with the installed memory types. detection of memory type and size is done via the system management bus (smb) interface on the ich3-m. this two-wire bus is used to extract the sdram type and size information from the serial presence detect port on the sdram so-dimms. sdram so-dimms contain a 5-pin serial presence detect interface, including scl (serial clock), sda (serial data) and sa[2:0]. devices on the smbus have a 7-bit address. for the sdram so-dimms, the upper 4 bits are fixed at 1010. the lower three bits are strapped on the sa[2:0] pins. scl and sda are connected directly to the system management bus on the ich3-m. thus data is read from the serial presence detect port on the so-dimms via a series of io cycles to the south bridge. bios essentially needs to determine the size and type of memory used for each of the rows of memory in order to properly configure the intel 830 chipset family memory interface. 5.3.2.1.2 sdram register programming this section provides an overview of how the required information for programming the sdram registers is obtained from the serial presence detect ports on the so-dimms. the serial presence detect ports are used to determine refresh rate, ma and md buffer strength, row type (on a row by row basis), sdram timings, row sizes, and row page sizes. the following table lists a subset of the data available through the on board serial presence detect rom on each so-dimm. table 36. data bytes on so-dimm used for programming sdram registers byte function 2 memory type (edo, sdr sdram) 3 # of row addresses, not counting bank addresses 4 # of column addresses 5 # of banks of sdram (single or double sided so-dimm) 11 ecc, no ecc 12 refresh rate 17 # banks on each device 36-41 access time from clock for cas# latency 1 through 7 42 data width of sdram components 126 memory frequency table 36 is only a subset of the defined spd bytes on the so-dimms. these bytes collectively provide enough data for programming the intel 830 chipset family sdram registers.
intel ? 830 chipset family 298338-003 datasheet 157 r 5.3.3 sdram address translation and decoding the intel 830 chipset family contains address decoders that translate the address received on the host bus, or the hub interface to an effective memory address. decoding and translation of these addresses vary with the three sdram types. also, the number of pages, page sizes, and densities supported vary with the 4 sdram types. in general, the intel 830 chipset family supports 64-mb, 128-mb, 256-mb, and 512-mb sdram devices. the multiplexed row/column address to the sdram memory array is provided by the sm_ba[1:0] and sm_ma[12:0] signals. these addresses are derived from the host address bus as defined by the table above for sdram devices. table 37. address translation and decoding address usage row page bs bs ma ma ma ma ma ma ma ma ma ma ma ma ma tech depth width row col bank size 1 0 12 11 10 9 8 7 6 5 4 3 2 1 0 64 mb 4m 16 12 8 2 32 mb 2k 12 11 x 15 14 13 24 23 22 21 20 19 18 17 16 12 11 x x pa x x 10 9 8 7 6 5 4 3 128 mb 8m 16 12 9 2 64 mb 4k 13 12 x 15 14 25 24 23 22 21 20 19 18 17 16 13 12 x x pa x 11 10 9 8 7 6 5 4 3 256 mb 16m 16 13 9 2 128 mb 4k 13 12 15 14 26 25 24 23 22 21 20 19 18 17 16 13 12 x x pa x 11 10 9 8 7 6 5 4 3 512 mb 16m 16 13 10 2 256 mb 8k 14 13 15 27 26 25 24 23 22 21 20 19 18 17 16 14 13 x x pa 12 11 10 9 8 7 6 5 4 3 5.3.4 sdram performance description the overall sdram performance is controlled by the sdram timing register, pipelining depth used in the intel 830 chipset family, sdram speed grade, and the type of sdram used in the system. besides this, the exact performance in a system is also dependent on the total memory supported, external buffering and memory array layout. the most important contribution to overall performance by the system memory controller is to minimize the latency required to initiate and complete requests to memory, and to support the highest possible bandwidth (full streaming, quick turn-arounds). one measure of performance is the total flight time to complete a cache line request. a true discussion of performance really involves the entire chipset, not just the system memory controller. 5.4 intel 830m and 830mg chipset internal graphics description the intel 830m and 830mg chipset gmch-m provides a highly integrated graphics accelerator and pciset while allowing a flexible integrated system graphics solution.
intel ? 830 chipset family 158 datasheet 298338-003 r figure 15. intel 830m and 830mg chipset gmch-m graphics block diagram a gp 2.0 interface instr./ data setup/transform 3d engine scan conversion texture engine raster engine 2d engine overlay sprite cursor primary display secondary display motion compensation a lpha blend/ gamma/ cursor cntl mux port dac dvoa dvob dvoc ddc memory control direct rdram clocks/reset built-in scan power mgmt gpio high bandwidth access to data is provided through the system memory port. the intel 830m and 830mg chipset gmch-m can access uma memory located in system memory at 1.06 gb/s. the intel 830m and 830mg chipset uses a tiling architecture to minimize page miss latencies and thus maximize effective rendering bandwidth. 5.4.1 3d/2d instruction processing the intel 830m and 830mg gmch-m contain an extensive set of instructions that control various functions including 3d rendering, blt operations, display, mpeg decode acceleration, and overlay. the 3d instructions set 3d pipeline states and control the processing functions. the 2d instructions provide an efficient method for invoking blt operations. 5.4.2 3d engine the 3d engine of the intel 830m and 830mg chipset gmch-m has been designed with a deep pipelined architecture, where performance is maximized by allowing each stage of the pipeline to simultaneously operate on different primitives or portions of the same primitive. gmch-m supports perspective-correct texture mapping, multitextures, bump-mapping, cubic environment maps, bilinear, trilinear & anisotropic mip mapped filtering, gouraud shading, alpha-blending, vertex and per pixel fog, and z/w buffering. these features are independently enabled (disabled) via a set of 3d instructions. the 3d pipeline subsystem performs the 3d rendering acceleration. the main blocks of the pipeline are the setup engine, scan converter, texture pipeline, and raster pipeline. a typical programming
intel ? 830 chipset family 298338-003 datasheet 159 r sequence would be to send instructions to set the state of the pipeline followed by rendering instructions containing 3d primitive vertex data. 5.4.2.1 setup engine the intel 830m and 830mg chipset gmch-m 3d setup engine takes the input data associated with each vertex of a 3d primitive and computes the various parameters required for scan conversion. in formatting this data, gmch-m maintains sub-pixel accuracy. the per-vertex data is converted into gradients that can be used to interpolate the data at any pixel within a polygon (colors, alpha, z depth, fog, and texture coordinates). the pixels covered by a polygon are identified and per-pixel texture addresses are calculated. 5.4.2.2 viewport transform and perspective divide the 3d-geometry pipeline involves transformation of vertices from model space to clipping space followed by clip test and clipping. lighting can be performed during the transformation or at any other point in the pipeline. after clipping, the next stage involves perspective divide followed by transformation to the viewport or screen space. the intel 830m and 830mg chipset gmch-m can support viewport transform and perspective divide portion of the 3d geometry pipeline in hardware. 5.4.2.3 3d primitives and data formats support the 3d primitives rendered by the intel 830m and 830mg chipset gmch-m are points, lines, discrete triangles, line strips, triangle strips, triangle fans, and polygons. in addition to this, gmch-m supports directx6?s flexible vertex format (fvf), which enables the application to specify a variable length of parameter list obviating the need for sending unused information to the hardware. strips, fans, and indexed vertices as well as fvf improves delivered vertex rate to the setup engine significantly. 5.4.2.4 pixel accurate fast scissoring and clipping operation the intel 830m and 830mg chipset gmch-m supports clipping to a scissoring rectangle within the drawing window. gmch-m ?s clipping and scissoring in hardware reduce the need for software to process polygons, and thus improves performance. during the setup stage, gmch-m clips polygons to the drawing window. the scissor rectangle accelerates the clipping process by allowing the driver to clip to a bigger region than the hardware renders to. the scissor rectangle needs to be pixel accurate, and independent of line and point width. gmch-m supports a single scissor box rectangle. 5.4.2.5 backface culling as part of the setup, the intel 830m and 830mg chipset gmch-m discards polygons from further processing, if they are facing away from or towards the user?s viewpoint. this operation, referred to as ?back face culling? is accomplished based on the ?clockwise? or ?counter-clockwise? orientation of the vertices on a primitive. this can be enabled or disabled by the driver. 5.4.2.6 scan converter the scan converter takes the vertex and edge information is used to identify all pixels that are affected by features being rendered. it works on a per-polygon basis, and one polygon may be entering the pipeline while calculations finish on another.
intel ? 830 chipset family 160 datasheet 298338-003 r 5.4.2.7 texture engine as texture sizes increase beyond the bounds of graphics memory, executing textures from graphics memory becomes impractical. the intel 830m and mg chipset gmch-m, using intel?s direct memory execution model, simplifies this process by rendering each scene using the texture located in system memory. the 830m and 830mg chipsets include a cache controller to avoid frequent memory fetches of recently used texture data. the 830m and 830mg chipsets allow an image, pattern, or video to be placed on the surface of a 3d polygon. the texture engine performs texture color or chromakey matching, texture filtering (anisotropic, trilinear, and bilinear interpolation), and yuv to rgb conversions. 5.4.2.8 perspective correct texture support textured polygon is generated by mapping a 2d texture pattern onto each pixel of the polygon. a texture map is like wallpaper pasted onto the polygon. since polygons are rendered in perspective, it is important that texture be mapped in perspective as well. without perspective correction, texture is distorted when an object recedes into the distance. perspective correction involves a compute-intensive "per-pixel-divide" operation on each pixel. perspective correction is necessary for realistic 3d graphics. 5.4.2.8.1 texture decompression directx7.0 supports texture compression to reduce the bandwidth required to deliver textures. as the textures? average sizes (512x512) get larger with higher color depth and multiple textures become the norm, it becomes increasingly important to provide a mechanism compress textures. the intel 830m and 830mg chipset gmch-m supports dx7 decompression. texture decompression formats supported include dxt1, dxt2, dxt3, dxt4, dxt5. 5.4.2.9 texture colorkey and chromakey colorkey and chromakey describe two methods of removing a specific color or range of colors from a texture map before it is applied to an object. for ?nearest? texture filter modes, removing a color simply makes those portions of the object transparent (the previous contents of the back buffer show through). for ?linear? texture filtering modes, the texture filter is modified if only the non-nearest neighbor texels match the key (range). colorkeying occurs with paletted textures and removes colors according to an index (before the palette is accessed). when a color palette is used with indices to indicate a color in the palette, the indices can be compared against a state variable ?colorkey index value? and if a match occurs and colorkey is enabled, then this value?s contribution is removed from the resulting pixel color. the intel 830m and 830mg chipset gmch-m defines index matching as colorkey. chromakeying can be performed for both paletted and non-paletted textures, and removes texels that fall within a specified color range. the chromakey mode refers to testing the argb or yuv components to see if they fall between high and low state variable values. if the color of a texel contribution is in this range and chromakey is enabled, then this contribution is removed from the resulting pixel color. 5.4.2.10 anti-aliasing aliasing is one of the artifacts that degrade image quality. in its simplest manifestation, aliasing causes the jagged staircase effects on sloped lines and polygon edges. another artifact is the moir patterns, which occur as a result of the fact that there is very small number of pixels available on screen to contain the data of a high-resolution texture map.
intel ? 830 chipset family 298338-003 datasheet 161 r full scene anti-aliasing uses supersampling, which means that the image is rendered internally at a higher resolution than it is displayed on screen. the intel 830m and 830mg gmch-m can render internally at 1600x1200 and then this image is downsampled (via a bilinear filter) to the screen resolution of 640x480 and 800x600. full scene anti-aliasing removes jaggies at the edges as well as moir patterns. the gmch-m renders the supersampled image up to 2kx2k pixel dimensions. the gmch-m then reads it as a texture and bilinear filters it to the final resolution. 5.4.2.11 texture map filtering many texture-mapping modes are supported. perspective correct mapping is always performed. as the map is fitted across the polygon, the map can be tiled, mirrored in either the u or v directions, or mapped up to the end of the texture and no longer placed on the object (this is known as clamp mode). the way a texture is combined with other object attributes is also definable. ? 830m/830mg gmch-m supports up to 12 levels-of-detail (lods) ranging in size from 2048x2048 to 1x1 texels. (a texel is defined as a texture map element). included in the texture processor is a texture cache, which provides efficient mip-mapping. ? 830m/830mg gmch-m supports 7 types of texture filtering: ? nearest (also known as point filtering): texel with coordinates nearest to the desired pixel is used. (this is used if only one lod is present). ? linear (also known as bilinear filtering): a weighted average of a 2x2 area of texels surrounding the desired pixel are used. (this is used if only one lod is present). ? nearest mip nearest (also known as point filtering): this is used if many lods are present. the nearest lod is chosen and the texel with coordinates nearest to the desired pixel are used. ? linear mip nearest (bilinear mip mapping): this is used if many lods are present. the nearest lod is chosen and a weighted average of a 2x2 area of texels surrounding the desired pixel are used (four texels). this is also referred to as bilinear mip mapping. ? nearest mip linear (point mip mapping): this is used if many lods are present. two appropriate lods are selected and within each lod the texel with coordinates nearest to the desired pixel are selected. the final texture value is generated by linear interpolation between the two texels selected from each of the mip maps. ? linear mip linear (trilinear mip mapping): this is used if many lods are present. two appropriate lods are selected and a weighted average of a 2x2 area of texels surrounding the desired pixel in each mip map is generated (four texels per mip map). the final texture value is generated by linear interpolation between the two texels generated for each of the mip maps. trilinear mip mapping is used minimize the visibility of lod transitions across the polygon. ? anisotropic mip nearest (anisotropic filtering): this is used if many lods are present. the nearest lod-1 level will be determined for each of four sub-samples for the desired pixel. these four sub-samples are then bilinear filtered and averaged together. ? both d3d (directx 6.0) and ogl (rev.1.1) allows support for all these filtering modes. 5.4.2.12 multiple texture composition 830m/830mg gmch-m also performs multiple texture composition. this allows the combination of two or greater mip maps to produce a new one with new lods and texture attributes in a single or iterated pass. the setup engine supports up to four texture map coordinates in as single pass. gmch-m allows up to two bilinear mip maps or a single trilinear mip map to be composited in a single pass. greater than two bilinear mip maps or more than one trilinear mip map would require multiple passes.
intel ? 830 chipset family 162 datasheet 298338-003 r the actual blending or composition of the mip maps is done in the raster engine. the texture engine provides the required texels including blending information. flexible vertex format support allows multi-texturing because it makes it possible to pass more than one texture in the vertex structure. 5.4.2.13 cubic environment mapping environment maps allow applications to render scenes with complex lighting and reflections while significantly decreasing cpu load. there are several methods to generate environment maps such as spherical, circular, and cubic. 830m/830mg gmch-m has selected to support cubic reflection mapping over spherical and circular since it is the best choice to provide real-time environment mapping for complex lighting and reflections. cubic mapping requires a texture map for each of the 6 cube faces. these can be generated by pointing a camera with a 90-degree field-of-view in the appropriate direction. per-vertex vectors (normal, reflection or refraction) are interpolated across the polygon and the intersection of these vectors with the cube texture faces is calculated. texel values are then read from the intersection point on the appropriate face and filtered accordingly. 5.4.2.14 bump mapping bump mapping is a feature in the 830m/830mg gmch-m that enables a surface to appear wrinkled or dimpled without the need to model these depressions geometrically. by perturbing environment map texture coordinates on a per pixel basis using delta values read from the bump map, non-uniform lighting effects (reflections, etc.) can be applied. this can give flat objects a bumpy or raised appearance. embossing, a simpler form of bump mapping, is achieved by layering two identical texture maps. it can be supported thro ugh software to give the appearance of depth. 5.4.3 raster engine the raster engine is where the color data such as fogging, specular rgb, texture map blending, etc. is processed. the final color of the pixel is calculated and the rgba value combined with the corresponding components resulting from the texture engine. these textured pixels are modified by the specular and fog parameters. these specular highlighted, fogged, textured pixels are color blended with the existing values in the frame buffer. in parallel, stencil, alpha and depth buffer tests are conducted which will determine whether the frame and depth buffers will be updated with the new pixel values. 5.4.3.1 texture map blending multiple textures can be blended together in an iterative process and applied to a primitive. 830m/830mg gmch-m allows up to four distinct or shared texture coordinates and texture maps to be specified onto the same polygon. also, gmch-m supports using a texture coordinate set to access multiple texture maps. state variables in multiple texture are bound to texture coordinates, texture map or texture blending. 5.4.3.2 combining intrinsic and specular color components the intel 830m and 830mg gmch-m allows an independently specified and interpolated ?specular rgb? attribute to be added to the post-texture blended pixel color. this feature provides a full rgb specular highlight to be applied to a textured surface, permitting a high quality reflective colored lighting effect not available in devices, which apply texture after the lighting components have been combined. if specular-add state variable is disabled, only the resultant colors from the map blending are used. if this
intel ? 830 chipset family 298338-003 datasheet 163 r state variable is enabled, rgb values from the output of the map blending are added to values for rs, gs, bs on a component by component basis. 5.4.3.3 color shading modes the raster engine will support the flat and gouraud shading modes. these shading modes are programmed by the appropriate state variables issued through the command stream. flat shading is performed by smoothly interpolating the vertex intrinsic color components (red, green, blue), specular (r,g,b), fog, and alpha to the pixel, where each vertex color has the same value. the setup engine substitutes one of the vertex?s attribute values for the other two vertices attribute values thereby creating the correct flat shading terms. this condition is set up by the appropriate state variables issued prior to rendering the primitive. gouraud shading is performed by smoothly interpolating the vertex intrinsic color components (red, green, blue). specular (rgb), fog, and alpha to the pixel, where each vertex color has a different value. all the attributes can be selected independently to one of the shading mode by setting the appropriate value state variables. 5.4.3.4 color dithering color dithering in the gmch-m helps to hide color quantization errors. color dithering takes advantage of the human eye?s propensity to ?average? the colors in a small area. input color, alpha, and fog components are converted from 8-bit components to 5-bit or 6- bit component by dithering. dithering is performed on blended textured pixels. in 32-bit mode, dithering is not performed on the components 5.4.3.5 vertex and per pixel fogging fogging is used to create atmospheric effects such as low visibility conditions in flight simulator-type games. it adds another level of realism to computer-generated scenes. fog can be used for depth cueing or hiding distant objects. with fog, distant objects can be rendered with fewer details (less polygons), thereby improving the rendering speed or frame rate. fog is simulated by attenuating the color of an object with the fog color as a function of distance, and the greater the distance, the higher the density (lower visibility for distant objects). there are two ways to implement the fogging technique: per-vertex (linear) fogging and per-pixel (non-linear) fogging. the per-vertex method interpolates the fog value at the vertices of a polygon to determine the fog factor at each pixel within the polygon. this method provides realistic fogging as long as the polygons are small. with large polygons (such as a ground plane depicting an airport runway), the per-vertex technique results in unnatural fogging gmch-m supports both types of fog operations, vertex and per pixel or table fog. if fog is disabled, the incoming color intensities are passed unchanged to the destination blend unit. if fog is enabled, the incoming pixel color is blended with the fog color based on a fog coefficient on a per pixel basis using the following equation before sending to the destination blend unit. 5.4.3.6 alpha blending (frame buffer) alpha blending in the intel 830m and 830mg gmch-m adds the material property of transparency or opacity to an object. alpha blending combines a source pixel color (rsgsbs) and alpha (as) component with a destination pixel color (rdgdbd) and alpha(ad) component. for example, this is so that a glass
intel ? 830 chipset family 164 datasheet 298338-003 r surface on top (source) of a red surface (destination) would allow much of the red base color to show through. blending allows the source and destination color values to be multiplied by programmable factors and then combined via a programmable blend function. the combined and independent selection of factors and blend functions for color and alpha is supported. 5.4.3.7 color buffer formats: (destination alpha) the raster engine will support 8-bit, 16-bit, and 32-bit color buffer formats. the 8-bit format is used to support planar yuv420 format, which used only in motion compensation and arithmetic stretch format. the bit format of color and z will be allowed to mix. the intel 830m and 830mg gmch-m will support an 8-bit destination alpha in 32-bit mode. destination alpha will be supported in 16-bit mode in 1555 or 4444 format. gmch-m does not support general 3d rendering to 8-bit surfaces. 8-bit destinations are supported for operations on planar yuv surfaces (e.g., stretch blts) where each 8-bit color component is written in a separate pass. gmch-m also supports a mode where both u and v planar surfaces can be operated on simultaneously. the frame buffer of gmch-m contains at least two hardware buffers-the front buffer (display buffer) and the back buffer (rendering buffer). while the back buffer may actually coincide with (or be part of) the visible display surface, a separate (screen or window-sized) back buffer is typically used to permit double-buffered drawing. that is, the image being drawn is not visible until the scene is complete and the back buffer made visible or copied to the front buffer via a 2d blt operation. rendering to one buffer and displaying from the other buffer removes image tearing artifacts. additionally, more than two back buffers (e.g., triple-buffering) can be supported. 5.4.3.8 depth buffer the raster engine will be able to read and write from this buffer and use the data in per fragment operations that determine resultant color and depth value of the pixel for the fragment are to be updated or not. typical applications for entertainment or visual simulations with exterior scenes require far/near ratios of 1000 to 10000. at 1000, 98 percent of the range is spent on the first 2 percent of the depth. this can cause hidden surface artifacts in distant objects, especially when using 16-bit depth buffers. a 24-bit z- buffer provides 16 million z-values as opposed to only 64k with a 16-bit z-buffer. with lower z- resolution, two distant overlapping objects may be assigned the same z-value. as a result, the rendering hardware may have a problem resolving the order of the objects, and the object in the back may appear through the object in the front. by contrast, when w (or eye-relative z) is used, the buffer bits can be more evenly allocated between the near and far clip planes in world space. the key benefit is that the ratio of far and near is no longer an issue, allowing applications to support a maximum range of miles, yet still get reasonably accurate depth buffering within inches of the eye point. the selection of depth buffer size is relatively independent of the color buffer. a 16 bit z/w or 24 bit z/w buffer can be selected with a 16-bit color buffer. z buffer is not supported in 8-bit mode. 5.4.3.9 stencil buffer the raster engine will provide 8-bit stencil buffer storage in 32-bit mode and the ability to perform stencil testing. stencil testing controls 3d drawing on a per pixel basis, which conditionally eliminates a
intel ? 830 chipset family 298338-003 datasheet 165 r pixel on the outcome of a comparison between a stencil reference value and the value in the stencil buffer at the location of the source pixel being processed. they are typically used in multipass algorithms to achieve special effects, such as decals, outlining, shadows and constructive solid geometry rendering. one of three possible stencil operations is performed when stencil testing is enabled. the stencil operation specifies how the stencil buffer is modified when a fragment passes or fails the stencil test. the selection of the stencil operation to be performed is based upon the result of the stencil test and the depth test. a stencil write mask is also included that controls the writing of particular bits into the stencil buffer. it selects between the destination value and the updated value on a per-bit basis. the mask is 8- bit wide. 5.4.3.10 projective textures 830m/830mg gmch-m will support two simultaneous projective textures at full rate processing. these textures require 3 floating-point texture coordinates to be included in the fvf format. projective textures enable special effects such as projecting spot light textures obliquely onto walls, etc. 5.4.4 2d engine the 830m and 830mg chipset gmch-m provide an extensive set of 2d instructions and 2d hw acceleration for block transfers of data (blts). the blt engine provides the ability to copy a source block of data to a destination and perform operations (e.g., rop1, rop2, and rop3) on the data using a pattern, and/or another destination. the stretch blt engine is used to move source data to a destination that need not be the same size, with source transparency. performing these common tasks in hardware reduces cpu load, and thus improves performance. 5.4.4.1 gmch-m vga registers and enhancements the 2d registers are a combination of registers defined by ibm* when the video graphics array (vga) was first introduced and others that intel has added to support graphics modes that have color depths, resolutions, and hardware acceleration features that go beyond the original vga standard. 5.4.4.2 256-bit pattern fill and blt engine use of this blt engine accelerates the graphical user interface (gui) of microsoft* windows*. the gmch-m blt engine provides hardware acceleration of block transfers of pixel data for many common windows operations. the term blt refers to a block transfer of pixel data between memory locations. the blt engine can be used for the following: ? move rectangular blocks of data between memory locations ? data alignment ? perform logical operations (raster ops) the rectangular block of data does not change as it is transferred between memory locations. data to be transferred can consist of regions of memory, patterns, or solid color fills. a pattern will always be 8x8 pixels wide and may be 8, 16, or 32 bits per pixel. the 830m/830mg gmch-m blt engine has the ability to expand monochrome data into a color depth of 8, 16, or 32 bits. blts can be either opaque or transparent. opaque transfers, move the data specified to the destination. transparent transfers compare destination color to source color and write according to the mode of transparency selected.
intel ? 830 chipset family 166 datasheet 298338-003 r data is horizontally and vertically aligned at the destination. if the destination for the blt overlaps with the source memory location, gmch-m can specify which area in memory to begin the blt transfer. hardware is included for all 256 raster operations (source, pattern, and destination) defined by microsoft, including transparent blt. gmch-m has instructions to invoke blt operations, permitting software to set up instruction buffers and use batch processing as described in the instruction processing section. gmch-m can perform hardware clipping during blts. 5.4.4.3 alpha stretch blt the stretch blt function can stretch source data in the x and y directions to a destination larger or smaller than the source. stretch blt functionality expands a region of memory into a larger or smaller region using replication and interpolation. the stretch blt function also provides format conversion and data alignment. 5.4.5 planes and engines intel 830m and 830mg gmch display can be functionality delineated into: planes and engines (pipes and ports). a plane consists of rectangular shaped image that has characteristics such as source, size, position, method, and format. these planes get attached to source surfaces, which are rectangular memory surfaces with a similar set of characteristics. they are also associated with a particular destination pipe. a pipe consists of a set of planes that will be combined and a timing generator. a port is the destination for the result of the pipe. therefore, planes are associated with pipes and pipes are associated with ports . 5.4.5.1 dual display functionality the display consists of two display pipes. pipes have a set of planes that are assigned to them as sources. the analog display port is restricted to pipe a, while any of the dvos may use either pipe a or pipe b. this limits the resolutions available on a digital display when an analog crt is active. please refer to the intel ? 830m pc10 product requirements (please contact local intel representative).
intel ? 830 chipset family 298338-003 datasheet 167 r table 38. dual display usage model display pipe a display pipe b crt lcd crt dvi crt tv crt lcd (dvob+dvoc) crt dvi (dvob+dvoc) lcd tv lcd dvi (dvob+dvoc) lcd (dvob+dvoc) dvi lcd (dvob+dvoc) tv dvi tv 5.4.6 hardware cursor plane the intel 830m and 830mg chipsets support two hardware cursors. the cursor plane is one of the simplest display planes. with a few exceptions, has a fixed size of 64x64 and a fixed z-order (top). in legacy modes, cursor can cause the display data below it to be inverted. in the alpha blend mode, true color cursor data can be alpha blended into the display stream. it can be assigned to either display pipe a or display pipe b and dynamically flipped from one to the other when both are running. 5.4.6.1 cursor color formats color data can be in an indexed format or a true color format. indexed data uses the entries in the four- entry cursor palette to convert the two-bit index to a true color format before being passed to the blenders. the index can optionally specify that a cursor pixel be transparent or cause an inversion of the pixel value below it or one of two colors from the cursor palette. blending of yuv or rgb data is only supported with planes that have data of the same format. 5.4.6.2 cursor hot spot there is the additional function of defining a cursor hot spot. this hot spot is the pixel that is positioned over the user selection. this is accomplished by allowing negative xy offset values and ones that exceed the size of the underlying active region and trimming the excess display data. 5.4.6.3 popup plane the popup plane is used for control functions in mobile applications. this is not used for typical desktop applications. only the hardware cursor has a higher z-order precedence over the hardware icon. in standard modes (non-vga) either cursor a or cursor b can be used as a popup icon. for vga modes, 32-bpp data format is not supported.
intel ? 830 chipset family 168 datasheet 298338-003 r 5.4.6.4 popup color formats source color data for the popup is in an indexed format. indexed data uses the entries in the four-entry cursor palette to convert the two-bit index to a true color format before being passed to the blenders. blending of color data is only supported with data of the same format. 5.4.7 overlay plane the overlay engine provides a method of merging either video capture data (from an external video capture device) or data delivered by the cpu, with the graphics data on the screen. 5.4.7.1 multiple overlays a single overlay plane and scalar is implemented. this overlay plane can be connected to the primary display, secondary display or in bypass mode. in the default mode, it appears on the primary display. the overlay may be displayed in a multi-monitor scenario for single-pipe simultaneous displays only. picture-in-picture feature is supported via software through the arithmetic stretch blitter. 5.4.7.2 source/destination color-/chroma-keying overlay source/destination chroma-keying enables blending of the overlay with the underlying graphics background. destination color-/chroma-keying can be used to handle occluded portions of the overlay window on a pixel-by-pixel basis that is actually an underlay. destination color keying supports a specific color (8 or 15 bit) mode as well as 32 bit alpha blending. source color-/chroma-keying is used to handle transparency based on the overlay window on a pixel-by- pixel basis. this is used when ?blue screening? an image to overlay the image on a new background later. 5.4.7.3 gamma correction to compensate for overlay color intensity loss, the overlay engine supports independent gamma correction. this allows the overlay data to be converted to linear data or corrected for the display device when not blending. 5.4.7.4 yuv to rgb conversion the format conversion can be bypassed in the case of rgb source data. 5.4.7.5 color control color control provides a method of changing the color characteristics of the pixel data. it is applied to the data while in yuv format and uses input parameters such as brightness, saturation, hue (tint) and contrast. this feature is supplied for the overlay only and works in yuv formats only. 5.4.7.6 x/y mirroring both x or y mirroring in the overlay is supported for video conferencing applications .
intel ? 830 chipset family 298338-003 datasheet 169 r 5.4.7.7 dynamic bob and weave interlaced data that originates from a video camera creates two fields that are temporally offset by 1/60 of a second. there are several schemes to de-interlace the video stream: line replication, vertical filtering, field merging and vertical temporal filtering. field merging takes lines from the previous field and inserts them into the current field to construct the frame ? this is known as weaving. this is the best solution for images with little motion; however, showing a frame that consists of the two fields will have serration or feathering of moving edges when there is motion in the scene. vertical filtering or ?bob? interpolates adjacent lines rather replicating the nearest neighbor. this is the best solution for images with motion however, it will have reduced spatial resolution in areas that have no motion and introduces jaggies. in absence of any other de-interlacing, these form the baseline and are supported by intel 830 m and mg chipset gmch-m. 5.4.8 video functionality 5.4.8.1 mpeg-2 decoding gmch-m mpeg2 decoding supports hardware motion compensation (mc). gmch-m can accelerate video decoding for the following video coding standards: ? mpeg-2: full feature support ? mpeg-1: full feature support ? h.261: full feature support ? h.263: full feature support ? h.263+: most of features with some exceptions of h.263+ optional features ? mpeg-4: only supports some features in the simple profile. the intel 830m and 830mg chipset hwmc interface is optimized for microsoft?s va api. hardware video acceleration api (hva) is a generic directdraw and directshow interface supported in windows 2000 and windows 98 millennium to provide video decoding acceleration. direct va is the open standard implementation of hva, which is natively supported by the intel 830m and 830mg chipset?s hardware. 5.4.8.2 hardware motion compensation the motion compensation (mc) process consists of reconstructing a new picture by predicting (either forward, backward, or bi-directional) the resulting pixel colors from one or more reference pictures. the intel 830m and 830mg gmch-m receives the video stream and implements motion compensation and subsequent steps in hardware. performing motion compensation in hardware reduces the processor demand of software-based mpeg-2 decoding, and thus improves system performance. 5.5 intel 830m and 830mg chipset internal graphics display interface 830m/830mg gmch-m has two dedicated display ports, the analog port and digital display port a (dvoa). digital display port b (dvob) and port c (dvoc) are multiplexed with the agp interface and are compromised if an external agp graphics device is in use. examples of this are tv encoders, external dacs, lvds transmitters, and tmds transmitters. each display port has control signals that
intel ? 830 chipset family 170 datasheet 298338-003 r may be used to control, configure and/or determine the capabilities of an external device. the data that is sent out the display port is selected from one of the two possible sources; display pipe a or display pipe b. dvob & dvoc can also operate in a ?gang? mode, where the data bus is connected to both display ports, allowing a single device to take data at twice the pixel rate. gmch-m?s digital display ports are capable of driving a 165-mhz pixel clock. when in dual channel mode (dvob + dvoc), gmch-m can be configured in gang mode to drive larger digital displays. the intel 830m and 830mg chipset has three digital interfaces through display port (dvoa, dvob, and dvoc). each interface is capable of driving a 165-mhz pixel clocks up to 165 mhz. the dvo interface can support a variety of tv encoders, external dacs, lvds transmitters, and tmds transmitters. each display port has control signals that may be used to control, configure and/or determine the capabilities of an external device. the data that is sent out the display port is selected from one of the two possible sources; display pipe a or display pipe b. dvob & dvoc can also operate in a ?gang? mode, where the data bus is connected to both display ports, allowing a single device to take data at twice the pixel rate. when in dual channel mode (dvob + dvoc), gmch-m can be configured in gang mode to drive larger digital displays. in addition, the intel 830m chipset can also support a discrete agp graphics device by multiplexing an agp interface with the dvob and dvoc interfaces. 5.5.1 analog display port characteristics the analog display port provides a rgb signal output along with a hsync and vsync signal. there is an associated ddc signal pair that is implemented using gpio pins dedicated to the analog port. the intended target device is for a crt based monitor with a vga connector. 5.5.1.1 integrated ramdac the display function contains a ram-based digital-to-analog converter (ramdac) that transforms the digital data from the graphics and video subsystems to analog data for the crt monitor. three 8-bit dacs provide the r, g, and b signals to the monitor. 5.5.1.2 ddc (display data channel) ddc is defined by vesa. its purpose is to allow communication between the host system and display. both configuration and control information can be exchanged allowing plug-and-play systems to be realized. support for ddc 1 and 2 is implemented. 5.5.2 dvo display interface the intel 830m and mg gmch-m has several options for driving digital displays. the intel 830m and 830mg chipset gmch-m contains a dedicated digital display channel that can support dvo devices. the intel 830m chipset also has two digital display channels that are multiplexed on the agp interface. when an external agp graphics accelerator is not present, the intel 830m chipset can use the multiplexed dvos to provide extra dvo display options. 5.5.2.1 dedicated digital display channel - dvoa the intel 830m and 830mg gmch-m has a dedicated port for digital display support. it will consist of a 12-bit digital data bus with accompanying clocks and control signals. please refer to section 3.6.1 for a detailed description of these signals. this port utilizes a 1.5-v interface for high speed signaling,
intel ? 830 chipset family 298338-003 datasheet 171 r supporting a pixel clock up to 165 mhz. the port is designed to connect to a transmission device capable of tmds or tv-out type signaling. for more details on the functionality of this interface, please refer to the latest dvo specification. 5.5.2.2 multiplexed digital display channels ? dvob and dvoc the intel 830m gmch-m also has the capability to support additional digital display devices through two digital visual ports muxed with the agp signals. when an external graphics accelerator is utilized via agp, these digital display capabilities are compromised. the two multiplexed dvos are very similar to the dedicated dvo. the muxed dvos each support a pixel clock up to 165 mhz and can support a variety of transmission devices. when using a 24-bit external transmitter, it will be possible to pair the two dvos to support a single digital display with higher resolutions and refresh rates. 5.5.2.2.1 optional high speed (dual channel) interface the multiplexed digital display ports can operate in either two 12-bit port mode or a single 24-bit mode. the 24-bit mode uses the 12-bit dvob data pins combined with the dvoc data pins to make a 24-bit bus. this doubles the transfer rate capabilities of the port. in the single port case, horizontal periods have a granularity of a single pixel clock; in the double case horizontal periods have a granularity of two pixel clocks. in both cases, data is transferred on both edges of the differential clock. 5.5.2.3 ddc (display data channel) the dedicated digital display interface (dvoa) uses the ddc2_clk/ddc2_data or i2c_clk /i2c_data to interrogate the panel. gmch-m supports the ddc2b protocol to initiate the transfer of edid information. the dedicated digital display interface uses the i2c bus to interrogate the external transmitter. the multiplexed digital display interface (dvob & dvoc) uses the m_i2c_clk/m_i2c_data or m_ddc1_clk/m_ddc1_data to interrogate the panel. gmch-m supports the ddc2b protocol to initiate the transfer of edid data. the multiplexed digital display interface uses the m_i2c bus to interrogate the external transmitter. 5.5.2.4 third party tmds/lvds support capabilities the intel 830m and 830mg chipset gmch-m is compliant with the dvi specification 1.0. when combined with a dvi compliant device, the gmch-m dvo port can drive a flat panel or a digital crt. 5.5.2.5 tv encoder capabilities the intel 830m and 830mg chipset gmch-m supports tv encoders through the digital video output (dvo) interface. gmch-m will generate the proper timing for the external encoder. the external encoder is responsible for generation of the proper format signal. since the gmch-m dvo interface is 1.5 v, care should be taken to ensure that the tv encoder is operational at that signaling voltage. the tv-out interface on gmch-m is addressable as a master device. this allows an external tv encoder device to drive a pixel clock signal on dvox_clkin that the intel 830m and 830mg chipset will use as a reference frequency. the frequency of this clock is dependent on the output resolution required. data is driven to the encoder across 12 data lines, along with clock pair and sync signals. the encoder can expect a continuous flow of data from gmch-m because data will not be throttled.
intel ? 830 chipset family 172 datasheet 298338-003 r 5.5.2.5.1 flicker filter and overscan compensation overscan compensation scaling and the flicker filter is done in the external tv encoder chip. care must be taken to allow for support of tv sets with high performance de-interlacers and progressive scan displays connected to by way of a non-interlaced signal. timing will be generated with pixel granularity to allow more overscan ratios to be supported. 5.5.2.5.2 direct yuv from overlay when source material is in the yuv format and is destined for a device that can take yuv format data in, it is desired to send the data without converting it to rgb. this avoids the truncation errors associated with multiple color conversion steps. the common situation will be that the overlay source data is in the yuv format and will bypass the conversion to rbg as it is sent to the tv port directly. 5.5.2.5.3 analog content protection analog content protection will be provided through the external encoder using macrovision 7.01. dvd software must verify the presence of a macrovision tv encoder before playback continues. simple attempts to disable the macrovision operation must be detected. 5.5.2.5.4 support of progressive scan sdtv tvs support will be included for progressive scan tv devices thro ugh the tv port. this su pport will include the resolutions of 480p and 1080i using both a yuv analog signal with sync on y and a rgb hv connection for tvs with that connection. table 39. dvo usage model dvoa dvob dvoc lcd dvi tv lcd tv dvi lcd dvi or tv dvi (dvob+dvoc) lcd (dvob+dvoc) dvi or tv lcd dvi or tv dvi or tv dvi or tv lcd the intel 830m and 830mg chipset gmch-m do not support two tv encoders devices at a time . 5.5.3 concurrent and simultaneous display the intel 830m and 830mg chipset gmch-m has two independent pipes, each with its own timing generator and dot clock, and thus is able to support two displays concurrently. windows* 98 and windows* 2000 have enabled support for multi-monitor display. there are two types of multi-monitor solutions: concurrent and simultaneous. concurrent displays different data on two screens whereas simultaneous displays the same information on both displays. the gmch-m also supports a combination of concurrent and simultaneous displays.
intel ? 830 chipset family 298338-003 datasheet 173 r 5.6 intel 830m and 830mp discrete agp interface the 830m and 830mp chipset will support 1.5-v agp 1x/2x/4x devices. the agp signal buffers will have one mode of operation; 1.5-v drive/receive (not 3.3-v tolerant). the gmch-m will support 4x (266mt/s) clocking transfers for read and write data, and sideband addressing. the gmch-m has a 32- deep agp request queue. the gmch-m integrates a fully associative 16 entry translation look-aside buffer. agp semantic transactions to system sdram do not get snooped and are therefore not coherent with the cpu caches. pci semantic transactions on agp to system sdram are snooped. agp semantic accesses to hub interface/pci are not supported. pci semantic access from an agp master to hub interface is not supported. 5.6.1 agp target operations as an initiator, the 830m and 830mp gmch-m does not initiate cycles using agp enhanced protocols. the gmch-m supports agp target interface to main memory only. the gmch-m supports interleaved agp and pci transactions. the following table summarizes target operation support of gmch-m for agp masters. table 40. agp commands supported by gmch-m when acting as an agp target agp command c/be[3:0]# gmch-m host bridge encoding cycle destination response as agp target read 0000 main memory low priority read 0000 hub interface complete with random data hi-priority read 0001 main memory high priority read 0000 hub interface complete with random data reserved 0010 n/a no response reserved 0011 n/a no response write 0100 main memory low priority write 0100 hub interface cycle goes to sdram with be?s inactive hi-priority write 0101 main memory high priority write 0101 hub interface cycle goes to sdram with be?s inactive - does not go to hub interface reserved 0110 n/a no response reserved 0111 n/a no response long read 1000 main memory low priority read hub interface complete locally with random data - does not go to hub interface hi-priority long read 1001 main memory high priority read hub interface complete with random data flush 1010 gmch-m complete with qw of random data reserved 1011 n/a no response
intel ? 830 chipset family 174 datasheet 298338-003 r fence 1100 gmch-m no response ? flag inserted in gmch- m request queue reserved 1101 n/a no response reserved 1110 n/a no response reserved 1111 n/a no response note: n/a refers to a function that is not applicable. as a target of an agp cycle, the gmch-m supports all the transactions targeted at main memory and summarized in the table above. the gmch-m supports both normal and high priority read and write requests. the gmch-m will not support agp cycles to hub interface. agp cycles do not require coherency management and all agp initiator accesses to main memory using agp protocol are treated as non-snoopable cycles. these accesses are directed to the agp aperture in main memory that is programmed as either uncacheable (uc) memory or write combining (wc) in the processor?s mtrrs. 5.6.2 agp transaction ordering the intel 830m and 830mp chipset gmch-m observes transaction ordering rules as defined by the agp 2.0 specification. 5.6.3 agp electricals 4x/2x/1x and pci data transfers use 1.5v signaling levels as described in the agp 2.0 specification. 5.6.4 support for pci-66 devices the intel 830m and 830mp chipset gmch-m?s agp interface may be used as a pci-66 mhz interface with the following restrictions: ? support for 1.5-v operation only. ? support for only one device. gmch-m will not provide arbitration or electrical support for more than one pci-66 device. ? the pci-66 device must meet the agp 2.0 electrical specification. ? the gmch-m does not provide full pci-to-pci bridge support between agp/pci and hub interface. traffic between agp and hub interface is limited to hub interface-to-agp memory writes. ? lock# signal is not present. neither inbound nor outbound locks are supported. ? serr#/perr# signals are not present. ? 16-clock subsequent data latency timer (instead of 8) 5.6.5 4x agp protocol in addition to the 1x and 2x agp protocol the intel 830m and 830mp gmch-m supports 4x agp read and write data transfers, and 4x sideband address generation. 4x operation will be compliant with the 4x agp spec as currently described in agp 2.0. the 4x data transfer protocol provides 1.06 gb/s transfer rates. the control signal protocol for the 4x data transfer protocol is identical to 1x/2x protocol. in 4x mode 16 bytes of data are transferred during
intel ? 830 chipset family 298338-003 datasheet 175 r each 66-mhz clock period. the minimum throttle-able block size remains four 66-mhz clocks which means 64 bytes of data is transferred per block. three additional signal pins are required to implement the 4x data transfer protocol. these signal pins are complementary data transfer strobes for the ad bus (2) and the sba bus (1). 5.6.6 fast writes the fast write (fw) transaction is from the core logic to the agp master acting as a pci target. this type of access is required to pass data/control directly to the agp master instead of placing the data into main memory and then having the agp master read the data. for 1x transactions, the protocol simply follows the pci bus specification. however, for higher speed transactions (2x or 4x), fw transactions will follow a combination for pci and agp bus protocols for data movement. 5.6.7 agp-to-memory read coherency mechanism the global write buffer (gwb) in the intel 830mpand 830m chipset is used to post write data from the cpu, agp/pci, and hub interfaces prior to the data actually being written to system sdram. reads to system sdram are allowed to pass writes in the gwb. this policy requires that all reads to sdram be checked against the writes in the gwb to maintain data coherency. if an agp read hits a write in the gwb, that particular write in the gwb and all writes queued in front of it are written to sdram prior to the read. after the data hit by the agp read is written to sdram the agp read cycle is generated to the sdram. 5.6.8 pci semantic transactions on agp the intel 830m and 830mp chipset gmch-m accepts and generates pci semantic transactions on the agp bus. the gmch-m guarantees that pci semantic accesses to sdram are kept coherent with the cpu caches by generating snoops to the cpu bus. 5.6.8.1 pci read snoop-ahead and buffering the intel 830m and 830mp chipset gmch-m issues snoops dynamically for the various types of memory read transactions and retains the contents of the agp/pci-to-sdram read buffers between agp/pci transactions. for memory reads the gmch-m will issue one snoop and the entire cache line of read data will be buffered. if a memory read bursts across the cache line, another snoop will be issued. subsequent memory read transaction hitting the cache line buffer will return data from the buffer. for memory read line and memory read multiple the gmch-m issues two snoops (a snoop followed by a snoop-ahead) on the host bus and releases the cpu bus for other traffic. when the first dw of the first cache line is delivered and frame# is still asserted, the gmch-m will issue another snoop-ahead on the host bus. this allows the gmch-m to continuously supply data during memory read line and memory read multiple bursts. when the transaction terminates there may be a minimum of 2 cache lines and a maximum of 2 cache line plus 7 dwords buffered. subsequent memory reads hitting the buffers will return data from the buffer. 5.6.8.2 intel 830m and 830mp chipset gmch-m initiator and target operations the following table summarizes target operation support of the intel 830m and 830mp chipset gmch- m for agp/pci1 bus initiators. the cycles can be destined to either main memory or the hub interface bus.
intel ? 830 chipset family 176 datasheet 298338-003 r table 41. pci commands supported by gmch-m when acting as a pci target pci command c/be[3:0]# encoding gmch-m cycle destination response as pci target interrupt acknowledge 0000 n/a no response special cycle 0001 n/a no response i/o read 0010 n/a no response i/o write 0011 n/a no response reserved 0100 n/a no response reserved 0101 n/a no response memory read 0110 main memory read 0110 hub interface no response memory write 0111 main memory posts data 0111 hub interface no response reserved 1000 n/a no response reserved 1001 n/a no response configuration read 1010 n/a no response configuration write 1011 n/a no response memory read multiple 1100 main memory read 1100 hub interface no response dual address cycle 1101 n/a no response memory read line 1110 main memory read 1110 hub interface no response memory write and invalidate 1111 main memory posts data 1111 hub interface no response note: n/a refers to a function that is not applicable. as a target of an agp/pci cycle, gmch-m only supports the following transactions: memory read - the gmch-m will issue one snoop and the entire cache line of read data will be buffered. if a memory read bursts across the cache line another snoop will be issued but the transaction will be disconnected on the cache line boundary. subsequent memory read transaction hitting the cache line buffer will return data from the buffer. memory read line, and memory read multiple - these commands are supported identically by the gmch-m. the gmch-m issues two snoops (a snoop followed by a snoop-ahead) on the host bus and releases the cpu bus for other traffic. when the first dw of the first cache line is delivered and frame# is still asserted, the gmch-m will issue another snoop-ahead on the host bus. this allows the gmch-m to continuously supply data during memory read line and memory read multiple bursts. when the transaction terminates there may be a minimum of 2 cache lines and a maximum of 2 cache line plus 7 dwords buffered. subsequent memory reads hitting the buffers will return data from the buffer. memory write and memory write and invalidate - these commands are aliased and processed identically. the gmch-m supports data streaming for pci-to-sdram writes based on its
intel ? 830 chipset family 298338-003 datasheet 177 r ability to buffer up to 128 bytes (16 qwords) of data before a snoop cycle must be completed on the host bus. the gmch-m is typically able to support longer write bursts, with the maximum length dependent upon concurrent host bus traffic during pci-sdram write data streaming. fast back-to-back transactions - gmch-m as a target supports fast back-to-back cycles from a pci initiator. as a pci initiator the gmch-m is responsible for translating host cycles to agp/pci1 cycles. the gmch-m also transfers hub interface to agp/pci1 write cycles. the following table shows all the cycles that need to be translated.
intel ? 830 chipset family 178 datasheet 298338-003 r table 42. pci commands supported by gmch-m when acting as an agp/pci1 initiator gmch-m host brid g e source bus command other encoded information corresponding pci1 command c/be[3:0]# encoding source bus: host deferred reply don?t care none n/a interrupt acknowledge length 8 bytes none n/a special cycle shutdown none n/a halt none n/a stop clock grant none n/a all other combinations none n/a branch trace message none none n/a i/o read length 8 bytes up to 4 bex asserted i/o read 0010 i/o write length 8 bytes up to 4 bex asserted i/o write 0011 i/o read to 0cfch length 8 bytes up to 4 bex asserted configuration read 1010 i/o write to 0cfch length 8 bytes up to 4 bex asserted configuration write 1011 length < 8 bytes without all bes asserted memory read 0110 memory read (code or data) length = 8 bytes with all bes asserted memory read 1110 memory read invalidate length = 16 bytes none n/a length = 32 bytes code only memory read 1110 length < 8 bytes without all bes asserted memory write 0111 memory write length = 16 bytes none n/a length = 32 bytes memory write 0111 locked access all combinations unlocked access 1 as applicable reserved encodings all combinations none n/a ea memory access address 4 gb none n/a source bus: hub interface memory write - memory write 0111 notes: 1. cpu to agp/pci1 bus can result in deadlocks. locked access to agp/pci1 bus is strongly discouraged 2. n/a refers to a function that is not applicable. not supported refers to a function that is available but specifically not implemented on gmch-m.
intel ? 830 chipset family 298338-003 datasheet 179 r as an initiator of agp/pci1 cycle, the gmch-m only supports the following transactions: memory read - all cpu to agp/pci1 reads will use the memory read command. memory write - gmch-m initiates agp/pci1 cycles on behalf of the cpu or hub interface. gmch- m does not issue memory write and invalidate as an initiator. gmch-m does not support write merging or write collapsing. gmch-m will combine cpu-to-pci writes (dword or qword) to provide bursting on the agp/pci1 bus. gmch-m allows non-snoopable write transactions from hub interface to the agp/pci1 bus. i/o read and write - i/o read and write from the cpu are sent to the agp/pci1 bus. i/o base and limit address range for pci1 bus are programmed in agp/pci1 configuration registers. all other accesses that do not correspond to this programmed address range are forwarded to hub interface. exclusive access - gmch-m will not issue a locked cycle on agp/pci1 bus on the behalf of either the cpu or hub interface. hub interface and cpu locked transactions to agp/pci1 will be initiated as unlocked transactions by the gmch-m on the agp/pci1 bus. configuration read and write - host configuration accesses to internal gmch-m registers are driven onto agp/pci1 as type 1 configuration cycles where they are then claimed by the gmch-m. this is done to support co-pilot mode. host configuration cycles to agp/pci1 are forwarded as type 1 configuration cycles. 5.6.8.3 gmch-m retry/disconnect conditions the intel 830m and 830mp gmch-m generates retry/disconnect according to the agp specification rules when being accessed as a target from the agp interface (using pci semantics). 5.6.8.4 delayed transaction when an agp/pci-to-sdram read cycle is retried by the gmch-m it will be processed internally as a delayed transaction. the intel 830m and 830mp gmch-m supports the delayed transaction mechanism on the agp target interface for the transactions issued using pci semantics. this mechanism is compatible with the pci 2.2 specification. the process of latching all information required to complete the transaction, terminating with retry, and completing the request without holding the master in wait-states is called a delayed transaction. the gmch-m latches the address and command when establishing a delayed transaction. the gmch-m generates a delayed transaction on the agp only for sdram read accesses. 5.7 intel 830 chipset family gmch-m power and thermal management the following list provides the gmch-m power and thermal management features: ? acpi 1.0b & 2.0 support ? mobile power reduction operating modes (c3, s1) ? system states: s0, s1, s3, s4, s5 ? cpu states: c0, c1, c2, c3
intel ? 830 chipset family 180 datasheet 298338-003 r ? graphics states: d0, d1, d3 ? compatible with intel 815em agp busy/stop protocol ? enhanced intel speedstep ? technology support ? thermal throttling for main memory, and graphics 5.7.1 acpi 2.0 support advanced configuration and power management interface (acpi) primarily describes and runs motherboard devices. it is completely controlled by the operating system that os drivers directly power down pci/agp devices. system or smi bios plays a part of waking the system, however. device drivers save and restore state while bus drivers change the physical power state of the device. the intel 830 chipset family gmch-m power management architecture is designed to allow single systems to support multiple suspend modes and to switch between those modes as required. a suspended system can be resumed via a number of different events. the system returns to full operation where it can continue processing or be placed into another suspend mode (potentially a lower power mode than it resumed from). gmch-m supports the minimum requirements for acpi support. gmch-m must support the minimum requirements for both system logic and for graphics controllers, as well as be capable of controlling monitors minimum functions. the transition sequences of entering and exiting system, cpu and graphics states are described in respective sections below. 5.7.2 acpi states supported 5.7.2.1 intel 830m and 830mp chipset acpi supported states when a discrete agp interface is used, the intel 830m and 830mp chipset supports the following acpi states: 1. system states g0/s0 full on g1/s1 power on suspend (pos). system context preserved. g1/s3 suspend to ram (str). power and context lost to chipset. g1/s4 suspend to disk (std). all power lost (except wakeup on ich3-m) g2/s5 hard off. total reboot. 2. cpu states c0 full on c1 auto halt c2 quick start c3 deep sleep. clock to cpu stopped clock to cpu stopped or cpu dpslp# pin asserted
intel ? 830 chipset family 298338-003 datasheet 181 r 5.7.2.2 intel 830m and 830mg chipset acpi supported states when internal graphics device is used, the intel 830m and 830mg chipset support the following acpi states: 1. system states g0/s0 full on g1/s1 power on suspend (pos). system context preserved. g1/s3 suspend to ram (str). power and context lost to chipset. g1/s4 suspend to disk (std). all power lost (except wakeup on ich3-m) g2/s5 hard off. total reboot. 2. cpu states c0 full on c1 auto halt c2 quick start c3 deep sleep. clock to cpu stopped clock to cpu stopped or cpu dpslp# pin asserted 3. internal graphics (igd) states: d0 full on, display active d1 low power state, low latency recovery. d3hot all state lost other than pci configuration. memory lost (optionally). d3cold power off
intel ? 830 chipset family 182 datasheet 298338-003 r 5.7.3 intel 830 chipset family system and cpu states table 43 shows the state combinations that the intel 830 chipset family supports. table 43. intel 830 chipset family system and cpu states global (g) state sleep (s) state cpu (c) state processor state description g0 s0 c0 full on full on g0 s0 c1 auto-halt auto halt g0 s0 c2 quick start quick start g0 s0 c3 deep sleep deep sleep g1 s1 c3 deep sleep power on suspend g1 s3 power off power off suspend to ram g1 s4 power off power off suspend to disk g2 s5 power off power off hard off. g3 na power off power off mechanical off. 5.7.4 intel 830 chipset family cpu ?c? states 5.7.4.1 full-on (c0) this is the only state that runs software. all clocks are running, stpclk# is deasserted and the processor core is active. the processor can service snoops and maintain cache coherency in this state. 5.7.4.2 auto-halt (c1) the first level of power reduction occurs when the processor executes an auto-halt instruction. this stops the execution of the instruction stream and greatly reduces the processors power consumption. the processor can service snoops and maintain cache coherency in this state. 5.7.4.3 quickstart (c2) the next level of power reduction occurs when the processor is placed into the quick start state by the assertion of stpclk#. mobile quickstart state is a lower power version of the desktop stop grant state. the processor can service snoops and maintain cache coherency in this state. the system can transition from the c0 state to the c2 state for several reasons. software . c2 is entered when software reads the level 2 register. this is an acpi defined register but bios or apm (via bios) can use this facility when entering a low power state. throttling . this function can be enabled or disabled via a configuration bit. when this function is enabled stpclk# will be asserted to place the processor into the c2 state with a programmable duty cycle. this is an acpi defined function but bios or apm (via bios) can use this facility. thermal override . the chipset will detect thermal events via an input to the ich3-m. when a thermal threshold has been exceeded, a thermal sensor will assert a signal to the ich3-m. if the signal
intel ? 830 chipset family 298338-003 datasheet 183 r remains asserted for more than 2 seconds the chipset will initiate thermal throttling. stpclk# will be asserted to place the processor into the c2 state with a programmable duty cycle. this function can be enabled or disabled via a configuration bit. the thermal override condition is handled by the ich3-m. 5.7.4.4 deep sleep (c3) the deep sleep and deeper sleep states are identical as far as the intel 830 chipset family gmch-m is concerned. the only difference externally is that the cpu voltage is lowered for deeper sleep state to enable even more power saving. deeper sleep is supported on the mobile intel pentium iii processor-m but not on the mobile celeron processors. the c3 entry and exit sequence is also followed by an enhanced intel speedstep? technology transition. c3 entry will generally occur when the system is idle, and no bus master activity has taken place recently as indicated by pci req# signals and agp_busy# (although agp_busy# being active does not guarantee c3 will not be entered). enhanced intel speedstep technology transitions may occur at any time, while the system is busy and bus master activity is occurring. there will be no attempt to wait for the system to be idle for an enhanced intel speedstep technology transition. c3 may be entered even if agp_busy# is active, since there is a delay from the time agp_busy# is sampled by the os and c3 is actually entered. agp_busy# does not prevent c3 entry in hardware, it only indicates to the os that activity is present. the os will choose c2 rather than c3 in this case. agp_busy# active will cause a c3 exit, however, so the c3 mode will be brief if agp_busy# is active. an enhanced intel speedstep technology transition, which appears to the gmch-m exactly as a c3 entry/exit, will occur regardless of the state of agp_busy#. the gmch-m can assume that no agp, agp/pci, or hub interface cycle (except special cycles) will occur while the gmch-m is in the c3 state. the processor cannot snoop its caches to maintain coherency while in the c3 state. 5.7.5 intel 830mp and 830m chipset agp_busy# protocol with external graphics the agp_busy# and stp_agp# signals allow power management signaling between an external agp graphics controller and the ich3-m. agp_busy# indicates that the agp device is busy. c3_stat# (stp_agp#) is the signal, which used for indicating to the agp device that a c3 state transition is beginning or ending. agp_busy# (ich3-m signal) and stp_agp# (agp graphics controller signal) are not directly connected to the gmch-m. for proper implementations, please consult intel field application engineers. 5.7.6 intel 830m and 830mg internal graphics device agp_busy# protocol in igd mode, agp_busy# pin is a 3.3-v open drain output which indicates to the ich3-m that c3 should be entered, or it should be exited if already in c3. when internal graphics device (igd) is used, c3 must be entered without stopping the chipset clock or the memory controller. 5.7.7 enhanced intel speedstep ? ? ? ? technology (applicable with mobile intel pentium iii processor-m only) enhanced intel speedstep technology allows the system to operate in multiple performance states. enhanced intel speedstep technology offers two cpu/system operational modes:
intel ? 830 chipset family 184 datasheet 298338-003 r maximum performance mode : maximum cpu core frequency, requiring a higher cpu core voltage. battery optimized mode : reduced cpu core frequency to extend battery life. allows for lower cpu core voltage for additional power savings. enhanced intel speedstep technology allows the processor switch to between two core frequencies automatically based on cpu demand, without having to reset the processor or change the system bus frequency. the processor has two bus ratios programmed into it instead of one and the ghi# signal controls which one is used. after reset, the processor will start in the lower of its two core frequencies, the ?battery optimized? mode. an operating mode transition to the high core frequency can be made by putting the processor into the deep sleep state, raising the core voltage, setting ghi# low, and returning to the normal state. this puts the processor into the ?maximum performance? mode. reversing these steps transitions the processor back to the low-core frequency. most of the control for is done in the ich3-m. however, the intel 830 chipset family gmch-m must cooperate on certain functions. 5.7.8 intel 830 chipset family system ?s? states 5.7.8.1 powered-on-suspend (pos) (s1) the deepest level of power savings that can be achieved by only shutting down clocks occurs in the s1 state. the only clock remaining active in the system in the s1 state is the rtc clock. this clock is used to detect wake events and to run the hardware in the resume well in the ich3-m used to reactivate the system. during the s1 state the cpu and the intel 830 chipset family gmch-m power is on, however there is no activity, so the only power consumed is the leakage power. the clock synthesizer) is powered off, this shuts the clocks off in the host, memory, and i/o clock groups. if the d1 state is used for internal graphics, a clock must be provided to gmch-m for dpms signaling to the crt. 5.7.8.2 suspend-to-ram (str) (s3) the final level of power savings for the intel 830 chipset family gmch-m is achievable when the host clock, memory group, and i/o clock group clocks are shutdown and the gmch-m is powered down. this occurs when the system transitions to the s3 state. during transition to the s3 state, first the stpclk# is asserted and the stop grant cycle snooped by the gmch-m and forwarded over hub interface where it is received by the ich3-m. at this point the gmch-m is functioning in the c2 state. the gmch-m places all of the sdram components into the self-refresh mode. after the gmch-m has placed all of the sdram components in self refresh, it is safe to enter the str state. the ich3-m will then assert a signal, slp_s1#, to the clock synthesizer to shutdown all of the clocks in the host and memory clock groups. the gmch-m will assume that no agp, agp/pci, or hub interface cycle (except special cycles) will occur while the gmch-m is in the c3 state. the processor cannot snoop its caches to maintain coherency while in the c3 state. gmch-m contains no isolation circuitry and must be powered down once str is reached. if gmch- m is powered up and driving outputs to devices that are powered down, component damage will result.
intel ? 830 chipset family 298338-003 datasheet 185 r 5.7.8.3 s4 (suspend to disk), s5 (soft off) state the intel 830 chipset family does not distinguish between suspend to ram (s3), suspend to disk (s4) and soft off (s5) states. from the 830 chipset family perspective, entry and exit to s4 or s5 states, is the same as entry and exit to s3 state. 5.7.9 intel 830m and 830mg chipset internal graphics ?d? states pc9x implies that d0 and d3 are obligatory for graphics controllers. d0, d2, and d3 are obligatory for monitors. intel 830m and 830mg gmch-m also implements d1 for the graphics controller and monitors. system sdram state is generally controlled by s-states and c-states rather than d-states. with internal graphics the system sdram will remain available when the cpu is in c3. 5.7.9.1 d0 graphics adapter state ? active state in the d0 power state, everything is operating. this is the normal on state for the icd graphics functions. the gmch-m graphics functions enter this state out of power-on-reset. 5.7.9.2 the d1 graphics adapter state in the d1 power state, the graphics must go to a lower power state. the displays are blank, but memory and registers must be maintained. the emphasis is on a fast recovery in this mode. 5.7.9.3 the d3 graphics adapter state the d3 power state is the lowest power mode. displays are off, and the registers and memory need not be maintained. the pci config space must be accessible, in order to write the power state back to d0. when the os decides to put the igd graphics functions into d3 power state, it calls the igd graphics driver so that the driver saves the device context. device context consists of the igd graphics mode as well as non-local video memory context. external parts context must also be stored. 5.7.9.4 monitor [analog crt] states the monitor is considered a child device of the graphics controller. it?s acpi states are controlled through the graphics controller. dpms (display power management signaling) is a vesa (video electronics standards association) specification that provides a method for the graphics controller to put the monitor in a particular power management state by controlling the presence or absence of pulses on the hsync and vsync signals. the d state of the crt monitor can be set independently of the graphics controller, but will always be equal to or higher (in number, lower in power) than the graphics controller. the monitor is considered a ?child device? to the graphics controller. table 44 lists each combination.
intel ? 830 chipset family 186 datasheet 298338-003 r table 44. combinations of crt and graphics power down states graphics controller crt state hsync/vsync status d0 d0 = on pulse hsync and vsync d0 d1 = standby pulse vsync d0 d2 = suspend pulse hsync d0 d3 = off no pulse on hsync and vsync d1 d1 pulse vsync d1 d2 pulse hsync d1 d3 no pulse on hsync and vsync d3 d3 no pulse on hsync and vsync in d1 state, the graphics controller must be able to toggle either hsync or vsync, depending on the crt state. 5.7.9.5 dpms clock signaling in s1 (d1) state when the intel 830m and 830mg gmch-m graphics controller is in the d1 state, the graphics core clock and dot clocks are stopped, causing hsync and vsync generation to stop. if the system is configured to allow the graphics controller to be in d1 while the system is in mobile s1, all clocks in the system, including the clock generator chip are shut off. potentially the only clock running is the 32 khz of the real time clock. the dpms clock signal is muxed with gad30 provides clock source to generate pulses on hsync and vsync in the d1 state. the dpms clock signal requires an external clock source, which may be 32 khz or a 33/66 mhz clock. dpms_clk is not required if s1 states is not supported. 5.7.10 system memory dynamic cke support to reduce emi and preserve battery life, clocks to unpopulated so-dimms are turned off. the drb registers are read to determine if the row is populated. clocks are turned off in pairs because sm_clk[1:0] go to one so-dimm, sm_clk[3:2] go to another so-dimm.. the main memory sdrams are power managed during normal operation and in low power modes. each row has a separate cke (clock enable) pin that is used for power management. cke is used to put the sdram rows into power down mode. active power management is employed during normal operation. the memory setting is determined by the thermals of the system and the number of chips in a row. following refresh, all sdrams are powered down except the one for which there is the first pending request, if any. 5.7.11 intel 830 chipset family gmch-m thermal management with the addition of integrated graphics device, passive heat dissipation may not be enough and active cooling may reach its limit. counter based throttling does not correlate well with the actual environment, especially in a notebook where the outside ambient temperature varies greatly, along with internal conditions, such as heavy 3d content. the intel 830 chipset family gmch-m has several methods for monitoring and/or handling thermal issues. gmch-m contains an on-die thermal sensor is used for emergency throttling and shutdown. gmch-m contains a bandwidth monitor on the igd and the sdram interfaces. if the bandwidth
intel ? 830 chipset family 298338-003 datasheet 187 r exceeds a programmed amount, the gmch-m will automatically stall to avoid thermal problems. intel will provide a cmti software suite to profile system for optimal thermal management. please contact local fae for support. 5.7.11.1 thermal sensor the intel 830 chipset family gmch-m has an on-die thermal sensor for emergency throttling and shutdown. a thermal sensor provides a closed loop feedback path, and an emergency indicator. this sensor has two programmable trip points. the following will occur: 1. software should cause an intel speedstep technology transition to lower power/frequency. 2. the thermal sensor provides throttling either by hardware or a combination of hardware and software. 3. hardware may reduce the temperature by: a. throttling the 3d rendering b. throttling the main memory 4. software may reduce the temperature by: a. changing the 3d throttling parameters. b. shutting off functions. c. driver throttling 5.7.11.2 graphic thermal throttling the intel 830m and 830mg chipset 3d engine contains throttling mechanism between 3d engine and the memory interface. in non-throttled-state, the 3d pipe has two signals that control the flow of data to and from the local cache. there are three programmable values for the 3d pipe duty cycle, of which one (at most) is in use at any given time. 5.7.11.3 system and graphics memory bandwidth monitoring and throttling the intel 830 chipset family has the capability for bandwidth monitoring/throttle mechanism for the system memory interface (applicable to the entire chipset family). if the counter window exceeds the bandwidth threshold, then the sdram throttling mechanism will be invoked to limit the memory reads/writes to a lower bandwidth. the bandwidth monitoring mechanism consists of a counter to measure sdram bandwidth being used. depending on what is being monitored, reads, and writes or both, a counter is incremented. if the number of read/writes during the monitoring period exceeds the value programmed, the throttling mechanism is invoked. if the intel 830 chipset family gmch-m detects an idle cycle where no traffic is encountered during the throttling window, the counter decrements and no throttling takes place. once the bandwidth reaches the determined bandwidth, the gmch will start to throttle and continue throttling determined by the activity percentage. if the bandwidth never exceeds the set value, no throttling will take place. the gmch will exit the throttling mechanism and return to monitoring traffic where the process starts over again. 5.8 clocking the intel 830 chipset family gmch-m has the following clocks: ? 133 mhz, spread spectrum, low voltage differential htclk(#) for processor side bus ? 66.666 mhz 3.3 v, spread spectrum, gbout output clock for external hub/agp/pci buffer
intel ? 830 chipset family 188 datasheet 298338-003 r ? 66.666 mhz 3.3 v, spread spectrum, gbin from external buffer for agp/hub interface ? 48-mhz, spread spectrum, 3.3 v drefclk for the display frequency syntheses (applicable only when internal graphics device is used) ? 75-85 mhz dvox_clkin for tv encoder mode (applicable only when discrete agp device is used) the intel 830 chipset family has inputs for a low voltage, differential pair of clocks called htclk and htclk#. these pins receive a buffered host clock from the external clock synthesizer. this clock is used by all of the gmch-m logic. this clock is also the reference clock for the graphics core pll. the graphic core and display interfaces are asynchronous to the rest of the gmch-m. the graphics core runs at 100-166 mhz. the display plls uses the non-spread spectrum 48-mhz input to generate frequency range of 12-350 mhz. 5.9 xor test chains another feature of the intel 830 chipset family is the support for xor chain test modes. the xor chain test mode is used by product engineers during manufacturing and oems during board level connectivity tests. the main purpose of this test mode is to detect connectivity shorts between adjacent pins and to check proper bonding between i/o pads and i/o pins. there are 11 xor test chains built into the chipset. 5.9.1.1 test mode entry excluding the rac chain, all that is required to prepare the gmch-m for xor chain testing is to pull dvoa_d[7] and g_par/add_detect high prior to deasserting pcirst#. the following event sequence will put the gmch-m into xor testability mode: 1. deassert pcirst# high, deassert dvoa_d[11;8:6;4:3] low, assert g_par/add_detect high. 2. assert pcirst# low; assert dvoa_d[7:6] high and maintain g_par/add_detect high 3. deassert pcirst# high. 4. xor chain patterns can be applied to all gmch-m interfaces (except for rac) after pcirst# is deasserted. 5. dvoa_d[11;8:6;4:3] and g_par/add_detect can be ?don?t care?. see figure 16 for more details.
intel ? 830 chipset family 298338-003 datasheet 189 r figure 16. xor chain test mode entry events diagram pcirst# dvoa_d[3] don't care dvoa_d[4] don't care don't care don't care don't care don't care dvoa_d[6] dvoa_d[7] dvoa_d[8] dvoa_d[11] g_par don't care the assertion of dvoa_d[6] high in figure 16 is optional. the 830 chipset family supports dual ended termination for the cpu but only single ended termination is necessary when using the xor test chains. 5.9.1.2 rac chain initialization on the rac chain, special timing requirements need to be followed in order to use it. the event sequence (see section 5.9.1.2) to enter test mode for the rac chain is identical to that for all other chains and is shown in figure 16 above. the application of test patterns to the inputs of the rac chain must adhere to the timing requirements shown in figure 17. table 45 lists the minimum and maximum timings for the time parameters in figure 17. this includes the maximum test enable (t1) and output propagation delays (t2), and minimum period for the application of a test pattern (t3).
intel ? 830 chipset family 190 datasheet 298338-003 r figure 17. rac chain timing diagram iocten (internal signal) nc (ball f12) dqa dqb rq ctm(cfm) ctmb(cfmb) d0 d1 d1 d0 x t1 t2 t3 t1 t2 pcirst# table 45. rac chain timing descriptions symbol description min max unit t1 ioct test enable delay 0 100 ns t2 i/o to ioct output delay 0 25 ns t3 i/o connectivity sequence period 30 ns
intel ? 830 chipset family 298338-003 datasheet 191 r 5.9.1.3 xor chain test pattern consideration for differential pairs below are the differential signals in the xor chains that must be treated as pairs. pin1 and pin2 as shown below must always be complementary to each other. for example, if a 1 is driven on adstb0, a 0 must be driven on adstb0# and vice versa. this will need to be considered when applying test patterns to these chains. table 46. xor chain differential pairs pin1 pin2 xor chain adstb0 adstb0# agp1 adstb1 adstb1# agp1 sbstb sbstb# agp2 dvoadata(0) dvoadata(1) dvo pstrb pstrb# hublink
intel ? 830 chipset family 192 datasheet 298338-003 r 5.9.1.4 xor chain exclusion list please see below for a list of pins that are not included in the xor chains (excluding all vcc/vss): 1. gtl_ref0 2. gtl_ref1 3. cpurst# 4. gtl_rcomp 5. htclk# 6. htclk 7. drefclk 8. dvoa_rcomp 9. blue# 10. blue 11. green 12. green# 13. red 14. red# 15. gbin 16. gbout 17. reset# 18. agp_rcomp 19. agpref 20. hlref 21. hl_rcomp 22. sm_ref0 23. sm_ref1
intel ? 830 chipset family 298338-003 datasheet 193 r 5.9.1.5 nc balls the 830 chipset family contains four nc (no connect) balls that are not used in any chipset features. however, these four nc balls are used as input and/or output to some of the xor test chains. the following table lists the balls and associated xor chain. table 47. nc ball and associated xor chain ball xor chain 1 e11 psb2 2 e20 sm1 3 f20 sm1 4 f12 rac
intel ? 830 chipset family 194 datasheet 298338-003 r 5.9.1.6 xor chain connectivity/ordering the following tables contain the ordering for all of the 830 chipset family xor chains and pin to ball mapping information: table 48. xor chain agp1 ball pin xor out a19 sma5 1 w25 gad29 2 y29 gad31 3 v25 gad27 4 w26 gad28 5 w27 gad30 6 w29 gad26 7 v27 gad22 8 v28 gad23 9 v29 gad25 10 u26 gad24 11 u27 gad21 12 u29 gdstb1 13 u28 gdstbb1 14 t25 gcbe3 15 t26 gad20 16 t27 dvoc_d0 17 t29 gad18 18 r24 gad17 19 r25 gad16 20 p29 gcbe1 21 n29 gad12 22 n27 gad15 23 n26 gad14 24 m29 gad8 25 m28 gad9 26 m27 gad11 27 m25 gad13 28 l29 gdstb0 29 l28 gdstbb0 30 l27 gcbe0 31 l26 gad4
intel ? 830 chipset family 298338-003 datasheet 195 r 32 k29 gad6 33 k27 gad7 34 k26 dvob_d1 35 l24 gad10 36 j29 gad0 37 k25 gad3 38 j28 gad1 39 j27 gad5 table 49. xor chain agp2 ball pin xor out a17 sma9 1 ad29 ggntb 2 ab25 grbfb 3 ac27 greqb 4 ac28 gst0 5 ac29 gst1 6 aa25 gsba2 7 ab26 gpipeb 8 ab27 gst2 9 ab29 gwbfb 10 y24 gsba3 11 aa27 gsbstb 12 aa28 gsbstbb 13 w24 gsba6 14 aa24 gsba1 15 y26 gsba5 16 aa29 gsba0 17 y27 gsba4 18 y28 gsba7 19 r29 gframeb 20 r27 gcbe2 21 r28 gdevselb 22 p28 gpar 23 p27 gtrdyb 24 p26 girdyb 25 n25 gstopb
intel ? 830 chipset family 196 datasheet 298338-003 r table 50. xor chain dvo ball pin xor out c16 smba1 1 ad20 dvo clkin 2 ae21 dvo intr 3 aj22 dvod0 4 ah22 dvod1 5 ag22 dvod2 6 af22 dvo hsync 7 aj23 dvod3 8 ae22 dvo field 9 ah23 dvod4 10 ag23 dvod5 11 af23 dvo vsync 12 ad21 dvo blank 13 aj24 dvo clk 14 ag24 dvo clkb 15 ae23 dvod6 16 aj25 dvod8 17 ae24 dvod7 18 ah25 dvod9 19 ag25 dvod10 20 aj26 dvod11
intel ? 830 chipset family 298338-003 datasheet 197 r table 51. xor chain psb1 ball pin xor out e17 smcs0 1 g6 h_rs2b 2 d3 h_hitb 3 c1 h_adsb 4 h6 h_rs0b 5 g5 h_dbsyb 6 f4 h_drdyb 7 e3 h_a4 8 g4 h_trdyb 9 j6 h_lockb 10 d1 h_hitmb 11 h4 h_rs1b 12 g3 h_a5 13 k6 h_req0b 14 e1 h_bnrb 15 k5 h_req2b 16 f2 h_a9 17 f1 h_a8 18 l6 h_req4b 19 k4 h_req3b 20 h2 h_a3 21 m6 h_a7 22 l4 h_bprib 23 m4 h_req1b 24 n4 h_a6 25 y2 h_d32 26 aa1 h_d34 27 aa2 h_d38 28 aa4 h_d33 29 ab1 h_d36 30 ab3 h_d39 31 ac1 h_d45 32 ac2 h_d42 33 ac3 h_d49 34 ac4 h_d37 35 aa6 h_d35
intel ? 830 chipset family 198 datasheet 298338-003 r 36 ad1 h_d41 37 ad2 h_d40 38 ad4 h_d47 39 ae1 h_d59 40 ae3 h_d52 41 af1 h_d63 42 af2 h_d55 43 ac6 h_d44 44 ae4 h_d57 45 ab6 h_d43 46 af3 h_d46 47 ag1 h_d58 48 ag2 h_d53 49 ae5 h_d51 50 ad6 h_d48 51 af4 h_d54 52 ag3 h_d62 53 ah3 h_d50 54 ag4 h_d60 55 ah4 h_d61 56 aj3 h_d56
intel ? 830 chipset family 298338-003 datasheet 199 r table 52. xor chain psb2 ball pin xor out e11 nc 1 f3 h_a11 2 j4 h_deferb 3 h3 h_a28 4 g1 h_a13 5 j3 h_a10 6 h1 h_a15 7 k3 h_a31 8 l3 h_a23 9 j2 h_a19 10 j1 h_a25 11 n5 h_a14 12 m3 h_a29 13 k1 h_a22 14 l2 h_a20 15 l1 h_a24 16 m2 h_a18 17 p6 h_a12 18 n3 h_d6 19 m1 h_a30 20 p4 h_a16 21 p3 h_d9 22 n1 h_a26 23 p2 h_d15 24 p1 h_d1 25 r4 h_a21 26 r3 h_d10 27 r2 h_d17 28 r1 h_d5 29 t5 h_a27 30 t4 h_a17 31 t3 h_d14 32 t1 h_d18 33 u4 h_d0 34 u6 h_d4 35 u3 h_d20
intel ? 830 chipset family 200 datasheet 298338-003 r 36 u2 h_d3 37 u1 h_d11 38 v4 h_d8 39 v3 h_d16 40 v2 h_d30 41 v1 h_d24 42 w4 h_d13 43 w3 h_d19 44 v6 h_d12 45 w1 h_d23 46 w5 h_d7 47 y3 h_d31 48 y4 h_d21 49 w6 h_d2 50 y6 h_d26 51 y1 h_d25 52 aa3 h_d22 53 ab4 h_d28 54 ad3 h_d27 55 ab5 h_d29
intel ? 830 chipset family 298338-003 datasheet 201 r table 53. xor chain gpio ball pin xor out c15 sma11 1 ad28 hsync 2 ac24 agp busy 3 ad27 ddc1 data 4 ac25 i2c data 5 ad26 ddc2 data 6 ae29 vsync 7 ae27 ddc1 clk 8 ae26 ddc2 clk 9 ad25 i2c clk table 54. xor chain hub ball pin xor out a18 sma4 1 e28 hld7 2 g25 hlrqm 3 e29 hld6 4 f27 hld5 5 g26 hld0 6 f28 hlstbb 7 g29 hlstb 8 g27 hlrqi 9 f29 hld4 10 h26 hlstop 11 h27 hld3 12 h28 hld1 13 h29 hld2
intel ? 830 chipset family 202 datasheet 298338-003 r table 55. xor chain sm1 ball pin xor out a20 sma0 1 c24 smrclk 2 a24 smoclk 3 g22 smd42 4 a23 smd44 5 d22 smd43 6 f21 smd45 7 d21 smd46 8 e20 nc 9 f20 nc 10 a22 smd47 12 b20 sma1 14 d19 smcas 15 f18 smdqm0 16 b19 sma2 17 c17 sma6 18 b17 sma8 20 d15 smcs3 22 f13 smdqm7 23 a15 smclk0 24 b14 smclk2 26 d13 smdqm2 27 c13 smcke2 28 a13 smcke0 32 d12 smdqm3 33 a11 smd49 34 b11 smd50 35 b10 smd52 36 f11 smd48 37 a9 smcke3 38 c9 smcke1 39 d9 smd54 40 f10 smd51 42 b8 smd53 43 f9 smd56 44 b7 smd55
intel ? 830 chipset family 298338-003 datasheet 203 r 45 d7 smd59 46 a6 smd57 47 c6 smd58 48 e6 smd61 49 b5 smd60 50 a4 smd62 51 a3 smclk3 53 b2 smclk1 54 d4 smd63 table 56. xor chain sm2 ball pin xor out c19 sma3 1 d29 smd0 2 c29 smd1 3 c28 smd33 4 b28 smd34 5 e27 smd32 6 d27 smd2 7 e26 smd35 8 c27 smd3 9 a27 smd4 10 c26 smd36 11 b26 smd5 12 e24 smd6 13 a26 smd38 14 d25 smd37 15 c25 smd7 16 b25 smd9 17 e23 smd8 18 d24 smd39 19 a25 smd41 20 f23 smd40 21 c23 smd10 22 b23 smd12 23 f22 smd11 24 c22 smd13
intel ? 830 chipset family 204 datasheet 298338-003 r 25 e21 smd14 26 b22 smd15 27 a21 smwe 28 c20 smras 29 e18 smdqm4 30 d18 smdqm1 31 f17 smdqm5 32 c18 sma7 33 d16 smcs2 34 b16 smba0 35 a16 sma10 36 c14 sma12 37 f14 smdqm6 38 c12 smd16 39 c11 smd18 40 a10 smd19 41 c10 smd20 42 d10 smd17 43 f8 smd27 44 e9 smd23 45 c8 smd21 46 a7 smd22 47 c7 smd24 48 e8 smd25 49 d6 smd29 50 a5 smd26 51 c5 smd28 52 b4 smd30 53 c4 smd31
intel ? 830 chipset family 298338-003 datasheet 205 r table 57. xor chain cmos ball pin xor out f16 smcs1 1 ag6 gclk 2 aj6 rclk 3 af7 sck 4 ah7 cmd 5 aj7 sio table 58. xor chain rac ball pin xor out f12 nc 1 aj20 dqa7 2 ag20 dqa6 3 aj19 dqa5 4 ag19 dqa4 5 aj18 dqa3 6 ag18 dqa2 7 aj17 dqa1 8 ag17 dqa0 9 ah15 ctm 10 aj16 cfm 11 aj15 ctm_b 12 ah16 cfm_b 13 aj14 rq7 14 ag14 rq6 15 aj13 rq5 16 ag13 rq4 17 ah13 rq3 18 ag12 rq2 19 aj12 rq1 20 ag11 rq0 21 aj11 dqb0 22 ah10 dqb1 23 aj10 dqb2 24 ag10 dqb3 25 aj9 dqb4
intel ? 830 chipset family 206 datasheet 298338-003 r 26 ag9 dqb5 27 aj8 dqb6 28 ag8 dqb7
intel ? 830 chipset family 298338-003 datasheet 207 r 6 intel 830 chipset family performance the system performance for the intel 830 chipset family gmch-m described below is a breakdown of the data streams that complement the mobile intel pentium iii processor-m. this section describes the overall performance of the gmch-m. following categories of performance are examined: ? cpu/830 chipset family gmch-m: intel 830 chipset family supports mobile intel pentium iii processor-m ? system memory: intel 830 chipset gmch-m supports pc133 main memory ? agp only available with 830m and 830mp chipset ? dvo only available with 830m and 830mg chipset table 59. system bandwidths interface clock speed (mhz) samples per clock data rate (mega-samples/s) data width (bytes) bandwidth (mb/s) cpu bus 133 1 133 8 1066 sdram 133 1 133 8 1064 agp 2.0 66 4 266 4 1066 dvo 165 2 330 1.5 495 dvo gang mode 165 2 330 3 990 pci 2.2 33 1 33 4 133 note: *theoretical bandwidths only.
intel ? 830 chipset family 208 datasheet 298338-003 r 7 mechanical specification 7.1 intel 830mp chipset gmch-m ballout diagram figure 18 and figure 19 show the ballout of the intel 830mp chipset.
intel ? 830 chipset family 298338-003 datasheet 209 r figure 18. intel 830mp ballout diagram (left) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a sm_clk3 smd62 smd26 smd57 smd22 vcc_sm sm_cke3 smd19 smd49 vcc_sm sm_ck e0 vss b sm_clk1 vss smd30 smd60 vss smd55 smd53 vss smd52 smd50 vss vss sm_clk2 c h_ads# gtl_ rcomp vss smd31 smd28 smd58 smd24 smd21 sm_ck e1 sm d20 smd18 smd16 sm_cke2 sma12 d h_hitm# vss h_hit# smd63 vcc_sm smd29 smd59 vcc_sm smd54 smd17 vcc_sm sm_dqm3 sm_dqm2 vcc_sm e h_bnr# vtt h_a4# vss sm_vref 1 smd61 vss smd25 smd23 vss nc vcc_sm vss vss f h_a8# h_a9# h_a11# h_drdy# vtt sm_rcomp vccq _ sm smd27 smd56 smd51 smd48 nc sm_dqm7 sm_dqm6 g h_a13# vss h_a5# h_trdy# h_dbsy# h_rs2# vcca_ cpll vssa_cpll vss vcc_sm vcc_sm h h_a15# h_a3# h_a28# h_rs1# vss h_rs0# vcc j h_a25# h_a19# h_a10# h_defer# vtt h_lock# gtl_refa k h_a22# v ss h_a31# h_req3# h_req2# h_req0# vcc l h_a24# h_a20# h_a23# h_bpri# vss h_req4# vcc m h_a30# h_a18# h_a29# h_req1# vtt h_a7# vss vss vcc n h_a26# vss h_d6# h_a6# h_a14# vcc vss vss vss p h_d1# h_d15# h_d9# h_a16# vss h_a12# vcc vss vss r h_d5# h_d17# h_d10# h_a21# vtt cpu_rst# vcc vss vss t h_d18# vss h_d14# h_a17# h_a27# vcc vcc vss vss u h_d11# h_d3# h_d20# h_d0# vss h_d4# vss vss vss v h_d24# h_d30# h_d16# h_d8# vtt h_d12# vss vss vdd_lm w h_d23# vss h_d19# h_d13# h_d7# h_d2# vcc y h_d25# h_d32# h_d31# h_d21# vss h_d26# vcc aa h_d34# h_d38# h_d22# h_d33# vtt h_d35# gtl_refb ab h_d36# vss h_d39# h_d28# h_d29# h_d43# vcc ac h_d45# h_d42# h_d49# h_d37# vss h_d44# vss v cc_cmos vcc_cmos vcc_lm v cc_lm ad h_d41# h_d40# h_d27# h_d47# vtt h_d48# vssa_hpll vss vss vss vcc_lm vcc_lm vcc_lm ramref [0] ae h_d59# vss h_d52# h_d57# h_d51# vcca_ hpll vcc_cmos vss vss vss vss vss vss ramref [1] af h_d63# h_d55# h_d46# h_d54# vss vcc_cm os sck vss vss vss vss vss vss vss ag h_d58# h_d53# h_d62# h_d60# vtt gclk vss dqb7 dqb5 dqb3 rq0 rq2 rq4 rq6 ah vss h_d50# h_d61# htclk# vss cmd vss vss dqb1 vss vss rq3 vss aj h_d56# htclk vss gm_rclk sio dqb6 dqb4 dqb2 dqb0 rq1 rq5 rq7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
intel ? 830 chipset family 210 datasheet 298338-003 r figure 19. intel 830mp ballout (right) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 sm_ clk0 sma10 sma9 sma4 sma5 sma0 smwe smd47 smd44 sm_oclk smd41 smd38 smd4 a vss smba0 sma8 vss sma2 sma1 vss smd15 smd12 vss smd9 smd5 vss smd34 b sma11 smba1 sma6 sma7 sma3 smras vss smd13 smd10 sm_r clk smd7 smd36 smd3 smd33 smd1 c sm_cs3# sm_cs2# vcc_sm smdqm1 smcas vcc_sm smd46 smd43 vcc_sm smd39 smd37 vcc_sm smd2 vss smd0 d vccq_ sm vss sm_cs0# smdqm4 vss nc smd14 vss smd8 smd6 vss smd35 smd32 hl7 hl6 e vccq_ sm sm_cs1# smdqm5 smdqm0 vss nc smd4 5 smd11 smd40 sm_vref0 vcca_ pll1 vcc_ hub hl5 hlstrb# hl4 f vccq_sm vccq_sm vss smd42 vcc_ sm vssa_ dpll1 hl8 hl0 hl9 vss hlstrb g vcc hlref vss hl10 hl3 hl1 hl2 h hrcomp vcc_hub agpref vcc_ agp g_ad5 g_ad1 g_ad0 j vcc agp_ rcomp g_ad3 g_ad2 g_ad7 vss g_ad6 k vcc_agp g_ad10 vss g_ad4 g_cbe0# ad_stb0# ad_st b0 l vcc vcc vss vss vcc g_ad13 vcc_ agp g_ad11 g_ad9 g_ad8 m vss vss vss vss vccq_agp g_stop# g_ad14 g_ad15 vss g_ad12 n vss vss vss vcc vcc vss g_irdy# g_trdy# g_par g_cbe1# p vss vss vss vcc g_ad17 g_ad16 vcc_ ag p g_cbe2# g_devsel# g_frame# r vss vss vss vcc vcc g_cbe3# g_ad20 g_ad19 vss g_ad18 t vss vss vss vss vcc_agp vss g_ad24 g_ad21 ad_stb1# ad_stb1 u vdd_lm vdd_lm vss vss vcc g_ad27 vcc_ agp g_ad22 g_ad23 g_ad25 v vddq_a gp sba6 g_ad29 g_ad28 g_ad30 vss g_ad26 w vcc sba3 vss sba5 sba4 sba7 g_ad31 y vcc_agp sba1 sba2 vcc_ agp sb_stb sb_stb# sba0 aa vss reset# rbf# pipe# st2 vss wbf# a b drefclk vcca_ dpll0 vcc_dvo dvoa_ rcomp vss agpb usy# i2c_ data vss req# st0 st1 ac vdd_lm vdd_lm vcc_lm vcc_lm vcc_lm dvoa_clk int dvoa_ blank# vss vcc_gpio gbout i2c_clk ddc2_da ddc1_da hsync g_gnt# ad vdd_lm vdd_lm vss vcc_lm vss vssa_dpll 0 dvoa_ intr# dvoa_fld /st l dvoa_d6 dvoa_d7 vcc_ gpio ddc2_ck ddc1_ck vss vsync ae vss vss vss vss vss vss vcc_dvo dvoa_hsync dvoa_vsync vcc_dvo vss vcca_ dac vss red# red af vss vss dqa0 dqa2 dqa4 dqa6 vss dvoa_d2 dvoa_d5 dvoa_clk # dvo_d10 g bin vcca_ dac green# green ag ctm cfm# vss vss vss vss vss dvoa_d1 dvoa_d4 vss dvo_d9 vssa_dac blue# blue ah ctm# cfm dqa1 dqa3 dqa5 dqa7 vss dvoa_d0 dvoa_d3 dvoa_clk dvo_d11 refset aj reserved reserved reserve d reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved dvoa_d8 reserved reserved reserved reserved reserved reserved reserved
intel ? 830 chipset family 298338-003 datasheet 211 r 7.2 intel 830m chipset gmch-m ballout diagram figure 20 and figure 21 show the ballout of the intel 830m chipset.
intel ? 830 chipset family 212 datasheet 298338-003 r figure 20. intel 830m chipset ballout diagram (left) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a sm_clk3 smd62 smd26 smd57 smd22 vcc_sm sm_cke3 smd19 smd49 vcc_sm sm_ck e0 vss b sm_clk1 vss smd30 smd60 vss smd55 smd53 vss smd52 smd50 vss vss sm_clk2 c h_ads# gtl_ rcomp vss smd31 smd28 smd58 smd24 smd21 sm_ck e1 sm d20 smd18 smd16 sm_cke2 sma12 d h_hitm# vss h_hit# smd63 vcc_sm smd29 smd59 vcc_sm smd54 smd17 vcc_sm sm_dqm3 sm_dqm2 vcc_sm e h_bnr# vtt h_a4# vss sm_vref 1 smd61 vss smd25 smd23 vss nc vcc_sm vss vss f h_a8# h_a9# h_a11# h_drdy# vtt sm_rcomp vccq _ sm smd27 smd56 smd51 smd48 nc sm_dqm7 sm_dqm6 g h_a13# vss h_a5# h_trdy# h_dbsy# h_rs2# vcca_ cpll vssa_cpll vss vcc_sm vcc_sm h h_a15# h_a3# h_a28# h_rs1# vss h_rs0# vcc j h_a25# h_a19# h_a10# h_defer# vtt h_lock# gtl_refa k h_a22# v ss h_a31# h_req3# h_req2# h_req0# vcc l h_a24# h_a20# h_a23# h_bpri# vss h_req4# vcc m h_a30# h_a18# h_a29# h_req1# vtt h_a7# vss vss vcc n h_a26# vss h_d6# h_a6# h_a14# vcc vss vss vss p h_d1# h_d15# h_d9# h_a16# vss h_a12# vcc vss vss r h_d5# h_d17# h_d10# h_a21# vtt cpu_rst# vcc vss vss t h_d18# vss h_d14# h_a17# h_a27# vcc vcc vss vss u h_d11# h_d3# h_d20# h_d0# vss h_d4# vss vss vss v h_d24# h_d30# h_d16# h_d8# vtt h_d12# vss vss vdd_lm w h_d23# vss h_d19# h_d13# h_d7# h_d2# vcc y h_d25# h_d32# h_d31# h_d21# vss h_d26# vcc aa h_d34# h_d38# h_d22# h_d33# vtt h_d35# gtl_refb ab h_d36# vss h_d39# h_d28# h_d29# h_d43# vcc ac h_d45# h_d42# h_d49# h_d37# vss h_d44# vss v cc_cmos vcc_cmos vcc_lm v cc_lm ad h_d41# h_d40# h_d27# h_d47# vtt h_d48# vssa_hpll vss vss vss vcc_lm vcc_lm vcc_lm ramref [0] ae h_d59# vss h_d52# h_d57# h_d51# vcca_ hpll vcc_cmos vss vss vss vss vss vss ramref [1] af h_d63# h_d55# h_d46# h_d54# vss vcc_cm os sck vss vss vss vss vss vss vss ag h_d58# h_d53# h_d62# h_d60# vtt gclk vss dqb7 dqb5 dqb3 rq0 rq2 rq4 rq6 ah vss h_d50# h_d61# htclk# vss cmd vss vss dqb1 vss vss rq3 vss aj h_d56# htclk vss gm_rclk sio dqb6 dqb4 dqb2 dqb0 rq1 rq5 rq7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
intel ? 830 chipset family 298338-003 datasheet 213 r figure 21. intel 830m chipset ballout diagram (right) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 sm_ clk0 sma10 sma9 sma4 sma5 sma0 smwe smd47 smd44 sm_oclk smd41 smd38 smd4 a vss smba0 sma8 vss sma2 sma1 vss smd15 smd12 vss smd9 smd5 vss smd34 b sma11 smba1 sma6 sma7 sma3 smras vss smd13 smd10 sm_r clk smd7 smd36 smd3 smd33 smd1 c sm_cs3# sm_cs2# vcc_sm smdqm1 smcas vcc_sm smd46 smd43 vcc_sm smd39 smd37 vcc_sm smd2 vss smd0 d vccq_ sm vss sm_cs0# smdqm4 vss nc smd14 vss smd8 smd6 vss smd35 smd32 hl7 hl6 e vccq_ sm sm_cs1# smdqm5 smdqm0 vss nc smd4 5 smd11 smd40 sm_vref0 vcca_ pll1 vcc_ hub hl5 hlstrb# hl4 f vccq_sm vccq_sm vss smd42 vcc_sm vssa_ dpll1 hl8 hl0 hl9 vss hlstrb g vcc hlref vss hl10 hl3 hl1 hl2 h hrcomp vcc_hub agpref/ dvobc_ref vcc_ agp g_ad5/ g_ad1/ g_ad0/ j vcc agp_ rcomp g_ad3/ g_ad2/ g_ad7/ vss g_ad6/ k vcc_agp g_ad10/ vss g_ad4/ g_cbe0#/ ad_stb0#/ ad_stb0/ l vcc vcc vss vss vcc g_ad13/ vcc_ agp g_ad11/ g_ad9/ g_ad8/ m vss vss vss vss vccq_agp g_stop# g_ad14/ g_ad15 vss g_ad12/ n vss vss vss vcc vcc vss g_irdy#/ g_trdy#/ g_par g_cbe1#/ p vss vss vss vcc g_ad17/ g_ad16/ vcc_ agp g_cbe2# g_devsel#/ g_frame#/ r vss vss vss vcc vcc g_cbe3#/ g_ad20/ g_ad19/ vss g_ad18/ t vss vss vss vss vcc_agp vss g_ad24/ g_ad21/ ad_stb1#/ ad_stb1/ u vdd_lm vdd_lm vss vss vcc g_ad27/ vcc_ agp g_ad22/ g_ad23/ g_ad25/ v vddq_agp sba6 g_ad29/ g_ad28/ g_ad30/ vss g_ad26/ w vcc sba3 vss sba5 sba4 sba7 g_ad31/ y vcc_agp sba1 sba2 vcc_ agp sb_stb sb_stb# sba0 aa vss reset# rbf# pipe# st2 vss wbf# a b drefclk vcca_ dpll0 vcc_dvo dvoa_ rcomp vss agpbusy# i2c_ data vss req# st0 st1 ac vdd_lm vdd_lm vcc_lm vcc_lm vcc_lm dvoa_clk int dvoa_ blank# vss vcc_gpio gbout i2c_clk ddc2_da ddc1_da hsync g_gnt# ad vdd_lm vdd_lm vss vcc_lm vss vssa_dpll 0 dvoa_ intr# dvoa_fld /stl dvoa_d6 dvoa_d7 vcc_ gpio ddc2_ck ddc1_ck vss vsync ae vss vss vss vss vss vss vcc_dvo dvoa_hsync dvoa_vsync vcc_dvo vss vcca_ dac vss red# red af vss vss dqa0 dqa2 dqa4 dqa6 vss dvoa_d2 dvoa_d5 dvoa_clk # dvoa_d10 gbin vcca_ dac green# green ag ctm cfm# vss vss vss vss vss dvoa_d1 dvoa_d4 vss dvoa_d9 vssa_dac blue# blue ah ctm# cfm dqa1 dqa3 dqa5 dqa7 vss dvoa_d0 dvoa_d3 dvoa_clk dvoa_d8 dvoa_d11 refset aj reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved dvob_d2 dvob_vsync dvob_hsync dvob_d0 dvob_d1 dvob_d4 dvob_d5 dvob_d8 dvob_d3 dvob_d7 dvob_clk# dvob_clk dvob_d6 dvob_d9 dvob_d11 dvobc_c lkint# dvob_fl d/stl dvob_d10 dvob_bl ank# m_ddc1_ clk m_i2c_c lk m_ddc1_ data m_i2c_ data dvoc_ vsync dvoc_ hsync dvoc_bl ank# dvoc_d0 dvoc_d1 dvoc_d5 dvoc_d7 dvoc_d2 dvoc_clk# dvoc_clk dvoc_d6 dvoc_d4 dvoc_d3 dvoc_d8 dvoc_d10 dvoc_d11 dvobc_intr#/ dpms_clk dvoc_d9 dvoc_fld/ stl
intel ? 830 chipset family 214 datasheet 298338-003 r 7.3 intel 830mg gmch-m ballout diagram figure 22 and figure 23 show the ballout of the intel 830mg chipset.
intel ? 830 chipset family 298338-003 datasheet 215 r figure 22. intel 830mg chipset ballout diagram (left) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a sm_clk3 smd62 smd26 smd57 smd22 vcc_sm sm_cke3 smd19 smd49 vcc_sm sm_ck e0 vss b sm_clk1 vss smd30 smd60 vss smd55 smd53 vss smd52 smd50 vss vss sm_clk2 c h_ads# gtl_ rcomp vss smd31 smd28 smd58 smd24 smd21 sm_ck e1 sm d20 smd18 smd16 sm_cke2 sma12 d h_hitm# vss h_hit# smd63 vcc_sm smd29 smd59 vcc_sm smd54 smd17 vcc_sm sm_dqm3 sm_dqm2 vcc_sm e h_bnr# vtt h_a4# vss sm_vref 1 smd61 vss smd25 smd23 vss nc vcc_sm vss vss f h_a8# h_a9# h_a11# h_drdy# vtt sm_rcomp vccq _ sm smd27 smd56 smd51 smd48 nc sm_dqm7 sm_dqm6 g h_a13# vss h_a5# h_trdy# h_dbsy# h_rs2# vcca_ cpll vssa_cpll vss vcc_sm vcc_sm h h_a15# h_a3# h_a28# h_rs1# vss h_rs0# vcc j h_a25# h_a19# h_a10# h_defer# vtt h_lock# gtl_refa k h_a22# v ss h_a31# h_req3# h_req2# h_req0# vcc l h_a24# h_a20# h_a23# h_bpri# vss h_req4# vcc m h_a30# h_a18# h_a29# h_req1# vtt h_a7# vss vss vcc n h_a26# vss h_d6# h_a6# h_a14# vcc vss vss vss p h_d1# h_d15# h_d9# h_a16# vss h_a12# vcc vss vss r h_d5# h_d17# h_d10# h_a21# vtt cpu_rst# vcc vss vss t h_d18# vss h_d14# h_a17# h_a27# vcc vcc vss vss u h_d11# h_d3# h_d20# h_d0# vss h_d4# vss vss vss v h_d24# h_d30# h_d16# h_d8# vtt h_d12# vss vss vdd_lm w h_d23# vss h_d19# h_d13# h_d7# h_d2# vcc y h_d25# h_d32# h_d31# h_d21# vss h_d26# vcc aa h_d34# h_d38# h_d22# h_d33# vtt h_d35# gtl_refb ab h_d36# vss h_d39# h_d28# h_d29# h_d43# vcc ac h_d45# h_d42# h_d49# h_d37# vss h_d44# vss v cc_cmos vcc_cmos vcc_lm v cc_lm ad h_d41# h_d40# h_d27# h_d47# vtt h_d48# vssa_hpll vss vss vss vcc_lm vcc_lm vcc_lm ramref [0] ae h_d59# vss h_d52# h_d57# h_d51# vcca_ hpll vcc_cmos vss vss vss vss vss vss ramref [1] af h_d63# h_d55# h_d46# h_d54# vss vcc_cm os sck vss vss vss vss vss vss vss ag h_d58# h_d53# h_d62# h_d60# vtt gclk vss dqb7 dqb5 dqb3 rq0 rq2 rq4 rq6 ah vss h_d50# h_d61# htclk# vss cmd vss vss dqb1 vss vss rq3 vss aj h_d56# htclk vss gm_rclk sio dqb6 dqb4 dqb2 dqb0 rq1 rq5 rq7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
intel ? 830 chipset family 216 datasheet 298338-003 r figure 23. intel 830mg chipset ballout diagram (right) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 sm_ clk0 sma10 sma9 sma4 sma5 sma0 smwe smd47 smd44 sm_oclk smd41 smd38 smd4 a vss smba0 sma8 vss sma2 sma1 vss smd15 smd12 vss smd9 smd5 vss smd34 b sma11 smba1 sma6 sma7 sma3 smras vss smd13 smd10 sm_r clk smd7 smd36 smd3 smd33 smd1 c sm_cs3# sm_cs2# vcc_sm smdqm1 smcas vcc_sm smd46 smd43 vcc_sm smd39 smd37 vcc_sm smd2 vss smd0 d vccq_ sm vss sm_cs0# smdqm4 vss nc smd14 vss smd8 smd6 vss smd35 smd32 hl7 hl6 e vccq_ sm sm_cs1# smdqm5 smdqm0 vss nc smd4 5 smd11 smd40 sm_vref0 vcca_ pll1 vcc_ hub hl5 hlstrb# hl4 f vccq_sm vccq_sm vss smd42 vcc_sm vssa_ dpll1 hl8 hl0 hl9 vss hlstrb g vcc hlref vss hl10 hl3 hl1 hl2 h hrcomp vcc_hub dvobc_ref vcc_ agp dvob_ d2 dvob_ vsync dvob_ hsync j vcc dvobc_ rcomp dvob_ d0 dvob_ d1 dvob_ d4 vss dvob_ d5 k vcc_agp dvob_ d8 vss dvob_ d3 dvob_ d7 dvob_ clk# dvob_ clk l vcc vcc vss vss vcc vcc_ agp dvob_ d11 dvob_ d9 dvob_ d6 m vss vss vss vss vccq_agp g_stop# dvob_ fld/ stl g_ad15 vss dvob_ d10 n vss vss vss vcc vcc vss m_ddc1_ clk g_par dvob_ blank# p vss vss vss vcc dvoc_ hsync dvoc_ vsync vcc_ agp g_cbe2# m_i2c_ data m_ddc1_ data r vss vss vss vcc vcc dvoc_ d5 dvoc_ d1 dvoc_ d0 vss dvoc_ blank# t vss vss vss vss vcc_agp vss dvoc_ d7 dvoc_ d2 dvoc_ clk# dvoc_ clk u vdd_lm vdd_lm vss vss vcc dvoc_ d8 vcc_ agp dvoc_ d3 dvoc_ d4 dvoc_ d6 v vddq_agp sba6 dvoc_ d10 dvoc_ d11 dvobc_int r# / dpms_clk vss dvoc_ d9 w vcc sba3 vss sba5 sba4 sba7 dvoc_ fld/ stl y vcc_agp sba1 sba2 vcc_ agp sb_stb sb_stb# sba0 aa vss reset# rbf# pipe# st2 vss wbf# a b drefclk vcca_ dpll0 vcc_dvo dvoa_rcomp vss agpbusy# i2c_ data vss req# st0 st1 ac vdd_lm vdd_lm vcc_lm vcc_lm vcc_lm dvoa_ clkint dvoa_ blank# vss vcc_gpio gbout i2c_clk ddc2_da ddc1_da hsync g_gnt# ad vdd_lm vdd_lm vss vcc_lm vss vssa_dpll 0 dvoa_intr# dvoa_fld/ stl dvoa_d6 dvoa_d7 vcc_ gpio ddc2_ck ddc1_ck vss vsync ae vss vss vss vss vss vss vcc_dvo dvoa_hsync dvoa_vsync vcc_dvo vss vcca_ dac vss red# red af vss vss dqa0 dqa2 dqa4 dqa6 vss dvoa_d2 dvoa_d5 dvoa_clk# dvoa_d10 gbin vcca_ dac green# green ag ctm cfm# vss vss vss vss vss dvoa_d1 dvoa_d4 vss dvoa_d9 vssa_dac blue# blue ah ctm# cfm dqa1 dqa3 dqa5 dqa7 vss dvoa_d0 dvoa_d3 dvoa_clk dvoa_d8 dvo_d11 refset aj dvobc_ clkint# m_i2c _ clk reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
intel ? 830 chipset family 298338-003 datasheet 217 r 7.4 intel 830mp gmch-m signal list table 60 provides an alphabetical signal listing of 830mp chipset gmch-m ballouts. table 60. intel 830mp chipset ballout signal name list ball # signal name l29 ad_stb0 l28 ad_stb0# u29 ad_stb1 u28 ad_stb1# c1 ads# ac24 agpbusy# k24 agp_rcomp j25 agpref ah28 blue [reserved] ah27 blue# [reserved] e1 bnr# l4 bpri# aj16 cfm [reserved] ah16 cfm# [resreved] ah7 cmd [reserved] r6 cpurst# ah15 ctm [reserved] aj15 ctm# [reserved] g5 dbsy# ae27 ddc1_clk [resreved] ad27 ddc1_data [reserved] ae26 ddc2_clk [resreved] ad26 ddc2_data [resreved] j4 defer# ag17 dq_a0 [reserved] aj17 dq_a1 [reserved] ag18 dq_a2 [reserved] aj18 dq_a3 [reserved] ball # signal name ag19 dq_a4 [reserved] aj19 dq_a5 [reserved] ag20 dq_a6 [reserved] aj20 dq_a7 [reserved] aj11 dq_b0 [reserved] ah10 dq_b1 [reserved] aj10 dq_b2 [reserved] ag10 dq_b3 [reserved] aj9 dq_b4 [reserved] ag9 dq_b5 [reserved] aj8 dq_b6 [reserved] ag8 dq_b7 [reserved] f4 drdy# ac19 drefclk [reserved] ad20 dv0a_clkint [reserved] ad21 dvoa_blank# [reserved] ag24 dvoa_clk# [reserved] aj24 dvoa_clk [reserved] aj22 dvoa_d0 [reserved] ah22 dvoa_d1 [reserved] ag25 dvoa_d10 [reserved] aj26 dvoa_d11 [reserved] ag22 dvoa_d2 [reserved]
intel ? 830 chipset family 218 datasheet 298338-003 r ball # signal name aj23 dvoa_d3 [reserved] ah23 dvoa_d4 [reserved] ag23 strap[0] ] ae23 dvoa_d6 [reserved] ae24 strap[1] aj25 strap[2] ah25 dvoa_d9 [reserved] ae22 dvoa_fld/stl [reserved] af22 dvoa_hsync [reserved] ae21 dvoa_intr# [reserved] ac22 dvoa_rcomp [reserved] af23 dvoa_vsync [reserved] j29 g_ad0 j28 g_ad1 l24 g_ad10 m27 g_ad11 n29 g_ad12 m25 g_ad13 n26 g_ad14 n27 g_ad15 r25 g_ad16 r24 g_ad17 t29 g_ad18 t27 g_ad19 k26 g_ad2 t26 g_ad20 u27 g_ad21 v27 g_ad22 v28 g_ad23 u26 g_ad24 v29 g_ad25 ball # signal name w29 g_ad26 v25 g_ad27 w26 g_ad28 w25 g_ad29 k25 g_ad3 w27 g_ad30 y29 g_ad31 l26 g_ad4 j27 g_ad5 k29 g_ad6 k27 g_ad7 m29 g_ad8 m28 g_ad9 l27 g_c/be0# p29 g_c/be1# r27 g_c/be2# t25 g_c/be3# r28 g_devsel# r29 g_frame# ad29 g_gnt# p26 g_irdy# p28 g_par ac27 g_req# n25 g_stop# p27 g_trdy# ag26 gbin ad24 gbout ag6 gm_gclk [reserved] aj6 gm_rclk [reserved] ag29 green [reserved] ag28 green# [reserved] c2 gtl_rcomp j7 gtl_refa aa7 gtl_refb
intel ? 830 chipset family 298338-003 datasheet 219 r ball # signal name j3 ha10# f3 ha11# p6 ha12# g1 ha13# n5 ha14# h1 ha15# p4 ha16# t4 ha17# m2 ha18# j2 ha19# l2 ha20# r4 ha21# k1 ha22# l3 ha23# l1 ha24# j1 ha25# n1 ha26# t5 ha27# h3 ha28# m3 ha29# h2 ha3# m1 ha30# k3 ha31# e3 ha4# g3 ha5# n4 ha6# m6 ha7# f1 ha8# f2 ha9# u4 hd0# p1 hd1# r3 hd10# u1 hd11# v6 hd12# w4 hd13# t3 hd14# ball # signal name p2 hd15# v3 hd16# r2 hd17# t1 hd18# w3 hd19# w6 hd2# u3 hd20# y4 hd21# aa3 hd22# w1 hd23# v1 hd24# y1 hd25# y6 hd26# ad3 hd27# ab4 hd28# ab5 hd29# u2 hd3# v2 hd30# y3 hd31# y2 hd32# aa4 hd33# aa1 hd34# aa6 hd35# ab1 hd36# ac4 hd37# aa2 hd38# ab3 hd39# u6 hd4# ad2 hd40# ad1 hd41# ac2 hd42# ab6 hd43# ac6 hd44# ac1 hd45# af3 hd46# ad4 hd47#
intel ? 830 chipset family 220 datasheet 298338-003 r ball # signal name ad6 hd48# ac3 hd49# r1 hd5# ah3 hd50# ae5 hd51# ae3 hd52# ag2 hd53# af4 hd54# af2 hd55# aj3 hd56# ae4 hd57# ag1 hd58# ae1 hd59# n3 hd6# ag4 hd60# ah4 hd61# ag3 hd62# af1 hd63# w5 hd7# v4 hd8# p3 hd9# d3 hit# d1 hitm# j23 hl_rcomp h24 hlref g26 hl0 h28 hl1 h26 hl10 h29 hl2 h27 hl3 f29 hl4 f27 hl5 e29 hl6 e28 hl7 g25 hl8 g27 hl9 ball # signal name j6 hlock# g29 hlstrb f28 hlstrb# k6 hreq0# m4 hreq1# k5 hreq2# k4 hreq3# l6 hreq4# ad28 hsync [reserved] aj4 htclk ah5 htclk# g4 htrdy# ad25 i2c_clk [reserved] ac25 i2c_data [reserved] e11 nc e20 nc f12 nc f20 nc ab26 pipe# ad14 ram_refa ae14 ram_refb ab25 rbf# af29 red af28 red# aj27 refset ab24 reset# ag11 rq0 [reserved] aj12 rq1 [reserved] ag12 rq2 [reserved] ah13 rq3 [reserved] ag13 rq4 [reserved] aj13 rq5 [reserved] ag14 rq6 [reserved] aj14 rq7 [reserved] h6 rs0#
intel ? 830 chipset family 298338-003 datasheet 221 r ball # signal name h4 rs1# g6 rs2# aa27 sb_stb aa28 sb_stb# aa29 sba0 aa24 sba1 aa25 sba2 y24 sba3 y27 sba4 y26 sba5 w24 sba6 y28 sba7 af7 sck [reserved] aj7 sio [reserved] b16 sm_ba0 c16 sm_ba1 d19 sm_cas# a13 sm_cke0 c9 sm_cke1 c13 sm_cke2 a9 sm_cke3 a15 sm_clk0 b2 sm_clk1 b14 sm_clk2 a3 sm_clk3 e17 sm_cs0# f16 sm_cs1# d16 sm_cs2# d15 sm_cs3# f18 sm_dqm0 d18 sm_dqm1 d13 sm_dqm2 d12 sm_dqm3 e18 sm_dqm4 f17 sm_dqm5 f14 sm_dqm6 ball # signal name f13 sm_dqm7 a20 sm_ma0 b20 sm_ma1 a16 sm_ma10 c15 sm_ma11 c14 sm_ma12 b19 sm_ma2 c19 sm_ma3 a18 sm_ma4 a19 sm_ma5 c17 sm_ma6 c18 sm_ma7 b17 sm_ma8 a17 sm_ma9 d29 sm_md0 c29 sm_md1 c23 sm_md10 f22 sm_md11 b23 sm_md12 c22 sm_md13 e21 sm_md14 b22 sm_md15 c12 sm_md16 d10 sm_md17 c11 sm_md18 a10 sm_md19 d27 sm_md2 c10 sm_md20 c8 sm_md21 a7 sm_md22 e9 sm_md23 c7 sm_md24 e8 sm_md25 a5 sm_md26 f8 sm_md27 c5 sm_md28
intel ? 830 chipset family 222 datasheet 298338-003 r ball # signal name d6 sm_md29 c27 sm_md3 b4 sm_md30 c4 sm_md31 e27 sm_md32 c28 sm_md33 b28 sm_md34 e26 sm_md35 c26 sm_md36 d25 sm_md37 a26 sm_md38 d24 sm_md39 a27 sm_md4 f23 sm_md40 a25 sm_md41 g22 sm_md42 d22 sm_md43 a23 sm_md44 f21 sm_md45 d21 sm_md46 a22 sm_md47 f11 sm_md48 a11 sm_md49 b26 sm_md5 b11 sm_md50 f10 sm_md51 b10 sm_md52 b8 sm_md53 d9 sm_md54 b7 sm_md55 f9 sm_md56 a6 sm_md57 c6 sm_md58 d7 sm_md59 e24 sm_md6 b5 sm_md60 ball # signal name e6 sm_md61 a4 sm_md62 d4 sm_md63 c25 sm_md7 e23 sm_md8 b25 sm_md9 a24 sm_oclk c20 sm_ras# c24 sm_rclk f6 sm_rcomp e5 sm_refa f24 sm_refb a21 sm_we# ac28 st0 ac29 st1 ab27 st2 n6 vcc t6 vcc h7 vcc k7 vcc l7 vcc w7 vcc y7 vcc ab7 vcc p12 vcc r12 vcc t12 vcc m14 vcc m15 vcc m16 vcc p18 vcc r18 vcc t18 vcc h23 vcc k23 vcc y23 vcc
intel ? 830 chipset family 298338-003 datasheet 223 r ball # signal name m24 vcc p24 vcc t24 vcc v24 vcc l23 vcc_agp u24 vcc_agp j26 vcc_agp m26 vcc_agp r26 vcc_agp v26 vcc_agp aa23 vcc_agp aa26 vcc_agp ac8 vcc_cmos ac9 vcc_cmos ae7 vcc_cmos af6 vcc_cmos ac21 vcc_dvo af21 vcc_dvo af24 vcc_dvo ad23 vcc_gpio ae25 vcc_gpio j24 vcc_hub f26 vcc_hub ac10 vcc_lm ac11 vcc_lm ad11 vcc_lm ad12 vcc_lm ad13 vcc_lm ad17 vcc_lm ad18 vcc_lm ad19 vcc_lm ae18 vcc_lm d5 vcc_sm d8 vcc_sm d11 vcc_sm g11 vcc_sm ball # signal name d14 vcc_sm d17 vcc_sm d20 vcc_sm d23 vcc_sm g23 vcc_sm d26 vcc_sm g10 vcc_sm e12 vcc_sm a8 vcc_sm a12 vcc_sm g7 vcca_cpll af26 vcca_dac ag27 vcca_dac ac20 vcca_dpll0 f25 vcca_dpll1 ae6 vcca_hpll w23 vccq_agp n24 vccq_agp e15 vccq_sm f7 vccq_sm f15 vccq_sm g19 vccq_sm g20 vccq_sm v14 vdd_lm v15 vdd_lm v16 vdd_lm ad15 vdd_lm ad16 vdd_lm ae15 vdd_lm ae16 vdd_lm a14 vss b13 vss c3 vss c21 vss e14 vss f19 vss
intel ? 830 chipset family 224 datasheet 298338-003 r ball # signal name d2 vss g2 vss k2 vss n2 vss t2 vss w2 vss ab2 vss ae2 vss ah2 vss b3 vss e4 vss h5 vss l5 vss p5 vss u5 vss y5 vss ac5 vss af5 vss aj5 vss b6 vss ah6 vss e7 vss ac7 vss ag7 vss ad8 vss ae8 vss af8 vss ah8 vss b9 vss g9 vss ad9 vss ae9 vss af9 vss ah9 vss e10 vss ad10 vss ball # signal name ae10 vss af10 vss ae11 vss af11 vss ah11 vss b12 vss m12 vss n12 vss u12 vss v12 vss ae12 vss af12 vss ah12 vss e13 vss m13 vss n13 vss p13 vss r13 vss t13 vss u13 vss v13 vss ae13 vss af13 vss n14 vss p14 vss r14 vss t14 vss u14 vss af14 vss ah14 vss b15 vss n15 vss p15 vss r15 vss t15 vss u15 vss
intel ? 830 chipset family 298338-003 datasheet 225 r ball # signal name af15 vss ag15 vss e16 vss n16 vss p16 vss r16 vss t16 vss u16 vss af16 vss ag16 vss m17 vss n17 vss p17 vss r17 vss t17 vss u17 vss v17 vss ae17 vss af17 vss ah17 vss b18 vss m18 vss n18 vss u18 vss v18 vss af18 vss ah18 vss e19 vss ae19 vss af19 vss ah19 vss af20 vss ah20 vss b21 vss g21 vss ag21 vss ball # signal name ah21 vss aj21 vss e22 vss ad22 vss ab23 vss ac23 vss b24 vss ah24 vss e25 vss h25 vss l25 vss p25 vss u25 vss y25 vss af25 vss ac26 vss b27 vss af27 vss d28 vss g28 vss k28 vss n28 vss t28 vss w28 vss ab28 vss ae28 vss g8 vssa_cpll ah26 vssa_dac ae20 vssa_dpll0 g24 vssa_dpll1 ad7 vssa_hpll ae29 vsync e2 vtt f5 vtt j5 vtt m5 vtt
intel ? 830 chipset family 226 datasheet 298338-003 r ball # signal name r5 vtt v5 vtt aa5 vtt ad5 vtt ag5 vtt ab29 wbf#
intel ? 830chipset family 298338-002 datasheet 227 r 7.5 intel 830m gmch-m signal list table 61. intel 830m chipset ballout signal name list ball # signal name l29 ad_stb0 / dvob_clk l28 ad_stb0#/ dvob_clk# u29 ad_stb1/ dvoc_clk u28 ad_stb1#/ dvoc_clk# c1 ads# ac24 agpbusy# k24 agp_rcomp/ dvobc_rcomp j25 agpref/ dvobc_ref ah28 blue ah27 blue# e1 bnr# l4 bpri# aj16 cfm [reserved] ah16 cfm# [reserved] ah7 cmd [reserved] r6 cpurst# ah15 ctm [reserved] aj15 ctm# [reserved] g5 dbsy# ae27 ddc1_clk ad27 ddc1_data ae26 ddc2_clk ad26 ddc2_data j4 defer# ag17 dq_a0 [reserved] ball # signal name aj17 dq_a1 [reserved] ag18 dq_a2 [reserved] aj18 dq_a3 [reserved] ag19 dq_a4 [reserved] aj19 dq_a5 [reserved] ag20 dq_a6 [reserved] aj20 dq_a7 [reserved] aj11 dq_b0 [reserved] ah10 dq_b1 [reserved] aj10 dq_b2 [reserved] ag10 dq_b3 [reserved] aj9 dq_b4 [reserved] ag9 dq_b5 [reserved] aj8 dq_b6 [reserved] ag8 dq_b7 [reserved] f4 drdy# ac19 drefclk ad20 dv0a_clkint ad21 dvoa_blank# ag24 dvoa_clk# aj24 dvoa_clk aj22 dvoa_d0 ah22 dvoa_d1 ag25 dvoa_d10
intel ? 830 chipset family 228 datasheet 298338-003 r ball # signal name aj26 dvoa_d11 ag22 dvoa_d2 aj23 dvoa_d3 ah23 dvoa_d4 ag23 dvoa_d5 /strap[0] ae23 dvoa_d6 ae24 dvoa_d7 /strap[1] aj25 dvoa_d8 /strap[2] ah25 dvoa_d9 ae22 dvoa_fld/stl af22 dvoa_hsync ae21 dvoa_intr# ac22 dvoa_rcomp af23 dvoa_vsync j29 g_ad0/ dvob_hsync j28 g_ad1/ dvob_vsync l24 g_ad10/ dvob_d8 m27 g_ad11/ dvob_d11 n29 g_ad12/ dvob_d10 m25 g_ad13/ dvobc_clkint# n26 g_ad14/ dvob_fld/stl n27 g_ad15 r25 g_ad16/ dvoc_vsync r24 g_ad17/ dvoc_hsync t29 g_ad18/ dvoc_blank# t27 g_ad19 k26 g_ad2 t26 g_ad20/ dvoc_d1 ball # signal name u27 g_ad21/ dvoc_d2 v27 g_ad22/ dvoc_d3 v28 g_ad23/ dvoc_d4 u26 g_ad24/ dvoc_d7 v29 g_ad25/ dvoc_d6 w29 g_ad26/ dvoc_d9 v25 g_ad27/ dvoc_d8 w26 g_ad28/ dvoc_d11 w25 g_ad29/ dvoc_d10 k25 g_ad3/ dvoc_d0 w27 g_ad30/ dvobc_intr# /dprms_clk y29 g_ad31/ dvoc_fld/stl l26 g_ad4/ dvob_d3 j27 g_ad5/ dvob_d2 k29 g_ad6/ dvob_d5 k27 g_ad7/ dvob_d4 m29 g_ad8/ dvob_d6 m28 g_ad9/ dvob_d9 l27 g_c/be0#/ dvob_d7 p29 g_c/be1#/ dvob_blank# r27 g_c/be2# t25 g_c/be3#/ dvoc_d5 r28 g_devsel#/ mi2cdata
intel ? 830 chipset family 298338-003 datasheet 229 r ball # signal name m_i2c_data r29 g_frame#/ m_ddc1_data ad29 g_gnt# p26 g_irdy#/ m_i2c_clk p28 g_par ac27 g_req# n25 g_stop# p27 g_trdy#/ m_ddc1_clk ag26 gbin ad24 gbout ag6 gm_gclk aj6 gm_rclk ag29 green ag28 green# c2 gtl_rcomp j7 gtl_refa aa7 gtl_refb j3 ha10# f3 ha11# p6 ha12# g1 ha13# n5 ha14# h1 ha15# p4 ha16# t4 ha17# m2 ha18# j2 ha19# l2 ha20# r4 ha21# k1 ha22# l3 ha23# l1 ha24# j1 ha25# n1 ha26# t5 ha27# ball # signal name r29 g_frame#/ m_ddc1_data ad29 g_gnt# p26 g_irdy#/ m_i2c_clk p28 g_par ac27 g_req# n25 g_stop# p27 g_trdy#/ m_ddc1_clk ag26 gbin ad24 gbout ag6 gm_gclk aj6 gm_rclk ag29 green ag28 green# c2 gtl_rcomp j7 gtl_refa aa7 gtl_refb j3 ha10# f3 ha11# p6 ha12# g1 ha13# n5 ha14# h1 ha15# p4 ha16# t4 ha17# m2 ha18# j2 ha19# l2 ha20# r4 ha21# k1 ha22# l3 ha23# l1 ha24# j1 ha25# n1 ha26# t5 ha27#
intel ? 830 chipset family 230 datasheet 298338-003 r ball # signal name h3 ha28# m3 ha29# h2 ha3# m1 ha30# k3 ha31# e3 ha4# g3 ha5# n4 ha6# m6 ha7# f1 ha8# f2 ha9# u4 hd0# p1 hd1# r3 hd10# u1 hd11# v6 hd12# w4 hd13# t3 hd14# p2 hd15# v3 hd16# r2 hd17# t1 hd18# w3 hd19# w6 hd2# u3 hd20# y4 hd21# aa3 hd22# w1 hd23# v1 hd24# y1 hd25# y6 hd26# ad3 hd27# ab4 hd28# ab5 hd29# u2 hd3# v2 hd30# ball # signal name y3 hd31# y2 hd32# aa4 hd33# aa1 hd34# aa6 hd35# ab1 hd36# ac4 hd37# aa2 hd38# ab3 hd39# u6 hd4# ad2 hd40# ad1 hd41# ac2 hd42# ab6 hd43# ac6 hd44# ac1 hd45# af3 hd46# ad4 hd47# ad6 hd48# ac3 hd49# r1 hd5# ah3 hd50# ae5 hd51# ae3 hd52# ag2 hd53# af4 hd54# af2 hd55# aj3 hd56# ae4 hd57# ag1 hd58# ae1 hd59# n3 hd6# ag4 hd60# ah4 hd61# ag3 hd62# af1 hd63#
intel ? 830 chipset family 298338-003 datasheet 231 r ball # signal name w5 hd7# v4 hd8# p3 hd9# d3 hit# d1 hitm# j23 hl_rcomp h24 hlref g26 hl0 h28 hl1 h26 hl10 h29 hl2 h27 hl3 f29 hl4 f27 hl5 e29 hl6 e28 hl7 g25 hl8 g27 hl9 j6 hlock# g29 hlstrb f28 hlstrb# k6 hreq0# m4 hreq1# k5 hreq2# k4 hreq3# l6 hreq4# ad28 hsync aj4 htclk ah5 htclk# g4 htrdy# ad25 i2c_clk ac25 i2c_data e11 nc e20 nc f12 nc f20 nc ball # signal name ab26 pipe# ad14 ram_refa ae14 ram_refb ab25 rbf# af29 red af28 red# aj27 refset ab24 reset# ag11 rq0 [reserved] aj12 rq1 [reserved] ag12 rq2 [reserved] ah13 rq3 [reserved] ag13 rq4 [reserved] aj13 rq5 [reserved] ag14 rq6 [reserved] aj14 rq7 [reserved] h6 rs0# h4 rs1# g6 rs2# aa27 sb_stb aa28 sb_stb# aa29 sba0 aa24 sba1 aa25 sba2 y24 sba3 y27 sba4 y26 sba5 w24 sba6 y28 sba7 af7 sck [reserved] aj7 sio [reserved]
intel ? 830 chipset family 232 datasheet 298338-003 r ball # signal name b16 sm_ba0 c16 sm_ba1 d19 sm_cas# a13 sm_cke0 c9 sm_cke1 c13 sm_cke2 a9 sm_cke3 a15 sm_clk0 b2 sm_clk1 b14 sm_clk2 a3 sm_clk3 e17 sm_cs0# f16 sm_cs1# d16 sm_cs2# d15 sm_cs3# f18 sm_dqm0 d18 sm_dqm1 d13 sm_dqm2 d12 sm_dqm3 e18 sm_dqm4 f17 sm_dqm5 f14 sm_dqm6 f13 sm_dqm7 a20 sm_ma0 b20 sm_ma1 a16 sm_ma10 c15 sm_ma11 c14 sm_ma12 b19 sm_ma2 c19 sm_ma3 a18 sm_ma4 a19 sm_ma5 c17 sm_ma6 c18 sm_ma7 b17 sm_ma8 a17 sm_ma9 ball # signal name d29 sm_md0 c29 sm_md1 c23 sm_md10 f22 sm_md11 b23 sm_md12 c22 sm_md13 e21 sm_md14 b22 sm_md15 c12 sm_md16 d10 sm_md17 c11 sm_md18 a10 sm_md19 d27 sm_md2 c10 sm_md20 c8 sm_md21 a7 sm_md22 e9 sm_md23 c7 sm_md24 e8 sm_md25 a5 sm_md26 f8 sm_md27 c5 sm_md28 d6 sm_md29 c27 sm_md3 b4 sm_md30 c4 sm_md31 e27 sm_md32 c28 sm_md33 b28 sm_md34 e26 sm_md35 c26 sm_md36 d25 sm_md37 a26 sm_md38 d24 sm_md39 a27 sm_md4 f23 sm_md40
intel ? 830 chipset family 298338-003 datasheet 233 r ball # signal name a25 sm_md41 g22 sm_md42 d22 sm_md43 a23 sm_md44 f21 sm_md45 d21 sm_md46 a22 sm_md47 f11 sm_md48 a11 sm_md49 b26 sm_md5 b11 sm_md50 f10 sm_md51 b10 sm_md52 b8 sm_md53 d9 sm_md54 b7 sm_md55 f9 sm_md56 a6 sm_md57 c6 sm_md58 d7 sm_md59 e24 sm_md6 b5 sm_md60 e6 sm_md61 a4 sm_md62 d4 sm_md63 c25 sm_md7 e23 sm_md8 b25 sm_md9 a24 sm_oclk c20 sm_ras# c24 sm_rclk f6 sm_rcomp e5 sm_refa f24 sm_refb a21 sm_we# ac28 st0 ball # signal name ac29 st1 ab27 st2 n6 vcc t6 vcc h7 vcc k7 vcc l7 vcc w7 vcc y7 vcc ab7 vcc p12 vcc r12 vcc t12 vcc m14 vcc m15 vcc m16 vcc p18 vcc r18 vcc t18 vcc h23 vcc k23 vcc y23 vcc m24 vcc p24 vcc t24 vcc v24 vcc l23 vcc_agp u24 vcc_agp j26 vcc_agp m26 vcc_agp r26 vcc_agp v26 vcc_agp aa23 vcc_agp aa26 vcc_agp ac8 vcc_cmos ac9 vcc_cmos
intel ? 830 chipset family 234 datasheet 298338-003 r ball # signal name ae7 vcc_cmos af6 vcc_cmos ac21 vcc_dvo af21 vcc_dvo af24 vcc_dvo ad23 vcc_gpio ae25 vcc_gpio j24 vcc_hub f26 vcc_hub ac10 vcc_lm ac11 vcc_lm ad11 vcc_lm ad12 vcc_lm ad13 vcc_lm ad17 vcc_lm ad18 vcc_lm ad19 vcc_lm ae18 vcc_lm d5 vcc_sm d8 vcc_sm d11 vcc_sm g11 vcc_sm d14 vcc_sm d17 vcc_sm d20 vcc_sm d23 vcc_sm g23 vcc_sm d26 vcc_sm g10 vcc_sm e12 vcc_sm a8 vcc_sm a12 vcc_sm g7 vcca_cpll af26 vcca_dac ag27 vcca_dac ac20 vcca_dpll0 ball # signal name f25 vcca_dpll1 ae6 vcca_hpll w23 vccq_agp n24 vccq_agp e15 vccq_sm f7 vccq_sm f15 vccq_sm g19 vccq_sm g20 vccq_sm v14 vdd_lm v15 vdd_lm v16 vdd_lm ad15 vdd_lm ad16 vdd_lm ae15 vdd_lm ae16 vdd_lm a14 vss b13 vss c3 vss c21 vss e14 vss f19 vss d2 vss g2 vss k2 vss n2 vss t2 vss w2 vss ab2 vss ae2 vss ah2 vss b3 vss e4 vss h5 vss l5 vss p5 vss
intel ? 830 chipset family 298338-003 datasheet 235 r ball # signal name u5 vss y5 vss ac5 vss af5 vss aj5 vss b6 vss ah6 vss e7 vss ac7 vss ag7 vss ad8 vss ae8 vss af8 vss ah8 vss b9 vss g9 vss ad9 vss ae9 vss af9 vss ah9 vss e10 vss ad10 vss ae10 vss af10 vss ae11 vss af11 vss ah11 vss b12 vss m12 vss n12 vss u12 vss v12 vss ae12 vss af12 vss ah12 vss e13 vss ball # signal name m13 vss n13 vss p13 vss r13 vss t13 vss u13 vss v13 vss ae13 vss af13 vss n14 vss p14 vss r14 vss t14 vss u14 vss af14 vss ah14 vss b15 vss n15 vss p15 vss r15 vss t15 vss u15 vss af15 vss ag15 vss e16 vss n16 vss p16 vss r16 vss t16 vss u16 vss af16 vss ag16 vss m17 vss n17 vss p17 vss r17 vss
intel ? 830 chipset family 236 datasheet 298338-003 r ball # signal name t17 vss u17 vss v17 vss ae17 vss af17 vss ah17 vss b18 vss m18 vss n18 vss u18 vss v18 vss af18 vss ah18 vss e19 vss ae19 vss af19 vss ah19 vss af20 vss ah20 vss b21 vss g21 vss ag21 vss ah21 vss aj21 vss e22 vss ad22 vss ab23 vss ac23 vss b24 vss ah24 vss e25 vss h25 vss ball # signal name l25 vss p25 vss u25 vss y25 vss af25 vss ac26 vss b27 vss af27 vss d28 vss g28 vss k28 vss n28 vss t28 vss w28 vss ab28 vss ae28 vss g8 vssa_cpll ah26 vssa_dac ae20 vssa_dpll0 g24 vssa_dpll1 ad7 vssa_hpll ae29 vsync e2 vtt f5 vtt j5 vtt m5 vtt r5 vtt v5 vtt aa5 vtt ad5 vtt ag5 vtt ab29 wbf#
intel ? 830 chipset family 298338-003 datasheet 237 r 7.6 intel 830mg gmch-m signal list table 62. intel 830mg chipset ballout signal name list ball # signal name l29 dvob_clk l28 dvob_clk# u29 dvoc_clk u28 dvoc_clk# c1 ads# ac24 agpbusy# k24 dvobc_rcomp j25 dvobc_ref ah28 blue ah27 blue# e1 bnr# l4 bpri# aj16 cfm [reserved] ah16 cfm# [reserved] ah7 cmd [reserved] r6 cpurst# ah15 ctm [reserved] aj15 ctm# [reserved] g5 dbsy# ae27 ddc1_clk ad27 ddc1_data ae26 ddc2_clk ad26 ddc2_data j4 defer# ag17 dq_a0 [reserved] aj17 dq_a1 [reserved] ag18 dq_a2 [reserved] aj18 dq_a3 [reserved] ag19 dq_a4 [reserved] aj19 dq_a5 [reserved] ball # signal name ag20 dq_a6 [reserved] aj20 dq_a7 [reserved] aj11 dq_b0 [reserved] ah10 dq_b1 [reserved] aj10 dq_b2 [reserved] ag10 dq_b3 [reserved] aj9 dq_b4 [reserved] ag9 dq_b5 [reserved] aj8 dq_b6 [reserved] ag8 dq_b7 [reserved] f4 drdy# ac19 drefclk ad20 dv0a_clkint ad21 dvoa_blank# ag24 dvoa_clk# aj24 dvoa_clk aj22 dvoa_d0 ah22 dvoa_d1 ag25 dvoa_d10 aj26 dvoa_d11 ag22 dvoa_d2 aj23 dvoa_d3 ah23 dvoa_d4 ag23 dvoa_d5/ strap[0] ae23 dvoa_d6 ae24 dvoa_d7/ strap[7] aj25 dvoa_d8/ strap[8] ah25 dvoa_d9 ae22 dvoa_fld/stl af22 dvoa_hsync ae21 dvoa_intr#
intel ? 830 chipset family 238 datasheet 298338-003 r ball # signal name ac22 dvoa_rcomp af23 dvoa_vsync j29 dvob_hsync j28 dvob_vsync l24 dvob_d8 m27 dvob_d11 n29 dvob_d10 m25 dvobc_clkint# n26 dvob_fld/stl n27 g_ad15 r25 dvoc_vsync r24 dvoc_hsync t29 dvoc_blank# t27 g_ad19 k26 g_ad2 t26 dvoc_d1 u27 dvoc_d2 v27 dvoc_d3 v28 dvoc_d4 u26 dvoc_d7 v29 dvoc_d6 w29 dvoc_d9 v25 dvoc_d8 w26 dvoc_d11 w25 dvoc_d10 k25 dvob_d0 w27 dvobc_intr#/dpms_clk y29 dvoc_fld/stl l26 dvob_d3 j27 dvob_d2 k29 dvob_d5 k27 dvob_d4 m29 dvob_d6 m28 dvob_d9 l27 dvob_d7 p29 dvob_blank# r27 g_c/be2# t25 dvoc_d5 r28 m_i2c_data r29 m_ddc1_data ad29 g_gnt# p26 m_i2c_clk ball # signal name p28 g_par ac27 g_req# n25 g_stop# p27 m_ddc1_clk ag26 gbin ad24 gbout ag6 gm_gclk aj6 gm_rclk ag29 green ag28 green# c2 gtl_rcomp j7 gtl_refa aa7 gtl_refb j3 ha10# f3 ha11# p6 ha12# g1 ha13# n5 ha14# h1 ha15# p4 ha16# t4 ha17# m2 ha18# j2 ha19# l2 ha20# r4 ha21# k1 ha22# l3 ha23# l1 ha24# j1 ha25# n1 ha26# t5 ha27# h3 ha28# m3 ha29# h2 ha3# m1 ha30# k3 ha31# e3 ha4# g3 ha5# n4 ha6# m6 ha7# f1 ha8# f2 ha9#
intel ? 830 chipset family 298338-003 datasheet 239 r ball # signal name u4 hd0# p1 hd1# r3 hd10# u1 hd11# v6 hd12# w4 hd13# t3 hd14# p2 hd15# v3 hd16# r2 hd17# t1 hd18# w3 hd19# w6 hd2# u3 hd20# y4 hd21# aa3 hd22# w1 hd23# v1 hd24# y1 hd25# y6 hd26# ad3 hd27# ab4 hd28# ab5 hd29# u2 hd3# v2 hd30# y3 hd31# y2 hd32# aa4 hd33# aa1 hd34# aa6 hd35# ab1 hd36# ac4 hd37# aa2 hd38# ab3 hd39# u6 hd4# ad2 hd40# ad1 hd41# ac2 hd42# ab6 hd43# ac6 hd44# ac1 hd45# af3 hd46# ball # signal name ad4 hd47# ad6 hd48# ac3 hd49# r1 hd5# ah3 hd50# ae5 hd51# ae3 hd52# ag2 hd53# af4 hd54# af2 hd55# aj3 hd56# ae4 hd57# ag1 hd58# ae1 hd59# n3 hd6# ag4 hd60# ah4 hd61# ag3 hd62# af1 hd63# w5 hd7# v4 hd8# p3 hd9# d3 hit# d1 hitm# j23 hl_rcomp h24 hlref g26 hl0 h28 hl1 h26 hl10 h29 hl2 h27 hl3 f29 hl4 f27 hl5 e29 hl6 e28 hl7 g25 hl8 g27 hl9 j6 hlock# g29 hlstrb f28 hlstrb# k6 hreq0# m4 hreq1#
intel ? 830 chipset family 240 datasheet 298338-003 r ball # signal name k5 hreq2# k4 hreq3# l6 hreq4# ad28 hsync aj4 htclk ah5 htclk# g4 htrdy# ad25 i2c_clk ac25 i2c_data e11 nc e20 nc f12 nc f20 nc ab26 pipe# ad14 ram_refa ae14 ram_refb ab25 rbf# af29 red af28 red# aj27 refset ab24 reset# ag11 rq0 [reserved] aj12 rq1 [reserved] ag12 rq2 [reserved] ah13 rq3 [reserved] ag13 rq4 [reserved] aj13 rq5 [reserved] ag14 rq6 [reserved] aj14 rq7 [reserved] h6 rs0# h4 rs1# g6 rs2# aa27 sb_stb aa28 sb_stb# aa29 sba0 aa24 sba1 ball # signal name aa25 sba2 y24 sba3 y27 sba4 y26 sba5 w24 sba6 y28 sba7 af7 sck [reserved] aj7 sio [reserved] b16 sm_ba0 c16 sm_ba1 d19 sm_cas# a13 sm_cke0 c9 sm_cke1 c13 sm_cke2 a9 sm_cke3 a15 sm_clk0 b2 sm_clk1 b14 sm_clk2 a3 sm_clk3 e17 sm_cs0# f16 sm_cs1# d16 sm_cs2# d15 sm_cs3# f18 sm_dqm0 d18 sm_dqm1 d13 sm_dqm2 d12 sm_dqm3 e18 sm_dqm4 f17 sm_dqm5 f14 sm_dqm6 f13 sm_dqm7 a20 sm_ma0 b20 sm_ma1 a16 sm_ma10 c15 sm_ma11 c14 sm_ma12 b19 sm_ma2 c19 sm_ma3 a18 sm_ma4 a19 sm_ma5 c17 sm_ma6
intel ? 830 chipset family 298338-003 datasheet 241 r ball # signal name c18 sm_ma7 b17 sm_ma8 a17 sm_ma9 d29 sm_md0 c29 sm_md1 c23 sm_md10 f22 sm_md11 b23 sm_md12 c22 sm_md13 e21 sm_md14 b22 sm_md15 c12 sm_md16 d10 sm_md17 c11 sm_md18 a10 sm_md19 d27 sm_md2 c10 sm_md20 c8 sm_md21 a7 sm_md22 e9 sm_md23 c7 sm_md24 e8 sm_md25 a5 sm_md26 f8 sm_md27 c5 sm_md28 d6 sm_md29 c27 sm_md3 b4 sm_md30 c4 sm_md31 e27 sm_md32 c28 sm_md33 b28 sm_md34 e26 sm_md35 c26 sm_md36 d25 sm_md37 a26 sm_md38 d24 sm_md39 a27 sm_md4 f23 sm_md40 a25 sm_md41 g22 sm_md42 d22 sm_md43 ball # signal name a23 sm_md44 f21 sm_md45 d21 sm_md46 a22 sm_md47 f11 sm_md48 a11 sm_md49 b26 sm_md5 b11 sm_md50 f10 sm_md51 b10 sm_md52 b8 sm_md53 d9 sm_md54 b7 sm_md55 f9 sm_md56 a6 sm_md57 c6 sm_md58 d7 sm_md59 e24 sm_md6 b5 sm_md60 e6 sm_md61 a4 sm_md62 d4 sm_md63 c25 sm_md7 e23 sm_md8 b25 sm_md9 a24 sm_oclk c20 sm_ras# c24 sm_rclk f6 sm_rcomp e5 sm_refa f24 sm_refb a21 sm_we# ac28 st0 ac29 st1 ab27 st2 n6 vcc t6 vcc h7 vcc k7 vcc l7 vcc w7 vcc y7 vcc
intel ? 830 chipset family 242 datasheet 298338-003 r ball # signal name ab7 vcc p12 vcc r12 vcc t12 vcc m14 vcc m15 vcc m16 vcc p18 vcc r18 vcc t18 vcc h23 vcc k23 vcc y23 vcc m24 vcc p24 vcc t24 vcc v24 vcc l23 vcc_agp u24 vcc_agp j26 vcc_agp m26 vcc_agp r26 vcc_agp v26 vcc_agp aa23 vcc_agp aa26 vcc_agp ac8 vcc_cmos ac9 vcc_cmos ae7 vcc_cmos af6 vcc_cmos ac21 vcc_dvo af21 vcc_dvo af24 vcc_dvo ad23 vcc_gpio ae25 vcc_gpio j24 vcc_hub f26 vcc_hub ac10 vcc_lm ac11 vcc_lm ad11 vcc_lm ad12 vcc_lm ad13 vcc_lm ad17 vcc_lm ball # signal name ad18 vcc_lm ad19 vcc_lm ae18 vcc_lm d5 vcc_sm d8 vcc_sm d11 vcc_sm g11 vcc_sm d14 vcc_sm d17 vcc_sm d20 vcc_sm d23 vcc_sm g23 vcc_sm d26 vcc_sm g10 vcc_sm e12 vcc_sm a8 vcc_sm a12 vcc_sm g7 vcca_cpll af26 vcca_dac ag27 vcca_dac ac20 vcca_dpll0 f25 vcca_dpll1 ae6 vcca_hpll w23 vccq_agp n24 vccq_agp e15 vccq_sm f7 vccq_sm f15 vccq_sm g19 vccq_sm g20 vccq_sm v14 vdd_lm v15 vdd_lm v16 vdd_lm ad15 vdd_lm ad16 vdd_lm ae15 vdd_lm ae16 vdd_lm a14 vss b13 vss c3 vss c21 vss e14 vss
intel ? 830 chipset family 298338-003 datasheet 243 r ball # signal name f19 vss d2 vss g2 vss k2 vss n2 vss t2 vss w2 vss ab2 vss ae2 vss ah2 vss b3 vss e4 vss h5 vss l5 vss p5 vss u5 vss y5 vss ac5 vss af5 vss aj5 vss b6 vss ah6 vss e7 vss ac7 vss ag7 vss ad8 vss ae8 vss af8 vss ah8 vss b9 vss g9 vss ad9 vss ae9 vss af9 vss ah9 vss e10 vss ad10 vss ae10 vss af10 vss ae11 vss af11 vss ah11 vss ball # signal name b12 vss m12 vss n12 vss u12 vss v12 vss ae12 vss af12 vss ah12 vss e13 vss m13 vss n13 vss p13 vss r13 vss t13 vss u13 vss v13 vss ae13 vss af13 vss n14 vss p14 vss r14 vss t14 vss u14 vss af14 vss ah14 vss b15 vss n15 vss p15 vss r15 vss t15 vss u15 vss af15 vss ag15 vss e16 vss n16 vss p16 vss r16 vss t16 vss u16 vss af16 vss ag16 vss m17 vss
intel ? 830 chipset family 244 datasheet 298338-003 r ball # signal name n17 vss p17 vss r17 vss t17 vss u17 vss v17 vss ae17 vss af17 vss ah17 vss b18 vss m18 vss n18 vss u18 vss v18 vss af18 vss ah18 vss e19 vss ae19 vss af19 vss ah19 vss af20 vss ah20 vss b21 vss g21 vss ag21 vss ah21 vss aj21 vss e22 vss ad22 vss ab23 vss ac23 vss b24 vss ah24 vss e25 vss ball # signal name h25 vss l25 vss p25 vss u25 vss y25 vss af25 vss ac26 vss b27 vss af27 vss d28 vss g28 vss k28 vss n28 vss t28 vss w28 vss ab28 vss ae28 vss g8 vssa_cpll ah26 vssa_dac ae20 vssa_dpll0 g24 vssa_dpll1 ad7 vssa_hpll ae29 vsync e2 vtt f5 vtt j5 vtt m5 vtt r5 vtt v5 vtt aa5 vtt ad5 vtt ag5 vtt ab29 wbf#
intel ? 830 chipset family 298338-003 datasheet 245 r 7.7 intel 830 chipset family chipset package dimensions figure 24 outlines the mechanical dimensions for the intel 830 chipset family gmch-m. the package is a 625-ball grid array (bga) package. figure 24. intel 830 chipset family gmch-m package dimensions

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