8/23/2010 page 1 of 2 pacific silicon sensor series 8 data sheet part description ad100-8-to52-s1 order # 06-035 pin 1 ? 2.54 3 pl anode pin 3 cathode 12.7 3 pl pin circle 1 pin 4 case active area: 0.00785 mm (100 m dia) 2 backside view ? 5.40 116 viewing angle ? 3.00 ? 4.70 3.60 frontside view ?0.46 2.70 features description applications ? ? 100 m active area ? high gain at low bias voltage ? fast rise time ? low capacitance 0.00785 mm 2 high speed, high gain avalanche photodiode with n on p cons truction. hermetically packaged in a to-52-s1 with a clear borosilicate glass window cap. ? high speed optical communications ? laser range finder ? medical equipment ? high speed photometry absolute maximum rating spectral response at m = 100 symbol parameter min max units t stg storage temp -55 +125 c t op operating temp -40 +100 c t soldering soldering temp 10 seconds +260 c electrical power dissipation @ 22 c - 100 mw optical peak value, once for 1 second - 200 mw i ph (dc) continuous optical operation - 250 a i ph (ac) pulsed signal input 50 s ?on? / 1 ms ?off? - 1 ma electro-optical characteristics @ 22 c symbol characteristic test conditions min typ max units i d dark current m = 100* --- 50 100 pa c capacitance m = 100* --- 0.8 --- pf v br breakdown voltage i d = 2 a 120 190 --- v temperature coefficient of v br 0.35 0.45 0.55 v/k responsivity m = 100; = 0 v; = 800 nm 45 50 --- a/w ?? 3db bandwidth -3db 2 --- --- ghz t r rise time --- --- 180 ps optimum gain 50 60 --- ?excess noise? factor m = 100 --- 2.2 --- ?excess noise? index m = 100 --- 0.2 --- noise current m = 100 --- 0.15 --- pa/hz 1/2 max gain 200 --- --- nep noise equivalent power m = 100; = 880 nm --- 3.0 x 10 -15 --- w/hz 1/2 * measurement conditions: setup of photo current 50 pa at m = 1 and irradiated by a 680 nm, 60 nm bandwidth led. increase the p hoto current up to 5.0 na, (m = 100) by internal multiplication due to an increasing bias voltage. 400 500 600 700 800 900 1000 1100 wavelength (nm) responsivity (a/w) 0 10 20 30 40 50 60 h o r s c o m p l i a n t
8/23/2010 page 2 of 2 disclaimer: due to our policy of continued developmen t, specifications are subject to change without notice. typical gain vs bias voltage quantum efficiency for m = 1 1 102030405060708090100110120130140150 bias voltage (v) gain 1 10 100 1000 10000 wavelength (nm) qe 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 400 480 560 640 720 800 880 960 1040 device schematic suggested circuit schematic pin 1 pin 4 pin 3 bias supply voltage current limiting resistor min. 0.1 f capacitor closest to apd apd diode, protective circuit read-out circuit or 50 ohm load resistance application notes ? current should be limited by a protecting resistor or current limiting ic inside the power supply. ? use of low noise read-out ic. ? for high gain applications (m>50) bias voltage should be temperature compensated. ? for low light level applications, blo cking of ambient light should be used. handling precautions: ? soldering temperature - 260 c for 10 seconds max. the device must be protected against solder flux vapor. ? minimum pin length - 2 mm ? esd protection - standard prec autionary measures are sufficient. ? storage - store devices in conductive foam. ? avoid skin contact with window. ? clean window with ethyl alcohol if necessary. ? do not scratch or abrade window. usa: pacific silicon sensor, inc. 5700 corsa avenue, #105 westlake village, ca 91362 usa phone (818) 706-3400 fax (818) 889-7053 email: sales@pacific-sensor.com www.pacific-sensor.com proud members of the silicon sensor international ag group of companies international sales: silicon sensor international ag peter-behrens-str. 15 d-12459 berlin, germany phone +49 (0)30-63 99 23 10 fax +49 (0)30-63 99 23 33 email: sales@silicon-sensor.de www.silicon-sensor.de
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