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rev. 0.4 4/08 copyright ? 2008 by silicon laboratories si5316 si5316 p recision c lock j itter a ttenuator description the si5316 is a low jitter, precision jitter attenuator for high-speed communication systems, including oc-48, oc-192, 10g ethernet, and 10g fibre channel. the si5316 accepts dual clock inputs in the 19, 38, 77, 155, 311, or 622 mhz frequency range and generates a jitter-attenuated clock output at the same frequency. within each of these clock ranges, the device can be tuned approximately 15% higher than nominal sonet/sdh frequencies, up to a maximum of 710 mhz in the 622 mhz range. the si5316 is based on silicon laboratories' 3rd-generation dspll ? technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated pll solution that eliminates the need for external vcxo and loop filter components. the dspll loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. operating from a single 1.8, 2.5, or 3.3 v supply, the si5316 is ideal for providin g jitter attenuation in high performance timing applications. applications ? optical modules ? sonet/sdh oc-48/oc-192/stm-16/stm-64 line cards ? 10gbe, 10gfc line cards ? itu g.709 line cards ? wireless basestations ? test and measurement ? synchronous ethernet features ? fixed frequency jitter attenuator with selectable clock ranges at 19, 38, 77, 155, 311, and 622 mhz (710 mhz max) ? support for sonet, 10gbe, 10gfc, and corresponding fec rates ? ultra-low jitter clock output with jitter generation as low as 0.3 ps rms (50khz?80mhz) ? integrated loop filter with selectable lo op bandwidth (100 hz to 7.9 khz) ? meets oc-192 gr-253-core jitter specifications ? dual clock inputs with integrated clock select mux ? one clock input can be 1x, 4x, or 32x the frequency of the second clock input ? single clock output with selectable signal format: lvpecl, lvds, cml, cmos ? lol, los alarm outputs ? pin programmable settings ? on-chip voltage regulator for 1.8 5%, 2.5 10%, or 3.3 v 10% operation ? small size (6 x 6 mm 36-lead qfn) ? pb-free, rohs compliant dspll ? frequency select xtal or refclock signal format ckin1 ckout signal detect loss of signal bandwidth select loss of lock ckin2 pll bypass clock select vdd (1.8, 2.5, or 3.3 v) gnd disable ck1div ck2div
si5316 2 rev. 0.4 table 1. performance specifications 1 (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max unit temperature range t a ?40 25 85 oc supply voltage v dd 2.97 3.3 3.63 v 2.25 2.5 2.75 v 1.71 1.8 1.89 v supply current i dd f out = 622.08 mhz lvpecl format output ? 217 243 ma f out = 19.44 mhz cmos format output ? 194 220 ma disable mode ? 165 215 ma input/output clock fre- quency (ckin1, ckin2, ckout) ck f frqsel[1:0] = ll frqsel[1:0] = lm frqsel[1:0] = lh frqsel[1:0] = ml frqsel[1:0] = mm frqsel[1:0] = mh 19.38 38.75 77.5 155.0 310.0 620.0 ? ? ? ? ? ? 22.28 44.56 89.13 178.25 356.5 710.0 mhz 3-level input pins input mid current i imm see note 2. ?2 ? 2 a input clocks (ckin1, ckin2) differential voltage swing ckn dpp 0.25 ? 1.9 v pp common mode voltage ckn vcm 1.8 v 5% 0.9 ? 1.4 v 2.5 v 10% 1.0 ? 1.7 v 3.3 v 10% 1.1 ? 1.95 v rise/fall time ckn trf 20?80% ? ? 11 ns duty cycle (minimum pulse width) ckn dc whichever is smaller 40 ? 60 % 2??ns output clock (ckout) common mode v ocm lvpecl 100 load line-to-line v dd ?1.42 ? v dd ?1.25 v differential ou tput swing v od 1.1 ? 1.9 v pp single ended output swing v se 0.5 ? 0.93 v rise/fall time cko trf 20?80% ? 230 350 ps duty cycle uncertainty cko dc lvpecl differential 100 line-to-line; measured at 50% point ?40 ? 40 ps pll performance jitter generation lvpecl output, f in =f out =622.08 bw[1:0] = hm j gen 50 khz?80 mhz ? 0.32 0.42 ps rms 12 khz?20 mhz ? 0.31 0.41 ps rms notes: 1. for a more comprehensive listing of device specifications, pl ease consult the silicon laboratories any-rate precision clock family reference manual. this document can be downloaded from www.silabs.com/timing . 2. this is the amount of leakage that t he 3-level input can tolerate from an external driver. see the family reference manual. in most designs, an external resistor voltage divider is recommended.
si5316 rev. 0.4 3 jitter transfer j pk ?0.050.1db external reference jitter transfer j pkextn ? 30 ? khz phase noise f in =f out =622.08 cko pn 100 hz offset ? ?65 ?50 dbc/hz 1 khz offset ? ?95 ?87 dbc/hz 10 khz offset ? ?110 ?100 dbc/hz 100 khz offset ? ?117 ?110 dbc/hz 1 mhz offset ? ?130 ?125 dbc/hz subharmonic noise f in =f out =622.08 sp subh phase noise @ 100 khz offset ? ?90 ?85 dbc spurious noise f in =f out =622.08 sp spur max spur @ n x f3 (n > 1, n x f3 < 100 mhz) ? ?98 ?75 dbc package thermal resistance junction to ambient ja still air ? 38 ? oc/w table 2. absolute maximum ratings parameter symbol value unit dc supply voltage v dd ?0.5 to 3.6 v lvcmos input voltage v dig ?0.3 to (v dd + 0.3) v operating junction temperature t jct ?55 to 150 oc storage temperature range t stg ?55 to 150 oc esd hbm tolerance (100 pf, 1.5 k ? ); all pins except ckin+/ckin? 2 kv esd mm tolerance; all pins except ckin+/ckin? 200 v esd hbm tolerance (100 pf, 1.5 k ? ); ckin+/ckin? 700 v esd mm tolerance; ckin+/ckin? 150 v latch-up tolerance jesd78 compliant note: permanent device damage may occur if the absolute maximu m ratings are exceeded. functional operation should be restricted to the conditions as specified in the operation se ctions of this data sheet. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. table 1. performance specifications 1 (continued) (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max unit notes: 1. for a more comprehensive listing of device specifications, pl ease consult the silicon laboratories any-rate precision clock family reference manual. this document can be downloaded from www.silabs.com/timing . 2. this is the amount of leakage that t he 3-level input can tolerate from an external driver. see the family reference manual. in most designs, an external resistor voltage divider is recommended.
si5316 4 rev. 0.4 figure 1. typical phase noise plot jitter band jitter, rms brick wall, 100 hz to 100 mhz 1,279 fs sonet_oc48, 12 khz to 20 mhz 315 fs sonet_oc192_a, 20 khz to 80 mhz 335 fs sonet_oc192_b, 4 mhz to 80 mhz 194 fs sonet_oc192_c, 50 khz to 80 mhz 318 fs brick wall, 800 hz to 80 mhz 343 fs -160 -140 -120 -100 -80 -60 -40 -20 0 100 1000 10000 100000 1000000 10000000 100000000 offset frequency (hz) phase noise (dbc/hz)
si5316 rev. 0.4 5 figure 2. si5316 typical application circuit si5316 cs ck1div 2 c1b c2b ck2div 2 frqsel[1:0] 2 lol bwsel[1:0] 2 sfout[1:0] 2 rate 2 dbl_by 2 rst xa xb ckout+ ckout? vdd gnd crystal (114.285 mhz) crystal/ref clk rate input clock select input clock 1 pre-divider select input clock 2 pre-divider select frequency select bandwidth select signal format select clock output disable/ bypass mode control reset ckin_1 loss of signal ckin_2 loss of signal pll loss of lock indicator clock output ckin1+ ckin1? input clock sources 1 1. assumes differential lvpecl termination (3.3 v) on clock inputs. notes: option 1: 100 0.1 f 0.1 f + ? ferrite bead system power supply c 3 c 2 c 1 c 4 0.1 f 0.1 f 0.1 f 1 f 130 130 82 82 v dd = 3.3 v ckin2+ ckin2? 130 130 82 82 v dd = 3.3 v xa xb 38.88 mhz refclk+ option 2: 0.1 f 38.88 mhz refclk? 0.1 f v dd 15 k 15 k v dd 15 k 15 k v dd 15 k 15 k v dd 15 k 15 k v dd 15 k 15 k v dd 15 k 15 k v dd 15 k 15 k 2. denotes 3-level input pins with states designated as l (ground), m (v dd /2), and h (v dd ).
si5316 6 rev. 0.4 1. functional description the si5316 is a precision jitter attenuator for high-speed communication systems, incl uding oc-48/stm-16, oc- 192/stm-64, 10g ethernet, and 10g fibre channel. the si5316 accepts dual clock inputs in the 19, 38, 77, 155, 311, or 622 mhz frequency range and generates a jitter-attenuated clock output at the same frequency. within each of these clock ranges, the device can be tuned approximately 15% higher than nominal sonet/sdh frequencies, up to a maximum of 710 mhz in the 622 mhz range. the si5316 is based on silicon laboratories' 3rd-generation dspll ? technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated pll solution that eliminates the need for external vcxo and loop filter components . for applications which require input clocks at different frequencies, the frequency of ckin1 can be 1x, 4x, or 32x the frequency of ckin2 as specified by the ck1div and ck2div inputs. the si5316 pll loop bandwidth is selectable via the bwsel[1:0] pins and supports a range from 100 hz to 7.9 khz. to calculate pote ntial loop bandwidth values for a given input/output clock frequency, silicon laboratories offers a pc-based software utility, dspll sim , that calculates valid loop bandwidth settings automatically. this utilit y can be downloaded from http://www.silabs.com/timing ; click on documentation. the si5316 supports manual active input clock selection. the si5316 monitors both input clocks for loss-of-signal and provides a los alarm when it detects missing pulses on either input clock. hitless switching is not supported by the si5316. during a clock transition, the phase of the output clock will slew at a rate defined by the pll loop bandwidth unt il the original input clock phase to output clock phase is restored. the device monitors the lock status of the pll. the lock detect algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. the si5316 has one differential clock output. the electrical format of the cl ock output is programmable to support lvpecl, lvds, cml, or cmos loads. for system-level debugging, a bypass mode is available which drives the output clock directly from the input clock, bypassing the internal dspll. the device is powered by a single 1.8, 2.5, or 3.3 v supply. 1.1. external reference an external, 38.88 mhz clock or a low-cost 114.285 mhz 3rd overtone crystal is used as part of a fixed-frequency oscillator within the dspll. this external reference is required for the device to operate. silicon laboratories recomme nds using a high quality crystal. specific recommendations may be found in the family reference manual. an external 38.88 mhz clock from a high quality ocxo or tcxo can also be used as a reference for the device. in digital hold, the dspl l remains locked to this external reference. any changes in the frequency of this reference when the dspll is in digital hold will be tracked by the output of th e device. note that crystals can have temperature sensitivities. 1.2. further documentation consult the silicon laborato ries any-rate precision clock family reference ma nual (frm) for detailed information about the si5316. additional design support is available from silicon laboratories through your distributor. silicon laboratories has developed a pc-based software utility called dspll sim to simplify device configuration, including frequency planning and loop bandwidth selection. the frm and this utility can be downloaded from http://www.silabs.com/timing ; click on documentation.
si5316 rev. 0.4 7 2. pin descriptions: si5316 table 3. si5316 pin descriptions pin # pin name i/o signal level description 1 rst ilvcmos external reset. active low input that performs external hardware reset of device. resets all internal logic to a known state. clock outputs are tristated during reset. after rising edge of rst signal, the si5316 will perform an internal self-calibration when a valid signal is present. this pin has a weak pull-up. 2, 9, 28, 29, 36 nc ? ? no connect. these pins must be left unconnected for normal operation. 3c1bolvcmos ckin1 loss of signal. active high loss-of-signal indicator for ckin1. once triggered, the alarm will remain active until ckin1 is validated. 0 = ckin1 present 1 = los on ckin1 4c2bolvcmos ckin2 loss of signal. active high loss-of-signal indicator for ckin2. once triggered, the alarm will remain active until ckin2 is validated. 0 = ckin2 present 1 = los on ckin2 5, 10, 32 v dd v dd supply supply. the device operates from a 1.8, 2.5, or 3.3 v supply. bypass capaci- tors should be associated with the following v dd pins: 50.1 f 10 0.1 f 32 0.1 f a 1.0 f should also be placed as close to device as is practical. *note: denotes 3-level input pin with states desi gnated as l (ground), m (vdd/2), and h (vdd). 1 2 3 29 30 31 32 33 34 35 36 20 21 22 23 24 25 26 27 10 11 12 13 14 15 16 17 4 5 6 7 8 nc rst c2b c1b gnd vdd xa vdd rate0 ckin2+ ckin2? dbl_by rate1 ckin1+ ckin1? cs bwsel0 bwsel1 frqsel1 ck1div ck2div nc sfout1 gnd vdd sfout0 ckout? ckout+ nc gnd pad frqsel0 gnd 9 18 19 28 xb lol gnd nc nc
si5316 8 rev. 0.4 7 6 xb xa ianalog external crystal or reference clock. external crystal should be connected to these pins to use internal oscillator based re ference. refer to family reference manual for interfacing to an external reference. external reference must be from a high-quality clock source (tcxo, ocxo). frequency of crystal or external clock is set by the rate pins. 8, 19*, 20*, 31 gnd gnd supply ground. must be connected to system gr ound. minimize the ground path impedance for optimal performance of this device. grounding these pins does not eliminate the requirement to ground the gnd pad on the bottom of the package. *note: may be left nc. 11 15 rate0 rate1 i 3-level* external crystal or reference clock rate. three level inputs that select the type and rate of external crystal or reference clock to be applied to the xa/xb port. refer to the family reference manual for settings. th ese pins have both a weak pull-up and a weak pull-down; they default to m. the "hh" setting is not sup- ported. some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 12 13 ckin2+ ckin2? imulti clock input 2. differential input clock. this in put can also be driven with a single- ended signal. 14 dbl_by i 3-level* output disable/bypass mode control. controls enable of ckout divider/output buffer path and pll bypass mode. l = ckout enabled m = ckout disabled h = bypass mode with ckout enabled this pin has a weak pull-up and weak pull-down and defaults to m. some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 16 17 ckin1+ ckin1? imulti clock input 1. differential input clock. this in put can also be driven with a single- ended signal. 18 lol o lvcmos pll loss of lock indicator. this pin functions as the active high pll loss of lock indicator. 0=pll locked 1 = pll unlocked 21 cs i lvcmos input clock select. this pin functions as the input clock selector. this input is internally deglitched to prevent inadvertent clock switching during changes in the cksel input state. 0 = select ckin1 1 = select ckin2 must be driven high or low. table 3. si5316 pin descriptions (continued) pin # pin name i/o signal level description *note: denotes 3-level input pin with states desi gnated as l (ground), m (vdd/2), and h (vdd).
si5316 rev. 0.4 9 23 22 bwsel1 bwsel0 i 3-level bandwidth select. three level inputs that select the dspll closed loop bandwidth. detailed operations and timing char acteristics for these pins may be found in the any-rate precision clock family reference manual. these pins are both pull-ups and pull-downs and default to m. some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 25 24 frqsel1 frqsel0 i 3-level frequency select. sets the output frequency of the device. when the frequency of ckin1 is not equal to ckin2, the lower frequency input clock must be equal to the output clock frequency. these pins have both weak pull-ups and weak pull-downs and default to m. some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 26 ck1div i 3-level input clock 1 pre-divider select. pre-divider on ckin1. used wit h ck2div to divide input clock frequencies to a common value. l = ckin1 input divider set to 1. m = ckin1 input divider set to 4. h = ckin1 input divider set to 32. this pin has a weak pull-up and weak pull-down and defaults to m. some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 27 ck2div i 3-level input clock 2 pre-divider select. pre-divider on ckin2. used wit h ck1div to divide input clock frequencies to a common value. l = ckin2 input divider set to 1. m = ckin2 input divider set to 4. h = ckin2 input divider set to 32. this pin has a weak pull-up and weak pull-down and defaults to m. some designs may require an external resistor voltage divider when driven by an active device that will tri-state. table 3. si5316 pin descriptions (continued) pin # pin name i/o signal level description *note: denotes 3-level input pin with states desi gnated as l (ground), m (vdd/2), and h (vdd).
si5316 10 rev. 0.4 33 30 sfout0 sfout1 i 3-level signal format select. three level inputs that select the output signal format (common mode voltage and differential swing) for ckout. valid settings include lvpecl, lvds, and cml. also includes selections for cmos mode, tristate mode, and tristate/sleep mode. these pins have both weak pull-ups and weak pull-downs and default to m. some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 34 35 ckout? ckout+ omulti clock output. differential output clock with a frequency selected from a table of val- ues. output signal format is select ed by sfout pins. output is differ- ential for lvpecl, lvds, and cm l compatible modes. for cmos format, both output pins drive id entical single-ended clock outputs. gnd pad gnd gnd supply ground pad. the ground pad must provide a low thermal and electrical impedance to a ground plane. table 3. si5316 pin descriptions (continued) pin # pin name i/o signal level description *note: denotes 3-level input pin with states desi gnated as l (ground), m (vdd/2), and h (vdd). sfout[1:0] signal format hh lvds hm reserved hl cml mh lvpecl mm reserved ml lvds?low swing lh cmos lm disabled ll reserved
si5316 rev. 0.4 11 3. ordering guide ordering part number package r ohs6, pb-free temperature range si5316-c-gm 36-lead 6 x 6 mm qfn yes ?40 to 85 c
si5316 12 rev. 0.4 4. package outline: 36-lead qfn figure 3 illustrates the package details for the si5316. table 4 lis ts the values for the di mensions shown in the illustration. figure 3. 36-pin quad flat no-lead (qfn) table 4. package dimensions symbol millimeters symbol millimeters min nom max min nom max a 0.80 0.85 0.90 l 0.50 0.60 0.70 a1 0.00 0.02 0.05 ??12o b 0.18 0.25 0.30 aaa ? ? 0.10 d 6.00 bsc bbb ? ? 0.10 d2 3.95 4.10 4.25 ccc ? ? 0.08 e 0.50 bsc ddd ? ? 0.10 e 6.00 bsc eee ? ? 0.05 e2 3.95 4.10 4.25 notes: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jede c outline mo-220, variation vjjd. 4. recommended card reflow profile is per the jede c/ipc j-std-020c specif ication for small body components.
si5316 rev. 0.4 13 5. recommended pcb layout figure 4. pcb land pattern diagram
si5316 14 rev. 0.4 table 5. pcb land pattern dimensions dimension min max e 0.50 bsc. e5.42 ref. d5.42 ref. e2 4.00 4.20 d2 4.00 4.20 ge 4.53 ? gd 4.53 ? x ? 0.28 y0.89 ref. ze ? 6.31 zd ? 6.31 notes (general): 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on ipc-sm-782 guidelines. 4. all dimensions shown are at maximum ma terial condition (mmc ). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. notes (solder mask design): 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. notes (stenc il design): 1. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. a 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. notes (card assembly): 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components.
si5316 rev. 0.4 15 d ocument c hange l ist revision 0.23 to 0.24 ? changed lvttl to lvcmos in table 2, ?absolute maximum ratings,? on page 3. ? added figure 1, ?typical phase noise plot,? on page 4. ? showed preferred interface for an external reference clock in figure 2, ?si5316 typical application circuit,? on page 5. ? updated 3. "ordering guide" on page 11. ? added ?5. recommended pcb layout?. revision 0.24 to revision 0.3 ? changed 1.8 v operating range 5%. ? updated table 1 on page 2. ? updated table 2 on page 3. ? updated table 3 on page 7. ? added table under figure 1 on page 4. ? updated 1. "functional description" on page 6. ? clarified 2. "pin descriptions: si5316" on page 7 including pull-up/pull-down. revision 0.3 to revision 0.4 ? updated table 1, ?performance specifications 1 ,? on page 2. ? updated table 3, ?si5316 pin descriptions,? on page 7. ? updated figure 2, ?si5316 typical application circuit,? on page 5. ? updated 1.1. "external reference" on page 6. ? updated 2. "pin descriptions: si5316" on page 7.
si5316 16 rev. 0.4 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: clockinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and 5323 are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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