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| syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 1 product list sm59264c25, 25mhz 128kb internal flash mcu SM59264C40, 40mhz 128kb internal flash mcu description the sm59264 series product is an 8-bit single chip micro controller with 128kb on-chip flash which including 64kb program flas h & 64kb data flash and 1k byte ram embedded. it has in-system programming (isp) function a nd is a derivative of the 8052 micro controller family. it has twsi interface which is compatible with standard vesa ddc/ci. it has 4-channel spwm build-in. user can access on-chip expanded ram with easier and faster way by its ?bank mapping direct addressing mode? scheme. with its hardware features and powerf ul instruction set, it?s straight forward to make it a versatile and cost effective controller for those applications which demand up to 32 i/o pins for pdip package or up to 36 i/o pins for plcc/qfp package, or applic ations which need up to 64k byte flash memory for program and/or for data. to program the on-chip flash memory, a commercial writer is available to do it in parallel programming method. the on-chip flash memory can be programmed in either parallel or serial interface with its isp feature. ordering information yymmv sm59264ihhkl yy: year, ww: month v: version identifier{ , a, b,?} i: process identif ier {l=3.0v~3.6v,c=4.5v~ 5.5v} hh: working clock in mhz {25, 40} k: package type postfix {as below table} l:pb free identifier {no text is non-pb free p is pb free} postfix package pin / pad configuration dimension p 40l pdip page 2 page 31 j 44l plcc page 2 page 32 q 44l qfp page 2 page 33 features z working voltage:4.5v through 5.5v z general 8052 family compatible z 12 clocks per machine cycle z 64k byte on chip program flash with in-system programming(isp) capability z 64k byte on-chip data flash with isp capability z twsi(two wire serial bus) interface compliant with vesa ddc 2b/2bi/2b+ standard z 1024 bytes on-chip ram z three 16 bit timers/counters z one watch dog timer z four 8-bit i/o ports for pdip package z four 8-bit i/o ports + one 4-bit i/o ports for plcc or qfp package z full duplex serial channel z bit operation instruction z industrial level z 8-bit unsigned division z 8-bit unsigned multiply z bcd arithmetic z direct addressing z indirect addressing z nested interrupt z two priority level interrupt z a serial i/o port z power save modes: idle mode and power down mode z code protection function z low emi (inhibit ale) z reset with address $000 0 blank initiate isp service program z isp service program space configurable in n*512 byte (n=0 to 8) size z 4 channel spwm function taiwan 6f, no.10-2 li- hsin 1st road , science-based industrial park, hsinchu, taiwan 30078 tel: 886-3-567-1820 886-3-567-1880 fax: 886-3-567-1891 886-3-567-1894
syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 2 pin configuration syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 3 block diagram syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 4 pin description 40l pdip pin# 44l qfp pin# 44l plcc pin# symbol active i/o names 1 40 2 p1.0/t2 i/o bit 0 of port 1 & timer 2 clock out 2 41 3 p1.1/t2ex i/o bit 1 of port 1 & timer 2 control 3 42 4 p1.2 i/o bit 2 of port 1 4 43 5 p1.3/spwm0 i/o bit 3 of port 1 & spwm channel 0 5 44 6 p1.4/spwm1 i/o bit 4 of port 1 & spwm channel 1 6 1 7 p1.5/spwm2 i/o bit 5 of port 1 & spwm channel 2 7 2 8 p1.6/scl i/o bit 6 of port 1 & twsi bus clock 8 3 9 p1.7/sda i/o bit 7 of port 1 & twsi bus data 9 4 10 res h i reset 10 5 11 p3.0/rxd i/o bit 0 of port 3 & receiver data 11 7 13 p3.1/txd i/o bit 1 of port 3 & transmit data 12 8 14 p3.2/#int0 l/- i/o bit 2 of port 3 & low true interrupt 0 13 9 15 p3.3/#int1 l/- i/o bit 3 of port 3 & low true interrupt 1 14 10 16 p3.4/t0 i/o bit 4 of port 3 & timer 0 15 11 17 p3.5/t1 i/o bit 5 of port 3 & timer 1 16 12 18 p3.6/#wr i/o bit 6 of port 3 & ext. memory write 17 13 19 p3.7/#rd i/o bit 7 of port 3 & ext. mem. read 18 14 20 xtal2 o crystal out 19 15 21 xtal1 i crystal in 20 16 22 vss sink voltage, ground 21 18 24 p2.0/a8 i/o bit 0 of port 2 & bit 8 of ext. memory address 22 19 25 p2.1/a9 i/o bit 1 of port 2 & bit 9 of ext. memory address 23 20 26 p2.2/a10 i/o bit 2 of port 2 & bit 10 of ext. memory address 24 21 27 p2.3/a11 i/o bit 3 of port 2 & bit 11 of ext. memory address 25 22 28 p2.4/a12 i/o bit 4 of port 2 & bit 12 of ext. memory address 26 23 29 p2.5/a13 i/o bit 5 of port 2 & bit 13 of ext. memory address 27 24 30 p2.6/a14 i/o bit 6 of port 2 & bit 14 of ext. memory address 28 25 31 p2.7/a15 i/o bit 7 of port 2 & bit 15 of ext. memory address 29 26 32 #psen o program storage enable 30 27 33 ale o address latch enable 31 29 35 #ea l i external access 32 30 36 p0.7/ad7 i/o bit 7 of port 0 & data/address bit 7 of ext. memory 33 31 37 p0.6/ad6 i/o bit 6 of port 0 & data/address bit 6 of ext. memory 34 32 38 p0.5/ad5 i/o bit 5 of port 0 & data/address bit 5 of ext. memory 35 33 39 p0.4/ad4 i/o bit 4 of port 0 & data/address bit 4 of ext. memory 36 34 40 p0.3/ad3 i/o bit 3 of port 0 & data/address bit 3 of ext. memory 37 35 41 p0.2/ad2 i/o bit 2 of port 0 & data/address bit 2 of ext. memory 38 36 42 p0.1/ad1 i/o bit 1 of port 0 & data/address bit 1 of ext. memory 39 37 43 p0.0/ad0 i/o bit 0 of port 0 & data/address bit 0 of ext. memory 40 38 44 vdd drive voltage, +5 vcc 17 23 p4.0 i/o bit 0 of port 4 28 34 p4.1 i/o bit 1 of port 4 39 1 p4.2 i/o bit 2 of port 4 6 12 p4.3 i/o bit 3 of port 4 syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 5 special function register (sfr) the address $80 to $ff can be access ed by direct addressing mode only. address $80 to $ff is sfr area. the following table lists the sfrs which are identical to general 8052, as well as sm59264 extension sfrs. special function register (sfr) memory map $f8 $ff $f0 b ispfah ispfal ispfd ispc $f7 $e8 $ef $e0 acc $e7 $d8 p4 $df $d0 psw $d7 $c8 t2con t2mod rcap2l rcap2h tl2 th2 $cf $c0 twsis twsia twsic1 twsic2 twsitxd twsirxd $c7 $b8 ip ip1 sconf $bf $b0 p3 $b7 $a8 ie ie1 ifr $af $a0 p2 spwmc spwmd0 spwmd1 spwmd2 spwmd3 $a7 $98 scon sbuf p1con wdtc $9f $90 p1 wdtkey $97 $88 tcon tmod tl0 tl1 th0 th1 $8f $80 p0 sp dpl dph rcon pcon $87 note: the text of sfrs with bold type characters are extension sp ecial function registers for sm59264 addr sfr reset 7 6 5 4 3 2 1 0 85h rcon 00h rams7 rams6 rams5 rams4 rams3 rams2 rams1 rams0 97h wdtkey 00h wdtkey7 wdtkey6 wdtkey5 wdt key4 wdtkey3 wdtkey2 wdtkey1 wdtkey0 9bh p1con **0000** twsisdae twsiscle spw me3 spwme2 spwme1 spwme0 9fh wdtc 0*0**000 wdte clear ps2 ps1 ps0 a3h spwmc ******00 spfs1 spfs0 a4h spwmd0 00h spwmd04 spwmd03 spwmd02 spwmd01 spwmd00 brm02 brm01 brm00 a5h spwmd1 00h spwmd14 spwmd13 spwmd12 spwmd11 spwmd10 brm12 brm11 brm10 a6h spwmd2 00h spwmd24 spwmd23 spwmd22 spwmd21 spwmd20 brm22 brm21 brm20 a7h spwmd3 00h spwmd34 spwmd33 spwmd32 spwmd31 spwmd30 brm32 brm31 brm30 bfh sconf 0***0000 wdr dfen ispe ome alei c0h twsis 0000*100 rxif txif tfif nakif rxak master txak c1h twsia 10100000 twsia7 twsia6 twsia5 twsia4 twsia3 twsia2 twsia1 ext addr c2h twsic1 0***0001 twsie bus busy twsifs2 twsifs1 twsifs0 c3h twsic2 00h match srw restart mrw c4h twsitxd ffh twsitxd7 twsitxd6 twsitxd5 twsitx d4 twsitxd3 twsitxd2 twsitxd1 twsitxd0 syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 6 c5h twsirxd 00h twsirxd7 twsirxd6 tw sirxd5 twsirxd4 twsirxd3 tw sirxd2 twsirxd1 twsirxd0 a9h ie1 00 etwsi aah ifr 00 twsif bah ip1 00 ptwsi c8h t2con 00h tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 c9h t2mod ******00 * * * * * * t2oe dcen d8h p4 ****1111 p4.3 p4.2 p4.1 p4.0 f4h ispfah 00h fa15 fa14 fa13 fa12 fa11 fa10 fa9 fa8 f5h ispfal 00h fa7 fa6 fa5 fa4 fa3 fa2 fa1 fa0 f6h ispfd 00h fd7 fd6 fd5 fd4 fd3 fd2 fd1 fd0 f7h ispc 0*0***00 start fau0 f1 f0 extension function description 1. memory structure the sm59264 is the general 8052 hardware core to int egrate the expanded 768 byte dat a ram, 64kb flash program memory with isp function module and 64kb data flash as a sing le chip micro controller. its memory structure follows general 8052 structure plus sm59264 propr ietary external ram structure. 1.1 program memory the sm59264 has 64k byte on-chip flash memory which used as general program memory, on which include up to 4k byte specific isp service program me mory space. the address range for the 64k byte is $0000 to $ffff. the address range for the isp service program is $f000 to $ffff. the i sp service program size can be partitioned as n blocks of 512 byte (n=0 to 8). when n=0 means no isp service prog ram space available, total 64k byte memory used as program memory. when n=1 means memory address $fe00 to $ffff reserved for isp service program. when n=2 means memory address $fc00 to ffff re served for isp service program,...etc . value n can be set and programmed into sm59264 by writer. 1.1.1 program code security movc instruction executed from external program memory space will not be ab le to fetch internal codes from on chip program memory after the chip is protected on the writer. syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 7 note: the single flash block address structure for doing the is p function to the on-chip data flash as well as program rom flash. 1.2 data memory the sm59264 has 1k bytes on-chip ram, 256 bytes of it are the same as general 8052 internal memory structure while the expanded 768 bytes on-chip ram can be accessed by external memory addressing method (by instruction movx), or by ?bank mapping direct addressing mode? as described in page 9. the sm59264 also has 64k bytes data flash embedded in. the contents of data flash can be erased or programmed by software control and can be read by movx instruction. user can use movx instruction to access in ternal ram, internal data flash or external memory by setting ome and dfen. the different setting of ome and dfen will map to different memory block. syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 8 dfen ome address of movx below 768 address of movx over 768 0 0 external memory external memory 0 1 internal ram external memory 1 0 internal data flash internal data flash 1 1 internal ram internal data flash syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 9 note: external ram address structure for reading the on-chip data flash. 1.2.1 data memory - lowe r 128 byte ($00 to $7f) data memory $00 to $ff is the same as 8052. the address $00 to $7f can be accessed by direct and indirect addressing modes. address $00 to $1f is register area. address $20 to $2f is memory bit area. address $30 to $7f is for general memory area. 1.2.2 data memory - higher 128 byte ($80 to $ff) the address $80 to $ff can be accessed by indirect addressing mode or by bank mapping direct addressing mode. address $80 to $ff is data area. 1.3 data flash - ($0000 to $ffff) sm59264 has 64k byte on-chip data flash embedded. the 64 kb on-chip data flash can be read by direct external addressing mode (by movx instruction) which means user does not need to care about 17th flash address bit (fa16). to read 64kb on-chip data flash is similar to read 64kb exte rnal ram. however, to write (program) data flash is much different from to read data flash. user need to use sync mos proprietary isp function, such as byte program/chip erase/page erase/protect, to the data flash. to do isp function to data flash need to set fau0 bit of ispc ($f7) at first. user has to recognize 64k program rom flash and 64kb data flash as combined one single 128kb flash area for isp function. 64k byte data flash resides on top of the 64k byte program rom flas h. please see isp function description on page 14 for detail. syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 10 read data flash: using direct external addressing mode (by instruction movx). reading on-chip data flash will be the same as reading external ram with movx instruction. for example, movx a, @dptr or movx a, @ri ; i=0,1 instruction with 16-bit addressing space. write data flash: using isp ?byte program? f unction will have to set the fau0 bit at first. erase data flash: including isp ?chip erase? function and ?page erase? function. when using ?chip erase? function, it will erase all the 64k byte data flash plus 64k byte program rom flash except the isp service program space if lock bit ?n? been configured. chip protect flash: using isp ?chip protect? function will protect the 64k byte data flash plus 64k byte program rom flash from read out. once flash been protected, the content read will be all ?00?. for ?byte program? and ?page erase? flash-address-dependent isp functions, user need to specify the fau0 bit (=fa16) of ispc ($f7) at first for doing with data flash space. t he 64k data flash also can be programmed or erased on writer. 1.3.1 second data pointer register - rcon ( $85) and movx @ri, i=1,2 with read function using rcon register with movx @ri, i=0,1 instruction ena bles sm59264 has second data pointer register (dptr) with read function only. the content of rcon register det ermines high byte address of 64kb data flash while content of movx@ri instruction determines low byte address. th is feature similar to dph and dpl register of movx @ dptr instruction but with read function only. using movx @r i instruction to write data to the data flash will have no effect. system control register (sconf, $bf) bit-7 bit-0 wdr unused unused unus ed dfen ispe ome alei read / write: r/w - - - r/w r/w r/w r/w reset value: 0 * * * 0 0 0 0 wdr: watch dog timer reset. when system reset by watch dog timer overflow, wdr will be set to 1, the bit 7 (wdr) of sconf is watch dog timer reset bit. it will be set to 1 when reset signal generated by wdt overflow. user should check wdr bit whenever un-p redicted reset happened. dfen: 64k data flash enable bit. the defa ult setting of dfen bit is 0 (disable). ispe: isp enable bit ome: 768 bytes on-chip ram enable bit, the bit 1 (ome) of sconf can enable or disable the on-chip expanded 768 byte ram. the default setting of ome bit is 0 (disable). alei: ale output inhibit bit, to reduce emi, setting bit 0 (alei) of sconf can inhibit the clock signal in fosc/6hz output to the ale pin. syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 11 1.4 i/o pin configuration the ports 1, 2 and 3 of standard 8051 have internal pull- up resistor, and port 0 has open-drain outputs. each i/o pin can be used independently as an input or an output. for i/o ports to be used as an input pin, the port bit latch must contain a ?1? which turns off the output driver fet. then for port 1, 2 and 3 port pin is pulled high by a weak internal pull-up, and can be pulled low by an external source. the po rt 0 has open-drain outputs which means its pull-ups are not active during normal port operation. writing ?1? to the port 0 bit latch w ill causing bit floating so that it can be used a s a high-impedance input. the port 4 used as gpio will has the sa me function as port 1, 2 and 3. syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 12 2. port 4 for plcc or qfp package: the bit addressable port 4 is available with plcc or qf p package. the port 4 has only 4 pins and its port address is located at 0d8h. the function of port 4 is the sa me as the function of port 1, port 2 and port 3. port4 (p4, $d8) bit-7 bit-0 unused unused unused unused p4.3 p4.2 p4.1 p4.0 read / write: - - - - r/w r/w r/w r/w reset value: * * * * 1 1 1 1 the bit 3, bit 2, bit 1, bit 0 output the setting to pin p4.3, p4.2, p4.1, p4.0 respectively. 3. in-system programming (isp) function the sm59264 can generate flash control signal by internal hardware circuit. user utilize flash control register, flash address register and flash data register to perform the in-system progr amming (isp) function without removing the sm59264 from the system. the sm59264 provides internal flash control signal wh ich can do flash program/chip erase/page erase/protect functions. user need to design and use any kind of inte rface which sm59264 can input dat a. user then utilize isp service program to perform the flash program /chip erase/page erase/protect functions. 3.1 isp service program the isp service program is a user developed firmware progra m which resides in the isp se rvice program space. after user developed the isp service program, user then determi ne the size of the isp service program. user need to program the isp service program in the sm59264 for the isp purpose. the isp service program were developed by user so that it should includes any features which relates to the flash memory programming function as well as communication protocol between sm59264 and host device which output data to the sm59264. for example, if user utilize uart interface to receive/transmit data between sm59264 and host device, the isp service program should include baud rate, c hecksum or parity check or any error-checking mechanism to avoid data transmission error. the isp service program can be initiated under sm59264 active or idle mode. it can not be initiated under power down mode. 3.2 lock bit (n) the lock bit n has two functions: one is for service program si ze configuration and the other is to lock the isp service program space from flash erase function. the isp service program space address range from $f000 to $ffff. it can be divided as blocks of n*512 byte. (n=0 to 8). when n=0 means no isp function, all of 64k byte flash memory can be used as program memory. when n=1 means isp service program occupies 512 byte while the re st of 63.5k byte flash memory can be used as program memory. the maximum isp service progra m allowed is 4k byte for n=8. unde r such configuration, the usable program memory space is 60k byte. syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 13 after n determined, sm59264 will reserve the isp service program space downwa rd from the top of the program address $ffff. the start addres s of the isp service program located at $fx00 while x is an even number, depending on the lock bit n. please see page 7 program memory diagr am for this isp service program space structure. the lock bit n function is different from the flash protect function. the chip er ase function can erase all of the flash memory space including 64kb program flash & 64kb data flash, except for the locked isp service program space. if the flash not been protected, the content of flash program still can be read. if t he flash been protected, the overall content of flash program memory space includi ng isp service program space can not be read. 3.3 program the isp service program after lock bit n is set and isp service program been progra mmed, the isp service program memory will be protected (locked) automatically. the lock bit n has its own progra m/erase timing. it is different from the flash memory program/erase timing so the locked isp service program ca n not be erased by flash erase function. if user need to erase the locked isp service program, he can do it by writ er only. user can not change isp service program when sm59264 was in system. 3.4 initiate isp service program to initiate the isp service program is to load the progra m counter (pc) with start addr ess of isp service program and execute it. there are three ways to do so: (1) blank reset. hardware reset with first flash address blank ($0000=#ffh) will load the pc with start address of isp service program. (2) execute ?jump? instruction can load the star t address of the isp service program to pc. (3) enter?s isp service program by hardware setting. us er can force sm59264 enter isp service program by setting p2.6, p2.7 ?low or p4.3 ?low? during hardware reset period. in application system design, user should take care of the setting of p2.6, p2.7 and p4.3 at reset period to prevent sm59264 from entering isp service program. enters isp service program by hardware setting: syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 14 user can initiate general 8052 uart function to initiate the isp service program. after isp service program executed, user need to reset the sm59264, either by hardware reset or by wdt, or jump to the address $0000 to re-start the firmware program. 3.5 isp registers - system control register (sconf, $bf) bit-7 bit-0 wdte unused unused un used dfen ispe ome alei read / write: r/w - - - r/w r/w r/w r/w reset value: 0 * * * 0 0 0 0 the bit 2 (ispe) of sconf is isp enable bit. user can enable ov erall isp function by setting ispe bit to 1, setting ispe to 0 will disable overall isp function. the function of ispe behaves like a security key. user can di sable overall isp function to prevent software program be erased accidentally. 3.6 isp registers: ispfah, ispf al, ispfd and ispc registers the ispfah & ispfal provide the 16-bit flash memory addr ess for isp function. the flash memory address should not include the isp service program space address. if t he flash memory address indicated by ispfah & ispfal registers overlay with the isp servic e program space address, the flash prog ram/page erase of isp function executed thereafter will have no effect. when performing byte program isp function, the content of ispfd register will be programmed to the flash address which indicated by ispfah and ispfal registers. isp registers- flash address- high register (ispfah, $f4) bit-7 bit-0 fa15 fa14 fa13 fa12 fa11 fa10 fa9 fa8 read / write: r/w r/w r/ w r/w r/w r/w r/w r/w reset value: 0 0 0 0 0 0 0 0 fa15 ~ fa8: flash address-high for isp function isp registers - flash address-low register (ispfal, $f5) bit-7 bit-0 fa7 fa6 fa5 fa4 fa3 fa2 fa1 fa0 read / write: r/w r/w r/ w r/w r/w r/w r/w r/w reset value: 0 0 0 0 0 0 0 0 fa7 ~ fa0: flash address-low for isp function the ispfah & ispfal provide the 16-bit flash memory add ress for isp function. the flash memory address should not include the isp service program space address. if the flash memory address indicated by ispfah & ispfal registers overlay with the isp servic e program space address, the flash prog ram/page erase of isp function executed thereafter will have no effect. syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 15 isp registers - flash data register (ispfd, $f6) bit-7 bit-0 fd7 fd6 fd5 fd4 fd3 fd2 fd1 fd0 read / write: r/w r/w r/ w r/w r/w r/w r/w r/w reset value: 0 0 0 0 0 0 0 0 fd7 ~fd0 : flash data for isp function the ispfd provide the 8-bit data for isp function isp registers -flash cont rol register (ispc, $f7) bit-7 bit-0 start unused fauo unused unused unused ispf1 ispf0 read / write: r/w - r/w - - - r/w r/w reset value: 0 * 0 * * * 0 0 ispf[1:0] : isp function select bit ispf [1:0] isp function 00 byte program 01 chip protect 10 page erase (512byte) 11 chip erase start : isp function start bit = 1 : start isp function which indicated by bit 1, bit 0 (ispf1, ispf0) = 0 : no operation fau0 : 64k program flash or 64k data flash select bit = 1 : selected 64k data flash = 0 : selected 64k program flash note: the start bit is read-only by default, software must write three specific values 55h, aah and 55h sequentially to the ispfd register to enable the start bit write attribute. that is : mov ispfd, #55h mov ispfd, #0aah mov ispfd, #55h any attempt to set start bit will not be allowed without the procedure above. after start bit set to 1 then the sm59264 hardware circuit will latch flash address and data bus and hold the program counter until the start bit reset to 0 when isp function fi nished. the program counter (pc) will point to next instruction after start bit reset to 0. user does not need to check start bit status by software method. syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 16 to perform byte program/page erase isp function, user need to specify flash address at first. when performing page erase function, sm59264 will erase entire page which flash ad dress indicated by ispfah & ispfal registers located within the page. e.g. flash address: $xymn page erase function will erase from $xy00 to $x(y+1)ff (y: even number), or page erase function will erase from $x(y-1)00 to $xyff (y: odd number) to perform the chip erase isp function, sm59264 will er ase all the flash program memory and data flash memory except the isp service program space if lock bit n been configured. also, sm59264 will un-protect the flash memory automatically. to perform chip protect isp func tion, all the flash memory will be read #00h. e.g. isp service program to do the byte prog ram -to program #22h to the address $1005h mov ispfd, #55h mov ispfd, #0aah mov ispfd, #55h mov 0bfh, #04h ; enable sm59264 isp function mov 0f4h, #10h ; set flash address-high, 10h mov 0f5h, #05h ; set flash address-low, 05h mov 0f6h, #22h ; set flash data to be programmed, data = 22h mov 0f7h, #80h ; start to program #22h to the flash address $1005h ; after byte program finished, start bit of fcr will be reset to 0 automatically ; program counter then point to the next instruction 4. watch dog timer the watch dog timer (wdt) is a 16-bit free-running counter t hat generate reset signal if the counter overflows. the wdt is useful for systems which are su sceptible to noise, power glitches, or electronics discharge which causing software dead loop or runaway. the wdt function can help user software recover from abnormal software condition. the wdt is different from timer0, timer1 and timer2 of general 8052. to prevent a wdt reset can be done by software periodically clearing the wdt counter. user should check wdr bit of sconf register whenever un-predicted reset happened the purpose of the secure procedure is to prevent the wdtc value from being changed when system runaway. there is a 250khz rc oscillator embedded in chip. set wd te = ?1? will enable the rc oscillator and the frequency is independent to the system frequency. to enable the wdt is done by setting 1 to the bit 7 (wdte) of wdtc. after wdte set to 1, the 16-bit counter starts to count with the rc oscillator. it will generate a reset signal when overflows. the wdte bit will be cleared to 0 automatically when sm59264 been reset, either hardware reset or wdt reset. to reset the wdt is done by setting 1 to the clear bit of wdtc before the counter ov erflow. this will clear the content of the 16-bit counter and let the count er re-start to count from the beginning. syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 17 4.1 watch dog timer registers: watch dog timer registers - wdt control register (wdtc, $9f) bit-7 bit-0 wdte reserve clear unused unused ps2 ps1 ps0 read / write: r/w - r/w - - r/w r/w r/w reset value: 0 * 0 * * 0 0 0 wdte : watch dog timer enable bit clear : watch dog timer reset bit ps[2:0] : overflow period select bits ps [2:0] overflow period (ms) 000 2.048 001 4.096 010 8.192 011 16.384 100 32.768 101 65.536 110 131.072 111 262.144 watch dog key register - (wdtkey, $97h) bit-7 bit-0 wdt key7 wdt key6 wdt key5 wdt key4 wdt key3 wdt key2 wdt key1 wdt key0 read / write: w w w w w w w w reset value: 0 0 0 0 0 0 0 0 by default, the wdtc is read only. user need to write values 1eh, e1h sequentia lly to the wdtkey($9 7h) register to enable the wdtc write attribute, that is mov wdtkey, # 1eh mov wdtkey, # 0e1h when wdtc is set, user n eed to write another values e1h, 1eh sequentially to the wdtkey($97h) register to disable the wdtc write attribute, that is mov wdtkey, # 0e1h mov wdtkey, # 1eh syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 18 watch dog timer register - system control register (sconf, $bf) bit-7 bit-0 wdr unused unused unus ed dfen ispe ome alei read / write: r/w - - - r/w r/w r/w r/w reset value: 0 * * * 0 0 0 0 the bit 7 (wdr) of sconf is watch dog timer reset bit. it will be set to 1 when reset signal generated by wdt overflow. user should check wdr bit whenever un-predicted reset happened 5. reduce emi function the sm59264 allows user to reduce the emi emission by se tting 1 to the bit 0 (alei) of sconf register. this function will inhibit the clock signal in fosc/6hz output to the ale pin. 6. specific pulse widt h modulation (spwm) the specific pulse width modulation (spwm) module c ontains 1 kind of pwm sub module: spwm (specific pwm). spwm has five 8-bit channels. 6.1 spwm function description: the 8-bit spwm channel is composed of an 8-bit register which contains a 5-bit spwm in msb portion and a 3-bit binary rate multiplier (brm) in lsb portion. the value prog rammed in the 5-bit spwm port ion will determine the pulse length of the output. the 3-bit brm portion will generate and insert certain narrow pulses among an 8-spwm-cycle frame. the number of pulses generated is equal to the num ber programmed in the 3-bit brm portion. the usage of the brm is to generate equivalent 8-bit resolution spwm type dac with reasonably high repetition rate through 5-bit spwm clock speed. the spfs[1:0] settings of spwmc ($ a3) register are dividend of fosc to be spwm clock, fosc/2^(spfs[1:0]+1). the spwm output cycle frame repetiti on rate (frequency) equals (spwm clock)/32 which is [fosc/2^(spfs[1:0]+1)]/32. 6.2 spwm registers - p1co n, spwmc, spwmd[3:0] spwm registers - port1 configur ation register (p1con, $9b) bit-7 bit-0 twsidae twsicle spwme3 spwme2 spwme1 spwme0 unused unused read / write: r/w r/w r/w r/w r/w r/w - - reset value: 0 0 0 0 0 0 * * twsidae: when the bit set to one ,the co rresponding twsida pin is active as twsida function. when the bit reset to zero, the corresponding twsida pin is active as i/o pin. four bits are cleared upon reset. twsicle: when the bit set to one ,the co rresponding twsicle pin is active as twsicle function. when the bit reset to zero, the corresponding twsicle pin is active as i/o pin. four bits are cleared upon reset. spwme[3:0]: when the bit set to one, the corresponding spwm pin is active as spwm function. when the bit reset to zero, the corresponding spwm pin is active as i/o pin. four bits are cleared upon reset. syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 19 spwm registers -spwm control register (spwmc, $a3) bit-7 bit-0 unused unused unused unused unused unused spfs1 spfs0 read / write: - - - - - - r/w r/w reset value: * * * * * * 0 0 spfs[1:0] : these two bits is 2?s power paramete r to form a frequency divider for input clock. spfs1 spfs0 divider spwm clock, fo sc=20mhz spwm clock, fosc=24mhz 0 0 2 10mhz 12mhz 0 1 4 5mhz 6mhz 1 0 8 2.5mhz 3mhz 1 1 16 1.25mhz 1.5mhz spwm registers -spwm data register (spwmd[4:0], $ac, $a7 ~$a4) bit-7 bit-0 spwmd [4:0]4 spwmd [4:0]3 spwmd [4:0]2 spwmd [4:0]1 spwmd [4:0]0 brm [2:0]2 brm [2:0]1 brm [2:0]0 read / write: r/w r/w r/ w r/w r/w r/w r/w r/w reset value: 0 0 0 0 0 0 0 0 spwmd[4:0] : content of spwm data register. it deter mines duty cycle of spwm output waveform. brm[2:0] : will insert certain narro w pulses among an 8-spwm-cycle frame n = brm[2:0] number of spwm cycles inserted in an 8-cycle frame 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 example of spwm timing diagram: mov spwmd0 , #83h ; spwmd0[4:0]=10h (=16t high, 16t low), brm[2:0] = 3 mov p1con , #08h ; enable p1.3 as spwm output pin syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 20 (narrow pulse inserted by brm0 [2:0] setting, here brm0[2:0]=3) spwm clock = 1 / t = fosc / 2^(spfs[1:0]+1) the spwm output cycle frame frequency = spw m clock / 32 = [fosc/2^(spfs[1:0]+1)]/32 if user use fosc=20mhz, spfs[1:0] of spwmc=#03h, then spwm clock = 20mhz/2^4 = 20mhz/16 = 1.25mhz spwm output cycle frame frequenc y = (20mhz/2^4)/32=39.1khz syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 21 7. twsi interface (two wire serial interface) the twsi module uses the scl (clock) and the sda (data) line to communicate with external twsi interface. its speed can be selected to 6.25k~400kbps by software setti ng the br[2..0] contrtol bit. the twsi module provided 4 interrupts (rx, tx, nonack, txfail). it will generate and/or detects start, repeated start and stop signals automatically in master mode. the maximum communication length and the number of devic es that can be connected are limited by a maximum bus capacitance of 400pf. 7.1 twsi registers twsi status register (twsis, $c0) bit-7 bit-0 rxif txif tfif nakif - rxak master txak read / write: note1 note1 note1 note1 note2 note3 note3 reset value: 0 0 0 0 unused 1 0 0 note1:read and writer?0? only note2:read only note3:read and writer rxif: the data receive interrupt flag (rxif) is set afte r the twsirdb (twsi receive data buffer) is loaded with a newly receive data. once the irdb is loaded with rece ived data, no more received data can be loaded to the twsirdb register again. txif: the data transmit interrupt flag is set when the data of the twsitdb register is downloaded to the shift register or master transmit mode the iadr is dow nloaded to the shift register. it is software?s responsibility to fill the twsitdb register with new data when this bit is set. this bit is cleared by writing zero to it, write data to twsitdb or when reset. tfif: the transmit fail interrupt flag is set when the data transmit is fail, which as set master bit when the bb has been set by detecting the start condition on the lines or when the module is transmitting a one to sda line but detected a zero from sda line in master mode, which is also called arbitration loss. this bit is cleared by writing zero to it or by reset. nakif: the nonacknowledge interrupt flag is only set in the master transmit mode when there is no acknowledge bi detected after one byte data or calling address is transferred. th is bit is cleared by writing zero to it or by reset. rxak: if the received acknowledge bit (r xak) is low, it indicates an acknow ledge signal has been received after the completion of 8 data bits transmission on the bus. if r xak is high, it indicates no acknowledge signal has been detected at the 9th clock. then the module will release t he sda line for the master to generate stop or repeated start condition. it is set upon reset. syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 22 master: if set the master bit, the module will generate a star t condition to the sda and scl lines and send out the calling address which is stored in the iadr register. but if the tfif flag is set when transmit fail occurs on the lines, the module will discard the master mode by cl earing the master bit and release both sda and scl lines immediately. this bit can also be cleared by writ ing zero to it or when the nakif is set. when the master bit is cleared either by set nakif or software the module will generate a stop condition to the lines after the current byte transmission is done, and ignore the twsitdb data when next twsi transmit cycle if this data had not been transmit out. reset clears this bit. txak: the bit (txak) control the acknowledge transmit in receive mode, if it is cleared, a low (ack) will be generated at the 9th clock a fter receiving 8 bits data. when txak is set, a high (noack) will be generated at the 9th clock after receiving 8 bits data. reset clears this bit. twsi address register (twsia, $c1) bit-7 bit-0 read: write: twsia.7 twsia.6 twsia.5 twsia.4 twsia.3 twsia.2 twsia.1 extaddr reset value: 1 0 1 0 0 0 0 0 twsia[7:1] : these 7 bits can be the chip address in sl ave mode or the calling address when in master mode. this register is set as $a0 upon reset. extaddr : the extad bit is set to expand the chip addr ess of this module. when it is one, the module will acknowledge the general call address $00 and the addr ess comparison circuit will only compare the 4 msb bits in the ladr register. when it is zero, the module will only acknowledge to the specific address which is stored in the iadr r egister. it is zero after reset. twsi control register (twsic1, $c2) bit-7 bit-0 read: write: twsie - - - bb twsifs2 twsifs1 twsifs0 reset value: 0 0 0 0 0 0 0 1 twsie: if this twsi module enable bit (ie1) is set, the tw si module is enable. if the ie1 is clear, the interface is disable and all flags will restore its reset default states. reset clears this bit. bb : the bus busy flag is set after a start condition is detec ted, and is reset when a stop condition is detected. reset clears this bit. twsifs[2:0] :the three baud rate select bits will select one of the eight clock rates as the master clock when the module is in master mode. the serial clock frequency is equal to the external clock divided by the certain divider. these bits are cleared upon reset. syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 23 twsifs[2:0] baud rate 0:0:0 unused 0:0:1 400k 0:1:0 200k 0:1:1 100k 1:0:0 50k 1:0:1 25k 1:1:0 12.5k 1:1:1 6.25k note: clock source is fr om external (12m hz). twsi control register 2 (twsic2, $c3 ) bit-7 bit-0 read/write: match note1 srw note1 - - rstart note2 - - mrw note3 reset value: 1 0 0 0 0 0 0 0 note1:read and writer?0? only note2:read only note3:read and writer match : the match flag is set when the first received data (following start signal) in the irdb register which matches with the address or its extended addresses (extad=1) specified in the iadr. srw : the slave rw bit will indicate the data direction of twsi protocol. it is updated after the calling address is received in the slave mode. when it is one, the master will read the data from twsi module, so the module is in transmit mode. when it is zero, the master will send data to the twsi module, the module, the module is in receive mode. the reset clear it. restart: if set this restart bit in master mode (mast er=1), the module will generate a start condition to the sda and scl lines (after current ack bit) and send out the calling address which is stored in the twsiadr register. but if the tfif fl ag is set when transmit fail occurs on the lines, the module will discard the master mode by clearing the master bit and releas e bit sda and scl lines immediately. this bit will clear automatically after generate a start condition to the sda and scl lines. reset clears this bit. mrw : this mrw bit will be transmitted out as the bit 0 of the calling address when t he module sets the mas ter bit to enter the master mode. it will also det ermine the transfer direction of the fo llowing data bytes. when it is one, the module is in master receive mode. when it is zero, t he module is in master transmit mode. reset clears this bit. syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 24 twsi transmit data buffer (twsitxd, $c4) bit-7 bit-0 read: write: twsi txd.7 twsitxd.6 twsitxd.5 twsitxd.4 twsitx d.3 twsitxd.2 twsitxd.1 twsitxd.0 reset value: 0 0 0 0 0 0 0 0 the data written into this register will be automatically dow nloaded to the shift register when the module detects a calling address is matched and the bit 0 of the received data is one (slave transmit mode) or when the data in the shift register has been transmitted with received acknowledge bit (r xak) =0 in transmit mode. so if the program doesn?t write the data into the twsitdb register before the matched calling address is de tected or the shift register has been transmitted out, the module will pull down the scl line (a fter receive ackowledge bit). if write a data to the twsitxd register, then the written data will be downloaded to the shif t register immediately and the module will release the scl line, and the txif flag is set to generate another interrupt r equest for next data. so the s/w may need to write the next data to the twsitxd register and for the auto downloading of data to the sh ift register after the data in the shift register is transmitted over again with rxak=0. if the module receiver non-ackno wledge (rxak=1), the module will release the sda line for master to generate stop or repeated start conditions. twsi receive data buffer (twsirxd, $c5) bit-7 bit-0 read: twsird.7 twsird.6 twsird.5 twsird.4 tw sird.3 twsird.2 twsird.1 twsird.0 write: reset value: 0 0 0 0 0 0 0 0 the twsi receive data buffer (twsirxd) contains the la st received data when the match flag is one or the calling address from master when the match flag is zero. the twsi rxd register will be updated after a data byte is received and the previous received data had been read out, otherwise the ddc module will pull down to scl line to inhabit the next data transfer. it is a read-only register . the read operation of this register w ill clear the rxif flag. after the rxif flag is cleared, the register can load the received data again and set the rxif flag the venerate interrupt request for reading the newly received data. 7.2 twsi interrupt the twsi module will generate twsi interrupt once hardware circuit detects start signal of twsisda and twsiscl. the twsi interrupt vector locates at $3b. there are three sfrs for configuri ng twsi interrupt: ip1, ie1 and ifr. to use twsi interrupt is the same as to use ot her generic 8052 interrupts. that means using etwsi of ie1 for enable/disable twsi interrupt, using ptwsi for assign tw si interrupt priority. whenev er twsi interrupt occurs, twsiif will be set to 1. after twsi interrupt subrout ine (vector) be en executed, twsiif will be cleared to 0. syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 25 interrupt priority i register (ip1, $b9 ) bit-7 bit-0 read: write: r r r r r r ptwsi r reset value: 0 0 0 0 0 0 0 0 interrupt priority bit ptwsi = 1 assigns high interrupt priority interrupt priority bit ptwsi = 0 assigns low interrupt priority interrupt enable i register (ie1, $a9) bit-7 bit-0 read: write: r r r r r r etwsi r reset value: 0 0 0 0 0 0 0 0 interrupt enable bit etwsi = 1 enables the twsi interrupt interrupt enable bit etwsi = 0 disables the twsi interrupt interrupt flag register (ifr, $aa) bit-7 bit-0 read: write: r r r r r r twsiif r reset value: 0 0 0 0 0 0 0 0 interrupt flag bit twsiif will be set to 1 when twsi interrupt occurs. interrupt flag bit twsiif will be clear to 0 if twsi interrupt subroutine executed. 7.2 program algorithm when the twsi module detects an arbitrat ion loss in master, it will release both sda and scl lines immediately. but if there is no further stop condition detected, the module will be hanged up. syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 26 operating conditions symbol description min. typ. max. unit. remarks ta operating temperature -40 25 85 ambient temperature under bias vcc5 supply voltage 4.5 5.0 5.5 v fosc 40 oscillator frequency 3.0 40 40 mhz for 5v application dc characteristics (ta = -40 degree c to 85 degree c, vcc = 5.5v) symbol parameter valid min. max. unit test conditions vil1 input low voltage port 0,1,2,3,4,#ea -0.5 0.8 v vcc=5v vil2 input low voltage res, xtal1 00.8 v vih1 input high volt age port 0,1,2,3,4,#ea 2.0 vcc+0.5 v vih2 input high voltage res, xtal1 70%vcc vcc+0.5 v vol1 output low voltage port 0, ale, #psen 0.45 v iol=3.2ma vol2 output low vo ltage port 1,2,3,4 0.45 v iol=1.6ma 2.4 v ioh=-800ua voh1 output high voltage port 0 90%vcc v ioh=-80ua 2.4 v ioh=-60ua voh2 output high voltag e port 1,2,3,4,ale,#psen 90%vcc v ioh=-10ua iil logical 0 input current port 1,2,3,4 -75 ua vin=0.45v itl logical transition current port 1,2,3,4 -650 ua vin=2.0v ili input leakage current port 0, #ea 10 ua 0.45v syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 28 isp test conditions (40 mhz, typical operating conditions, valid for sm59264 series) symbol max remark chip erase 3000ms vcc = 5v page erase 10ms ? program 30us ? protect 400us ? application reference valid for sm59264 x'tal 3mhz 6mhz 9mhz 12mhz c1 30 pf 30 pf 30 pf 30 pf c2 30 pf 30 pf 30 pf 30 pf r open open open open x'tal 16mhz 25mhz 33mhz 40mhz c1 30 pf 15 pf 5 pf 2 pf c2 30 pf 15 pf 5 pf 2 pf r open 62k ? 6.8k ? 4.7k ? note: oscillation circuit may differs with different crystal or ceramic resonator in higher oscillation frequency which was due to each crystal or ceramic resonator has its own characteristics. user should check with the crystal or ceramic resonator manufacture for appropriate value of external components. please see sm59264 application note for details . syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 29 data memory read cycle timing program memory read cycle timing syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 30 data memory write cycle timing i/o ports timing syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 31 timing critical, requirement of external clock (vss=0.0v is assumed) tm.i external program memory read cycle tm.ii external data memory read cycle syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 32 tm.iii external data memory write cycle syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 33 pdip 40l (600mil) package informatio n note: 1. refer to jedec std.ms-011(ac). 2. dimension d and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. d and e1 are maximum plastic body size dimension include mold mismatch. 3. dimension b3 does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b3 dimension by more than 0.2mm . dimension in mm dimension in mil symbol min nom max min nom max a1 0.254 10 a2 3.683 3.810 3.937 145 150 155 b 0.356 0.500 0.660 14 20 26 b1 0.356 0.457 0.508 14 18 22 b2 1.016 1.270 1.524 40 50 60 b3 1.016 1.321 1.626 40 52 64 c 0.203 0.254 0.432 8 10 17 c1 0.203 0.254 0.356 8 10 14 d 52.07 52.2 52.32 2050 2055 2060 e 14.99 15.24 15.49 590 600 610 e1 13.69 13.87 13.94 539 546 549 e 2.540 100 eb 15.75 16.26 16.76 620 640 660 l 2.921 3.302 3.683 115 130 145 s 1.727 1.981 2.235 68 78 88 q1 1.651 1.778 1.905 65 70 75 0 10 0 10 syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 34 plcc 44l package informatio n unit symbol inch(ref) mm(base) a 0.180(max) 4.572(max) a1 0.024 0.005 0.52 0.14 a2 0.105 0.005 2.667 0.127 b 0.018 + 0.004 - 0.002 0.457 + 0.102 - 0.051 b1 0.028 + 0.004 - 0.002 0.711 + 0.102 - 0.051 c 0.010(typ) 0.254(typ) d 0.690 0.010 17.526 0.254 d1 0.653 0.003 16.586 0.076 d2 0.610 0.020 15.494 0.508 e 0.690 0.010 17.526 0.254 e1 0.653 0.003 16.586 0.076 e2 0.610 0.010 15.494 0.254 e 0.050(typ) 1.270(typ) y 0.003(max) 0.076(max) 0~5 0~5 syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 35 qfp 44l(10x10x2.0mm) package information note: 1. refer to jedc std.ms-022(ab). 2. dimension e1 do not include mold protrusion. allowable protrusion is 0.25mm per side.e1 are maximum plastic body size dimension include mold mismatch . 3. dimension b does not include dambar protrusion .allowable dambar protrusion shall not cause the lead width to exceed the maximum b3 dimension by more than 0.1 mm. dimension in mm dimension in mil symbol min nom max min nom max a 2.45 964 a1 0.05 0.15 0.25 2.1 6.0 9.6 a2 1.90 2.00 2.10 74.8 78.7 82.7 b 0.29 0.32 0.45 11.4 12.6 17.7 b1 0.29 0.30 0.41 11.4 11.8 16.1 c 0.11 0.17 0.23 4.3 6.7 9.1 c1 0.11 0.15 0.19 4.3 5.9 7.5 e 13.00 13.20 13.40 512 520 528 e1 9.90 10.00 10.10 390 394 398 e 0.800 31.5 l 0.73 0.88 1.03 28.7 34.6 40.6 l1 1.50 1.60 1.70 59.1 63.0 66.9 y 0.076 3 0 7 0 7 syncmos technologies intern ational, inc. sm59264 8-bits micro-controller with 128kb flash & 1kb ram & twsi & spwm embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.1 sm59264 08/2006 36 e mcu writer list company contact info programmer model number advantech 7f, no.98, ming-chung rd., shin-tien city, taipei, taiwan, roc web site: http://www.aec.com.tw tel:02-22182325 fax:02-22182435 e-mail: aecwebmaster@advantech.com.tw lab tool - 48xp (1 * 1) lab tool - 848 (1*8) hi-lo 4f, no. 20, 22, ln, 76, rui guang rd., nei hu, taipei, taiwan, roc. web site: http://www.hilosystems.com.tw tel:02-87923301 fax:02-87923285 e-mail: support@hilosystems.com.tw all - 11 (1*1) gang - 08 (1*8) leap 6th f1-4, lane 609, chunghsin rd., sec. 5, sanchung, taipei hsien, taiwan, roc web site: http://www.leap.com.tw tel:02-29991860 fax:02-29990015 e-mail: service@leap.com.tw leap-48 (1*1) su - 2000 (1*8) xeltek electronic co., ltd 338 hongwu road, nanjing, china 210002 web site: http://www.xeltek-cn.com tel:+86-25-84408399, 84543153-206 e-mail: xelclw@jlonline.com, xelgbw@jlonline.com superpro/2000 (1*1) superpro/280u (1*1) superpro/l+(1*1) |
Price & Availability of SM59264C40
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