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1/13 february 2002 AN1473 application note how to use the write to buffer feature of the m58lw064 family of flash memories introduction the m58lw064, a 64 mbit (4mb x16 or 2mb x32) non-volatile memory, is the first in a new family of leading-edge flash mem- ories from st microelectronics that uses multilevel cell technol- ogy. it can be read, erased and reprogrammed using a single low voltage (2.7v to 3.6v) core supply. two version are avail- able, the m58lw064a with a x16 bus and the m58lw064b with a x16/x32 bus. the memory is offered in various packag- es. the m58lw064a is available in tsop56 (14 x 20 mm) and tbga64 (1mm pitch). the m58lw064b is available in tbga80 (1mm pitch). the device has many advanced features: x16/x32 bus width, synchronous burst read, individual block protection, a one time programmable area and a write to buffer and program command to speed up the programming of the device. this application note explains how to use the write to buffer feature, emphasizing the software design considerations. description the write to buffer and program command is used to program the memory array. the memory is divided into blocks that can be erased independently. when using the write to buffer com- mand it is also useful to think of the memory as divided into buffers and pages, where: n a page is 4 words (or 2 double words), with a22-a3 fixed, and each word within the page is selected using a1 and a2. n a buffer is 4 pages (total of 16 words or 8 double words) with a22-a5 fixed, and each page within the buffer is selected with addresses a3 and a4. the write buffer allows the microprocessor to program from 4 to 16 words (or from 2 to 8 double words) in parallel, both speeding up the programming and freeing up the microproces- sor to perform other work. therefore the minimum buffer size for a program operation is a 4 word (or 2 double word) page. any attempt to program less than 4 words (or 2 double words) inside the page of a previously erased block will result in the correct programming of the word, however all other words in- sidethesamebufferwillbesettoffffh. contents n introduction n description n using the write to buffer and program command n programming time n suspending a write to buffer and program command n status register bits n common flash interface n examples C example 1: programming four words C example 2: programming sixteen words
AN1473 - application note 2/13 any attempt to change the buffer (change one of the addresses a22-a5) within the same write to buffer command will be ignored. only the first a22-a5 given for the first program address will be considered (see example 2). reprogramming once a buffer (1 to 4 pages) has been programmed it cannot be reprogrammed until the block containing that buffer has been erased (regardless of the current data and the data to be programmed). if a program operation is attempted in a buffer which was not previously erased, the operation will abort and the program/erase controller will set the error bits in the status register. when the status register error bits are set under these circumstances they cannot be reset by a clear status register command. in this case they can only be reset by a hardware reset or power-up sequence. no further write opera- tions are possible until the status register has been reset. to avoid the inconvenience of a hardware reset (which is generally not permitted on a board), it is sug- gested to modify the write to buffer algorithm in the software drivers to check if the buffer has been pre- viously erased. a read cycle should be added to check that the content of the buffer is ffffh, followed by a block erase cycle if necessary, before starting the write to buffer sequence. this does not affect the performance of the device as the delay introduced by this check is negligible compared to the program- ming time. refer to figure 1 for the recommended flowchart and appendix a for the recommended c- code. if the application does not require to reprogram the device then the standard flowchart shown in the m58lw064 datasheet can be used. using the write to buffer and program command the write to buffer and program command consists of (n+4) bus cycles, where (n+1) is the number of words to be programmed. the cycles must be asserted according to the timings described in the datasheet. as mentioned in the reprogramming section above, it is recommended to check that the buffer has been pre-erased before issuing the write to buffer and program command. figure 1, write to buffer and pro- gram flowchart, shows the suggested flowchart for using the write to buffer and program command. it includes a read cycle to check if the buffer has been pre-erased and a block erase cycle to erase the block if necessary. once the check has been done four successive steps are required to issue the command. 1. one bus write operation is required to set up the write to buffer and program command. issue the set up command (e8h) with the selected memory block address (ba) where the program operation should occur (any address in the block where the data will be programmed can be used). any bus read oper- ations will start to output the status register after the 1st cycle. bit 7 of the status register can be checked to verify if the program/erase controller (p/e.c) is ready to receive the next cycle (bit7 = 1). 2. use one bus write operation to write the same block address (ba) along with the value n on the data inputs/output, where n+1 is the number of words (x16 bus width) or double words (x32 bus width) to be programmed. 3. use n+1 bus write operations to load the address and data for each word or double word into the write buffer. see the constraints on the address combinations listed below. the addresses must have the same a5-a22. 4. finally, use one bus write operation to issue the final cycle to confirm the command (d0h) and start the program operation.
3/13 AN1473 - application note after the program operation has started the status register can be read by toggling output enable (g )to follow the progress of the operation. when program/erase controller bit 7 of the status register goes to high the operation is finished. invalid address combinations or failing to follow the correct sequence of bus write cycles will set an error in the status register and abort the operation without affecting the data in the memory array. the status register should be cleared before re-issuing the command. if the block being programmed is protected an error will be set in the status register and the operation will abort without affecting the data in the memory array. the block must be unprotected using the blocks unprotect command or by using the blocks temporary unprotect feature of the reset/power-down pin, rp . see datasheet for more details. programming time the equivalent programming time for a number of words n (n= 4 to 16) programmed within the same write to buffer command is: (buffer program time)/n so if you program the whole buffer within the same command you will obtain an equivalent program time per word of (buffer program time)/16. to optimize the programming time using the write to buffer feature the whole buffer should be programmed at once. please refer to the program, erase times and program erase endurance cycles table of the datasheet for the buffer programming time.
AN1473 - application note 4/13 figure 1. write to buffer and program flowchart write to buffer e8h command, block address ai06199 start write buffer data, start address yes x = n end no write n (1) , block address x = 0 write next buffer data, next program address (2) x = x + 1 program buffer to flash confirm d0h read status register no b7 = 1 yes full status register check note 1. n+1 is number of words or double words to be programmed. 2. next program address must have same a5-a22. read buffer to be programmed buffer data = ffffh write 20h write d0h to block address read status register b7 = 1 try again later write to buffer timeout yes yes no no yes no block erase full status register check any errors detected clear status register no yes
5/13 AN1473 - application note suspending a write to buffer and program command the m58lw064 features a program/erase suspend command which can be used to pause a write to buffer and program operation to allow a read operation in another block or pause an erase operation to perform a program or read operation in another block. one bus write cycle is required to issue the program/erase suspend command (b0h, address dont care) and pause the program/erase controller. to resume the operation the erase resume command can be issued (d0h, address dont care). please refer to the datasheet for further details. status register bits the status register provides information on the current or previous program, erase, block protect or blocks unprotect operation. the various bits in the status register convey information and errors on the operation. they are output on dq7-dq0. table 1 provides a summary of the status register bits associated with the write to buffer and program command. program/erase controller status (bit 7). the program/erase controller status bit indicates whether the program/erase controller is active or inactive. when the program/erase controller status bit is low, the program/erase controller is active and all other status register bits are high impedance; when the bit is high, the program/erase controller is inactive, and the operation has ended or is suspended. the con- tents of the entire status register should be checked for errors. program status (bit 4). the program status bit is used to identify a program or block protect failure. when the program status bit is low, the memory has successfully verified that the write buffer has pro- grammed correctly or the block is protected. when the program status bit is high, the program or block protect operation has failed. depending on the cause of the failure other status register bits may also be set to high. n if only the program status bit (bit 4) is set high, v oh , then the program/erase controller has applied the maximum number of pulses to the byte and still failed to verify that the write buffer has programmed correctly or that the block is protected. n if the failure is due to a program or block protect with v pp low, then v pp status bit (bit 3) is also set high. n if the failure is due to a program on a protected block then block protection status bit (bit 1) is also set high. n if the failure is due to a program or erase incorrect command sequence then erase status bit (bit 5) is also set high. v pp status (bit 3). the v pp status bit can be used to identify if a program, erase, block protection or block unprotection operation has been attempted when v pp is low. the v pp pin is only sampled at the beginning of a program or erase operation. when the v pp status bit is low, no program, erase, block protect or blocks unprotect operations have been attempted with v pp low, since the last clear status register command, or hardware reset. when the v pp status bit is high, a program, erase, block protection or block unprotection operation has been attempted with v pp low. program suspend status (bit 2). the program suspend status bit indicates that a program operation has been suspended and is waiting to be resumed. the program suspend status should only be consid- ered valid when the program/erase controller status bit is high. when the program suspend status bit is low, the program/erase controller is active or has completed its operation; when the bit is high, a program/erase suspend command has been issued and the memory is waiting for a program/erase resume command. when a program/erase resume command is issued the program suspend status bit returns low.
AN1473 - application note 6/13 block protection status (bit 1). the block protection status bit can be used to identify if a program or erase operation has tried to modify the contents of a protected block. when the block protection status bit is low, no program or erase operations have been attempted to pro- tected blocks since the last clear status register command or hardware reset; when the block protection status bit is high, a program or erase operation has been attempted on a protected block. once bits 4, 3 and 1 are set high, they can only be reset by a clear status register command or a hard- ware reset. refer to the datasheet for the other bits in the status register. table 1. summary of status register bits associated with write to buffer command common flash interface the m58lw064 supports the common flash interface (cfi). the cfi is a jedec approved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. the cfi contains information on the size of the buffer and information on the typical tim- eout for the write to buffer command. refer to the datasheet for further information. status register bits meaning bit 7=0 the internal p/e.c. is busy all other bits are high impedance bit 7=1 the internal p/e.c. is ready bit 4=1 program error bit4=1 bit1=1 program block protect failure bit4=1 bit3=1 program failure due to v pp error bit 7=1 bit 2=1 program suspended reading possible on another block bit 7=1 bit 5=1 erase suspended programming/reading possible on another block
7/13 AN1473 - application note examples example 1: programming four words table 2, shows the series of bus cycles required to program the data: 0101h (0000000100000001 in bi- nary), 0a0ah (0000101000001010), b1b1h (1011000110110001), cccch (1100110011001100) at the first four addresses of a previously erased device, where the initial status register value is 80h (bit 7 = 1, p/e.c inactive). table 3 shows the results, all data are programmed correctly and no errors are signalled in the status register. the equivalent programming time per word is: (buffer programming time)/4. table 2. example 1, command flow note: x = dont care, sr = 80h = 10000000 i.e. bit 7 = 1, bits6-0 = 0. table 3. example 1, results note: sr = 80h = 10000000 i.e. bit 7 = 1, bits6-0 = 0. cycle no. bus cycle type address data comment 1 write 0000h e8h write to buffer set up command 2 read 0000h status register toggle e to check sr. bit7 must be 1 to proceed 3 write 0000h 3h number of words to be programmed minus one 4 write 0000h 0101h address, content 5 write 0001h 0a0ah address, content 6 write 0002h b1b1h address, content 7 write 0003h cccch address, content 8 write x d0h confirm command 9 read 0000h status register toggle e to check sr. if bit7is 1 the operation is finished 10 write x ffh command to reset the memory to the read array mode 11 write read x x 70h status register read sr to verify if the operation completed successfully (sr=80h) address initial data data to program final data 0000h ffffh 0101h 0101h 0001h 0a0ah 0a0ah 0002h b1b1h b1b1h 0003h cccch cccch status register 80h - 80h
AN1473 - application note 8/13 example 2: programming sixteen words table 4, shows the series of bus cycles required to program the data: 0000h, 0001h, 0002h, , 000fh starting from address 0008h of a previously erased device, where the initial status register value is 80h (bit 7 = 1, p/e.c inactive). table 5 shows the results. at the end of the operation the status register will output 80h, and so it appears as thought the program operation was successful. however this is not en- tirely true as in this case, there is a change of buffer (change of address a5) which is ignored and so ad- dresses 0010h to 0017h remain unchanged (ffffh) while the programmed data from 0008h to 000fh will appear in the first addresses of the buffer. the equivalent programming time per word is: (buffer programming time)/16. table 4. example 3, command flow note: x = dont care, sr = 80h = 10000000 i.e. bit 7 = 1, bits6-0 = 0. cycle no. bus cycle type address data comment 1 write 0000h e8h write to buffer set up command 2 read 0000h status register toggle e to check sr. bit7 must be 1 to proceed 3 write 0000h 3h number of words to be programmed minus one 4 write 0008h 0000h address, content 5 write 0009h 0001h address, content 6 write 000ah 0002h address, content 7 write 000bh 0003h address, content 8 write 000ch 0004h address, content 9 write 000dh 0005h address, content 10 write 000eh 0006h address, content 11 write 000fh 0007h address, content 12 write 0010h 0008h address, content 13 write 0011h 0009h address, content 14 write 0012h 000ah address, content 15 write 0013h 000bh address, content 16 write 0014h 000ch address, content 17 write 0015h 000dh address, content 18 write 0016h 000eh address, content 19 write 0017h 000fh address, content 20 write x d0h confirm command 21 read 0000h status register toggle e to check sr. if bit7is 1 the operation is finished 22 write x ffh command to reset the memory to the read array mode 23 write read x x 70h status register read sr to verify if the operation completed successfully (sr=80h)
9/13 AN1473 - application note table 5. example 3, results note:sr = 80h = 10000000 i.e. bit 7 = 1, bits6-0 = 0. revision history table 6. document revision history address initial data data to program final data 0000h ffffh - 0008h 0001h - 0009h 0002h - 000ah 0003h - 000bh 0004h - 000ch 0005h - 000dh 0006h - 000eh 0007h - 000fh 0008h 0000h 0000h 0009h 0001h 0001h 000ah 0002h 0002h 000bh 0003h 0003h 000ch 0004h 0004h 000dh 0005h 0005h 000eh 0006h 0006h 000fh 0007h 0007h 0010h 0008h ffffh 0011h 0009h ffffh 0012h 000ah ffffh 0013h 000bh ffffh 0014h 000ch ffffh 0015h 000dh ffffh 0016h 000eh ffffh 0017h 000fh ffffh status register 80h - 80h date version revision details 01-feb-2002 -01 first issue
AN1473 - application note 10/13 appendix a. write to buffer and program c-code example below is an example for the function flashprogram, which can be implemented in software, in order to reproduce the flowchart shown in figure 1. /******************************************************************************* function: returntype flashprogram( udword udmode, udword udaddroff, udword udnrofelementsinarray, void *parray ) arguments: udmode changes between programming modes udaddroff is the address offset into the flash to be programmed udnrofelementsinarray holds the number of (double)words in the array. parray is a void pointer to the array with the contents to be programmed. return value: the function returns the following conditions: flash_success successful operation flash_address_invalid program range outside device flash_block_protected block to program is protected flash_double_programm_attempt the area to be programmed contains already programmed (double)words flash_program_failed failure not covered below flash_vpp_invalid vpp is not valid description: this function is used to program an array into the flash. it does not erase the flash first and will fail if the block(s) are not erased first. note that the function always programs all addresses within the same page by issuing a single program command, as is required by the device architecture. once the program command has completed the function checks the status register for errors. any errors are returned without any further attempts to program other addresses of the device. the function returns flash_success when all addresses have successfully been programmed. note: two program modes are available: - udmode = 0, normal programming mode the number of elements (udnumberofelementsinarray) contained in parray are programmed directly to the udaddroff within the flash - udmode > 0, repeated values program mode udmode is now a number of values, which is contained in parray. these numbers are repeatedly programmed according to the area defined by udaddroff and udnumberofelementsinarray. for example: values in parray: 11,3,32 |1 udmode: 3 |1 udaddroff: 100 |100 udnumberofelementsinarray: 7 |7 results in memory: addr:100: content: 11 | 1 addr:101: content: 3 | 1 addr:102: content: 32 | 1 addr:103: content: 11 | 1 addr:104: content: 3 | 1 addr:105: content: 32 | 1 addr:106: content: 11 | 1
11/13 AN1473 - application note pseudo code: step 1: check whether the data to be programmed are are within the flash memory step 1a: check whether the intended location is ready to program step 2: while there is more to be programmed step 3: determine limits of current set of 4/2 pages (word/dword) step 4: program within the next set of 4/2 pages (word/dword) step 5: decision between direct and modulo programming step 6: wait until the program/erase controller is ready step 7: check for any errors step 8: clear status register and return to read array mode step 9: return the error condition *******************************************************************************/ returntype flashprogram(udword udmode, udword udaddroff, udword udnrofelementsin array, void *parray ) { returntype rretval = flash_success; /* return value: initially optimistic */ ucpubustype *ucparraypointer; /* use an ucpubustype to access the array */ ucpubustype start,end, a; /* holds temp variables for step 1a */ udword udlastoff; /* holds the last offset to be programmed */ udword udendset; /* holds the end of the current set of pages */ ucpubustype ucstatus; /* holds the status register reads */ udword udnrofelementstoprg; /* number of words/double-words to be programmmed */ udword udmodulocounter = 0; /* holds counter for repeated programming mode */ /* check whether the data to be programmed are are within the flash memory space*/ udlastoff = udaddroff + udnrofelementsinarray - 1; if( udlastoff >= flash_size ) return flash_address_invalid; /* step 1a: check whether the intended location is ready to program */ start = udaddroff; end = udlastoff; for (a = start; a<=end; a++) { if (~flashread(a) != 0) { /* only words/dwords set to 1 can be programmed */ return flash_double_program_attempt; } /* endif*/ } /* next a */ /* step 2: while there is more to be programmed */ ucparraypointer = (ucpubustype *)parray; while( udaddroff <= udlastoff && rretval == flash_success ) { /* step 3: determine limits of current set of 4/2 pages (word/dword) */ udendset = udaddroff | (flash_write_buffer_size - 1); if( udendset > udlastoff ) udendset = udlastoff; udnrofelementstoprg = udendset - udaddroff + 1; /* number of (double)words to beprogrammed */
AN1473 - application note 12/13 /* step 4: program within the next set of 4/2 pages (word/dword) */ flashwrite( any_addr, cmd(0x0050) ); /* clear status register */ /* note ! csr also clears bit 1 bps as well as bits 3, 4 and 5 */ flashwrite( udaddroff, (ucpubustype)cmd(0x00e8) ); /* program setup */ flashwrite( udaddroff, cmd((ucpubustype)(udnrofelementstoprg - 1)) ); /* number of (double)words */ /* step 5: decision between direct and modulo programming */ if (udmode == 0) { while( udaddroff <= udendset ) flashwrite( udaddroff++, *(ucparraypointer++) ); /* direct value !! program value */ } else { while( udaddroff <= udendset ) flashwrite( udaddroff++, ucparraypointer[(udmodulocounter++) % udmode] ); } /* endif programming mode check */ flashwrite( any_addr, (ucpubustype)cmd(0x00d0) ); /* confirm program */ /* step 6: wait until program/erase controller is ready */ flashtimeout(0); /* initialize timeout counter */ do { ucstatus = flashread(any_addr); if (flashtimeout(5) == flash_operation_timeout) { flashreset(); return flash_operation_timeout; } /* endif */ } while( (ucstatus & cmdd(0x0080)) != cmdd(0x0080) ); /* wait until every action is finished (statusregister bit7 = 1) */ /* step 7: check for any errors */ if( ucstatus & cmdd(0x0008) ) rretval = flash_vpp_invalid; else if( ucstatus & cmdd(0x0002) ) rretval = flash_block_protected; else if( ucstatus & cmdd(0x0020) ) rretval = flash_program_failed; else if( ucstatus & cmdd(0x0010) ) rretval = flash_program_failed; } /* endwhile main program loop */ /* step 8: clear status register and return to read array mode */ flashwrite( any_addr, cmd(0x0050) ); /* clear status register */ /* note ! csr also clears bit 1 bps as well as bits 3, 4 and 5 */ flashreset(); /* read array command */ /* step 9: return the error condition */ return rretval; } /* endfunction flashprogram */
13/13 AN1473 - application note if you have any questions or suggestion concerning the matters raised in this document please send them to the following electronic mail address: ask.memory@st.com (for general enquiries) please remember to include your name, company, location, telephone number and fax number. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada- china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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