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tc59lm814/06cft-50,-55,-60 2002-08-19 1/38 toshiba mos digital integrated circuit silicon monolithic 4,194,304-words 4 banks 16-bits network fcram tm 8,388,608-words 4 banks 8-bits network fcram tm description network fcram tm is double data rate fast cycle random access memory. tc59lm814/06cft are network fcram tm containing 268,435,456 memory cells. tc59lm814cft is organized as 4,194,304-words 4 banks s 16 bits, tc59lm806cft is organized as 8,388,608 words 4 banks 8 bits. tc59lm814/06cft feature a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. tc59lm814/06cft can operate fast core cycle using the fcram tm core architecture compared with regular ddr sdram. tc59lm814/06cft is suitable for network, server and other applications where large memory density and low power consumption are required. the output driver for network fcram tm is capable of high quality fast data transfer under light loading condition. features tc59lm814/06 parameter -50 -55 -60 cl = 3 5.5 ns 6 ns 6.5 ns t ck clock cycle time (min) cl = 4 5 ns 5.5 ns 6 ns t rc random read/write cycle time (min) 25 ns 27.5 ns 30 ns t rac random access time (max) 22 ns 24 ns 26 ns i dd1s operating current (single bank) (max) 190 ma 180 ma 170 ma l dd2p power down current (max) 2 ma 2 ma 2 ma l dd6 self-refresh current (max) 3 ma 3 ma 3 ma ? fully synchronous operation ? double data rate (ddr) data input/output are synchronized with both edges of dqs. ? differential clock (clk and clk ) inputs cs , fn and all address input signals are sampled on the positive edge of clk. output data (dqs and dqs) is aligned to the crossings of clk and clk . ? fast clock cycle time of 5 ns minimum clock: 200 mhz maximum data: 400 mbps/pin maximum ? quad independent banks operation ? fast cycle and short latency ? bidirectional data strobe signal ? distributed auto-refresh cycle in 7.8 s ? self-refresh ? power down mode ? variable write length control ? write latency = cas latency-1 ? programable cas latency and burst length cas latency = 3, 4 burst length = 2, 4 ? organization tc59lm814cft: 4,194,304 words 4 banks 16 bits tc59lm806cft: 8,388,608 words 4 banks 8 bits ? power supply voltage v dd : 2.5 v 0.15 v v ddq : 2.5 v 0.15 v ? 2.5 v cmos i/o comply with sstl-2 (half strength driver) ? package: 400 875 mil, 66 pin tsopii, 0.65 mm pin pitch (tsopii66-p-400-0.65) notice: fcram is a trademark of fujitsu limited, japan.
tc59lm814/06cft-50,-55,-60 2002-08-19 2/38 pin names pin assignment (top view) pin name a0~a14 address input ba0, ba1 bank address dq0~dq7 ( 8) dq0~dq15 ( 16) data input/output cs chip select fn function control pd power down control clk, clk clock input dqs ( 8) udqs/ldqs ( 16) write/read data strobe v dd power ( + 2.5 v) v ss ground v ddq power ( + 2.5 v) (for i/o buffer) v ssq ground (for i/o buffer) v ref reference voltage nc 1 , nc 2 not connected tc59lm814cft tc59lm806cft 400 mil width 875 mil length 66 pin tsopii 0.65 mm lead pitch 1 66 2 65 3 64 4 63 5 62 6 61 7 60 8 59 9 58 10 57 11 56 12 55 13 54 14 53 15 52 16 51 17 50 18 49 19 48 20 47 21 46 22 45 23 44 24 43 25 42 26 41 27 40 28 39 29 38 30 37 31 36 32 35 33 34 pd pd clk clk v ss dq15 v ssq dq14 dq13 v ddq dq12 dq11 v ssq dq10 dq9 v ddq dq8 nc 1 v ssq udqs nc 1 v ref v ss nc 1 clk nc 1 a12 a11 a9 a8 a7 a6 a5 a4 v ss v ss dq7 v ssq nc 2 dq6 v ddq nc 2 dq5 v ssq nc 2 dq4 v ddq nc 2 nc 1 v ssq dqs nc 1 v ref v ss nc 1 clk nc 1 a12 a11 a9 a8 a7 a6 a5 a4 v ss cs cs v dd dq0 v ddq dq1 dq2 v ssq dq3 dq4 v ddq dq5 dq6 v ssq dq7 nc 1 v ddq ldqs nc 1 v dd nc 1 nc 1 a14 a13 fn nc 1 ba0 ba1 a10 a0 a1 a2 a3 v dd v dd dq0 v ddq nc 2 dq1 v ssq nc 2 dq2 v ddq nc 2 dq3 v ssq nc 2 nc 1 v ddq nc 2 nc 1 v dd nc 1 nc 1 a14 a13 fn nc 1 ba0 ba1 a10 a0 a1 a2 a3 v dd
tc59lm814/06cft-50,-55,-60 2002-08-19 3/38 block diagram note: the tc59lm806cft configuration is 32768 256 8 of cell array with the dq pins numbered dq0~dq7. the tc59lm814cft configuration is 32768 128 16 of cell array with the dq pins numbered dq0~dq15. dq0~dqn bank #1 dll clock buffer clk clk pd to each block command decoder cs fn address buffer control signal generator mode register refresh counter a0~a14 ba0, ba1 bank #0 memory cell array column decoder row decoder burst counter write address latch/ address comparator data control and latch circuit upper a ddress latch read data buffer dq buffer dqs lower address latch bank #2 bank #3 write data buffer
tc59lm814/06cft-50,-55,-60 2002-08-19 4/38 absolute maximum ratings symbol parameter rating unit notes v dd power supply voltage ? 0.3~ 3.3 v v ddq power supply voltage (for i/o buffer) ? 0.3~v dd + 0.3 v v in input voltage ? 0.3~v dd + 0.3 v v out dq pin voltage ? 0.3~v ddq + 0.3 v v ref input reference voltage ? 0.3~3.3 v t opr operating temperature 0~70 c t stg storage temperature ? 55~150 c t solder soldering temperature (10 s) 260 c p d power dissipation 1 w i out short circuit output current 50 ma caution: conditions outside the limits listed under ?absolute maximum ratings? may cause permanent damage to the device. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to ?absolute maximum ratings? conditions for extended periods may affect device reliability. recommended dc, ac operating conditions (notes: 1)(ta = = = = 0~70c) symbol parameter min typ. max unit notes v dd power supply voltage 2.35 2.5 2.65 v v ddq power supply voltage (for i/o buffer) 2.35 v dd v dd v v ref input reference voltage v ddq /2 96% v ddq /2 v ddq /2 104% v 2 v ih (dc) input dc high voltage v ref + 0.2 ? v ddq + 0.2 v 5 v il (dc) input dc low voltage ? 0.1 ? v ref ? 0.2 v 5 v ick (dc) differential clock dc input voltage ? 0.1 ? v ddq + 0.1 v 10 v id (dc) input differential voltage. clk and clk inputs (dc) 0.4 ? v ddq + 0.2 v 7, 10 v ih (ac) input ac high voltage v ref + 0.35 ? v ddq + 0.2 v 3, 6 v il (ac) input ac low voltage ? 0.1 ? v ref ? 0.35 v 4, 6 v id (ac) input differential voltage. clk and clk inputs (ac) 0.7 ? v ddq + 0.2 v 7, 10 v x (ac) differential ac input cross point voltage v ddq /2 ? 0.2 ? v ddq /2 + 0.2 v 8, 10 v iso (ac) differential clock ac middle level v ddq /2 ? 0.2 ? v ddq /2 + 0.2 v 9, 10
tc59lm814/06cft-50,-55,-60 2002-08-19 5/38 note: (1) all voltages referenced to v ss , v ssq . (2) v ref is expected to track variations in v ddq dc level of the transmitting device. peak to peak ac noise on v ref may not exceed 2% v ref (dc). (3) overshoot limit: v ih (max) = v ddq + 0.9 v with a pulse width 5 ns. (4) undershoot limit: v il (min) = ? 0.9 v with a pulse width 5 ns. (5) v ih (dc) and v il (dc) are levels to maintain the current logic state. (6) v ih (ac) and v il (ac) are levels to change to the new logic state. (7) v id is magnitude of the difference between clk input level and clk input level. (8) the value of v x (ac) is expected to equal v ddq /2 of the transmitting device. (9) v iso means {v ick (clk) + v ick ( clk )} /2 (10) refer to the figure below. (11) in the case of external termination, vtt (termination voltage) should be gone in the range of v ref (dc) 0.04 v. capacitance (v dd , , , , v ddq = = = = 2.5 v, f = = = = 1 mhz, ta = = = = 25 c) symbol parameter min max unit c in input pin capacitance 2.5 4.0 pf c inc clock pin (clk, clk ) capacitance 2.5 4.0 pf c i/o i/o pin (dq, dqs) capacitance 4.0 6.0 pf c nc 1 nc 1 pin capacitance ? 1.5 pf c nc 2 nc 2 pin capacitance 4.0 6.0 pf note: these parameters are periodically sampled and not 100% tested. the nc 2 pins have additional capacitance for adjustment of the adjacent pin capacitance. the nc 2 pins have power and ground clamp. v iso ( min ) v iso ( max ) v ick v ick v x v x v x v x v x v ick v ick clk clk v ss |v id (ac)| 0 v differential v iso v ss v id (ac)
tc59lm814/06cft-50,-55,-60 2002-08-19 6/38 recommended dc operating conditions (v dd , ,, , v ddq = = = = 2.5v 0.15v, ta = = = = 0 ~70 c) max symbol parameter -50 -55 -60 unit notes i dd1s operating current t ck = min; i rc = min, read/write command cycling, 0 v v in v il (ac) (max), v ih (ac) (min) v in v ddq , 1 bank operation, burst length = 4, address change up to 2 times during minimum i rc . 190 180 170 1, 2 i dd2n standby current t ck = min, cs = v ih , pd = v ih , 0 v v in v il (ac) (max), v ih (ac) (min) v in v ddq , all banks: inactive state, other input signals are changed one time during 4 t ck . 40 40 35 1 i dd2p standby (power down) current t ck = min, cs = v ih , pd = v il (power down), 0 v v in v ddq , all banks: inactive state 2 2 2 1 i dd5 auto-refresh current t ck = min; i refc = min, t refi = min, auto-refresh command cycling, 0 v v in v il (ac) (max), v ih (ac) (min) v in v ddq , address change up to 2 times during minimum i refc . 65 65 60 1 i dd6 self-refresh current self-refresh mode pd = 0.2 v, 0 v v in v ddq 3 3 3 ma symbol parameter min max unit notes i li input leakage current ( 0 v v in v ddq , all other pins not under test = 0 v) ? 5 5 a i lo output leakage current (output disabled, 0 v v out v ddq ) ? 5 5 a i ref v ref current ? 5 5 a i oh (dc) output source dc current v oh = v ddq ? 0.4 v ? 10 ? 3 i ol (dc) normal output driver output sink dc current v ol = 0.4 v 10 ? 3 i oh (dc) output source dc current v oh = v ddq ? 0.4 v ? 11 ? 3 i ol (dc) strong output driver output sink dc current v ol = 0.4 v 11 ? 3 i oh (dc) output source dc current v oh = v ddq ? 0.4 v ? 8 ? 3 i ol (dc) weaker output driver output sink dc current v ol = 0.4 v 8 ? 3 i oh (dc) output source dc current v oh = v ddq ? 0.4 v ? 7 ? 3 i ol (dc) weakest output driver output sink dc current v ol = 0.4 v 7 ? ma 3 notes: 1. these parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of t ck , t rc and i rc . 2. these parameters depend on the output loading. the specified values are obtained with the output open. 3. refer to output driver characteristics for the detail. output driver strength is selected by extended mode register.
tc59lm814/06cft-50,-55,-60 2002-08-19 7/38 ac characteristics and operating conditions (notes: 1, 2) -50 -55 -60 symbol parameter min max min max min max unit notes t rc random cycle time 25 ? 27.5 ? 30 ? 3 c l = 3 5.5 8.5 6 12 6.5 12 3 t ck clock cycle time c l = 4 5 8.5 5.5 12 6 12 3 t rac random access time ? 22 ? 24 ? 26 3 t ch clock high time 0.45 t ck ? 0.45 t ck ? 0.45 t ck ? 3 t cl clock low time 0.45 t ck ? 0.45 t ck ? 0.45 t ck ? 3 t ckqs dqs access time from clk ? 0.65 0.65 ? 0.75 0.75 ? 0.85 0.85 3, 8 t qsq data output skew from dqs ? 0.4 ? 0.45 ? 0.5 4 t ac data access time from clk ? 0.65 0.65 ? 0.75 0.75 ? 0.85 0.85 3, 8 t oh data output hold time from clk ? 0.65 0.65 ? 0.75 0.75 ? 0.85 0.85 3, 8 t qspre dqs (read) preamble pulse width 0.9 t ck ? 0.2 1.1 t ck + 0.2 0.9 t ck ? 0.2 1.1 t ck + 0.2 0.9 t ck ? 0.2 1.1 t ck + 0.2 3, 8 t hp clk half period (minimum of actual t ch , t cl ) min(t ch , t cl ) ? min(t ch , t cl ) ? min(t ch , t cl ) ? 3 t qsp dqs (read) pulse width t hp ? 0.55 ? t hp ? 0.6 ? t hp ? 0.65 ? 4, 8 t qsqv data output valid time from dqs t hp ? 0.55 ? t hp ? 0.6 ? t hp ? 0.65 ? 4, 8 t dqss dqs (write) low to high setup time 0.75 t ck 1.25 t ck 0.75 t ck 1.25 t ck 0.75 t ck 1.25 t ck 3 t dspre dqs (write) preamble pulse width 0.4 t ck ? 0.4 t ck ? 0.4 t ck ? 4 t dspres dqs first input setup time 0 ? 0 ? 0 ? 3 t dspreh dqs first low input hold time 0.25 t ck ? 0.25 t ck ? 0.25 t ck ? 3 t dsp dqs high or low input pulse width 0.45 t ck 0.55 t ck 0.45 t ck 0.55 t ck 0.45 t ck 0.55 t ck 4 c l = 3 1.3 ? 1.4 ? 1.5 ? 3, 4 t dss dqs input falling edge to clock setup time c l = 4 1.3 ? 1.4 ? 1.5 ? 3, 4 t dspst dqs (write) postamble pulse width 0.45 t ck ? 0.45 t ck ? 0.45 t ck ? 4 c l = 3 1.3 ? 1.4 ? 1.5 ? 3, 4 t dspsth dqs (write) postamble hold time c l = 4 1.3 ? 1.4 ? 1.5 ? 3, 4 t dssk udqs - ldqs skew (x16) -0.5 t ck 0.5 t ck -0.5 t ck 0.5 t ck -0.5 t ck 0.5 t ck t ds data input setup time from dqs 0.5 ? 0.5 ? 0.6 ? 4 t dh data input hold time from dqs 0.5 ? 0.5 ? 0.6 ? 4 t dipw data input pulse width (for each device) 1.5 ? 1.5 ? 1.9 ? t is command/address input setup time 0.9 ? 0.9 ? 1.0 ? 3 t ih command/address input hold time 0.9 ? 0.9 ? 1.0 ? 3 t ipw command/address input pulse width (for each device) 2.0 ? 2.0 ? 2.2 ? t lz data-out low impedance time from clk ? 0.65 ? ? 0.75 ? ? 0.85 ? 3,6,8 t hz data-out high impedance time from clk ? 0.65 ? 0.75 ? 0.85 ns 3,7,8
tc59lm814/06cft-50,-55,-60 2002-08-19 8/38 ac characteristics and operating conditions (notes: 1, 2) (continued) -50 -55 -60 symbol parameter min max min max min max unit notes t qslz dqs-out low impedance time from clk ? 0.65 ? ? 0.75 ? ? 0.85 ? 3,6,8 t qshz dqs-out high impedance time from clk ? 0.65 0.65 ? 0.75 0.75 ? 0.85 0.85 3,7,8 t qpdh last output to pd high hold time 0 ? 0 ? 0 ? t pdex power down exit time 2 ? 2 ? 2 ? 3 t t input transition time 0.1 1 0.1 1 0.1 1 t fpdl pd low input window for self-refresh entry ? 0.5 t ck 5 ? 0.5 t ck 5 ? 0.5 t ck 5 ns 3 t refi auto-refresh average interval 0.4 7.8 0.4 7.8 0.4 7.8 5 t pause pause time after power-up 200 ? 200 ? 200 ? s c l = 3 5 ? 5 ? 5 ? i rc random read/write cycle time (applicable to same bank) c l = 4 5 ? 5 ? 5 ? i rcd rda/wra to lal command input delay (applicable to same bank) 1 1 1 1 1 1 c l = 3 4 ? 4 ? 4 ? i ras lal to rda/wra command input delay (applicable to same bank) c l = 4 4 ? 4 ? 4 ? i rbd random bank access delay (applicable to other bank) 2 ? 2 ? 2 ? b l = 2 2 ? 2 ? 2 ? i rwd lal following rda to wra delay (applicable to other bank) b l = 4 3 ? 3 ? 3 ? i wrd lal following wra to rda delay (applicable to other bank) 1 ? 1 ? 1 ? c l = 3 5 ? 5 ? 5 ? i rsc mode register set cycle time c l = 4 5 ? 5 ? 5 ? i pd pd low to inactive state of input buffer ? 1 ? 1 ? 1 i pda pd high to active state of input buffer ? 1 ? 1 ? 1 c l = 3 15 ? 15 ? 15 ? i pdv power down mode valid from ref command c l = 4 18 ? 18 ? 18 ? c l = 3 15 ? 15 ? 15 ? i refc auto-refresh cycle time c l = 4 18 ? 18 ? 18 ? i ckd ref command to clock input disable at self-refresh entry 16 ? 16 ? 16 ? i lock dll lock-on time (applicable to rda command) 200 ? 200 ? 200 ? cycle
tc59lm814/06cft-50,-55,-60 2002-08-19 9/38 ac test conditions symbol parameter value unit notes v ih (min) input high voltage (minimum) v ref + 0.35 v v il (max) input low voltage (maximum) v ref ? 0.35 v v ref input reference voltage v ddq /2 v v tt termination voltage v ref v v swing input signal peak to peak swing 1.0 v vr differential clock input reference level v x (ac) v v id (ac) input differential voltage 1.5 v slew input signal minimum slew rate 1.0 v/ns v otr output timing measurement reference voltage v ddq /2 v note: (1) transition times are measured between v ih min (dc) and v il max (dc). transition (rise and fall) of input signals have a fixed slope. (2) if the result of nominal calculation with regard to t ck contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., t dqss = 0.75 t ck , t ck = 5 ns, 0.75 5 ns = 3.75 ns is rounded up to 3.8 ns.) (3) there parameters are measured from the differential clock (clk and clk ) ac cross point. (4) these parameters are measured from signal transition point of dqs crossing v ref level. (5) te t refi (max) applies to equally distributed refresh method. the t refi (min) applies to both burst refresh method and distribted refresh method. in such case, the average interval of eight consecutive auto-refresh commands has to be more than 400 ns always. in other words, the number of auto-refresh cycles which can be performed within 3.2 s (8 400 ns) is to 8 times in the maximum. (6) low impedance state is specified at v ddq /2 0.2 v from steady state. (7) high impedance state is specified where output buffer is no longer driven. (8) these parameters depend on the clock jitter. these parameters are measured at stable clock. z = 50 ? ac test load output v tt c l = 30 pf r t = 50 ? measurement point slew = (v ih min (ac) ? v il max (ac))/ ? t output v ih min (ac) ? t v ref v il max (ac) v swing ? t v ss v ddq v ref
tc59lm814/06cft-50,-55,-60 2002-08-19 10/38 power up sequence (1) as for pd , being maintained by the low state ( 0.2 v) is desirable before a power-supply injection. (2) apply v dd before or at the same time as v ddq . (3) apply v ddq before or at the same time as v ref . (4) start clock (clk, clk ) and maintain stable condition for 200 s (min). (5) after stable power and clock, apply desl and take pd =h. (6) issue emrs to enable dll and to define driver strength. (note: 1) (7) issue mrs for set cas latency (cl), burst type (bt), and burst length (bl). (note: 1) (8) issue two or more auto-refresh commands (note: 1). (9) ready for normal operation after 200 clocks from extended mode register programming. note: (1) sequence 6, 7 and 8 can be issued in random order. (2) l = logic low, h = logic high clk command dq address v dd v ddq v ref clk pd 2.5v ( typ ) 2.5v ( typ ) 1.25v ( typ ) 200 us ( min ) t pdex l pda l rsc l rsc l refc l refc 200clock c y cle ( min ) desl rda desl rda mrs desl wra ref desl wra ref desl op-code emrs op-code mrs hi-z dqs emrs mrs auto refresh cycle normal operation mrs
tc59lm814/06cft-50,-55,-60 2002-08-19 11/38 timing diagrams input timing timing of the clk, t ck t cl t ch cs dq (input) clk clk refer to the command truth table. t ck 1st 2nd t is t ih t is t ih t ipw 1st 2nd t is t ih t is t ih t ipw ua, ba la t is t ih t is t ih t ipw fn a0~a14 ba0, ba1 t ds t dh t ds t dh t dipw t dipw dqs t t t ck clk v ih v il v ih v il t cl t ch t t v ih (ac) v il (ac) cl k clk cl k v x v x v x v id (ac) clk
tc59lm814/06cft-50,-55,-60 2002-08-19 12/38 read timing (burst length = 4) ldqs dq0~dq7 udqs dq8~dq15 clk clk input (control & a dd r esses) hi-z dqs (output) dq (output) cas latency = 3 lal (after rda) t is t ih t ipw hi-z t ch t cl t ck hi-z dqs (output) dq (output) cas latency = 4 hi-z note: the correspondence of ldqs, udqs to dq. (tc59lm814cft) t qsq t qslz t qspre t ckqs t ckqs t qsp t qsp t ckqs t qshz t qsq t qsqv t qsqv t qsq t hz t lz t oh t ac t ac t ac preamble postamble t qslz t qspre t ckqs t ckqs t qsp t qsp t ckqs t qshz preamble postamble hi-z hi-z q0 q1 q2 q3 t qsq t qsq t qsqv t qsqv t qsq t hz t lz t oh t ac t ac t ac q0 q1 q2 q3 (desl)
tc59lm814/06cft-50,-55,-60 2002-08-19 13/38 write timing (burst length = 4) ldqs dq0~dq7 udqs dq8~dq15 t refi , t pause , i xxxx timing clk clk input (control & addresses) dqs (input) dq (input) cas latency = 3 lal (after wra) t is t ih t ipw t ch t cl t ck note: the correspondence of ldqs, udqs to dq. (tc59lm814cft) dqs (input) dq (input) cas latency = 4 t dspreh t dsp t dsp t ds preamble postamble t dsp t dss t dspres t dspst t dss t dspsth t dspre t dqss t dh t dipw d0 d1 t ds t dh d2 d3 t ds t dh t dspreh t dsp t dsp t ds preamble postamble t dsp t dqss t dspres t dspst t dss t dspsth t dspre t dqss t dh t dipw d0 d1 t ds t dh d2 d3 t ds t dh t dss t dqss (desl) cl k clk inpu t (control & addresses) command t is t ih note: ? i xxxx ? means ? i rc ? , ? i rcd ? , ? i ras ? , etc. t refi , t pause , i xxxx command t is t ih (desl)
tc59lm814/06cft-50,-55,-60 2002-08-19 14/38 write timing (x16 device) (burst length = 4) preamble clk clk inpu t (control & addresses) ldqs dq0~dq7 cas latency = 3 udqs dq8~dq15 lal wra ldqs dq0~dq7 cas latency = 4 udqs dq8~dq15 t ds postamble t dssk t dh d0 d1 t ds t dh d2 d3 t ds t dh t ds preamble postamble t dh d0 d1 t ds t dh d2 d3 t ds t dh t ds t dh t dssk t dssk t dssk t dh t ds t ds preamble t dssk t dh d0 d1 t ds t dh d2 d3 t ds t dh t ds preamble t dh d0 d1 t ds t dh d2 d3 t ds t dh t ds t dh t dssk t dssk t dssk t dh t ds (desl)
tc59lm814/06cft-50,-55,-60 2002-08-19 15/38 function truth table (notes: 1, 2, 3) command truth table (notes: 4) ? the first command symbol function cs fn ba1~ba0 a14~a9 a8 a7 a6~a0 desl device deselect h rda read with auto-close l h ba ua ua ua ua wra write with auto-close l l ba ua ua ua ua ? the second command (the next clock of rda or wra command) symbol function cs fn ba1~ ba0 a14~ a13 a12~ a11 a10~a9 a8 a7 a6~a0 lal lower address latch ( 16) h v v la lal lower address latch ( 8) h v la la ref auto-refresh l mrs mode register set l v l l l l v v notes: 1. l = logic low, h = logic high, = either l or h, v = valid (specified value), ba = bank address, ua = upper address, la = lower address 2. all commands are assumed to issue at a valid state. 3. all inputs for command (excluding selfx and pdex) are latched on the crossing point of differential clock input where clk goes to high. 4. operation mode is decided by the combination of 1st command and 2nd command. refer to ?state diagram? and the command table below. read command table command (symbol) cs fn ba1~ba0 a14~a9 a8 a7 a6~a0 notes rda (1st) l h ba ua ua ua ua lal (2nd) h la la 5 notes: 5. for x16 device, a7 is " " (either l or h). write command table ? tc59lm814cft command(symbol) cs fn ba1~ ba0 a14 a13 a12 a11 a10~ a9 a8 a7 a6~a0 wra (1st) l l ba ua ua ua ua ua ua ua ua lal (2nd) h lvw0 lvw1 uvw0 uvw1 la ? tc59lm806cft command(symbol) cs fn ba1~ ba0 a14 a13 a12 a11 a10~ a9 a8 a7 a6~a0 wra (1st) l l ba ua ua ua ua ua ua ua ua lal (2nd) h vw0 vw1 la la notes: 6. a14~ a11 are used for variable write length (vw) control at write operation.
tc59lm814/06cft-50,-55,-60 2002-08-19 16/38 function truth table (continued) vw truth table symbol function vw0 vw1 write all words l bl=2 write first one word h reserved l l write all words h l write first two words l h bl=4 write first one word h h notes: 7. for x16 device, lvw0 and lvw1 control dq0~dq7. uvw0 and uvw1 control dq8~dq15. mode register set command table command (symbol) cs fn ba1~ba0 a14~a9 a8 a7 a6~a0 notes rda (1st) l h mrs (2nd) l v l l v v 8 notes: 8. refer to ?mode register table?. auto-refresh command table pd function command (symbol) current state n ? 1 n cs fn ba1~ba0 a14~a9 a8 a7 a6~a0 notes active wra (1st) standby h h l l auto-refresh ref (2nd) active h h l self-refresh command table pd function command (symbol) current state n ? 1 n cs fn ba1~ba0 a14~a9 a8 a7 a6~a0 notes active wra (1st) standby h h l l self-refresh entry ref (2nd) active h l l 9, 10 self-refresh continue ? self-refresh l l self-refresh exit selfx self-refresh l h h 11 power down table pd function command (symbol) current state n ? 1 n cs fn ba1~ba0 a14~a9 a8 a7 a6~a0 notes power down entry pden standby h l h 10 power down continue ? power down l l power down exit pdex power down l h h 11 notes: 9. pd has to be brought to low within t fpdl from ref command. 10. pd should be brought to low after dq?s state turned high impedance. 11. when pd is brought to high from low, this function is executed asynchronously.
tc59lm814/06cft-50,-55,-60 2002-08-19 17/38 function truth table (continued) pd current state n ? 1 n cs fn address command action notes h h h desl nop h h l h ba, ua rda row activate for read h h l l ba, ua wra row activate for write h l h pden power down entry 12 h l l ? illegal idle l ? refer to power down state h h h la lal begin read h h l op-code mrs/emrs access to mode register h l h pden illegal h l l mrs/emrs illegal row active for read l ? invalid h h h la lal begin write h h l ref auto-refresh h l h pden illegal h l l ref (self) self-refresh entry row active for write l ? invalid h h h desl continue burst read to end h h l h ba, ua rda illegal 13 h h l l ba, ua wra illegal 13 h l h pden illegal h l l ? illegal read l ? invalid h h h desl data write&continue burst write to end h h l h ba, ua rda illegal 13 h h l l ba, ua wra illegal 13 h l h pden illegal h l l ? illegal write l ? invalid h h h desl nop idle after i refc h h l h ba, ua rda illegal h h l l ba, ua wra illegal h l h pden self-refresh entry 14 h l l ? illegal auto-refreshing l ? refer to self-refreshing state h h h desl nop idle after i rsc h h l h ba, ua rda illegal h h l l ba, ua wra illegal h l h pden illegal h l l ? illegal mode register accessing l ? invalid h ? invalid l l ? maintain power down mode l h h pdex exit power down mode idle after t pdex power down l h l ? illegal h ? invalid l l ? maintain self-refresh l h h selfx exit self-refresh idle after i refc l h l ? illegal self-refreshing notes: 12. illegal if any bank is not idle. 13. illegal to bank in specified states; function may be legal in the bank inidicated by bank address (ba). 14. illegal if t fpdl is not satisfied.
tc59lm814/06cft-50,-55,-60 2002-08-19 18/38 mode register table regular mode register (notes: 1) address ba1 * 1 ba0 * 1 a14~a8 a7 * 3 a6~a4 a3 a2~a0 register 0 0 0 te cl bt bl a7 test mode (te) a3 burst type (bt) 0 regular (default) 0 sequential 1 test mode entry 1 interleave a6 a5 a4 cas latency (cl) a2 a1 a0 burst length (bl) 0 0 reserved * 2 0 0 0 reserved * 2 0 1 0 reserved * 2 0 0 1 2 0 1 1 3 0 1 0 4 1 0 0 4 0 1 1 1 0 1 reserved * 2 1 reserved * 2 1 1 reserved * 2 extended mode register (notes: 4) address ba1 * 4 ba0 * 4 a14~a7 a6 a5~a2 a1 a0 * 5 register 0 1 0 dic 0 dic ds a6 a1 output drive impedance control (dic) 0 0 normal output driver 0 1 strong output driver 1 0 weaker output driver 1 1 weakest output driver a0 dll switch (ds) 0 dll enable 1 dll disable notes: 1. regular mode register is chosen using the combination of ba0 = 0 and ba1 = 0. 2. ?reserved? places in regular mode register should not be set. 3. a7 in regular mode register must be set to ?0? (low state). because test mode is specific mode for supplier. 4. extended mode register is chosen using the combination of ba0 = 1 and ba1 = 0. 5. a0 in extended mode register must be set to "0" to enable dll for normal operation.
tc59lm814/06cft-50,-55,-60 2002-08-19 19/38 state diagram standby (idle) self- refresh power down pden ( pd = l) pdex ( pd = h) selfx ( pd = h) mode register auto- refresh active active (restore) read write (buffer) pd = l pd = h wra rda mrs ref command input lal automatic return the second command at active state must be issued 1 clock after rda or wra command input. lal
tc59lm814/06cft-50,-55,-60 2002-08-19 20/38 timing diagrams single bank read timing (cl = 3) single bank read timing (cl = 4) clk clk hi-z dqs (output) dq (output) bl = 2 i rc = 5 cycles 0 1 2 3 4 5 6 7 8 9 10 11 rda lal rda lal rda hi-z hi-z q0 hi-z q1 q0 q1 hi-z hi-z hi-z hi-z hi-z q0 hi-z q1 q0 q1 hi-z hi-z q2 q3 q2 q3 cl = 3 command dqs (output) dq (output) bl = 4 desl desl i rc = 5 cycles lal i ras = 4 cycles i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle cl = 3 cl = 3 cl = 3 clk clk hi-z dqs (output) dq (output) bl = 2 i rc = 5 cycles 0 1 2 3 4 5 6 7 8 9 10 11 rda lal rda lal rda hi-z q0 hi-z q1 q0 q1 hi-z hi-z hi-z q0 hi-z q1 q0 q1 hi-z q2 q3 q1 cl = 4 command dqs (output) dq (output) bl = 4 desl desl i rc = 5 cycles lal i ras = 4 cycles i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle cl = 4 cl = 4 cl = 4 i rcd = 1 cycle q2
tc59lm814/06cft-50,-55,-60 2002-08-19 21/38 single bank write timing (cl = 3) single bank write timing (cl = 4) clk clk dqs (input) dq (input) bl = 2 0 1 2 3 4 5 6 7 8 9 10 11 wra lal d0 d1 wl = 2 command dqs (input) dq (input) bl = 4 i rc = 5 cycles d0 d1 t dqss d0 d1 t dqss d2 d3 desl wra lal desl wra lal i rc = 5 cycles i ras = 4 cycles i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle wl = 2 wl = 2 d0 d1 d2 d3 wl = 2 t dqss clk clk dqs (input) dq (input) bl = 2 0 1 2 3 4 5 6 7 8 9 10 11 wra lal d0 d1 wl = 3 command dqs (input) dq (input) bl = 4 i rc = 5 cycles d0 d1 d0 d1 t dqss d2 d3 desl wra lal desl wra lal i rc = 5 cycles i ras = 4 cycles i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle wl = 3 d0 d1 d2 d3 t dqss wl = 3 wl = 3 i rcd = 1 cycle note: means h or l
tc59lm814/06cft-50,-55,-60 2002-08-19 22/38 single bank read-write timing (cl = 3) single bank read-write timing (cl = 4) clk clk dqs dq bl = 2 0 1 2 3 4 5 6 7 8 9 10 11 rda lal command bl = 4 wra lal dqs dq desl desl rda lal i rc = 5 cycles i rc = 5 cycles hi-z hi-z hi-z q0 hi-z q1 d0 d1 hi-z hi-z hi-z hi-z hi-z q0 hi-z q1 d0 d1 hi-z hi-z q2 q3 d2 d3 cl = 3 i ras = 4 cycles i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle cl = 3 wl = 2 wl = 2 t dqss clk clk dqs dq bl = 2 0 1 2 3 4 5 6 7 8 9 10 11 rda lal command bl = 4 wra lal dqs dq desl desl rda lal i rc = 5 cycles i rc = 5 cycles hi-z hi-z q0 hi-z q1 d0 d1 hi-z hi-z hi-z q0 hi-z q1 d0 d1 hi-z q2 q3 d2 d3 cl = 4 i ras = 4 cycles i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle wl = 3 t dqss cl = 4 wl = 3
tc59lm814/06cft-50,-55,-60 2002-08-19 23/38 multiple bank read timing (cl = 3) multiple bank read timing (cl = 4) clk clk bl = 2 0 1 2 3 4 5 6 7 8 9 10 11 rdaa lala command i rc = 5 cycles hi-z qa0 hi-z hi-z hi-z cl = 3 rdab lalb desl lala rdac lalc rdad lald rdab bank ?a? bank add. (ba0, ba1) bank ?b? bank ?c? bank ?d? i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle i rbd = 2 cycles qa1 qb0 qb1 qa0 qa1 qc0 hi-z hi-z hi-z dqs (output) dq (output) qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qc0 bl = 4 dqs (output) dq (output) rdaa i rcd = 1 cycle i rcd = 1 cycle bank ?a? bank ?b? i rbd = 2 cycles i rbd = 2 cycles hi-z cl = 3 cl = 3 cl = 3 hi-z qa0 qa1 qa2 qa3 cl = 3 cl = 3 i rbd = 2 cycles clk clk bl = 2 0 1 2 3 4 5 6 7 8 9 10 11 rdaa lala command i rc = 5 cycles hi-z qa0 hi-z hi-z hi-z cl = 4 rdab lalb desl lala rdac lalc rdad lald rdab bank ?a? bank add. (ba0, ba1) bank ?b? bank ?c? bank ?d? i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle i rbd = 2 cycles qa1 qb0 qb1 qa0 qa1 hi-z hi-z dqs (output) dq (output) qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 bl = 4 dqs (output) dq (output) rdaa i rcd = 1 cycle i rcd = 1 cycle bank ?a? bank ?b? i rbd = 2 cycles i rbd = 2 cycles hi-z cl = 4 cl = 4 cl = 4 hi-z qa0 qa1 qa2 cl = 4 cl = 4 note: ? ? is don?t care. i rc to the same bank must be satisfied. i rbd = 2 cycles
tc59lm814/06cft-50,-55,-60 2002-08-19 24/38 multiple bank write timing (cl = 3) multiple bank write timing (cl = 4) clk clk bl = 2 0 1 2 3 4 5 6 7 8 9 10 11 wraa lala command i rc = 5 cycles da0 wl = 2 wrab lalb desl lala wrac lalc wrad lald wrab bank ?a? bank add. (ba0, ba1) bank ?b? bank ?c? bank ?d? i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle i rbd = 2 cycles da1 db0 db1 da0 da1 dqs (input) dq (input) da0 da1 da2 da3 db0 db1 db2 db3 bl = 4 dqs (input) dq (input) wraa i rcd = 1 cycle i rcd = 1 cycle bank ?a? bank ?b? i rbd = 2 cycles i rbd = 2 cycles t dqss i rbd = 2 cycles dc0 dc1 wl = 2 t dqss t dqss t dqss da0 da1 da2 da3 dc0 dc1 dc2 wl = 2 wl = 2 t dqss clk clk bl = 2 0 1 2 3 4 5 6 7 8 9 10 11 wraa lala command i rc = 5 cycles da0 wl = 3 wrab lalb desl lala wrac lalc wrad lald wrab bank ?a? bank add. (ba0, ba1) bank ?b? bank ?c? bank ?d? i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle i rbd = 2 cycles da1 db0 db1 da0 da1 dqs (input) dq (input) da0 da1 da2 da3 db0 db1 db2 db3 bl = 4 dqs (input) dq (input) wraa i rcd = 1 cycle i rcd = 1 cycle bank ?a? bank ?b? i rbd = 2 cycles i rbd = 2 cycles t dqss i rbd = 2 cycles dc0 dc1 wl = 3 t dqss t dqss t dqss da0 da1 da2 da3 dc0 dc1 wl = 3 wl = 3 t dqss note: means h or l. ? ? is don?t care i rc to the same bank must be satisfied.
tc59lm814/06cft-50,-55,-60 2002-08-19 25/38 multiple bank read-write timing (bl = 2) multiple bank read-write timing (bl = 4) clk clk cl = 3 0 1 2 3 4 5 6 7 8 9 10 11 wraa lala command i rbd = 2 cycles rdab lalb desl wrac lalc rdad desl wrac lalc bank ?a? bank add. (ba0, ba1) bank ?b? bank ?c? bank ?d? bank ?c? i rcd = 1 cycle i rc = 5 cycles i rwd = 2 cycles i rbd = 2 cycles dqs dq cl = 4 t dqss lald i rcd = 1 cycle i rwd = 2 cycles i wrd = 1 cycle i rcd = 1 cycle i wrd = 1 cycle i rcd = 1 cycle hi-z hi-z hi-z t dqss hi-z wl = 2 da0 da1 qb0 qb1 dc0 dc1 cl = 3 wl = 2 cl = 3 qd0 hi-z t dqss hi-z hi-z t dqss hi-z da0 da1 qb0 qb1 dc0 dc1 wl = 3 cl = 4 wl = 3 cl = 4 hi-z hi-z hi-z hi-z dqs dq clk clk cl = 3 0 1 2 3 4 5 6 7 8 9 10 11 wraa lala command i rbd = 2 cycles rdab lalb wrac lalc rdad lald bank ?a? bank add. (ba0, ba1) bank ?b? bank ?c? bank ?d? i rcd = 1 cycle i rwd = 3 cycles i rbd = 2 cycles dqs dq cl = 4 t dqss i rcd = 1 cycle i wrd = 1 cycle i rcd = 1 cycle i wrd = 1 cycle hi-z hi-z wl = 2 da0 da1 qb0 qb1 dc0 dc1 cl = 3 wl = 2 t dqss hi-z hi-z da0 da1 qb0 qb1 wl = 3 cl = 4 wl = 3 dqs dq i rcd = 1 cycle desl desl t dqss da2 da3 qb2 qb3 dc2 dc3 da2 da3 qb2 qb3 dc0 dc1 dc2 note: ? ? is don?t care i rc to the same bank must be satisfied. t dqss
tc59lm814/06cft-50,-55,-60 2002-08-19 26/38 single bank write with variable write length (vw) control (cl = 3, bl = 4, sequential mode) cl k clk 0 1 2 3 4 5 6 7 8 9 10 11 wra lal command i rc = 5cycles wra lal wra lal ua la=#3 vw=2 address ua la=#1 vw=1 ua la=#3 vw=2 i rc = 5cycles dqs (input) dq (input) last two data are masked. x8 desl desl d0 d1 d0 wra lal command wra lal wra lal ua la =#3 uvw=2 lvw =1 address ua ua udqs (input) dq8~dq15 (input) x16 desl desl la=#1 uvw=1 lvw =1 la=#3 uvw=2 lvw =1 d0 d1 d0 udqs (input) dq0~dq7 (input) d0 d0 note: dqs input must be continued till end of burst count even if some of laster data is masked. refer to "vw truth table". ( #1 ) address #3 #0 ( #2 ) ( #3 ) #1 ( #2 ) ( #0 ) last three data are last three data are last three data are last two data are masked. last three data are ( #1 ) address #3 #0 ( #2 ) ( #3 ) #1 ( #2 ) ( #0 ) ( #3 ) #1 ( #2 ) ( #0 ) ( #1 ) address #3 ( #2 ) ( #0 ) ( write first two words ) ( write first one word ) upper byte: write first two words lower byte: write first one word upper byte: write first one word lower byte: write first one word
tc59lm814/06cft-50,-55,-60 2002-08-19 27/38 mode register set timing (cl = 3, bl = 2) power down timing (cl = 3, bl = 2) clk clk hi-z dqs (output) dq (output) i rc = 5 cycles 0 1 2 3 4 5 6 7 8 9 10 11 rda lal rda mrs hi-z q0 hi-z q1 hi-z i rsc = 5 cycles cl = 3 command i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle rda or wra ba, ua la valid (op- code ) ba, ua a14~a0 ba0, ba1 desl desl clk clk hi-z dqs (output) dq (output) 0 1 2 3 4 5 6 7 n ? 1 n n + 1 n + 2 rda lal hi-z q0 hi-z q1 hi-z cl = 3 command i pda = 1 cycle desl rda or wra desl i rcd = 1 cycle t ih t is i pd = 1 cycle t pdex t qpdh pd power down entry power down exit note: ? ? is don?t care i pd is defined from the first clock rising edge after pd is brought to ?low?. i pda is defined from the first clock rising edge after pd is brought to ?high?. pd must be kept "high" level until end of burst data output. pd should be brought to high within t refi(max) to maintain the data written into cell. read cycle to power down mode l rc ( min ), t refi ( max )
tc59lm814/06cft-50,-55,-60 2002-08-19 28/38 power down timing (cl = 4) write cycle to power down mode cl k clk dqs (input) dq (input) 0 1 2 3 4 5 6 7 n ? 1 n n + 1 n + 2 wra lal hi-z d0 d1 hi-z command i pda = 1 cycle desl rda or wra desl wl=3 t ih t is i pd = 1 cycle t pdex pd power down entry power down exit note: ? ? is don?t care pd must be kept "high" level until wl+2 clock cycles from lal command. pd should be brought to high within t refi(max) to maintain the data written into cell. l rc ( min ), t refi ( max ) 8 9 2 clock cycles d2 d3 bl = 4 hi-z hi-z dqs (input) dq (input) hi-z d0 d1 hi-z bl = 2 hi-z hi-z
tc59lm814/06cft-50,-55,-60 2002-08-19 29/38 auto-refresh timing (cl = 3, bl = 4) clk clk hi-z dqs (output) dq (output) 0 1 2 3 4 5 6 7 n ? 1 n n + 1 n + 2 rda lal q0 hi-z q1 hi-z cl = 3 command i rc = 5 cycles desl rda or wra lal or mrs or ref i rcd = 1 cycle note: in case of cl = 3, i refc must be meet 15 clock cycles. when the auto-refresh operation is performed, the synthetic average interval of auto-refresh command specified by t refi must be satisfied. t refi is average interval time in 8 refresh cycles that is sampled randomly. wra ref i refc = 15 cycles hi-z i ras = 4 cycles i rcd = 1 cycle q2 q3 clk wra ref wra ref wra ref wra ref wra ref t 1 t 2 t 3 t 7 t 8 8 refresh cycle t refi = total time of 8 refresh cycle 8 t 1 + t 2 + t 3 + t 4 + t 5 + t 6 + t 7 + t 8 8 = t refi is specified to avoid partly concentrated current of refresh operation that is activated larger area than read / write operation. desl
tc59lm814/06cft-50,-55,-60 2002-08-19 30/38 self-refresh entry timing (cl = 3) self-refresh exit timing clk clk hi-z dqs (output) dq (output) 0 1 2 m ? 1 m m + 1 m + 2 * 1 hi-z command notes: 1. ? ? is don?t care. 2. clock should be stable prior to pd = ?high? if clock input is suspended in self-refresh mode. 3. desl command must be asserted during i refc after pd is brought to ?high?. 4. i pda is defined from the first clock rising edge after pd is brought to ?high?. 5. it is desirable that one auto-refresh command is issued just after self-refresh exit before any other operation. 6. any command (except read command) can be issued after i refc . 7. read command (rda + lal) can be issued after i lock . i lock t pdex i pda = 1 cycle * 4 pd desl * 3 lal * 7 wra * 5 ref * 5 desl rda * 7 n ? 1 n n + 1 p ? 1 p i refc command (1st) * 6 command (2nd) * 6 i rcd = 1 cycle i rcd = 1 cycle i refc self-refresh exit * 2 notes: 1. ? ? is don?t care. 2. pd must be brought to "low" within the timing between t fpdl (min) and t fpdl (max) to self refresh mode.when pd is brought to "low" after l pdv , fcram tm perform auto refresh and enter power down mode. 3. it is necessary that clock input is continued at least 16 clock cycles from ref command even though pd is brought to ?low? for self-refresh entry. clk clk hi-z dqs (output) dq (output) 0 1 2 3 4 5 m ? 1 m m + 1 wra ref qx hi-z command i rcd = 1 cycle i refc i ckd = 16 cycles * 3 desl * 1 t fpdl (min) t fpdl (max) i pdv * 2 t qpdh pd self refresh entry auto refresh
tc59lm814/06cft-50,-55,-60 2002-08-19 31/38 functional description network fcram tm the fcram tm is an acronym of fast cycle random access memory. the network fcram tm is competent to perform fast random core access, low latency, low consumption and high-speed data transfer. pin functions clock inputs: clk & the clk and clk inputs are used as the reference for synchronous operation. clk is master clock input. the cs , fn and all address input signals are sampled on the crossing of the positive edge of clk and the negative edge of clk . the dqs and dq output data are referenced to the crossing point of clk and clk . the timing reference point for the differential clock is when the clk and clk signals cross during a transition. power down: the pd input controls the entry to the power down or self-refresh modes. the pd input does not have a clock suspend function like a cke input of a standard sdrams, therefore it is illegal to bring pd pin into low state if any read or write operation is being performed. chip select & function control: & fn the cs and fn inputs are a control signal for forming the operation commands on fcram tm . each operation mode is decided by the combination of the two consecutive operation commands using the cs and fn inputs. bank addresses: ba0 & ba1 the ba0 and ba1 inputs are latched at the time of assertion of the rda or wra command and are selected the bank to be used for the operation. ba0 ba1 bank #0 0 0 bank #1 1 0 bank #2 0 1 bank #3 1 1 address inputs: a0~a14 address inputs are used to access the arbitrary address of the memory cell array within each bank. the upper addresses with bank addresses are latched at the rda or wra command and the lower addresses are latched at the lal command. the a0 to a14 inputs are also used for setting the data in the regular or extended mode register set cycle. upper a ddress lower address tc59lm806cft a0~a14 a0~a7 tc59lm814cft a0~a14 a0~a6 clk pd cs
tc59lm814/06cft-50,-55,-60 2002-08-19 32/38 data input/output: dq0~dq7 or dq15 the input data of dq0 to dq15 are taken in synchronizing with the both edges of dqs input signal. the output data of dq0 to dq15 are outputted synchronizing with the both edges of dqs output signal. data strobe: dqs or ldqs, udqs the dqs is bi-directional signal. both edges of dqs are used as the reference of data input or output. the ldqs is allotted for lower byte (dq0 to dq7) data. the udqs is allotted for upper byte (dq8 to dq15) data. in write operation, the dqs used as an input signal is utilized for a latch of write data. in read operation, the dqs that is an output signal provides the read data strobe. power supply: v dd , v ddq , v ss , v ssq v dd and v ss are power supply pins for memory core and peripheral circuits. v ddq and v ssq are power supply pins for the output buffer. reference voltage: v ref v ref is reference voltage for all input signals.
tc59lm814/06cft-50,-55,-60 2002-08-19 33/38 command functions and operations tc59lm814/06cft are introduced the two consecutive command input method. therefore, except for power down mode, each operation mode decided by the combination of the first command and the second command from stand-by states of the bank to be accessed. read operation (1st command + 2nd command = rda + lal) issuing the rda command with bank addresses and upper addresses to the idle bank puts the bank designated by bank address in a read mode. when the lal command with lower addresses is issued at the next clock of the rda command, the data is read out sequentially synchronizing with the both edges of dqs output signal (burst read operation). the initial valid read data appears after cas latency from the issuing of the lal command. the valid data is outputted for a burst length. the cas latency, the burst length of read data and the burst type must be set in the mode register beforehand. the read operated bank goes back automatically to the idle state after l rc . write operation (1st command + 2nd command = wra + lal) issuing the wra command with bank addresses and upper addresses to the idle bank puts the bank designated by bank address in a write mode. when the lal command with lower addresses is issued at the next clock of the wra command, the input data is latched sequentially synchronizing with the both edges of dqs input signal (burst write operation). the data and dqs inputs have to be asserted in keeping with clock input after cas latency-1 from the issuing of the lal command. the dqs have to be provided for a burst length. the cas latency and the burst type must be set in the mode register beforehand. the write operated bank goes back automatically to the idle state after l rc . auto-refresh operation (1st command + 2nd command = wra + ref) tc59lm814/06cft are required to refresh like a standard sdram. the auto-refresh operation is begun with the ref command following to the wra command. the auto-refresh mode can be effective only when all banks are in the idle state and all outputs are in hi-z states. in a point to notice, the write mode started with the wra command is canceled by the ref command having gone into the next clock of the wra command instead of the lal command. the minimum period between the auto-refresh command and the next command is specified by l refc . however, about a synthetic average interval of auto-refresh command, it must be careful. in case of equally distributed refresh, auto-refresh command has to be issued within once for every 7.8 s by the maximum. in case of burst refresh or random distributed refresh, the average interval of eight consecutive auto-refresh command has to be more than 400 ns always. in other words, the number of auto-refresh cycles which can be performed within 3.2 s (8 400 ns) is to 8 times in the maximum. self-refresh operation (1st command + 2nd command = wra + ref with = ?l?) it is the function of self-refresh operation that refresh operation can be performed automatically by using an internal timer. when all banks are in the idle state and all outputs are in hi-z states, the tc59lm814/06cft become self-refresh mode by issuing the self-refresh command. pd has to be brought to ?low? within t fpdl from the ref command following to the wra command for a self-refresh mode entry. in order to satisfy the refresh period, the self-refresh entry command should be asserted within 7.8 s after the latest auto-refresh command. once the device enters self-refresh mode, the desl command must be continued for l refc period. in addition, it is necessary that clock input is kept in l ckd period. the device is in self-refresh mode as long as pd held ?low?. during self-refresh mode, all input and output buffers except for pd are disabled, therefore the power dissipation lowers. regarding a self-refresh mode exit, pd has to be changed over from ?low? to ?high? along with the desl command, and the desl command has to be continuously issued in the number of clocks specified by l refc . the self-refresh exit function is asynchronous operation. it is required that one auto-refresh command is issued to avoid the violation of the refresh period just after l refc from self-refresh exit. power down mode ( = ?l?) when all banks are in the idle state and all outputs are in hi-z states, the tc59lm814/06cft become power down mode by asserting pd is ?low?. when the device enters the power down mode, all input and output buffers except for pd are disabled after specified time. therefore, the power dissipation lowers. to exit the power down mode, pd has to be brought to ?high? and the desl command has to be issued at next clk rising edge after pd goes high. the power down exit function is asynchronous operation. pd pd
tc59lm814/06cft-50,-55,-60 2002-08-19 34/38 mode register set (1st command + 2nd command = rda + mrs) when all banks are in the idle state, issuing the mrs command following to the rda command can program the mode register. in a point to notice, the read mode started with the rda command is canceled by the mrs command having gone into the next clock of the rda command instead of the lal command. the data to be set in the mode register is transferred using a0 to a14, ba0 and ba1 address inputs. the tc59lm814/06cft have two mode registers. these are regular and extended mode register. the regular or extended mode register is chosen by ba0 and ba1 in the mrs command. the regular mode register designates the operation mode for a read or write cycle. the regular mode register has four function fields. the four fields are as follows: (r-1) burst length field to set the length of burst data (r-2) burst type field to designate the lower address access sequence in a burst cycle (r-3) cas latency field to set the access time in clock cycle (r-4) test mode field to use for supplier only. the extended mode register has two function fields. the two fields are as follows: (e-1) dll switch field to choose either dll enable or dll disable (e-2) output driver impedance control field. once those fields in the mode register are set up, the register contents are maintained until the mode register is set up again by another mrs command or power supply is lost. the initial value of the regular or extended mode register after power-up is undefined, therefore the mode register set command must be issued before proper operation.
tc59lm814/06cft-50,-55,-60 2002-08-19 35/38 ? regular mode register/extended mode register change bits (ba0, ba1) these bits are used to choose either regular mrs or extended mrs ba1 ba0 a14~a0 0 0 regular mrs cycle 0 1 extended mrs cycle 1 reserved regular mode register fields (r-1) burst length field (a2 to a0) this field specifies the data length for column access using the a2 to a0 pins and sets the burst length to be 2 or 4 words. a2 a1 a0 burst length 0 0 0 reserved 0 0 1 2 words 0 1 0 4 words 0 1 1 reserved 1 reserved (r-2) burst type field (a3) the burst type can be chosen interleave mode or sequential mode. when the a3 bit is ?0?, sequential mode is selected. when the a3 bit is ?1?, interleave mode is selected. both burst types support burst length of 2 and 4 words. a3 burst type 0 sequential 1 interleave ? addressing sequence of sequential mode (a3) a column access is started from the inputted lower address and is performed by incrementing the lower address input to the device. the address is varied by the burst length as the following. addressing sequence for sequential mode data access address burst length data 0 n data 1 n + 1 data 2 n + 2 data 3 n + 3 2 words (address bits is la0) not carried from la0~la1 4 words (address bits is la1, la0) not carried from la1~la2 clk clk command dqs dq data 0 data 1 data 2 data 3 rda lal cas latency = 3
tc59lm814/06cft-50,-55,-60 2002-08-19 36/38 ? addressing sequence of interleave mode a column access is started from the inputted lower address and is performed by interleaving the address bits in the sequence shown as the following. addressing sequence for interleave mode data access address burst length data 0 ??? a8 a7 a6 a5 a4 a3 a2 a1 a0 data 1 ??? a8 a7 a6 a5 a4 a3 a2 a1 a0 data 2 ??? a8 a7 a6 a5 a4 a3 a2 a1 a0 data 3 ??? a8 a7 a6 a5 a4 a3 a2 a1 a0 2 words 4 words (r-3) cas latency field (a6 to a4) this field specifies the number of clock cycles from the assertion of the lal command following the rda command to the first data read. the minimum values of cas latency depends on the frequency of clk. in a write mode, the place of clock which should input write data is cas latency cycles ? 1. a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 reserved 0 1 1 3 1 0 0 4 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved (r-4) test mode field (a7) this bit is used to enter test mode for supplier only and must be set to ?0? for normal operation. (r-5) reserved field in the regular mode register ? reserved bits (a8 to a14) these bits are reserved for future operations. they must be set to ?0? for normal operation. extended mode register fields (e-1) dll switch field (a0) this bit is used to enable dll. when the a0 bit is set ?0?, dll is enabled. (e-2) output driver impedance control field (a1 / a6) this bit is used to choose output driver strength. four types of driver strength are supported. a6 a1 output driver impedance control 0 0 normal output driver 0 1 strong output driver 1 0 weaker output driver 1 1 weakest output driver (e-3) reserved field (a2 to a5, a7 to a14) these bits are reserved for future operations and must be set to ?0? for normal operation.
tc59lm814/06cft-50,-55,-60 2002-08-19 37/38 package dimensions weight: 0.51 g (typ.)
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