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| construction analysis qlogic ISP1040B scsi i/o processor report number: sca 9710-557 s e r v i n g t h e g l o b a l s e m i c o n d u c t o r i n d u s t r y s i n c e 1 9 6 4 17350 n. hartford drive scottsdale, az 85255 phone: 602-515-9780 fax: 602-515-9781 e-mail: ice@ice-corp.com internet: http://www.ice-corp.com www..net
- i - index to text title page introduction 1 major findings 1 technology description assembly 2 die process and design 2 - 3 analysis results i assembly 4 analysis results ii die process and design 5 - 7 analysis procedure 8 tables overall evaluation 9 package markings 10 wirebond strength 10 die and package materials 11 horizontal dimensions 12 vertical dimensions 13 - 1 - introduction this report describes a construction analysis of the qlogic ISP1040B scsi i/o processor. six devices were supplied for the analysis which were packaged in 208-pin plastic quad flat packs (pqfps) and date coded 9721. major findings questionable items: 1 none. special features: three metal, twin-well cmos process. sub-micron gate lengths (0.5 micron). 1 these items present possible quality or reliability concerns. they should be discussed with the manufacturer to determine their possible impact on the intended application. - 2 - technology description assembly: devices were packaged in 208-pin plastic quad flat packs (pqfps). copper (cu) gull-wing leadframe tinned with tin-lead (snpb) solder. dimpled paddle for added package strength, paddle was seated on a heat-spreader (al). paddle was attached to the heatspreader by a thermal adhesion. heatspreader was not visible on x-ray (figure 2). paddle was constructed of copper (cu) and internally plated with silver (ag). lead-locking provisions (anchors) at all pins. lead-locking holes at paddle tie bars. thermosonic ball bond method employing 1.1 mil o.d. gold wire. sawn dicing (full depth). silver-epoxy die attach. die process fabrication process: selective oxidation cmos process employing twin-wells, on a p- substrate. overlay passivation: a layer of silicon-nitride over a multilayered glass over a thin layer of silicon dioxide. metallization: three levels of metal defined by dry-etch techniques. all levels consisted of aluminum with titanium-nitride caps and barriers and thin titanium adhesion layers. all metal levels utilized standard vias and contacts. - 3 - technology description (continued ) intermetal dielectrics (imd2 and imd1): both interlevel dielectrics consisted of multiple layers of deposited glass with an sog (spin on glass) between for planarization. pre-metal glass: a single layer of cvd glass (bpsg) over various densified oxides. reflow was done prior to contact cuts. polysilicon: a single layer of dry-etched polycide (poly and tungsten-silicide). this layer was used to form all gates on the die. diffusions: standard implanted n+ and p+ diffusions formed the sources/drains of transistors. oxide sidewall spacers were used to provide the ldd spacing and were left in place. isolation: locos (local oxide). a step was noted in the oxide at well boundaries. wells: twin-wells were employed on a p substrate (no epi was used). the step in the oxide indicates a twin-well process was employed. memory cells: a 7t sram cell design consisting of three polycide select gates, two polycide storage gates, and two polycide pull-up transistors. metal 3 was not directly used in the array. metal 2 provided bit lines, word line b, and distributed gnd and vcc. metal 1 provided cell interconnect and word lines a and c. polycide formed all gates. buried contacts: no buried (poly-to-diffusion) contacts were employed. no fuses were noted. anti-dishing patterns were employed and power bus lines were slotted and beveled for stress relief. - 4 - analysis results i assembly: figures 1 - 8 questionable items: 1 none. special features: dimpled paddle on heatspreader. general items: devices were packaged in 208-pin plastic quad flat packs (pqfps). overall package quality: normal. no defects were found on the external or internal portions of the packages. the leadframe was constructed of copper (cu) and tinned with tin-lead (snpb). external pins were well formed and tinning of the leads was complete. no gaps were noted at lead exits. the paddle was plated with silver. dimpled paddles were used for added package strength. the heatspreader (al) was used below the paddle to distribute heat evenly in the package. wirebonding: thermosonic ball bond method using 1.1 mil o.d. gold wire. no bond lifts occurred and bond pull strengths were good (see page 10). wire spacing and placement was also good; intermetallic formation was complete. all three metal levels formed the bond pad structure. die attach: silver-epoxy of normal quantity and quality. die dicing: die separation was by sawing (full depth) and showed normal quality workmanship. no large chips or cracks were present at the die surface. 1 these items present possible quality or reliability concerns. they should be discussed with the manufacturer to determine their possible impact on the intended application. - 5 - analysis results ii die process and design: figures 9 - 30 questionable items: 1 none. special features: three metal, twin-well, cmos process. sub-micron gate lengths (0.5 micron p-channel). general items: fabrication process: selective oxidation cmos process employing twin-wells in a p substrate (no epi). design and layout: die layout was clean and efficient. alignment was good at all levels. die surface defects: none. no contamination, toolmarks, or processing defects were noted. overlay passivation: a layer of silicon-nitride over a multilayered glass over a layer of silicon-dioxide. overlay integrity tests indicated defect-free passivation. edge seal was good. metallization: three levels of metal defined by dry-etch techniques. all levels consisted of aluminum with titanium-nitride caps and barriers and thin titanium adhesion layers. all metal levels utilized standard vias and contacts. 1 these items present possible quality or reliability concerns. they should be discussed with the manufacturer to determine their possible impact on the intended application. - 6 - analysis results ii (continued) metal patterning: all metal layers were defined by a dry etch of good quality. contacts and vias were completely surrounded by aluminum. metal 1 and 2 lines were widened around contacts. metal defects: none. no voiding or notching of the metal layers was found. no silicon nodules were observed following removal of the metal layers. metal step coverage: metal 3 aluminum thinning up to 25 percent. metal 2 aluminum thinning up to 65 percent thinning. metal 3 aluminum thinning up to 60 percent. no problems foreseen. intermetal dielectrics (imd2 and imd1): both interlevel dielectrics consisted of multiple layers of deposited glass with an sog (spin on glass) between for planarization. contacts: via and contact cuts appeared to be defined by a dry-etch process. no significant over-etching was found. the cap metals were cleared on metals 1 and 2 at vias for better adhesion. contact cuts were sloped at all levels to aid in metal coverage. pre-metal glass: a single layer of cvd glass (bpsg) over various densified oxides. reflow was done prior to contact cuts. polysilicon: a single layer of dry-etched polycide (poly and tungsten-silicide). this layer was used to form all gates on the die. definition and coverage was good. isolation: local oxide (locos). no problems were present at the birdsbeaks or elsewhere. diffusions: standard implanted n+ and p+ diffusions formed the sources/drains of transistors. an ldd process was used employing oxide sidewall spacers. the spacers were left in place. diffusions were not silicided. no problems were found in these areas. - 7 - analysis results ii (continued) wells: twin-wells in a p substrate. definition was normal. the p-well could not be delineated; however the step in the oxide at the well boundaries indicates a twin- well process was employed. buried contacts: no buried contacts were used. special items: esd sensitivity: two samples were subjected to esd tests which revealed all pins passed following pulses of + 4000v. - 8 - procedure the devices were subjected to the following analysis procedures: external inspection esd sensitivity test x-ray package section and material analysis decapsulation internal optical inspection sem inspection of assembly features and passivation passivation integrity test wirepull test passivation removal and inspect metal 3 delayer to metal 2 and inspect delayer to metal 1 and inspect delayer to poly and inspect poly structures and die surface die sectioning (90 for sem) * measure horizontal dimensions measure vertical dimensions die material analysis wdx analysis * delineation of cross-sections is by silicon etch unless otherwise indicated. - 9 - overall quality evaluation: overall rating: normal detail of evaluation package integrity g package markings g die placement n die attach quality n wire spacing n wirebond placement g wirebond quality g dicing quality g wirebond method thermosonic ball bonds using 1.1 mil gold wire. die attach method silver-epoxy dicing method sawn (full depth) die surface integrity: toolmarks (absence) n particles (absence) n contamination (absence) g process defects (absence) g general workmanship n passivation integrity g metal definition n metal integrity n contact coverage g contact registration g contact defects g g = good, p = poor, n = normal, np = normal/poor - 10 - package markings top bottom qlogic tm corp. (molded markings) ISP1040B 2405101 korea (plus numbers) mcl7d23/n9721d uspat#5,276,807 wirebond strength wire material: 1.1 mil diameter gold die pad material: aluminum material at package post: silver sample # 1 # of wires tested: 30 bond lifts: 0 force to break - high: 15 g - low: 10 g - avg.: 12.2 g - std. dev.: 1.7 - 11 - die material analysis passivation: a layer of silicon-nitride over a multilayered glass over a layer of silicon-dioxide. metal 3: aluminum titanium-nitride cap and barrier. a thin titanium adhesion layer under the barrier. intermetal dielectrics (imd2 and imd1): multiple layers of silicon-dioxide with an sog between. metal 2: aluminum with a nitride cap and barrier. a thin titanium adhesion layer under the barrier. metal 1: aluminum with a nitride cap and barrier. a thin titanium adhesion layer under the barrier. pre-metal glass: a borophosphosilicate glass (bpsg) containing 7.6 wt. percent phosphorous and 3.3 wt. percent boron, over a layer of densified oxide. polycide: tungsten-silicide on polysilicon. package material analysis leadframe: copper (cu) internal plating: silver (ag) external plating: tin-solder (snpb) die attach: silver-epoxy (ag) - 12 - horizontal dimensions die size: 9.1 x 8.2 mm (358 x 322 mils) die area: 74.5 mm 2 (115, 276 mils 2 ) min pad size: 0.06 x 0.06 mm (4 x 4 mils) min pad window: 0.05 x 0.05 mm (3.5 x 3.5 mils) min pad space: 20 microns min metal 3 width: 1.5 micron min metal 3 space: 1.2 micron min metal 3 pitch: 2.7 microns min via (m3 - m2): 0.7 micron (round) min metal 2 width: 0.9 micron min metal 2 space: 1.5 micron min metal 2 pitch: 2.4 microns min via (m2 - m1): 0.8 micron (round) min metal 1 width: 1.0 micron min metal 1 space: 1.6 micron min metal 1 pitch: 2.6 microns min contact: 0.8 micron (round) min polycide width: 0.5 micron min polycide space: 0.7 micron min gate length - (n-channel): 0.6 micron - (p-channel): 0.5 micron - 13 - vertical dimensions die thickness: 0.4 mm (16.5 mils) layers passivation 3: 0.45 micron passivation 2: 0.35 micron passivation 1: 0.08 micron metallization 3 - cap: 0.02 micron (approximate) - aluminum: 0.75 micron - barrier: 0.04 micron intermetal dielectric 2 (imd2) - glass 2: 0.45 micron - glass 1: 0.2 micron metallization 2 - cap: 0.02 micron (approximate) - aluminum: 0.55 micron - barrier: 0.07 micron intermetal dielectric 1 (imd1) - glass 3: 0.45 micron - glass 2: 0.12 micron - glass 1: 0.1 micron metallization 1 - cap: 0.03 micron (approximate) - aluminum: 0.6 micron - barrier: 0.1 micron pre-metal glass: 0.5 micron polycide - silicide: 0.15 micron - poly: 0.1 micron local oxide: 0.4 micron n+ diffusion: 0.2 micron p+ diffusion: 0.25 micron n-well: 4 microns (approximate) - ii - index to figures assembly figures 1 - 8 die layout and identification figures 9 - 10 physical die structures figures 11 - 27 color drawing of die structure figure 27a cell structure figures 28 - 30 integrated circuit engineering corporation qlogic ISP1040B figure 1. the qlogic ISP1040B package. mag. 2.5x. integrated circuit engineering corporation qlogic ISP1040B figure 2. the qlogic ISP1040B pinout. integrated circuit engineering corporation qlogic ISP1040B figure 3. x-ray view of the package. mag. 4x. figure 4. optical view of the package illustrating general construction. mag. 20x. integrated circuit engineering corporation qlogic ISP1040B die hea tspreader p addle plastic p ackage leadframe mag. 800x mag. 80x figure 5. optical views of lead forming and lead exit. integrated circuit engineering corporation qlogic ISP1040B leadframe cu leadframe snpb tinning mag. 320x mag. 100x figure 6. optical views of dicing and die attach. integrated circuit engineering corporation qlogic ISP1040B die cu p addle dimples die cu p addle ag epoxy ag internal pla ting hea tspreader al mag. 280x mag. 140x figure 7. sem views of die corner and edge seal. 60 . integrated circuit engineering corporation qlogic ISP1040B die a tt ach a tt acked during decapsula tion p addle die edge of p assiv a tion mag. 6800x mag. 350x figure 7a. sem section views of the bond pad and edge seal structure. integrated circuit engineering corporation qlogic ISP1040B au p assiv a tion met al 3 met al 2 met al 1 pre-met al glass edge of p assiv a tion edge of die mag. 600x, 60 mag. 800x mag. 925x, 60 integrated circuit engineering corporation qlogic ISP1040B figure 8. optical and sem views of typical wirebonds. au au p ad au leadframe die integrated circuit engineering corporation qlogic ISP1040B figure 9. the qlogic ISP1040B intact circuit die. mag. 18x. figure 9a. optical view of markings from the surface of the die. mag. 300x. integrated circuit engineering corporation qlogic ISP1040B figure 10. optical views of die corners. mag. 100x. integrated circuit engineering corporation qlogic ISP1040B slots glass etch, mag. 7700x mag. 6500x figure 1 1. sem section views illustrating general construction. integrated circuit engineering corporation qlogic ISP1040B p assiv a tion 3 local oxide pol y ga tes met al 3 met al 2 met al 1 s/d p assiv a tion 2 p assiv a tion 3 pol y ga te met al 3 met al 2 met al 1 imd 1 imd 2 p assiv a tion 2 mag. 8800x mag. 4400x figure 1 1a. sem views illustrating passivation coverage. 60 . integrated circuit engineering corporation qlogic ISP1040B anti-dishing p a tterns mag. 26,000x mag. 13,000x figure 12. sem section views of metal 3 line profiles. integrated circuit engineering corporation qlogic ISP1040B p assiv a tion 3 p assiv a tion 2 p assiv a tion 1 met al 3 imd 2 imd 2 imd 1 met al 2 p assiv a tion 3 p assiv a tion 2 met al 3 p assiv a tion 1 barrier adhesion la yer mag. 5900x mag. 3700x figure 13. t opological sem views of metal 3 patterning. 0 . integrated circuit engineering corporation qlogic ISP1040B via met al 3 met al 3 met al 2 mag. 9100x mag. 20,000x mag. 20,000x integrated circuit engineering corporation qlogic ISP1040B figure 14. perspective sem views of metal 3 integrity . 60 . met al 3 met al 2 aluminum 3 barrier 3 figure 15. sem section view of metal 3-to-metal 2 via. mag. 26,000x. integrated circuit engineering corporation qlogic ISP1040B p assiv a tion 3 p assiv a tion 2 p assiv a tion 1 met al 3 met al 2 mag. 26,000x mag. 14,800x figure 16. sem section views of metal 2 line profiles. integrated circuit engineering corporation qlogic ISP1040B imd 2 met al 2 imd 1 pre-met al glass cap 2 sog aluminum 2 barrier 2 adhesion la yer mag. 5000x mag. 2700x figure 17. t opological sem views of metal 2 patterning. 0 . integrated circuit engineering corporation qlogic ISP1040B met al 2 figure 18. perspective sem views of metal 2 integrity . 60 . mag. 7700x mag. 29,600x integrated circuit engineering corporation qlogic ISP1040B figure 18a. sem section view of a metal 2-to-metal 1 via. mag. 26,000x cap 2 imd 1 cap 1 aluminum 2 65% thinning aluminum 1 barrier 2 barrier 1 pre-met al glass met al 2 cap 2 aluminum 2 barrier 2 mag. 52,000x mag. 26,000x figure 19. sem section views of metal 1 line profiles. integrated circuit engineering corporation qlogic ISP1040B aluminum 1 barrier 1 locos imd 1 sog aluminum 1 barrier 1 adhesion la yer mag. 4200x mag. 4400x mag. 6200x integrated circuit engineering corporation qlogic ISP1040B figure 20. t opological sem views of metal 1 patterning. 0 . met al 1 met al 1 met al 1 residual glass mag. 32,200x mag. 6500x figure 21. perspective sem views of metal 1 integrity . 60 . integrated circuit engineering corporation qlogic ISP1040B met al 1 cap 1 aluminum 1 barrier 1 metal-to-poly metal-to-n+ metal-to-p+ integrated circuit engineering corporation qlogic ISP1040B figure 22. sem section views of typical contacts. mag. 26,000x. cap 1 aluminum 1 barrier 1 locos pol y step in local oxide aluminum 1 imd 1 locos n+ imd 1 locos oxide over diffusion aluminum 1 barrier 1 p+ barrier 1 mag. 6500x mag. 3100x figure 23. t opological sem views of polycide patterning. 0 . integrated circuit engineering corporation qlogic ISP1040B pol y diffusion pol y n+ p+ ga tes mag. 4000x mag. 8000x mag. 26,000x integrated circuit engineering corporation qlogic ISP1040B figure 24. sem views of polycide coverage. 60 . pol y pol y diffusion pol y locos silicide diffusion n-channel p-channel glass-etch integrated circuit engineering corporation qlogic ISP1040B figure 25. sem section views of typical transistors. mag. 52,000x. pre-met al glass ga te oxide silicide pol y n+ s/d silicide p+ s/d sidew all sp acer silicide pol y ga te oxide figure 26. optical view of well structure. mag. 1240x. integrated circuit engineering corporation qlogic ISP1040B figure 27. sem section views of a typical birdsbeak. mag. 13,000x mag. 52,000x n-well p-substra te met al 3 met al 1 local oxide local oxide pol y densified oxide ga te oxide figure 27a. color cross section drawing illustrating device structure. orange = nitride, blue = metal, y ellow = oxide, green = poly , red = dif fusion, and gray = substrate integrated circuit engineering corporation qlogic ISP1040B p+ s/d poly silicide n+ s/d n-well p-well local oxide passivation 3 passivation 2 passivation 1 aluminum 3 aluminum 2 aluminum 1 cap 3 sog barrier 3 cap 2 barrier 2 cap 1 barrier 1 imd 2 imd 1 pre-metal glass p-substrate metal 2 metal 1 delayered integrated circuit engineering corporation qlogic ISP1040B figure 28. perspective sem views of the sram cell array . mag. 4200x, 60 . bitline word lines residual glass word lines metal 1 metal 2 figure 29. t opological sem views of sram cell. mag. 2400x, 0 . integrated circuit engineering corporation qlogic ISP1040B bit bit gnd v cc word b bit bit word c word a mag. 2400x, 0 figure 30. t opological sem view and schematic of sram cell. w o r d c w o r d b w o r d a b i t 5 6 4 2 3 1 b i t 7 integrated circuit engineering corporation qlogic ISP1040B 1 2 3 4 5 6 7 |
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