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copyright ? cirrus logic, inc. 1999 (all rights reserved) CS4297 product data sheet crystalclear? soundfusion? audio codec 97 features n ac97 1.03 compatible n industry leading mixed signal technology n 18-bit stereo full-duplex codec with fixed 48 khz sampling rate n four analog line-level stereo inputs for connec- tion from line in, cd, video and aux n two analog line-level mono inputs for speaker- phone and internal pc beeper n mono microphone input switchable from two external sources n high quality differential cd input n dual stereo line level outputs n extensive power management support n meets or exceeds microsofts ? pc97 and pc98 audio performance requirements. description the CS4297 is a ac97 1.03 compatible stereo au- dio codec designed for pc multimedia systems. using the industry leading crystalclear delta-sig- ma and mixed signal technology, the CS4297 paves the way for pc97-compliant desktop, porta- ble, and entertainment pcs, where high-quality audio is required. the CS4297, when coupled with a dc97 pci au- dio accelerator such as the cs4610, implements a cost-effective, superior quality, two-chip audio so- lution. the CS4297 audio codec 97 and cs4610 pci audio accelerator are the first members of the soundfusion family of advanced pci audio prod- ucts for next generation multimedia pcs. ordering info CS4297-kq, 48-pin tqfp, 9x9x1 mm CS4297-jq, 48-pin tqfp, 9x9x1 mm ds242f5 jun 99 ac'97 registers line cd aux video mic1 mic2 phone pc_beep line_out alt_line_out mono_out analog input mux and output mixer ac-link and ac'97 registers pcm_data gain / mute controls input mux s output mixer mixer / mux selects ac- link pwr mgt sync bit_clk sdata_out sdata_in reset# pcm_data dac 18 bits adc 18 bits
2 ds242f5 CS4297 crystalclear? soundfusion? audio codec 97 table of contents characteristics and specifications.....................................................4 analog characteristics .................................................................................4 mixer characteristics....................................................................................5 absolute maximum ratings .........................................................................5 recommended operating conditions ..........................................................5 power down states......................................................................................6 digital filter characteristics .........................................................................6 digital characteristics ..................................................................................7 serial port timing.........................................................................................7 serial port timing.........................................................................................8 parameter and term definitions ..........................................................10 general description .................................................................................12 overview ...................................................................................................12 digital section ...........................................................................................12 ac-link ...............................................................................................12 ac97 register interface .....................................................................12 power management ............................................................................12 analog section ..........................................................................................12 output mixer .......................................................................................12 input mux ............................................................................................12 volume control ...................................................................................12 ac97 implementation ................................................................................13 digital hardware description ..............................................................15 ac97 ac-link ...........................................................................................15 ac-link protocol .................................................................................15 ac-link serial data output frame ...........................................................15 slot 0: serial data output slot tags ...................................................16 slot 1: ac97 register address ..........................................................16 slot 2: ac97 register write data ......................................................17 slot 3: left channel pcm playback data ...........................................17 slot 4: right channel pcm playback data .........................................17 ac-link audio input frame .......................................................................18 slot 0: serial data input slot tag bits ................................................18 slot 1: read-back address port .........................................................19 slot 2: read-back data port ...............................................................19 slot 3: left channel pcm capture data .............................................19 slot 4: right channel pcm capture data ..........................................20 ac-link reset modes ...............................................................................21 cold ac97 reset ...............................................................................21 warm ac97 reset .............................................................................21 ac97 register reset .........................................................................21 ac-link protocol violation - loss of sync ...............................................21 register interface .....................................................................................22 reset register (index 00h) .................................................................23 master volume (index 02h) ................................................................23 alternate volume (index 04h) .............................................................23 master mono volume (index 06h) ......................................................23 pc_beep volume (index 0ah) ..........................................................24 phone_in volume (index 0ch) ...........................................................24 microphone volume (index 0eh) ........................................................24 stereo analog mixer input gain registers (index 10 - 18h) ...............25
ds242f5 3 CS4297 crystalclear? soundfusion? audio codec 97 input mux select register (index 1ah) ............................................... 25 record gain register (index 1ch) ..................................................... 26 record gain mix (index 1eh) ............................................................. 26 general purpose register (index 20h) ............................................... 26 powerdown control/status register (index 26h) ...............................27 reserved registers (index 28h - 58h) ................................................ 27 crystal revision and fab id register (index 5ah) ............................. 27 vendor reserved registers (index 5c - 7ah) .................................... 28 vendor id1 (index 7ch) .....................................................................28 power management ................................................................................... 29 analog hardware description ............................................................ 29 line-level inputs ....................................................................................... 29 microphone level inputs ........................................................................... 30 mono inputs .............................................................................................. 30 line level outputs .................................................................................... 31 miscellaneous analog signals .................................................................. 32 power supplies .........................................................................................32 grounding and layout ............................................................................. 33 performance plots ................................................................................... 34 pin descriptions........................................................................................... 39 digital i/o pins .................................................................................... 39 analog i/o pins ..................................................................................40 filter and reference pins ................................................................... 42 power supplies ..................................................................................43 references ................................................................................................... 43 package dimensions ................................................................................... 44 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/ microsoft is a registered trademark of microsoft corporation in the united states and/or other countries. intel is a registered trademark of intel corporation. preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best effort s to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provi d ed as is without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. for the use of this information, nor for inf ringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, tradem arks, or trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electron ic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc. items from any cirrus logic website or disk may be printed for use by the user. however, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form o r by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc.furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. the names of products of cirrus logic, inc. or ot her vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. a list of cirrus logic, inc. trade- marks and service marks can be found at http://www.cirrus.com.
4 ds242f5 CS4297 crystalclear? soundfusion? audio codec 97 analog characteristics (standard test conditions unless otherwise noted: t ambient = 25 c, avdd = 5.0 v 5%, dvdd = 3.3 v 5%; 1 khz input sine wave; sample frequency, fs = 48 khz; z al =10 k w/ 680 pf load c dl = 18 pf load (note 1); measurement bandwidth is 20 hz - 20 khz, 18-bit linear coding; mixer registers set for unity gain. notes: 1. z al refers to the analog output pin loading and c dl refers to the digital output pin loading. 2. parameter definitions are given in the parameter and term definitions section. 3. path refers to the signal path used to generate this data. these paths are defined in the parameter and term definitions section. 4. this specification is guaranteed by silicon characterization, it is not production tested. parameter (note 2) symbol path (note 3) CS4297-kq CS4297-jq unit min typ max min typ max full scale input voltage line inputs mic inputs (20 db=0) mic inputs (20 db=1) a-d a-d a-d 0.91 0.91 0.091 1.00 1.00 0.10 - - - 0.91 0.91 0.091 1.00 1.00 0.10 - - - v rms v rms v rms full scale output voltage line,alternate line, and mono outputs d-a 0.91 1.0 1.13 0.91 1.0 1.13 v rms frequency response (note 4) analog ac = 0.5 db dac ac = 0.5 db adc ac = 0.5 db fr a-a d-a a-d 20 20 20 - - - 20,000 20,000 20,000 20 20 20 - - - 20,000 20,000 20,000 hz hz hz dynamic range stereo analog inputs to line_out mono analog inputs to line_out dac dynamic range adc dynamic range dr a-a a-a d-a a-d 90 85 85 85 95 90 90 90 - - - - - - - - 90 85 87 85 - - - - db fs a db fs a db fs a db fs a dac snr (-20 db fs input w/ ccir-rms filter on output) snr d-a - 63 - - - - db total harmonic distortion + noise (-3 db fs input signal): line/alternate line output dac adc (all inputs except phone/mic) adc (phone/mic) thd+n a-a d-a a-d a-d - - - - -94 -86 -87 -87 -80 -80 -80 -74 - - - - - - - - -74 -74 -74 -74 db fs a db fs a db fs a db fs a power supply rejection ratio (1 khz, 0.5 v rms w/ 5 v dc offset)(note 4) 40 60 - - 40 - db interchannel isolation 70 87 - - 87 - db spurious tone (note 4) - -100 - - -100 - db fs input impedance (note 4) 10 - - 10 - - k w external load impedance 10 - - 10 - - k w output impedance (note 4) - 730 - - 730 - w input capacitance (note 4) - 5 - - 5 - pf vrefout 2.0 2.3 2.5 2.0 2.3 2.5 v
ds242f5 5 CS4297 crystalclear? soundfusion? audio codec 97 mixer characteristics (for CS4297-kq only) absolute maximum ratings (avss1 = avss2 = dvss1 = dvss2 = 0 v) recommended operating conditions (avss1 = avss2 = dvss1 = dvss2 = 0 v) parameter min typ max unit mixer gain range span line in, aux, cd, video, mic1 mic2, phone, pc beep line out, alternate line out, mono out - - 46.5 94.5 - - db db step size all volume controls except pc beep pc beep - - 1.5 3.0 - - db db parameter min typ max unit power supplies +3.3 v digital +5 v digital analog -0.3 -0.3 -0.3 - - - 6.0 6.0 6.0 v v v total power dissipation (supplies, inputs, outputs) - 210 450 mw input current per pin (except supply pins) -10 - 10 ma output current per pin (except supply pins) -15 - 15 ma analog input voltage -0.3 - avdd+ 0.3 v digital input voltage -0.3 - dvdd + 0.3 v ambient temperature (power applied) -55 - 110 c storage temperature -65 - 150 c parameter symbol min typ max unit power supplies +3.3 v digital +5 v digital analog dvdd1, dvdd2 dvdd1, dvdd2 avdd1, avdd2 3.135 4.75 4.75 3.3 5 5 3.465 5.25 5.25 v v v operating ambient temperature 0 - 70 c
6 ds242f5 CS4297 crystalclear? soundfusion? audio codec 97 power down states digital filter characteristics notes: 5. stop band rejection determines filter requirements. out-of-band rejection determines audible noise. 6. the integrated out-of-band generated by the dac process, during normal pcm audio playback, over a bandwidth 28.8 khz to 100 khz, with respect to a 1 v rms dac output. parameter min typ max unit full power 3.3 v digital 5 v digital 5 v analog - 12.7 21.4 35.0 - ma adcs and input mux powerdown (pr0) 3.3 v digital 5 v digital 5 v analog - 5.32 9.80 23.1 - ma dacs powerdown (pr1) 3.3 v digital 5 v digital 5 v analog - 9.25 16.0 30.0 - ma analog mixer powerdown, vref on (pr2) 3.3 v digital 5 v digital 5 v analog - 9.20 16.0 10.7 - ma analog mixer powerdown, vref off (pr3) 3.3 v digital 5 v digital 5 v analog - 5.30 9.80 ~0.00 - ma ac-link powerdown (pr4) 3.3 v digital 5 v digital 5 v analog - 3.30 6.92 23.0 - ma internal clock disable (pr5) 3.3 v digital 5 v digital 5 v analog - 0.004 0.005 0.001 - ma alternate line output buffer powerdown (pr6) 3.3 v digital 5 v digital 5 v analog - 5.30 9.80 20.3 - ma parameter CS4297-kq CS4297-jq unit min typ max min typ max transition band 0.4 f s - 0.6 f s 0.4 f s - 0.6 f s hz stop band 0.6 f s -- 0.6 f s -- hz stop band rejection (note 4, 5) 74 - - 74 - - db out-of-band energy (note 6) - -82 - - -40 - db group delay (note 4) - - 1 - - 1 ms
ds242f5 7 CS4297 crystalclear? soundfusion? audio codec 97 digital characteristics (avss = dvss = 0 v (see grounding and layout section)) serial port timing parameter symbol min typ max unit low level input voltage v il - -0.16 x dvddv high level input voltage v ih 0.40 x dvdd - - v high level output voltage v oh 0.70 x dvdd 0.99 x dvdd - v low level output voltage v ol - 0.03 0.10 x dvdd v input leakage current (ac-link inputs) -10 - 10 a output leakage current (tri-stated ac-link outputs) -10 - 10 a output buffer drive current (note 4) - 100 400 a parameter symbol min typ max unit reset timing dvdd 90% maximum value to reset# inactive pre-delay (note 4) t vdd2rst# 1.5 - - ms reset# active low pulse width t rst_low 1.0 - - m s reset# inactive to bit_clk start-up delay t rst2clk - 42.7 - ms 1st sync active to codec ready set t sync2crd - 40.6 - m s clocks bit_clk frequency - 12.288 - mhz bit_clk period t clk_period - 81.4 - ns bit_clk output jitter (depends on xtal_in source) - - 750 ps bit_clk high pulse width t clk_high - 40.7 - ns bit_clk low pulse width t clk_low - 40.7 - ns sync frequency - 48 - khz sync period t sync_period - 20.8 - m s sync high pulse width t sync_high -1.3- m s sync low pulse width t sync_low - 19.5 - m s sync active to reset# inactive pre-delay t rst2snyc - - 250 ms data setup and hold output propagation delay from rising edge of bit_clk t prop -68ns output hold from falling edge of bit_clk t ohold 5- -ns input setup time from falling edge of bit_clk t isetup 10 - - ns input hold time from falling edge of bit_clk t ihold 0- -ns input signal rise time t irise 2-6ns input signal fall time t ifall 2-6ns output signal rise time (note 4) t ofall 246ns output signal fall time (note 4) t ofall 246ns
8 ds242f5 CS4297 crystalclear? soundfusion? audio codec 97 serial port timing (continued) misc. timing parameters end of slot 2 to bit_clk, sdata_in low (pr4) t s2_pdown - 16.24 16.36 m s sync pulse width (pr4) t sync_pr4 1.0 - - m s sync inactive (pr4) to bit_clk start-up delay t sync2clk 162.8 244 - ns setup to trailing edge of reset# (test modes) (note 4) t setup2rst 15 - - ns rising edge of reset# to hi-z delay (note 4) t off - - 25 ns bit_clk t rst_low t rst2clk t vdd2rst# vdd reset# sync t rst2sync power up timing clocks bit_clk sync t irise t ifall t orise t ifall t clk_high t clk_low t sync_high t sync_low t sync_period t clk_period codec ready from startup or fault condition bit_clk t sync2crd codec_ready sync
ds242f5 9 CS4297 crystalclear? soundfusion? audio codec 97 bit_clk t setup t hold t co sdata_out, sync sdata_in bit_clk t s2_pdown sdata_in sdata_out sync write to 0x20 data pr4 don't care slot 1 slot 2 sync_pr4 sync2clk t t reset# sdata_out, sync t setup2rst sdata_in, t off bit_clk hi-z data setup and hold pr4 powerdown test mode
10 ds242f5 CS4297 crystalclear? soundfusion? audio codec 97 parameter and term definitions ac97 specification refers to the audio codec 97 component specification ver 1.03 published by intel ? corporation [1]. ac97 controller refers to the control chip which interfaces to the CS4297s ac-link. this has been also called dc97 [1]. set refers to a digital value of vcc, 1, or high. clear or cleared refers to a digital value of gnd, 0 or low. ac97 registers refers to the 64-field register map defined in the ac97 specification. adc refers to a single analog-to-digital converter in the CS4297. adcs refers to the stereo pair of analog-to-digital converters. dac a single digital-to-analog converter in the CS4297. dacs refers to the stereo pair of digital-to-analog converters. codec refers to the set of adcs, dacs, and analog mixer portions of the CS4297. fft fast fourier transform. resolution the number of bits in the output words to the dacs, and in the input words to the adcs. differential nonlinearity the worst case deviation from the ideal code width. units in lsb. db fs a db fs is defined as db relative to full-scale. the a indicates an a weighting filter was used.
ds242f5 11 CS4297 crystalclear? soundfusion? audio codec 97 frequency response (fr) fr is the deviation in signal level verses frequency. the 0 db reference point is 1 khz. the amplitude corner, ac, lists the maximum deviation in amplitude above and below the 1 khz reference point. the listed minimum and maximum frequencies are guaranteed to be within the ac from minimum frequency to maximum frequency inclusive. dynamic range (dr) dr is the ratio of the rms full-scale signal level divided by the rms sum of the noise floor, in the presence of a signal, available at any instant in time (no change in gain settings between measurements). measured over a 20 hz to 20 khz bandwidth with units in db fs a. total harmonic distortion plus noise (thd+n) thd+n is the ratio of the rms sum of all non-fundamental frequency components, divided by the rms full-scale signal level. it is tested using a -3 db fs input signal and is measured over a 20 hz to 20 khz bandwidth with units in db fs a. signal to noise ratio (snr) snr, similar to dr, is the ratio of an arbitrary sinusoidal input signal to the rms sum of the noise floor, in the presence of a signal. it is measured over a 20 hz to 20 khz bandwidth with units in db. interchannel isolation the amount of 1 khz signal present on the output of the grounded ac-coupled line input channel with 1 khz 0 db signal present on the other line input channel. units in db. interchannel gain mismatch for the adcs, the difference in input voltage to get and equal code on both channels. for the dacs, the difference in output voltages for each channel when both channels are fed the same code. units in db. paths: [4] a-d: analog in, through the adc, onto the serial link. d-a: serial interface inputs through the dac to the analog output a-a: analog in to analog out (analog mixer)
12 ds242f5 CS4297 crystalclear? soundfusion? audio codec 97 general description overview the CS4297 is a mixed-signal serial codec based on the ac'97 specification. it is designed to be paired with a digital controller, typically located on the pci bus. the ac97 controller is responsible for all communications between the CS4297 and the rest of the system. the CS4297 functions as an analog mixer, a stereo adc, a stereo dac, and a control and digital audio stream interface to the ac97 controller. the CS4297 contains two distinct functional sec- tions: digital and analog. the digital section in- cludes the ac-link registers, power management support, sync detection circuitry, and ac-link serial port interface logic. the analog section in- cludes the analog input multiplexor (mux), stereo output mixer, mono output mixer, stereo adcs, stereo dacs, and analog volume controls. digital section ac-link the ac-link is the 5-wire digital interface to the ac97 controller chip. the CS4297 generates the bit_clk and the sdata_in signals. the ac97 controller must drive the sync, sdata_out and reset# signals. please refer to the ac-link timing section for the timing characteristics of the interface. the interface uses the sync signal, which is synchronous with bit_clk, to align the data within the frame. the ac-link signals may be referenced to either 5 volts or 3.3 volts. the CS4297 should use the same digital supply voltage as the ac97 controller chip. ac97 register interface the CS4297 implements the ac97 registers in accordance with the ac97 specification. see the register interface section for details on the CS4297s register set. power management the CS4297 supports a number of different power down modes. they are accessed through register 0x26h of the CS4297 register interface. please refer to the power management section of the data sheet. analog section please refer to figure 1, mixer diagram, for a high level graphical representation of the CS4297 ana- log mixer structure. output mixer there are two output mixers on the CS4297. the stereo output mixer sums together the analog inputs to the CS4297 according to the settings in the vol- ume control registers. the mono output mixer gen- erates a monophonic sum of the left and right channels from the stereo output mixer. however, the mono output mixer does not include the pc_beep and phone signals which are included in the stereo output mix. the stereo output mix is sent to the line_out and alt_line_out out- put pins of the CS4297. the mono output mix is sent to the mono_out output pin on the CS4297. input mux the input multiplexor controls which analog input is sent to the adcs. the output of the input mux is converted to stereo 18-bit digital pcm data and sent to the ac97 controller chip in slots 3 and 4 of the ac-link sdata_in signal. vo l u m e c o n t r o l the volume control registers of the ac97 register interface control analog input level to the input mixer, the master volume level, and the alternate
ds242f5 13 CS4297 crystalclear? soundfusion? audio codec 97 volume level. all analog volume controls, except pc_beep, implement controlled volume steps at nominally 1.5 db per step. pc_beep uses 3 db steps. the analog inputs allow a mixing range of +12 db of signal gain to -34.5 db of signal attenu- ation. the analog output volume controls allow from 0 db to -94.5 db of attenuation. the pc_beep input volume control allows from 0 db to -45 db of attenuation. ac97 implementation the CS4297 implements an ac97 compliant de- sign as defined in the intel audio codec 97 speci- fication version 1.03. due to certain design trade- offs and implementation decisions, the CS4297 dif- fers from the ac97 specification in a a few minor ways. the following list captures the specification deviations and the implementation decisions made to resolve ambiguities. 1. the rising edge of reset# must occur at least 1.5 ms after the digital power supply dvdd reaches 90% of maximum value. 2. the digital input voltage threshold levels are specified as percentages of the vdd digital power supply and are ttl level compatible. min v ih = 0.4 x vdd, max v il = 0.16 x vdd. 3. the delay between setting the pr4 bit to power- ing down the ac-link interface is implemented as 16.24 m s. figure 1. mixer diagram
14 ds242f5 CS4297 crystalclear? soundfusion? audio codec 97 4. the digital outputs are specified with a 18 pf ca- pacitive load. 5. the nominal vrefout level is 2.2 v. 6. all analog mixer input and output paths are de- signed to achieve greater than 90 dbfsa dynamic range. 7. all stereo-to-mono mixer stages contain a scale factor of -6 db to prevent output clipping of the summed mono signal. 8. when the analog mixer is powered down, the control registers for record select and record gain are frozen. the analog mixer stage must be powered up to gain access to these registers. 9. the headphone output pins have been imple- mented as an alternate line output. these pins must drive loads greater than 10 k w , just as the line outputs. 10. reserved bits in the ac97 serial data input stream may return a set or a cleared value. 11. the vref pin defined in the ac97 specifica- tion has been renamed to refflt. this pin is used for internal filtering and should not be used as an external circuit bias voltage. the vrefout pin is used to supply biasing voltages to external analog circuitry. this pin is not capable of supplying 5 ma of bias current as the specification indicates.
ds242f5 15 CS4297 crystalclear? soundfusion? audio codec 97 digital hardware description ac97 ac-link the ac-link is the serial connection between the ac97 controller and the CS4297. the interface consists of 5 signal lines (2 data, 2 clocks, and 1 re- set). the basic connections of the link are shown in figure 2. the signals will be explained in detail be- low. ac-link protocol the CS4297 serial interface is designed according to the ac97 specification to allow connection to any ac97 controller. an ac-link audio frame is divided into 13 slots; 1 16-bit slot and 12 20-bit slots. during each audio frame, data is passed bi-di- rectionally between the CS4297 and the ac97 controller. ac-link serial data output frame for the serial data output frame, the sync, bit_clk, and sdata_out signals are used. in the serial data output frame, data is passed on the sdata_out pin from the ac97 controller to the CS4297. in figure 3 and in the following frame slot definitions, the position of each bit lo- cation within the frame is noted. the first bit posi- tion in a new serial data frame is f0 and the last bit position in the serial data frame is f255. when sync goes active (high) and is sampled ac- tive by the CS4297 (on the falling edge of bit_clk), both devices are synchronized to a new serial data frame. the data on the sdata_out pin at this clock edge is the final bit of the previous serial data frames data. on the next rising edge of bit_clk, the first bit of slot 0 is driven by the ac97 controller on the sdata_out pin. the CS4297 latches in this data, as the first bit of the frame, on the next falling edge of the bit_clk clock signal. digital ac'97 controller cs4 297 sync bit_clk sdata_out sdata_in reset# figure 2. ac-link connections 20.8us (48 khz) tag phase data phase 12.288 mhz 81.4 ns sync bit_clk sdata_out sdata_in f0 f1 f2 f16 f15 f14 f13 f12 f36 f56 f76 0 f255 valid frame slot 1 valid slot 2 valid x x x x r/w wd15 wd14 f37 f57 lp17 lp16 rp17 lc17 lc16 rc17 rd15 rd14 0 0 0 0 0 codec ready slot 1 valid slot 2 valid bit frame position f0 f1 f2 f16 f15 f14 f13 f12 f36 f56 f76 f255 f37 f57 bit frame position f255 f255 x x 0 0 f97 f97 x slot 0 slot 1 slot 2 slot 3 slot 4 slots 5-12 figure 3. ac-link input and output framing
16 ds242f5 CS4297 crystalclear? soundfusion? audio codec 97 slot 0: serial data output slot tags the first slot, slot 0, is a 16-bit slot which contains information about the validity of data for the remaining 12 slots. the 16 bits of this slot are defined as: valid frame - bit 15 determines if any of the following slots contain valid data. if this bit is set, at least one of the other 12 slots contain valid data. if this bit is cleared, the remainder of the frame will be ig- nored. slot 1 valid - bit 14 indicates the validity of data in the serial data output slot 1. if this bit is set, slot 1 contains valid data. if this bit is cleared, slot 1 will be ignored. slot 2 valid - bit 13 indicates the validity of data in the serial data output slot 2. if this bit is set, slot 2 contains valid data. if this bit is cleared, slot 2 will be ignored. slot 3 valid - bit 12 indicates the validity of data in the serial data output slot 3. if this bit is set, slot 3 contains valid data. if this bit is cleared, slot 3 will be ignored. slot 4 valid - bit 11 indicates the validity of data in the serial data output slot 4. if this bit is set, slot 4 contains valid data. if this bit is cleared, slot 4 will be ignored. slot 0 bits 10 through 0 represent unimplemented data slots in the CS4297 and will be ignored. the input pcm data to the CS4297 on the sdata_out pin is shifted out msb justified (most significant bit of the actual data of the 20-bit slots). in any case where there are less than 20-bits of valid data for a slot (i.e.: 18-bit pcm data in a 20-bit slot), the trailing bits of the slot must be cleared by the ac97 con- troller. for slots 5 - 12, the ac97 controller should clear each bit in each frame, however data in these slots will be ignored. slot 1: ac97 register address slot 1 indicates the register address of the current frames register access. the 20 bits of this slot are de- fined as: table 1. command address port bit definition r/w - bit 19 is the read/write bit. when this bit is set, a read of the ac97 register specified by the register index will occur. when the bit is cleared, a write will occur. in both cases, register accesses only occur when the slot valid bit 14 of slot 0 (f1) corresponding to slot 1 is set. ri6 - ri0 - bits 18-12 contain the 7-bit register index to the ac97 registers in the CS4297. all registers are defined at word addressable boundaries. bit 12 will be saved for historic purposes but is not decoded. bits 11-0 are reserved and should always be cleared the ac97 controller. f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 bit 1514131211109876543210 valid frame slot 1 valid slot 2 valid slot 3 valid slot 4 valid not used f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33 f34 f35 bit 191817161514131211109876543210 r/w ri6 ri5 ri4 ri3 ri2 ri1 ri0 reserved
ds242f5 17 CS4297 crystalclear? soundfusion? audio codec 97 slot 2: ac97 register write data slot 2 indicates the register data of the current frames register write access.the 20 bits of this slot are defined as: wd15 - wd0 - bits 19-4 contain the 16-bit value to be written to the register. bits 3-0 are ignored, but should always be cleared. if the access is a read, this slot is ignored. the data in slot 2 will only be valid when the slot valid bit 13 of slot 0 (f2) corresponding to slot 2 is set. note : for any write to an ac97 register, the write is defined to be an atomic access. this means that when the slot valid bit for slot 1 is set, the slot valid bit for slot 2 should always be set during the same audio frame. no write access may be split across 2 frames. slot 3: left channel pcm playback data slot 3 contains the left channel data. the 20 bits of this slot are defined as: lp17 - lp0 - this is the 18-bit pcm playback 2s compliment data for the left channel dac in the CS4297. the pcm playback data will be taken from the most significant 18 of the 20 bits in the slot. the least significant 2 bits will be ignored. any pcm data from the ac97 controller that is not at least 18- bits should be left justified in slot 3 and dithered or zero-padded in the unused bit positions. slot 4: right channel pcm playback data slot 4 contains the right channel data. the 20 bits of this slot are defined as: rp17 - rp0 - this is the 18-bit pcm playback 2s compliment data for the right channel dac in the CS4297. the pcm playback data will be taken from the most significant 18 of the 20 bits in the slot. the least significant 2 bits will be ignored. any pcm data from the ac97 controller that is not at least 18- bits should be left justified in slot 4 and dithered or zero-padded in the unused bit positions. f36 f37 f38 f39 f40 f41 f42 f43 f44 f45 f46 f47 f48 f49 f50 f51 f52 f53 f54 f55 bit 19181716151413121110987654 3210 wd15 wd14 wd13 wd12 wd11 wd10 wd9 wd8 wd7 wd6 wd5 wd4 wd3 wd2 wd1 wd0 reserved f56 f57 f58 f59 f60 f61 f62 f63 f64 f65 f66 f67 f68 f69 f70 f71 f72 f73 f74 f75 bit 191817161514131211109876543210 lp17 lp16 lp15 lp14 lp13 lp12 lp11 lp10 lp9 lp8 lp7 lp6 lp5 lp4 lp3 lp2 lp1 lp0 reserved f76 f77 f78 f79 f80 f81 f82 f83 f84 f85 f86 f87 f88 f89 f90 f91 f92 f93 f94 f95 bit 191817161514131211109876543210 rp17 rp16 rp15 rp14 rp13 rp12 rp11 rp10 rp9 rp8 rp7 rp6 rp5 rp4 rp3 rp2 rp1 rp0 reserved
18 ds242f5 CS4297 crystalclear? soundfusion? audio codec 97 ac-link audio input frame an ac-link serial data input frame uses the sync, bit_clk, and sdata_in signals are used. in the serial data input frame, data is passed on the sdata_in pin from the CS4297 to the ac97 controller. the data format for the input frame is very similar to the output frame. synchro- nization of the CS4297 to the ac97 controller is performed in the same manner. please refer to fig- ure 3 for the serial port timing waveform. slot 0: serial data input slot tag bits the first slot, slot 0, is a 16-bit slot which contains information about the validity of data for the remaining 12 slots. the 16 bits of this slot are defined as: codec ready - bit 15 indicates the readiness of the CS4297s ac-link and the ac97 control and status registers. immediately after a cold reset this bit will be returned to the ac97 controller cleared. once the CS4297s clocks and voltages are stable, this bit will be set. until the codec ready bit is set, no ac- link transactions should be attempted by the ac97 controller. note: this codec ready bit does not indicate readiness of the dacs, adcs, vref, or any other analog function. those must be checked in the powerdown/status register by the ac97 controller. any accesses to the CS4297 while this bit is cleared will be ignored. slot 1 valid - bit 14 indicates the validity of data in the serial data input slot 1. if this bit is set, slot 1 contains valid data. if this bit is cleared, slot 1 should be ignored by the ac97 controller. slot 2 valid - bit 13 indicates the validity of data in the serial data input slot 2. if this bit is set, slot 2 contains valid data. if this bit is cleared, slot 2 should be ignored by the ac97 controller. slot 3 valid - bit 12 indicates the validity of data in the serial data input slot 3. if this bit is set, slot 3 contains valid data. if this bit is cleared, slot 3 should be ignored by the ac97 controller. slot 4 valid - bit 11 indicates the validity of data in the serial data input slot 4. if this bit is set, slot 4 contains valid data. if this bit is cleared, slot 4 should be ignored by the ac97 controller. slot 0 bits 10 through 0 represent unimplemented data slots in the CS4297 and should be ignored by the ac97 controller. f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 bit 1514131211109876543210 codec ready slot 1 valid slot 2 valid slot 3 valid slot 4 valid not used
ds242f5 19 CS4297 crystalclear? soundfusion? audio codec 97 slot 1: read-back address port slot 1 is the read-back address port. the read-back address port is used to echo the ac97 register address back to the ac97 controller when the CS4297 has been issued a read request from the previous frame. included only for historical purposes, this address may be used by the ac97 controller to synchro- nize read accesses. the CS4297 will only echo the register index for a read access. write accesses will not return valid data in slot 1. the 20 bits of this slot are defined as: ri6 - ri0 - bits 18-12 contain the 7-bit register index to the ac97 registers in the CS4297. all other undefined bits in slot 1 will be returned by the CS4297 cleared. slot 2: read-back data port slot 2 is the read-back data port. the read-back data port contains the register data requested by the ac97 controller from the previous read request. it reflects the valid data bits from the 16-bit ac97 reg- ister being read. all read requests will return read addresses and data on the following serial data frame. the 20 bits of this slot are defined as: wd15 - wd0 - bits 19-4 contain the 16-bit ac97 register value returned to the ac97 controller by the CS4297. bits 3-0 are undefined in slot 2 and will be returned by the CS4297 cleared. note: the CS4297 implements bus-keeper logic for its 16-bit registers. any read accesses from ac97 registers with undefined bits may return a set or clear value. the value returned depends on the state of that bit location from the previous access. no ac97 controller software dependencies should exist on the value of undefined ac97 register bits. for a list of the undefined bits in the ac97 register map, see table 2, mixer registers. slot 3: left channel pcm capture data slot 3 contains the left channel data. the 20 bits of this slot are defined as: lp17 - lp0 - this is the 18-bit pcm 2s compliment capture data from the left channel adc in the CS4297. the pcm capture data is left justified in the most significant 18 of the 20 bits in the slot. the least significant 2 bits will be cleared. f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33 f34 f35 bit 191817161514131211109876543210 0ri6ri5ri4ri3ri2ri1ri0000000000000 f36 f37 f38 f39 f40 f41 f42 f43 f44 f45 f46 f47 f48 f49 f50 f51 f52 f53 f54 f55 bit 191817161514131211109876543210 rd15 rd14 rd13 rd12 rd11 rd10 rd9 rd8 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 0 0 0 0 f56 f57 f58 f59 f60 f61 f62 f63 f64 f65 f66 f67 f68 f69 f70 f71 f72 f73 f74 f75 bit 191817161514131211109876543210 lp17 lp16 lp15 lp14 lp13 lp12 lp11 lp10 lp9 lp8 lp7 lp6 lp5 lp4 lp3 lp2 lp1 lp0 0 0
20 ds242f5 CS4297 crystalclear? soundfusion? audio codec 97 slot 4: right channel pcm capture data slot 4 contains the right channel data. the 20 bits of this slot are defined as: rp17 - rp0 - this is the 18-bit pcm 2s compliment capture data from the right channel adc in the CS4297. the pcm capture data is left justified in the most significant 18 of the 20 bits in the slot. the least significant 2 bits will be cleared. slots 5 through 12 are not implemented in the CS4297, and therefore will always be returned cleared for all bits. f76 f77 f78 f79 f80 f81 f82 f83 f84 f85 f86 f87 f88 f89 f90 f91 f92 f93 f94 f95 bit 191817161514131211109876543210 rp17 rp16 rp15 rp14 rp13 rp12 rp11 rp10 rp9 rp8 rp7 rp6 rp5 rp4 rp3 rp2 rp1 rp0 0 0
ds242f5 21 CS4297 crystalclear? soundfusion? audio codec 97 ac-link reset modes there are 3 methods to reset the CS4297. these are defined in the ac97 specification as cold ac97 reset, warm ac97 reset, and ac97 register reset. a cold ac97 reset is required to restart the ac-link when bit pr5 is set in register (0x26). cold ac97 reset a cold reset is performed simply by asserting re- set# in accordance with the minimum timing specifications in the serial port timing section of the data sheet. once de-asserted, all of the ac97 registers will be reset to their default power-on states and the bit_clk clock and sdata_in signals will be reactivated. the timing of power- up/reset events is discussed in detail in the power management section of the data sheet. warm ac97 reset the CS4297 may also be reactivated when the ac- link is powered down (refer to the pr4 bit descrip- tion in the power management section of the data sheet) by a warm reset. a warm reset allows the ac-link to be reactivated without losing informa- tion in the ac97 registers. warm reset is initiat- ed when the sync signal is driven high for at least 1 s and then driven low in the absence of the bit_clk clock signal. the bit_clk clock will not restart until at least 2 normal bit_clk clock periods ( 162.8 ns) after the sync signal is de-as- serted. ac97 register reset the third reset mode provides a register reset to the CS4297. this is available only when the CS4297s ac-link is active and the codec ready bit is set. the register reset allows all user accessible regis- ters in the CS4297 to be reset to their default, pow- er-up values. a register reset occurs when any value is written to ac97 register 00h. ac-link protocol violation - loss of sync the CS4297 was designed to handle sync proto- col violations. the following are situations where the sync protocol has been violated: the sync signal is not sampled high for exactly 16 bit_clk clock cycles at the start of an audio frame. the sync signal is not sampled high on the 256th bit_clk clock period after the previous sync assertion. the sync signal goes active high before the 256th bit_clk clock period after the previous sync assertion. upon loss of synchronization with the ac97 con- troller, the CS4297 will mute all analog outputs and clear the codec ready bit in the serial data input frame until 2 valid frames are detected. during this detection period, the CS4297 will ignore all regis- ter reads and writes and will discontinue the trans- mission of pcm capture data.
22 ds242f5 CS4297 crystalclear? soundfusion? audio codec 97 register interface table 2. mixer registers reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 00h reset 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0150h 02h master volume mute x ml5 ml4 ml3 ml2 ml1 ml0 x x mr5 mr4 mr3 mr2 mr1 mr0 8000h 04h alternate line out volume mute x ml5 ml4 ml3 ml2 ml1 ml0 x x mr5 mr4 mr3 mr2 mr1 mr0 8000h 06h master volume mono mute x x x x x x x x x mm5 mm4 mm3 mm2 mm1 mm0 8000h 08h reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h 0ah pc_beep volume mute x x x x x x x x x x pv3 pv2 pv1 pv0 x 0000h 0ch phone volume mute x x x x x x x x x x gn4 gn3 gn2 gn1 gn0 8008h 0eh mic volume mute x x x x x x x x 20db x gn4 gn3 gn2 gn1 gn0 8008h 10h line in volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 12h cd volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 14h video volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 16h aux volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 18h pcm out vol mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 1ah record select x x x x x sl2 sl1 sl0 x x x x x sr2 sr1 sr0 0000h 1ch record gain mute x x x gl3 gl2 gl1 gl0 x x x x gr3 gr2 gr1 gr0 8000h 1eh reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h 20h general purpose 0 0 0 0 0 0 mix ms lpbk 0 0 0 0 0 0 0 0000h 22h reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h 24h reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h 26h powerdown ctrl/stat 0 pr6 pr5 pr4 pr3 pr2 pr1 pr0 0 0 0 0 ref anl dac adc 000fh 28h reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 5ah crystal revision and fab id 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0301h .. .. 76hcrystal reserved xxxxxxxxx x xxxxxxxxxxh 78hcrystal reserved xxxxxxxxx x xxxxxxxxxxh 7ahcrystal reserved xxxxxxxxx x xxxxxxxxxxh 7ch vendor id1(cr) 0 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 4352h 7eh vendor id2(y2) 0 1 0 1 1 0 0 1 0 0 0 0 0 0 1 1 5903h
ds242f5 23 CS4297 crystalclear? soundfusion? audio codec 97 reset register (index 00h) any write to this register causes a register reset of the ac97 registers to occur. this forces all registers to return to their default state. reads from the reset register will return configuration information about the part. the CS4297 supports 18-bit dac and adc digital audio channels and the headphone output (in the form of the alternate line output). the value read from this register will always be 0x0150h. master volume (index 02h) the master volume control register controls the line_out signals volume. each register step corre- sponds to 1.5 db volume adjustment, thus offering a range between 0 db and 94.5 db of attenuation. mute - the msb of this register controls a master analog mute for the line_out_l and the line_out_r output signals. ml5 - ml0 - these bits control the left channels volume mr5 - mr0 - these bits control the right channels volume. the default value for this register is 8000h, corresponding to 0 db attenuation and mute on. alternate volume (index 04h) the alternate volume control register is used to control the alt_line_out signals volume. each reg- ister step corresponds to 1.5 db volume adjustment, thus offering a range between 0 db and 94.5 db of attenuation. mute - the msb of this register controls a master analog mute for the alt_line_out_l and the alt_line_out_r output signals. ml5 - ml0 - these bits control the left channels volume. mr5 - mr0 - these bits control the right channels volume. the default value for this register is 8000h, corresponding to 0 db attenuation and mute on. master mono volume (index 06h) the master mono volume control register controls the mono_out signals volume. each register step corresponds to 1.5 db volume adjustment, thus offering a range between 0 db and 94.5 db of attenuation. the msb of this register controls a master analog mute for the mono_out. bits mm5 - mm0 of the register are used to control the actual volume levels. the default value for this register is 8000h, corresponding to 0 db attenuation and mute on. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute x ml5 ml4 ml3 ml2 ml1 ml0 x x mr5 mr4 mr3 mr2 mr1 mr0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute x ml5 ml4 ml3 ml2 ml1 ml0 x x mr5 mr4 mr3 mr2 mr1 mr0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute x x x x x x x x x mm5 mm4 mm3 mm2 mm1 mm0
24 ds242f5 CS4297 crystalclear? soundfusion? audio codec 97 pc_beep volume (index 0ah) the pc_beep volume control register controls the mix of the pc_beep in the analog output mixer. each register step corresponds to 3.0 db volume adjustment, thus offering a range between 0 db and 45 db of attenuation. the msb of this register controls a master analog mute for the pc_beep. bits pv3 - pv0 of the register control the actual volume levels. note: the 4 valid data bits for the pc_beep volume control are not aligned to the least significant bits of the register. valid data bit 0 (pv0) corresponds to bit d1 of the register. also, each step of the value (pv3 - pv0) corresponds to a 3 db step in volume control, as opposed to all other gain controls, which have a 1.5 db step size. also note that the default state of the mute bit (bit d15) is cleared, meaning that the pc_beep is un- muted on power-up. phone_in volume (index 0ch) this register controls the gain level of the phone_in input source to the ouput mixer. each register step corresponds to a 1.5 db gain adjustment allowing a range of 12 db to -34.5 db of gain. the msb controls an analog mute for the phone_in signal. the default values for phone_in is 8008h, corresponding to 0 db attenuation and mute on. microphone volume (index 0eh) this register controls the gain level of the mic_in input source to the input mixer. it also controls the +20 db gain block which connects to the input volume control and to the input record mux. each register step (gn4 - gn0) corresponds to a 1.5 db gain adjustment allowing a range of 12 db to -34.5 db of gain. the 20db bit, when set, enables the 20 db gain block. the msb controls an analog mute for the mic_in signal. the mic_in source is selected through the general purpose register the default values for mic_in is 8008h, corresponding to 0 db attenuation and mute on. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute x x x x x x x x x x pv3 pv2 pv1 pv0 x d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mutexxxxxxxxxxgn4gn3gn2gn1gn0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mutexxxxxxxx20dbxgn4gn3gn2gn1gn0
ds242f5 25 CS4297 crystalclear? soundfusion? audio codec 97 stereo analog mixer input gain registers (index 10 - 18h) these registers control the gain levels of the analog input sources to the input mixer. each register step for all registers corresponds to 1.5 db gain adjustment, thus allowing a range of 12 db to -34.5 db of gain. the msb of these registers control an analog mute for each source to input mixer. bits gx4 - gx0 of the registers are used to control the gain levels for each source. the gain mapping for these bits is shown in table 3. for the stereo source registers (10h through 18h), the default values are 8808h, corresponding to 0 db at- tenuation for both channels, and mute on. input mux select register (index 1ah) this register selects the input source to pass to the adcs for capturing pcm data. the ac97 specification allows for independent control of the left and right channels for this mux. bits sl2 - sl0 provide the de- code for the left input mux, and bits sr2 - sr0 provide the decode for the right. shown below are the pos- sible values for each of these decodes: the default power-on value for this register is 0000h, selecting the mic inputs for both channels. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 xxxxxsl2sl1sl0xxxxxsr2sr1sr0 gx4 - gx0 gain level 00000 +12 db 00001 +10.5 db 00111 +1.5 db 01000 0 db 01001 -1.5 db 11111 -34.5 db table 3. analog mixer input gain values sx2 - sx0 record source 0mic 1 cd input 2 video input 3 aux input 4 line input 5stereo mix 6 mono mix 7 phone input table 4. input mux selection options
26 ds242f5 CS4297 crystalclear? soundfusion? audio codec 97 record gain register (index 1ch) this register controls the input gain on the analog source which is applied after the input mux and before the adcs. the 4-bit value allows for 0 db to +22.5 db of gain in 1.5 db steps. the most significant bit of the register controls an analog mute which mutes the signal prior to the adcs. the following table shows the possible gain values available: the default value for this register is 8000h, which corresponds to 0 db gain with mute on. record gain mix (index 1eh) the CS4297 does not support the optional 3rd adc for the mic pcm input. the record gain mix register has no function in the CS4297. writes to this register are ignored, and reads from this register will always return 0000h. general purpose register (index 20h) this register controls miscellaneous facets of the CS4297 mixer. the only bits which have defined func- tions in the CS4297 are the mix, ms, and lpbk bits. the mix bit selects which data to send to the mono output path. a cleared value enables the mono mix out (a mix of the 5 analog stereo sources plus pcm_out), while a set value passes the mic to the output. the ms (mic select) bit determines which of the 2 mic inputs are passed to the rest of the mixer. a cleared value selects the mic1 input, while a set value selects the mic2 input. the lpbk bit enables adc/dac loopback mode which is used to facilitate performance evaluation of the CS4297. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute x x x gl3 gl2 gl1 gl0 x x x x gr3 gr2 gr1 gr0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 000000mixmslpbk0000000 gx3 - gx0 gain 1111 +22.5 db 0000 0 db table 5. input mux selection options
ds242f5 27 CS4297 crystalclear? soundfusion? audio codec 97 powerdown control/status register (index 26h) the bits in this register correspond to the ac97 defined powerdown and status functions. see the follow- ing tables for the definitions of the individual bits which the CS4297 supports. reserved registers (index 28h - 58h) these registers are reserved for future use by the ac97 specification. the CS4297 ignores writes to these registers. crystal revision and fab id register (index 5ah) this vendor reserved register is being used by the CS4297 to indicate the revision level of the CS4297 as well as the fab id where the part was manufactured. this is in addition to the vendor id registers located below. the revision level is indicated in bits d11:8 and will be 03h for the release revision of the chip. the fab id is indicated in bits d3:0 and will be 01h. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 pr6 pr5 pr4 pr3 pr2 pr1 pr0 0 0 0 0 ref anl dac adc bit name function ref vref at nominal levels anl analog mixers, mux, and vol- ume controls ready dac dac ready to accept data adc adc ready to transmit data table 6. codec powerdown status bits d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0000001100000001 bit name function pr0 adcs and input mux powerdown pr1 dacs powerdown pr2 analog mixer powerdown (vref still on) pr3 analog mixer powerdown (vref off) pr4 ac-link powerdown (bit_clk off) pr5 internal clock disable pr6 alternate line output buffer powerdown table 7. codec powerdown control bits
28 ds242f5 CS4297 crystalclear? soundfusion? audio codec 97 vendor reserved registers (index 5c - 7ah) these registers are reserved for future use by the crystal as needed. the CS4297 ignores writes to these registers, and read values from these registers will return 0000h. vendor id1 (index 7ch) vendor id2 (index 7eh) the vendor id registers provide a means to determine the manufacturer of the ac97 part within a system. for the CS4297, the id registers contain the ascii code for the first 3 letters of crystal (cry). the final byte of register id2 is a revision field for the part. in the case of the CS4297, the revision is 03h. thus, register id1 contains the value 4352h, and register id2 contains 5903h. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0100001001010010 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0101100100000011 register # vendor id value 7ch 4352h 7eh 5903h table 8. vendor id register values
ds242f5 29 CS4297 crystalclear? soundfusion? audio codec 97 power management the ac97 specification defines a mixer register called the powerdown control/status register (in- dex 26h) for controlling power management func- tions within the CS4297. in the CS4297, 7 of these bits (bits 14 - 8) have defined functions. in effect, all portions of the codec can be shut down individ- ually and powered back up by a single cold or warm reset sequence. the following table shows the mapping of the pow- er control bits to the functions they manage: table 9. powerdown gpr bit functions when, for example, pr0 is set, the main adcs and the input mux are shut down and the adc bit (bit 0 in register 26h) is cleared to indicate the adcs are no longer in a ready state. the same is true for the dacs, the analog mixers, and the ref- erence voltage (vrefout). when the pr bit for one of these portions of the mixer is cleared, the mix- er section will begin a power-on process, and the corresponding powerdown status bit will be set when the hardware is in a ready state. bit pr4, which shuts down the ac-link, causes the ac-link to turn off the bit_clk and drive sdata_in to a 0. it also ignores sync and sdata_out in their normal capacities. to re- store operation to the part from this state, either a cold or a warm reset is required (see cold ac97 reset and warm ac97 reset). a cold reset will restore all mixer registers to their power-on default values. a warm reset will not alter the values of any mixer register (with the exception of clearing the pr4 bit of register 26h). setting bit pr5 causes a global powerdown of the codec. in this state, all internal clocks of the CS4297 are shut down. a cold reset is the only way to restore operation to the CS4297 in the glo- bal powerdown state. one important note: the CS4297 does not auto- matically mute any input or output when the pow- erdown bits are set. it is left to the software driver controlling the ac97 device to manage muting the input and output analog signals before putting the part into any power management state. analog hardware description the analog hardware consist of a four line-level stereo inputs, two selectable mono microphone in- puts, two mono inputs, a mono output, and dual, in- dependent stereo line outputs. this section describes the analog hardware needed to interface with these pins. line-level inputs the analog inputs consist of four stereo analog in- puts and four mono inputs. as shown in figure 1, the input to the adcs comes from the input mux which selects one of the following: phone (mono), aux, video, cd, mic1 or mic2 (mono), line, ste- reo output mix, or the mono output mix (mono). unused analog inputs should be connected together and then connected through a capacitor to analog ground or tied to the vrefout line directly. the analog input mixer is designed to accommo- date five stereo inputs and one mono input. these inputs are: a stereo line-level input (line), a mono microphone input (mic), a stereo cd-rom input (cd), a stereo auxiliary line-level input (aux), and the pcm output from the dacs. each of the stereo inputs has separate volume controls for each channel and one mute control for each left/right pair. the mono microphone input has one mute and one volume control. pr bit function pr0 main adcs and input mux powerdown pr1 main dacs powerdown pr2 analog mixer powerdown (vref on) pr3 analog mixer powerdown (vref off) pr4 ac-link powerdown (bit_clk off) pr5 internal clock disable pr6 alternate line out buffer powerdown
30 ds242f5 CS4297 crystalclear? soundfusion? audio codec 97 the inputs to the output mixer are: the input mixer output, the pc beep mono input, and the phone mono input. all analog inputs to the CS4297, including cd_gnd, should be capacitively coupled to the input pins. since many analog levels can be as large as 2v rms , the circuit shown in figure 4 can be used to attenuate the analog input by 6 db (to 1 v rms) which is the maximum voltage allowed for all the stereo line-level inputs: line_in, aux_in, and video_in. the cd line-level inputs have an extra pin, cd_gnd, which provides a pseudo-differential input for both cd_l and cd_r. this pin takes the common-mode noise out of the cd inputs when connected to the ground coming from the cd ana- log source. connecting the cd pins as shown in figure 5 provides extra attenuation of common mode noise coming from the cdrom drive, there- by producing a higher quality signal. one percent resistors are recommended since the better the re- sistors match, the better the common-mode attenu- ation of unwanted signals. if cd is not used, the inputs should be connected through ac capacitors to analog ground or connected to vrefout. microphone level inputs the microphone level inputs, mic1 and mic2, in- clude a selectable -34.5 db to +12 db gain stage for interfacing to an external microphone. an addition- al 20 db gain block is also available. figure 6 illus- trates a single-ended microphone input buffer circuit that will support lower gain mics. the cir- cuit in figure 6 supports dynamic mics and phan- tom-powered mics that use the right channel (ring) of the jack for power. mono inputs the mono input, pc_beep, is useful for mixing the output of the beeper (timer chip), provided in all pcs, with the rest of the audio signals. the at- tenuation control allows 16 levels in -3 db steps. in addition, a mute control is provided. the attenuator is a single channel block with the resulting signal sent to the output mixer where it is mixed with the left and right outputs. figure 7 illustrates a typical input circuit for the pc_beep input. if pc_beep is driven from a cmos gate, the 4.7 k w should be tied to agnd instead of va+. although this input is described for a low-quality beeper, the input is of the same high-quality as all other analog inputs and may be used for other purposes. the mono input, phone_in, can be used to inter- face to the output of a modem analog front end 6.8 k w 6.8 k w 1.0 m f 1.0 m f r l 6.8 k w 6.8 k w figure 4. line inputs 6.8 k w 6.8 k w 1.0 m f 1.0 m f cd_l cd_r 6.8 k w 6.8 k w 3.4 k w cd_gnd 2.0 m f 3.4 k w (all resistors 1%) figure 5. differential cdrom in 0.33 m f 220 pf np o 3.3 m f + 6.8 k w 47 k w mc33078 or mc33178 vrefout mic1 or mic2 1 m f + 0.33 m f x7r 2 k w 47 k w 0.1 m f 47 w 100 pf np o figure 6. microphone input
ds242f5 31 CS4297 crystalclear? soundfusion? audio codec 97 (afe) chip so that modem dialing signals and pro- tocol negotiations may be monitored through the audio system. like all other analog inputs, this pin must be ac coupled and the input signal must be limited to 1 v rms . line level outputs the analog output section provides a stereo line- level output and an alternate stereo line-level out- put. line_out_l, line_out_r, alt_line_out_l, and alt_line_out_r outputs should be capacitively coupled to external circuitry. the mono output, mono_out, can be used as ei- ther a sum of the left and right output channels at- tenuated by 6 db to prevent clipping at full scale or the selected mic_in signal. the mono out channel can be used to drive the pc internal mono speaker using an appropriate drive circuit. this approach allows the traditional pc sounds to be integrated with the rest of the audio system. the mute control is independent of the line outputs allowing the mono channel to mute the speaker without muting the line outputs. each of the 5 analog outputs, if used in the design, require 680 pf or larger npo dielectric capacitors between the corresponding pin and agnd. each analog output is dc biased up to the vrefout volt- age signal reference which is nominally 2.2 v. this requires that the output either be ac coupled to ex- ternal circuitry (ac load must be greater than 10 k w ) or dc coupled to a buffer op-amp biased at the vrefout voltage (see figure 8 for the recommended headphone op-amp circuit). 2.7 nf 47 k w 4.7 k w 0.1 m f pc_beep 1 +5va (low noise) or agnd - if cmos source figure 7. mono input figure 8. headphones driver agnd agnd agnd 1/4 watt 1/4 watt hp_out_r alt_line_out_l hp_out_l vrefout alt_line_out_r 22pf npo 39k w 4 1 2 3 22pf npo tda1308 + - 5 6 7 27k w 4 1 2 3 tda1308 + - 3 2 1 220 m f elec + 47k w 4 1 2 3 elec + 680pf npo 680pf npo 0.1 m f y5v 1.0 m f y5v 220 m f 10 w 10 w
32 ds242f5 CS4297 crystalclear? soundfusion? audio codec 97 miscellaneous analog signals the afilt1 and afilt2 pins must have a 390 pf npo capacitor (must not be smaller than 390 pf) to analog ground. these capacitors, along with an in- ternal resistor, provide a single-pole low-pass filter at the inputs to the adcs. by placing these filters at the input to the adcs, low-pass filters at each analog input pin are not necessary. the refflt pin lowers the noise of the internal voltage reference. a 1 m f (must not be greater than 1 m f) and 0.1 m f capacitor to analog ground should be connected with a short, wide trace to this pin (see figure 10 in the grounding and layout section for an example). no other connection should be made, as any coupling onto this pin will degrade the analog performance of the codec. likewise, digital signals should be kept away from refflt for similar reasons. the vrefout pin is typically 2.2 v and provides a common mode signal for single-supply external circuits. vrefout only supports light dc loads and should be buffered if ac loading is needed. for typical use, a 0.1 m f in parallel with a 1 m f capaci- tor should be connected to vrefout. power supplies the power supplies providing analog power should be as clean as possible to minimize coupling into the analog section which could degrade analog per- formance. the pins avdd1 and avdd2 supply power to all the analog circuitry on the CS4297. this 5 volt analog supply should be generated from a voltage regulator (7805 type) connected to a +12 volt supply. this helps isolate the analog cir- cuitry from noise typically found on +5 v digital supplies which power many digital circuits in a pc environment. a typical voltage regulator circuit for analog power using an mc78m05cdt is shown in figure 9. the digital power pins dvdd1 and dvdd2 should be connected to the same digital supply as the ac97 controllers ac-link interface. since the digital interface on the CS4297 may operate at ei- ther 3.3 v or 5 v, proper connection of these pins will depend on the digital power supply of the ac97 controller. +12vd agnd dgnd +5va 0.1 f y5v 10f elec + 10f elec + mc78m05cdt out 3 gnd 2 in 1 0.1f y5v figure 9. voltage regulator
ds242f5 33 CS4297 crystalclear? soundfusion? audio codec 97 grounding and layout figure 10 is the suggested layout for the CS4297. the decoupling capacitors should be located phys- ically as close to the pins as possible. also note the routing of the refflt decoupling capacitors and the isolation of that ground strip. it is strongly recommended that the device be locat- ed on a locally separate analog ground plane. this analog ground plane is used to keep noise from dig- ital ground return currents from modulating the CS4297s ground potential and degrading perfor- mance. the digital ground pins should be connect- ed to the digital ground plane and kept separate from the analog ground connections of the CS4297 and any other external analog circuitry. it is also recommended that the common connec- tion point between the two ground planes (required to maintain a common ground voltage potential) be located near the CS4297 just under the digital ground connections (vias). the ac-link digital in- terface connection traces should be routed such that digital ground plane lies underneath these signals (on the internal ground layer) from the ac97 con- troller continuously to the CS4297. analog ground to digital ground pin 1 0.1 f 390 pf npo 1f to analog ground to +5va to +5vd 0.1 f y5v to +5vd 0.1 f y5v y5v 0.1 f y5v to +5va avdd2 avss2 aflt2 aflt1 refflt avss1 avdd1 dvss1 dvss2 dvdd2 dvdd1 vrefout to via to analog ground figure 10. suggested layout for the CS4297
34 ds242f5 CS4297 crystalclear? soundfusion? audio codec 97 performance plots figures 11 through 26 show the overall frequency response, the thd+n over frequency, and the dr over frequency of the adcs, the dacs, the analog mixer (line in to line out) and the microphone in- puts. crosstalk plots and the noise floor fft plots of the dacs, the analog mixer and the muted noise floor of the CS4297 are also included. all plots were taken on a crd4297-1 with a CS4297-kq codec. figures 11, 14, 17, and 20: the frequency re- sponse plots were taken using a -20 db fs input signal swept over the frequency range of 20 hz to 20 khz and normalized to 0 db at 1 khz. figures 12, 15, 18, and 21: the thd+n plots were taken using a -3 db fs input signal swept over the frequency range of 20 hz to 20 khz. these perfor- mance plots used an a-weighted filter applied on the output with the exception of the adc thd+n plot. figures 13, 16, 19, and 22: the dynamic range plots were taken using a -50 db fs input signal swept over the frequency range of 20 hz to 20 khz. these performance plots used an a-weighted fil- ter applied on the output with the exception of the adc dynamic range plot. figure 23: the crosstalk plot was generated using a 0 db fs input signal on one channel of the line_in input and measuring the magnitude of the other output channel swept over the frequency range of 20 hz to 20 khz. this performance plots used an a-weighted filter applied on the output figures 24, 25, and 26: the noise floor plots were generated by running a 16k-point fft on the line_out output with no input signal applied. the muted noise floor plot was taken with the master mute bit set (bit d15, register 0x02h). these performance plots used an a-weighted fil- ter applied on the output all audio performance plots used unity gain set- tings on the analog volume controls. additionally, the microphone input plots were taken with the +20 db gain stage enabled (bit d6, register 0x0eh). the adc plots used the a-d signal path. the dac plots used the d-a signal path. the mixer and the microphone plots used the a-a signal path.
ds242f5 35 CS4297 crystalclear? soundfusion? audio codec 97 figure 11. adc frequency response figure 12. adc thd+n vs. frequency 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20 100 1 k 10 k 20 k frequency (hz) thd+n (db fs) 1 0.8 0.6 0.4 0.2 -0 -0.2 -0.4 -0.6 -0.8 20 100 1 k 10 k 20 k frequency (hz) amplitude (db) figure 13. adc dr vs. frequency figure 14. dac frequency response 1 0.8 0.6 0.4 0.2 -0 -0.2 -0.4 -0.6 -0.8 20 100 1 k 10 k 20 k frequency (hz) amplitude (db) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20 100 1 k 10 k 20 k frequency (hz) thd+n (db fs)
36 ds242f5 CS4297 crystalclear? soundfusion? audio codec 97 figure 15. dac thd+n vs. frequency figure 16. dac dr vs. frequency 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20 100 1 k 10 k 20 k frequency (hz) thd+n (db fs) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20 100 1 k 10 k 20 k frequency (hz) thd+n (db fs) figure 17. mixer frequency response figure 18. mixer thd+n vs. frequency 1 0.8 0.6 0.4 0.2 -0 -0.2 -0.4 -0.6 -0.8 20 100 1 k 10 k 20 k frequency (hz) amplitude (db) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20 100 1 k 10 k 20 k frequency (hz) thd+n (db fs)
ds242f5 37 CS4297 crystalclear? soundfusion? audio codec 97 figure 19. mixer dr vs. frequency figure 20. microphone frequency response 1 0.8 0.6 0.4 0.2 -0 -0.2 -0.4 -0.6 -0.8 20 100 1 k 10 k 20 k frequency (hz) amplitude (db) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20 100 1 k 10 k 20 k frequency (hz) thd+n (db fs) figure 21. microphone thd+n vs. frequency figure 22. microphone dr vs. frequency 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20 100 1 k 10 k 20 k frequency (hz) thd+n (db fs) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20 100 1 k 10 k 20 k frequency (hz) thd+n (db fs)
38 ds242f5 CS4297 crystalclear? soundfusion? audio codec 97 figure 23. mixer crosstalk vs. frequency figure 24. dac noise floor fft 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 20 100 1 k 10 k 20 k frequency (hz) amplitude (db fs a) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20 100 1 k 10 k 20 k frequency (hz) amplitude (db) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 20 100 1 k 10 k 20 k frequency (hz) amplitude (db fs a) figure 25. mixer noise floor fft figure 26. muted noise floor fft 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 20 100 1 k 10 k 20 k frequency (hz) amplitude (db fs a)
ds242f5 39 CS4297 crystalclear? soundfusion? audio codec 97 pin descriptions digital i/o pins reset# - ac97 chip reset, input this active low signal is the asynchronous cold reset input to the CS4297. the CS4297 must be reset before it can enter normal operating mode. sync - ac-link serial port sync pulse, input this signal is the serial port timing signal for the ac-link of the CS4297. its period is the reciprocal of the sample rate of the CS4297, 48 khz. this signal is generated by the ac97 controller and is synchronous to bit_clk. sync is also an asynchronous input when the CS4297 is in a warm reset state. a series terminating resistor of 47 w should be connected on this signal close to the device driving the signal. bit_clk - ac-link serial port master clock, output this output signal controls the master clock timing for the ac-link. it is a 12.288 mhz clock signal which is divided down by two from the xtl_in input clock. a series terminating resistor of 47 w should be connected on this signal close to the CS4297. c d _ au x _ v i d e o_ cd_ m i c phon au x _ v i d e o_ cd_gn m i c l i ne _ i n_ l i ne_ i n _ l l l r 2 e r r d 1 l r nc l ine _ o ut_l nc aflt1 refflt l i n e _ o ut_r nc nc aflt2 vrefout avss1 avdd1 n c nc nc n c nc nc a v ss2 n c a v d d 2 mo n o _ o ut 6 2 4 8 10 1 3 5 7 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 31 35 33 29 27 36 34 32 30 28 26 25 48 47 46 45 44 43 42 41 40 39 38 37 CS4297 - x q 48 - p i ntqfp bit_clk xtl_in dvss1 sdata_in sync dvdd1 xtl_out sdata_out dvdd2 reset# pc_beep dvss2 alt_line_out_r alt_line_out_l
40 ds242f5 CS4297 crystalclear? soundfusion? audio codec 97 sdata_out - ac-link serial data input stream to ac97, input this input signal transmits the control information and digital audio output streams to be sent to the dacs. the data is clocked into the CS4297 on the falling edge of bit_clk. a series terminating resistor of 47 w should be connected on this signal close to the device driving the input. sdata_in - ac-link serial data output stream from ac97, output this output signal transmits the status information and digital audio input streams from the adcs. the data is clocked out of the CS4297 on the rising edge of bit_clk. (see the digital hardware description section). a series terminating resistor of 47 w should be connected on this signal as close to the CS4297 as possible. xtl_in - crystal input this pin accepts either a crystal, with the other pin attached to xtl_out, or an external cmos clock. xtl_in must have a crystal or clock source attached for proper operation. the crystal frequency must be 24.576 mhz and designed for fundamental mode, parallel resonance operation. xtl_out - crystal output this pin is used for a crystal placed between this pin and xlt_in. if an external clock is used on xtl_in, this pin must be left floating with no traces or components connected to it. analog i/o pins pc_beep - analog mono source, input this signal is intended to be used as an internal pc beep connection to the audio subsystem. this source is not input to the stereo-to-mono mixer. the maximum allowable input is 1v rms (sinusoidal). this input is internally biased at the vrefout voltage reference and requires ac coupling to external circuitry. if this input is not used, it should be connected to the vrefout pin or ac coupled to analog ground. phone - analog mono source, input this signal is intended to be used as a voice modem connection to the audio subsystem. this source is not input to the stereo-to-mono mixer. the maximum allowable input is 1 v rms (sinusoidal). this input is internally biased at the vrefout voltage reference and requires ac coupling to external circuitry. if this input is not used, it should be connected to the vrefout pin or ac coupled to analog ground. mic1 - analog mono source, input this analog input is monophonic source to the analog output mixer. it is intended to be used as a desktop microphone connection to the audio subsystem. this input is mux selectable to the input mixer with the mic2 input source. the maximum allowable input is 1 v rms (sinusoidal). this input is internally biased at the vrefout voltage reference and requires ac coupling to external circuitry. if this input is not used, it should be ac coupled to analog ground.
ds242f5 41 CS4297 crystalclear? soundfusion? audio codec 97 mic2 - analog mono source, input this analog input is a monophonic source to the analog output mixer. it is intended to be used as an alternate microphone connection to the audio subsystem. this input is mux selectable to the input mixer with the mic1 input source. the maximum allowable input is 1 v rms (sinusoidal). this input is internally biased at the vrefout voltage reference and requires ac coupling to external circuitry. if this input is not used, it should be ac coupled to analog ground. line_in_l and line_in_r- analog line source, inputs these inputs form a stereo input pair to the CS4297. the maximum allowable input is 1v rms (sinusoidal). these inputs are internally biased at the vrefout voltage reference. ac coupling to external circuitry is required. if these inputs are not used, they should both be connected to the vrefout pin or both ac coupled, with separate ac coupling caps, to analog ground. cd_l and cd_r - analog cd source, inputs these inputs form a stereo input pair to the CS4297. it is intended to be used for the redbook cd audio connection to the audio subsystem. the maximum allowable input is 1 v rms (sinusoidal). these inputs are internally biased at the vrefout voltage reference. ac coupling to external circuitry is required. if these inputs are not used, they should both be connected to the vrefout pin or both ac coupled, with separate ac coupling caps, to analog ground. cd_gnd - analog cd common source, input this analog input is used to remove common mode noise from redbook cd audio signals. the impedance on the input signal path should be one half the impedance on the cd_l and cd_r input paths. this pin requires ac coupling to external circuitry. if this input is not used, it should be connected to the vrefout pin or ac coupled to analog ground. video_l and video_r - analog video audio source, inputs these inputs form a stereo input pair to the CS4297. it is intended to be used for the audio signal output of a video device. the maximum allowable input is 1 v rms (sinusoidal). these inputs are internally biased at the vrefout voltage reference. ac coupling to external circuitry is required. if these inputs are not used, they should both be connected to the vrefout pin or both ac coupled, with separate ac coupling caps, to analog ground. aux_l and aux_r - analog auxiliary source, inputs these inputs form a stereo input pair to the CS4297. the maximum allowable input is 1 v rms (sinusoidal). these inputs are internally biased at the vrefout voltage reference. ac coupling to external circuitry is required. if these inputs are not used, they should both be connected to the vrefout pin or both ac coupled, with separate ac coupling caps, to analog ground.
42 ds242f5 CS4297 crystalclear? soundfusion? audio codec 97 line_out_l and line_out_r - analog line level outputs these signals are analog outputs from the stereo output mixer. the full scale output voltage for output is nominally 1 v rms and is internally biased at the vrefout voltage reference. it is required to either ac couple these pins to external circuitry or dc couple them to a buffer op- amp biased at the vrefout voltage. these pins need a 680 pf npo capacitor attached to analog ground. alt_line_out_l and alt_line_out_r - analog alternate line level outputs these signals are analog outputs from the stereo output mixer. the full scale output voltage for each output is nominally 1 v rms and is internally biased at the vrefout voltage reference. it is required to either ac couple these pins to external circuitry or dc couple them to a buffer op- amp biased at the vrefout voltage. these pins need a 680 pf npo capacitor attached to analog ground. mono_out, analog mono line level output this signal is an analog output from the mono output mixer. this is a left and right channel mix of the output of the stereo input mixer. the full scale output is nominally 1 v rms and is internally biased at the vrefout voltage reference. ac coupling to external circuitry is required. this pin needs a 680 pf npo capacitor attached to analog ground. filter and reference pins refflt - internal reference voltage, input this is the voltage reference used internal to the part. a 0.1 m f and a 1 m f (must not be larger than 1 m f) capacitor with short, wide traces must be connected to this pin. no other connections should be made to this pin. vrefout - voltage reference, output all analog inputs and outputs are centered around vrefout which is nominally 2.2 volts. this pin may be used to level shift external circuitry, however any external loading should be buffered. aflt1 - left channel antialiasing filter input this pin needs a 390 pf npo capacitor attached to analog ground. aflt2 - right channel antialiasing filter input this pin needs a 390 pf npo capacitor attached to analog ground.
ds242f5 43 CS4297 crystalclear? soundfusion? audio codec 97 power supplies dvdd1, dvdd2 - digital supply voltage these pins provide the digital supply voltage for the ac-link section of the CS4297. these pins may be tied to +5 v digital or to +3.3 v digital. the CS4297 and digital controllers ac-link should share a common digital supply dvss1, dvss2 - digital ground these pins are the digital ground connection for the ac-link section of the CS4297. these pins should be isolated from analog ground currents. avdd1, avdd2 - analog supply voltage these pins provide the analog supply voltage for the analog and mixed signal sections of the CS4297. these pins must be tied to +5 volt power supply. it is strongly recommended that +5 volts be generated from a voltage regulator to ensure proper supply currents and noise immunity from the rest of the system. avss1, avss2 - analog ground these pins are the ground connection for the analog, mixed signal, and substrate sections of the CS4297. these pins should be isolated from digital ground currents. references 1) intel, audio codec 97 component specifica- tion , revision 1.03, september 15, 1996. http://developer.intel.com/pc-supp /platform/ac97 / 2) cirrus logic, cs4610 soundfusion pci audio accelerator data sheet. http://www.corp.cirrus.com/products/ overviews/cs4610.html 3) cirrus logic, crd4610-1 ac97 motherboard reference design data sheet. http://www.cirrus.com/ftp/pubs/4610rd1.pdf 4) steve harris, clif sanchez, personal computer audio quality measurements , ver 0.5 http://www.corp.cirrus.com/products/ papers/meas/meas.html 5) microsoft, pc design guidelines , http://www.microsoft.com/hwdev/desguid/
44 ds242f5 CS4297 crystalclear? soundfusion? audio codec 97 package dimensions inches millimeters dim min max min max a ---- 0.063 ---- 1.600 a1 0.002 0.006 0.050 0.150 b 0.007 0.011 0.170 0.270 d 0.343 0.366 8.700 9.300 d1 0.272 0.280 6.900 7.100 e 0.343 0.366 8.700 9.300 e1 0.272 0.280 6.900 7.100 e* 0.016 0.024 0.400 0.600 l 0.018 0.030 0.450 0.750 0.000 7.000 0.000 7.000 * nominal pin pitch is 0.50 mm controlling dimension is mm. jedec designation: ms026 48l tqfp package drawing e1 e d1 d 1 e l b a1 a
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