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implementing fddi over copper; the ansi x3t9.5 standard application note advanced micro devices the american national standards institute (ansi) x3t9 committee is developing the standard for the implementation of fddi links (pmd layer) on copper-shielded and unshielded twisted-pair cables. the content of this application note is consistent with the existing trends for specifying link parameters. however, at the time of this application note release, the standard is not complete and could introduce either new specifications, or changes in the existing specifications, neither of which would not be reflected in this paper.
amd publication# 18258 rev. a amendment /0 issue date: november 1993 implementing fddi over copper; the ansi x3t9.5 standard application note by advanced micro devices, inc., micro linear, and pulse engineering, inc. overview the proposed ansi tp-pmd standard has been demon- strated in interop tests and the x3t9.5 committee is pro- gressing quickly in preparing a final standard. the use of copper media significantly reduces the node cost by eliminating the need for expensive optical transceivers. both shielded twisted pair cable (stp) and data grade (category 5) unshielded twisted pair cable (utp-5) are covered in the new specification. although transmission distance is limited to 100 meters, the new tp-pmd is an important step in reducing the overall cost of fddi and bringing it to the desktop. to enable fddi transmission over copper, both analog and digital signal processing are required. advanced micro devices, micro linear and pulse engineering have worked together to provide a simple implementation for the proposed tp-pmd specification. amd's supernet a 2 chipset can be used for copper transmis- sion by removing the optical data links (odl) on existing adapter cards and concentrator boards and replacing them with a copper data link (cdl). the phy/pmd in- terface at the am79865 pdt and am79866a pdr remain intact. a high-performance cdl can be implemented us- ing an integrated transceiver made by micro linear and a filter/magnetics module made by pulse engineering for under $30. copper interface the tp-pmd standard introduces three main functional changes in the way the signal is processed: data scram- bling, mlt-3 format (encoding) for the line signal and adaptive equalization at the receiver. figure 1 depicts the signal characteristics at various points within the tp-pmd interface. amd's physical layer controller with scram- bler (plc-s) device, the am79c864a, provides the scrambling/de-scrambling function, while micro linear's ml6671 provides mlt-3 encoding/decoding and adap- tive equalization. pulse engineering provides the filter/ magnetics interface to the cable. 18258a-1 data format: parallel serial serial serial parallel parallel or serial content: encoded encoded encoded encoded encoded (4-bit) original (5-bit) encoded scrambled: yes yes yes yes yes signal format: nrz nrzi mlt-3 nrzi nrz am79c864a plc-s scrambler am79865 transmitter (pdt) mlt-3 encoder/ transmitter mlt-3 receiver/ decoder am79866a receiver (pdr) am79c864a plc-s descrambler figure 1. tp-pmd interface signal flow
amd 2 implementing fddi over copper; the ansi x3t9.5 standard figure 2 shows a block diagram of the tp-pmd interface. note that the phy/pmd interface is the same, regardless of whether an odl or cdl is used. both utilize serial 4b/5b encoded nrzi data. the only difference is that the data pattern is scrambled when using a cdl. the scram- bling function can be enabled and disabled in the plc-s to accommodate both cases. mlt-3 encoding nrzi and mlt-3 line signals are shown in figure 3. mlt-3 is an extension of nrzi: ones are represented by transitions and zeroes by the lack of transitions. the distinctive features of mlt-3 are: the signal has three possible voltage levels and the transitions are always be- tween two adjacent levels. mlt-3 encoding is used to control electro magnetic inter- ference (emi). the conversion from nrzi to mlt-3 shifts much of the spectral energy below 30 mhz. most impor- tantly, it reduces the spectral energy between 40 mhz and 70 mhz, a region where nrzi transmission has trouble meeting governmental emission requirements. figure 4 shows the mlt-3 spectrum. the proposed tp-pmd specification calls for a 2 v peak-to- peak transmitter output signal, which was used for this plot. ninety percent of the spectral energy lies below 40 mhz. however, to prevent inter-symbol-interference (isi) and for proper operation of the adaptive equalization, the data channel requires at least 90 mhz of bandwidth. scrambling/descrambling scrambling is required to avoid energy peaks in the spec- trum of the line signal. fddi allows for some repetitive data patterns which concentrate spectral energy. scram- bling tends to randomize these patterns. thus, scram- bling tends to average out the signal spectrum and reduce emi. ansi has selected stream-cipher scram- bling, mainly because its output spectral characteristics are essentially independent of the input pattern, which makes it less likely to lock-up, as compared to other scrambling techniques. the stream-cipher scrambling/ descrambling function has been included in the am79c864a plc-s device and may be enabled/dis- abled either through software or through hardware. note, the plc-s supports both copper and fiber designs as the scrambler is selectable. a theoretical description of stream-cipher scrambling may be found in appendix a. 18258a-2 1 2 3 4 5 6 7 8 9 10 11 12 13 adaptive equalizer mlt-3 decoder signal detector mlt-3 encoder gnd rd- rd+ sd+ sd- vcc case case vcc td+ td- v bb gnd filter filter rj-45 connector 1 2 3 4 5 6 7 8 receive agc amplifier transmit amplifier figure 2. copper data link block diagram
amd 3 implementing fddi over copper; the ansi x3t9.5 standard 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 1 1 1 0 0 1 1 1 0 1 0 0 1 0 1 0 0 1 1 1 1 0 1 1 data to be transmitted (after 4b/5b encoding and scrambling) line bit clock at the baud rate nrzi waveform mlt-3 waveform 18258a-3 figure 3. waveforms of nrzi and mlt-3 line signals 18258a-4 10.0 dbm 0 dbm -10 dbm -20 dbm -30 dbm -40 dbm -50 dbm -60 dbm -70 dbm 10 25 40 55 70 85 100 115 130 145 160 frequency C mhz figure 4. typical mlt-3 spectrum at the transmitter output adaptive equalization adaptive equalization is necessary to compensate for the cable attenuation and phase distortion that is encoun- tered at various lengths of stp and utp cable. stp ca- ble has a characteristic impedance of 150 w . 100 meters of this cable will attenuate a transmitted signal by 12 db (a factor of 4) at 62.5 mhz. 100 meters of utp-5 cable, such as at&t 1061 (z o = 100 w ), attenuates the signal by 18 db at 62.5 mhz. should the channel be equalized for the maximum length of either cable, it would be over-equal- ized for the shorter and intermediate lengths. over- equalization results in excessive signal jitter. with adaptive equalization, the receiver frequency response is optimized for any given segment of cable. in order to achieve this, the equalizer is constantly adjusted by a feedback loop. tp-pmd circuit the copper solution described in this application note has been based on three functional blocks: amd's supernet a 2 phy (am79c864a plc-s, am79865 pdt and am79866a pdr), micro linear's mlt-3 trans- ceiver (ml6671) and pulse engineering's filter/magnetic module (pe68502). an application circuit of the tp-pmd is shown in figure 5. this is a utp-5 implementation util- izing an rj-45 connector at the media interface. a 13-pin connection is shown at the phy-pmd interface which is pin compatible with the footprint of the sumitomo odl. a 9- or 22-pin footprint could also be used for compatibility with other common odl configurations from at&t, siemens and hp.
amd 4 implementing fddi over copper; the ansi x3t9.5 standard 1 2 3 4 20 5 6 7 8 9 10111213 14 15 16 17 19 1 2 3 4 20 5 6 7 8 9 10111213 14 15 16 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13 lsclk tdat 4-0 47 10 11 12 13 14 17 18 pbck fdtoff rsclk rdat 4-0 20 21 22 25 26 28 29 gnd physical layer controller (plc-s) am79c864a lpbck 23 4 lty ltx 0 1 tdat gnd v cc lsclk fotoff test tx ty v cc v cc gnd (nc) (nc) lpbck test gnd 2 34 rdat 0 1 am79865 pdt am79866a pdr lry lrx ry rx sdi lsclk sdo v cc gnd rsclk v cc 25mhz osc (ttl) 80 w v cc = +5v 130 w termination typical 50 pccl gnd vbb td C td + v cc nc case v cc sd C sd + rd C rd + gnd rgnd 25 21 10 15 14 phy/pmd interface 547 8 tgnda tgndd txnC txn+ rxout+ rxoutC sdC sd+ rtset1 rtset2 rtx1 rtx2 rset1 rset2 wflt lpbk txoff 1.91k w 500 w 4.99k w 8.0k w 17 18 24 23 27 26 29 28 9 12 11 2k w r5 v cc r1 r2 r3 r4 tpout+ tpoutC tpin+ tpinC tvcco tvcca cmref 32 22 16 31 30 20 19 r8 49.9 w r6 49.9 w r10 49.9 w r11 49.9 w c8 10 r9 8.2 w c9 0.1 v cc fb2 c6 0.1 c7 .01 2 4 5 1 3 6 8 7 c10 0.1 r10 8.2 w c5 0.1 c4 0.68 c3 0.68 1 2 8 3 rvcca rvccd cap1 cap2 c1 .01 fb1 v cc c2 0.1 * ml 6671 peC68502 sdcl 41 v cl +5 * *** * * 18 fb = ferrite bead, fair-rite 2743019446 9121316 8 7 2 1 j1 txC tx+ rxC rx+ scrm 18258a-5 figure 5. application circuit for the tp-pmd
amd 5 implementing fddi over copper; the ansi x3t9.5 standard transmit circuit the am79865 pdt sends scrambled nrzi data to the cdl at pecl signal levels. the ml6671 converts the nrzi data to three level, mlt-3 code. in mlt-3 coding, ones are represented by transitions and zeros are repre- sented by a lack of transitions. the transitions are always between two adjacent levels. the transmit level is set to 2 v peak-to-peak by placing a 2k w resistor between pins 17 and 18 of the ml6671. the rise time between adjacent levels (10% to 90%) out of the ml6671 is less than 1.0 ns. a low pass filter on the pe68502 increases the rise time to 3.0 ns, prior to launch- ing the signal onto the cable. a fast rise time maintains a clean eye pattern, but it also creates unnecessary over- shoot and emi that can develop when the signal encoun- ters punch down blocks in the wiring closet and cable imbalances. the 3.0 ns rise time has been found empiri- cally to be the optimum value for the application. the fil- ter/magnetics module also provides ac coupling, ground isolation and reduces radiated emissions by pro- viding common mode filtering. in the transmit channel, it is recommended that the transformer center tap be ac coupled to ground for added common mode filtering. figure 6 shows the mlt-3 eye pattern at the transmitter output into a 100 w resistive load. the output jitter of the transmitter is typically less than 2.5 ns. receive circuit the receive section consists of a differential equalization amplifier, signal detect circuitry and an mlt-3 to nrzi decoder. again, the signal is ac coupled from the media through a transformer in the pe68502 module. two 50 w resistors from pins 1 and 3 of the pe68502 to cmref (pin 32 of the ml6671) are part of the cable termination and also set a dc bias for the receive amplifier input. pin 4 of the module should also be connected to cmref. as with the transmit channel, ac coupling the center tap (pin 4) of the filter/magnetics module to ground improves common mode rejection of the channel and reduces noise susceptibility. it was found in early implementations of mlt-3 over utp-5 that fixed equalization cannot be optimized for all combinations of distances and cable performance. adaptive equalization changes the receiver gain and fre- quency response as a function of the received signal. the receiver amplifier has a dynamic range of 20:1, from 100 mv pp to 2.0 v pp . the equalizer boosts the high fre- quency content of the signal in order to compensate for cable filtering and/or distortion. equalization is adaptive and the receiver can compensate for lengths of utp-5 between 0 and 100 meters. figures 7 and 8 show the typical eye patterns of the nrzi signal recovered by the receiver (at rd+/C) after 10 and 100 meters of utp-5, respectively. in both cases, the jit- ter is held below 3.0 ns. figure 9 shows the jitter at the phy/pmd interface plotted as a function of cable length. 50 mv/div 2 ns/div 18258a-6 figure 6. mlt-3 eye pattern of the transmitter 150 mv/div 2 ns/div 18258a-7 figure 7. nrzi eye pattern out of the receiver, 10 meters utp-5 cable 150 mv/div 2 ns/div 18258a-8 figure 8. nrzi eye pattern out of the receiver, 100 meters utp-5 cable
amd 6 implementing fddi over copper; the ansi x3t9.5 standard signal detect voltage amplitude of the received signal is used as an in- dication of a working phy and pmd link. if the signal at the receiver input is greater than 100 mv the received sig- nal is interpreted as data, and the sd+ logic signal out of the ml6671 is asserted high (>3.8 vdc). the plc-s ac- knowledges that there is an active signal and monitors the line for data. if the signal amplitude is less than 100 mv pp , sd+ is asserted low (<3.5 vdc) and the plc-s is free for transmission. 5.60 5.40 5.20 5.00 4.80 4.60 4.40 4.20 4.00 3.80 3.60 3.40 3.20 3.00 2.80 2.60 2.40 2.20 2.00 1.80 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -0.20 50.00 100.00 150.00 200.00 0.00 cable length C meters jitter (ns) 18258a-9 figure 9. jitter vs. utp-5 cable length layout considerations in laying out the tp-pmd pc board, it is important to keep the tx+/txC and rd+/rdC signal lines as short (direct) as possible. the transmit and receive power planes should be isolated from one another with lc filter net- works. surface mount ferrite beads are suitable for the in- ductive elements of these filters. a ground plane should also be used. however, the ground plane should not ex- tend to within 0.150 of the output of the filter/magnetics module or the rj-45 connector. this separation should prevent common mode noise, that may develop on the ground, from coupling onto the media. grounds on con- nector shields should be attached to chassis ground. the shields should not be connected to analog or digital ground. since fcc compliance depends on both the cir- cuit characteristics and the system layout, test results will vary from implementation to implementation. three different mic connectors are specified in the x3t9.5 tp-pmd document. the rj-45 is used for utp-5 while a db-9 plug is used for the stp m-port and a db-9 socket is used for the stp a, b, or s-port. pin assign- ments for the three connectors are shown in figure 10. rj-45 receptacle for s-port pin # signal 1 transmit (tx+) 2 transmit (txC) 3 not used 4 not used 5 not used 6 not used 7 receive (rx+) 8 receive (rxC) mic receptacle for a, b, or s-port pin # signal 1 receive (rx+) 2 not used 3 not used 4 not used 5 transmit (tx+) 6 receive (rxC) 7 not used 8 not used 9 transmit (txC) shell chassis gnd mic plug for m-port pin # signal 1 transmit (tx+) 2 not used 3 not used 4 not used 5 receive (rx+) 6 transmit (txC) 7 not used 8 not used 9 receive (rxC) shell chassis gnd 18258a-11 18 5 1 96 15 69 figure 10. mic connectors and pin out
a-1 appendix a description of stream cipher scrambling appendix a about stream-cipher scrambling stream-cipher scrambling was selected by the xt3.9 standards committee mostly because its output spectral characteristic is essentially independent of the input pat- tern. the selection was between a stream-cipher algo- rithm and a self-synchronizing algorithm. the former seems to be more reliable in avoiding lock-up conditions but requires more components, especially on the receiver side, where the scrambled serial data need to be reframed. the stream-cipher scrambler and stream-cipher descrambler described below are implemented in the physical layer controller chip with scrambler (plc-s). the design is based on a stream-cipher version pre- sented at the standards committee. background scramblers modify data by mixing the output of a random generator with the original data. the mixing is performed by logic exclusive-or operations. at the receiver end, the descrambler adds the same random pattern (using the xor function) to the scrambled data. because the scrambler and descrambler patterns are the same, they cancel each other out and the descrambled data equal the original data. given the following patterns: original data = a random (scrambler and descrambler) = b descrambled output = c c = a ? b ? b because of the xor operation: b ? b = 0, c = a ? b ? b = a ? 0 = a the random generators used on both sides are shift reg- isters with xor feedback. the function can be expressed as the polynomial x j + x k . the output of the random gen- erator is bit j xored with bit k. this is also fed back to the input. the scrambler selected by the xt3.9 committee has j=11 and k=9. the polynomial is x 11 + x 9 . proper operation requires that the scrambler and descrambler generate the same random pattern and be synchronized. at any given instant, they must be in the same state and have the same output. in the case of the stream-cipher, the descrambler's random generator op- erates independently of the scrambler's random genera- tor. therefore, the descrambler must be synchronized to the scrambler before it can reliably decode data. in the fddi protocol, user data are preceded by line state patterns such as hls, mls, ils and qls. these patterns are repetitive and during their transmission, the incoming scrambled data are predictable. the following formula al- lows us to use the line states to synchronize the descrambler. h(n) = scrmdata(n) ? scrmdata(n-11) ? scrmdata(n-9) = data(n) where: h(n) is a test bit scrmdata(n) is scrambled data scrmdata(n-11), scrmdata(n-9) are the eleventh and ninth bits of scrambled data. data(n) is unscrambled data this relationship is true when data(11) equals data(9). three rules, based on the above formula, synchronize the descrambler: 1. if scrmdata(n) = scrmdata(n-11) and scrmdata(n) = scrmdata(n-9) then set descrambler input to scrmdata(n). 2. if scrmdata(n) = scrmdata(n-11) = 1 and scrmdata(n-1) = scrmdata(n-2) = scrmdata(n-2) = scrmdata(n-4) = scrmdata(n-6) = scrmdata(n-7) = scrmdata(n-8) = scrmdata(n-9) = 0, then set the descrambler to scrmdata(n). 3. otherwise descrm(n) = descrm(n-j) ? descrm(n-k). table a-1 below shows the line states and the corre- sponding detected test signals. table a-1. fddi line states and detected test signals line state data bits test bits h(n) hls 0010000100 0111001110 qls 0000000000 0000000000 mls 0000000100 0000001110 ils 1111111111 1111111111
amd a-2 appendix a hreg synchronization logic ureg clk clk clk clk 5 5 5 + C + C 5 55 5 5 clk capture clk 5 5 c out 5 scrambled data 5 output data 5 creg 18258a-12 figure a-1. plc-s descrambler logic diagram plc-s implementation the plc-s scrambler is a 5-bit parallel version of the se- rial data scrambler. the main functional pieces are: 1. sreg: scrambler shift register 2. creg: cipher shift registerrecords 10 bits of the scrambled data. 3. hreg: implements the formula c(n) ? c(n-11) ? c(n-9) 4. ureg: the descrambler shift register the descrambler is shown in figure a-1. it has two modes of operation: sample and normal. in the sample mode, ureg is not synchronized with sreg. the hreg portion monitors creg for the line states. when it detects one, it generates a signal called capture. capture forces ureg into a predetermined state. in normal operation ureg is synchronized to sreg. capture cannot be generated in this mode. synchronization the objective of synchronization is to set the descrambler shift register to the same state as the scrambler shift reg- ister. once the scrambler is synchronized, it will maintain synchronization because both devices implement the same function. hreg monitors 20 bits of data for a line state. the reason such a large number of bits are monitored is that the byte boundary is unpredictable. there are ten possible inputs for each line state. the repetitive nature of the line states reduces the possible inputs to one for qls and ils, and five for hls. when hreg detects a line state, the output data are set to the corresponding value. the input bits to ureg are set to the data value xored with the scrambled data input.
b-1 appendix b recommended cdl test circuit appendix b 18258a-13 gnd nc td C td + v cc nc gnd v cc sd C sd + rd C rd + gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 copper data link 12345678 rj-45 tx C tx + transmitter output utp-5 cable 100 meters vcc, +5v 5% pe-8271m 2k w 50 w 1:1 0.1 m f 82.5 w 82.5 w 3 4 /5 /7 2 20 2k w 130k w 10h116 10 0.1 m f 82.5 w 82.5 w 82.5 w 82.5 w 82.5 w +5v 5% 82.5 w 130k w 130k w 130k w vcc, +5v 5% sd C sd + rd C rd + 0.1 m f figure b-1.
amd b-2 appendix b further application details for further application details, refer to the following documents: amd supernet a 2 family for fddi, 1994 data book, pid #15502c 901 thompson place sunnyvale, ca 94088-3453 800-222-9323 408-749-5703 micro linear mlt-3 transceiver application note 2092 concourse drive san jose, ca 95131 408-433-5200 pulse engineering tp-fddi filter/magnetic modules, data sheet 12220 world trade drive san diego, ca 92128 619-674-8100 copyright ? 1993 advanced micro devices, all rights reserved. amd, the amd logo, and supernet are registered trademarks of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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