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? products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron?s production data sheet specifications. 09005aef80be2036/09005aef80be1fbd burst cellularram.fm - rev. a 7/03 en 1 ?2003 micron technology, inc. all rights reserved. 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance ? burst cellularram tm mt45w4mw16bfb MT45W2MW16Bfb for the latest data sheet, please refer to micron?s web site: www.micron.com/datasheets. features ? single device supports asynchronous, page, and burst operations v cc , v cc q voltages 1.70v?1.95v v cc 1.70v?2.25v v cc q (option w) random access time: 70ns burst mode write access continuous burst burst mode read access 4, 8, or 16 words, or continuous burst max clock rate: 104 mhz ( t clk = 9.62ns) burst initial latency: 39 ns (4 clocks) @ 104 mhz t aclk: 6.5ns @ 104 mhz page mode read access sixteen-word page size interpage read access: 70ns intrapage read access: 20ns low power consumption asynchronous read < 25ma intrapage read < 15ma initial access, burst read: (39ns [4 clocks] @ 104 mhz) < 35ma continuous burst read < 15ma standby: 90a (32mb), 100a (64mb) deep power-down < 10a low-power features temperature compensated refresh (tcr) partial array refresh (par) deep power-down (dpd) mode figure 1: ball assignment 54-ball fbga n ote: see table 1 on page 6 for ball descriptions, and figure 40 on page 50 for 54- ball mechanical drawing. note: a part marking guide for the fbga devices can be found on micron?s web site: www. micron.com/numberguide part number example: MT45W2MW16Bfb-701wt options marking v cc core voltage supply: 1.80v ? mt45 w xmx16bfb w v cc q i/o voltage 3.0v ? mt45wxm l 16bfb (contac t factory) 2.5v ? mt45wxm v 16bfb (contact factory) 1.8v ? mt45wxm w 16bfb w timing 60ns access (contact factory) 70ns access -70 85ns access -85 frequency 66 mhz 1 104 mhz 6 options (continued) marking configuration: 4 meg x 16 mt45w4mx16bfb 2 meg x 16 mt45w2mx16bfb package 54-ball fbga fb operating temperature range wireless (-25c to +85c) wt industrial (-40c to +85c) it (contact factory) a b c d e f g h j 1 2 3 4 5 6 top view (ball down) lb# dq8 dq9 v ss q v cc q dq14 dq15 a18 wait oe# ub# dq10 dq11 dq12 dq13 a19 a8 clk a0 a3 a5 a17 a21 a14 a12 a9 adv# a2 ce# dq1 dq3 dq4 dq5 we# a11 nc cre dq0 dq2 v cc v ss dq6 dq7 a20 nc a1 a4 a6 a7 a16 a15 a13 a10 nc
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 2 ?2003 micron technology, inc. all rights reserved. table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 list of tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 power-up initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 bus operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 page mode read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 burst mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mixed-mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 wait operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 lb#/ub# operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 low-power operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 standby mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 temperature compensated refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 partial array refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 deep power-down operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 bus configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 burst length (bcr[2:0]) default = continuous burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 burst wrap (bcr[3]) default = burst wraps within address bounda ries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 output impedance (bcr[5]) default = outputs use full drive stre ngth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 clock configuration (bcr[6]) default = tran sactions processed on risi ng edge of clock. . . . . . . . . . . . . . . . . . 18 wait configuration (bcr[8])default = wait transitions one clock before data valid/invalid . . . . . . . . . . . . 18 wait polarity (bcr[10]) default = wait active high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 latency counter (bcr[13:11]) default = three-clock latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 operating mode (bcr[15]) default = asynchronous operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 refresh configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 partial array refresh (rcr[2:0]) default = fu ll array refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 deep power-down (rcr[4]) default = dpd disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 temperature compensated refresh (rcr[6:5]) default = +85c operat ion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 page mode operation (rcr[7]) default = disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 absolute maximum ratings* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 asynchronous random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 asynchronous page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 initial access, burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 continuous burst read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 burst cellularram timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 appendix a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 how extended timings impact cell ularramtm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 asynchronous and page-mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 burst-mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 3 ?2003 micron technology, inc. all rights reserved. list of tables table 1: fbga ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2: bus operations ? asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3: bus operations ? burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4: abbreviated component marks ? cellularram fbga-packa ged components . . . . . . . . . . . . . . . . . . . . . 8 table 5: bus configuration register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6: sequence and burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 7: latency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8: refresh configuration register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 9: 64mb address patterns for par (a4 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 10: 32mb address patterns for par (a4 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 11: electrical characteristics and oper ating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 12: temperature compensated refresh specifications and cond itions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 13: partial array refresh specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 14: deep power-down specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 15: capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 16: output load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 17: asynchronous read cycle timing requirements1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 18: burst read cycle timing requirements1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 19: asynchronous write cycle timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 20: burst write cycle timing requiremen ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 21: initialization timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 22: initialization timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 23: asynchronous read timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 24: asynchronous read timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 25: asynchronous read timing parameters (page mode operat ion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 26: burst read timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 27: burst read timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 28: burst read timing parameters (wit h lb#/ub#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 29: burst read timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 30: burst read timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 31: asynchronous write timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 32: asynchronous write timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 33: asynchronous write timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 34: asynchronous write timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 35: burst write timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 36: burst write timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 37: write timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 38: read timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 39: write timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 40: read timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 41: write timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 42: read timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 43: write timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 44: read timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 45: write timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 46: read timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 47: revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 4 ?2003 micron technology, inc. all rights reserved. list of figures figure 1 ball assignment 54-ball fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 functional block diagram ? 4 meg x 16 and 2 meg x 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3 power-up initialization timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4 read operation (adv = low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5 write operation (adv = low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6 page mode read operation (adv = low). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 7 burst mode read (4-word burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8 burst mode write (4-word burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 9 wired or wait configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 10 refresh collision during read op eration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 11 refresh collision during write op eration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 12 configuration register write in asynchronous mode fo llowed by read . . . . . . . . . . . . . . . . . . . . . . . 15 figure 13 configuration register write in synchronous mode followed by read . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 14 wait configuration (bcr[8] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 15 wait configuration (bcr[8] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 16 wait configuration during burst operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 17 latency counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 18 ac input/output reference wavefo rm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 19 output load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 20 initialization period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 21 asynchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 22 asynchronous read using adv#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 23 page mode read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 24 single-access burst read operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 25 4-word burst read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 26 4-word burst read operation (wit h lb#/ub#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 27 read burst suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 28 continuous burst read with ou tput delay, bcr[8] = 0(1) for end-of-row condition . . . . . . . . . . . . . 38 figure 29 ce#-controlled asynchronous writ e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 30 lb#/ub#-controlled asynchronous write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 31 we#-controlled asynchronous write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 32 asynchronous write using adv#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 33 burst write operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 34 continuous burst write with output delay, bcr[8] = 0(1) for end-of-row condition . . . . . . . . . . . . 44 figure 35 burst write followed by burst read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 36 asynchronous write followed by burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 37 asynchronous write foll owed by burst read?adv# low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 38 asynchronous write fo llowed by asynchronous read?adv# low. . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 39 asynchronous write foll owed by asynchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 40 54-ball fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 41 extended timing for t cem, page mode disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 42 extended timing for t tm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 43 extended timing for t cem, page mode enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 44 extended asynchronous write operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 5 ?2003 micron technology, inc. all rights reserved. general description micron ? cellularram? products are high-speed, cmos dynamic random access memories developed for low-power, portable applications. the mt45w4mw16bfb is a 64mb device organized as 4 meg x 16 bits; the MT45W2MW16Bfb is a 32mb device organized as 2 meg x 16 bits. these devices include an industry-standard burst mode flash inter- face that dramatically incr eases read/write bandwidth compared with other low-power sram or pseudo sram offerings. to operate seamlessly on a burst flash bus, cellular- ram products have incorporated a transparent self- refresh mechanism. the hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. two user-accessible control registers define device operation. the bus configuration register (bcr) defines how the cellularram device interacts with the system memory bus and is nearly identical to its coun- terpart on burst mode flash devices. the refresh configuration register (rcr) is used to control how refresh is performed on the dram array. these registers are automatically loaded with default settings during power-up and can be updated anytime during normal operation. special attention has been focused on standby cur- rent consumption during self refresh. cellularram products include three system-accessible mechanisms used to minimize standby current. partial array refresh (par) limits refresh to only that part of the dram array that contains essential data. temperature compen- sated refresh (tcr) is used to adjust the refresh rate according to the case temperature. the refresh rate can be decreased at lower temperatures to minimize current consumption during standby. deep power- down (dpd) halts the refresh operation altogether and is used when no vital information is stored in the device. these three refresh mechanisms are adjusted through the rcr. figure 2: functional block diag ram ? 4 meg x 16 and 2 meg x 16 n ote: functional block diagrams il lustrate simplified device operation. see truth table, ball descri ptions, and timing diagrams for detailed information. a[20:0] (for 32mb) a[21:0] (for 64mb) input/ output mux and buffers control logic 2,048k x 16 (4,096k x 16) dram memory array ce# we# oe# clk a dv# cre wait lb# ub# dq[7:0 ] dq[15: 8] address decode logic refresh configuration register (rcr) bus configuration register (bcr)
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 6 ?2003 micron technology, inc. all rights reserved. l n ote: the clk and adv# inputs can be tied to v ss if the device is always operating in asynchronous or pa ge mode. the wait signal will be driven to an undefined state when operating in asynchronous or page mode. otherwise, during asynchro- nous operation, wait will be in a high-z condition. table 1: fbga ball descriptions fbga assignment symbol type description a3, a4, a5, b3, b4, c3, c4, d4, h2, h3, h4, h5, g3, g4, f3, f4, e4, d3, h1, g2, h6, e3 a[21:0] input address inputs: inputs for addresses during read and write operations. addresses are internally la tched during read and write cycles. the address lines are also used to define the value to be loaded into the bus configuration register or the refresh configuratio n register. on the 32mb device, a21 (ball e3) is not internally connected. j2 clk input clock: synchronizes the memory to the system operating frequency during synchronous operations. when configured for synchronous operation, the address is latched on the first rising (or falling, depending upon the bus configuration register setting) clk edge when adv# is active, or upon a rising adv# edge, whichever occurs first. clk is static during as ynchronous access read and write operations and during page read access operations. clk must be held low during asynchronous or page mode transactions. j3 adv# input address valid: indicates that a valid ad dress is present on the address inputs. addresses can be latched on the rising edge of adv# during read and write operations. adv# may be driven low during asynchrono us read and write operations. a6 cre input configuration register enable: when cre is high, write operations load the refresh configuration register or bus configuration register. b5 ce# input chip enable: activate s the device when low. when ce# is high, the device is disabled and goes into standby or deep power-down mode. a2 oe# input output enable: enables the output buff ers when low. when oe# is high, the output buffers are disabled. g5 we# input write enable: determines if a given cycle is a write cycle. if we# is low, the cycle is a write to either a configuration register or to the memory array. a1 lb# input lower byte enable. dq[7:0] b2 ub# input upper byte enable. dq[15:8] b6, c5, c6, d5, e5, f5, f6, g6, b1, c1, c2, d2, e2, f2, f1, g1 dq[15:0] input/ output data inputs/outputs. j1 wait output wait: provides data-valid feedback duri ng burst read and write operations. the signal is gated by ce#. wait is used to arbitrate collisions between refresh and read/write operations. wait is asserted when a burst crosses a row boundary. wait is also used to mask the delay asso ciated with opening a new internal page. wait is asserted and should be ignored during asynchronous and page mode operations. j4, j5, j6 nc ? not internally connected. d6 v cc supply device power supply: (1.70v?1.95v) powe r supply for device core operation. e1 v cc q supply i/o power supply: (1.70v?1.95v) powe r supply for inpu t/output buffers. e6 v ss supply v ss must be connected to ground. d1 v ss q supply v ss q must be connected to ground.
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 7 ?2003 micron technology, inc. all rights reserved. n ote: 1. when lb# and ub# are in select mode (low), dq[15:0] are affected. when only lb# is in select mode, dq[7:0] are affected. when only ub# is in the select mode, dq[15:8] are affected. 2. the wait polarity is configured through the bus configuration register (bcr[10]). 3. the device will cons ume active power in this mode whenever addresses are changed. 4. when the device is in standby mo de, address inputs and data inputs/outp uts are internally isolated from any external influence. 5. v in = v cc or 0v; all device balls must be static (unswitched) in order to achieve standby current. 6. dpd is maintained until rcr is reconfigured. 7. burst mode operation is initialized throug h the bus configuration register (bcr[15]). 8. the clock polarity is configured through the bus configuration register (bcr[6]). table 2: bus operations ? asynchronous mode mode power clk adv# ce# oe# we# cre lb#/ ub# wait 1 dq[15:0] 2 notes read active > standby l l l l h l l1 l data-out 3 write active > standby l l l x l l l1 l data-in 3 standby standby x x h x x l x x high-z 4 standby standby x x l x x l x x x 3, 5 configuration register active l l lhlhxlhigh-z dpd deep power-down l xhxxxxxhigh-z 6 table 3: bus operations ? burst mode mode power clk adv# ce# oe# we# cre lb#/ ub# wait 1 dq[15:0] 2 notes async read active > standby l l l l hllldata-out2, 3 async write active > standby l l l x l l l l data-in 2, 3 standby standby x x h x x l x x high-z 4 standby standby x x l x x l x x x 3, 5 initial burst read active > standby l l x h l l l data-out 2, 3, 7, 8 initial burst write active > standby l l h llxldata-in3, 7, 8 burst continue active > standby h l x x l x x data-in or data-out 3, 7, 8 burst suspend active > standby l x l x x l x x high-z 3, 7 configuration register active l l h l h x x high-z 7, 8 dpd deep power-down lxhxxxxxhigh-z6
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 8 ?2003 micron technology, inc. all rights reserved. n ote: 1. contact factory for availability. table 4: abbreviated component marks ? cellularram fbga-packaged components part number engineering sample qualified sample mt45w4mw16bfb-701 wt px344 pw344 mt45w4mw16bfb-706 wt px340 pw340 mt45w4mw16bfb-856 wt px345 pw345 MT45W2MW16Bfb-701 wt px244 pw244 MT45W2MW16Bfb-706 wt px240 pw240 MT45W2MW16Bfb-856 wt px245 pw245 mt45w4mw16bfb-706 it px352 1 pw352 1 mt45w4mw16bfb-856 it px354 1 pw354 1 mt45w4ml16bfb-856 it px355 1 pw355 1 mt45w4ml16bfb-706 it px357 1 pw357 1 MT45W2MW16Bfb-706 it px248 1 pw248 1 MT45W2MW16Bfb-856 it px250 1 pw250 1 mt45w2ml16bfb-856 it px251 1 pw251 1 mt45w2ml16bfb-706 it px253 1 pw253 1
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 9 ?2003 micron technology, inc. all rights reserved. functional description in general, the mt45w4mw16bfb device and the MT45W2MW16Bfb device ar e high-density alterna- tives to sram and pseudo sram products, popular in low-power, portable applications. the mt45w4mw16bfb device contains 67,108,864 bits organized as 4,194,304 ad dresses by 16 bits. the MT45W2MW16Bfb contains 33,554,432 bits organized as 2,097,152 addresses by 16 bits. both devices imple- ment the same high-speed bus interface found on burst mode flash products. the cellularram bus interface supports both asyn- chronous and burst mode transfers. page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous read protocol. power-up initialization cellularram products incl ude an on-chip voltage sensor used to launch the power-up initialization pro- cess. initialization will configure the bcr and the rcr with their default settings (see table 5 on page 16 and table 8 on page 21). v cc and v cc q must be applied simultaneously. when they reach a stable level at or above 1.70v, the device will require 150s to complete its self-initialization process. during the initialization period, ce# should remain high. when initialization is complete, the device is ready for normal operation. figure 3: power-up initialization timing bus operating modes the mt45w4mw16bfb and MT45W2MW16Bfb cellularram products incorp orate a burst mode inter- face found on flash products targeting low-power, wireless applications. this bus interface supports asynchronous, page mode, and burst mode read and write transfers. the specific interface supported is defined by the value loaded into the bus configuration register. page mode is controlled by the refresh config- uration register (rcr[7]). asynchronous mode cellularram products power up in the asynchro- nous operating mode. this mode uses the industry- standard sram control bus (ce#, oe#, we#, lb#/ ub#). read operations (figure 4) are initiated by bringing ce#, oe#, and lb#/ub# low while keeping we# high. valid data will be driven out of the i/os after the specified access time has elapsed. write operations (figure 5) occur when ce#, we#, and lb#/ ub# are driven low. during asynchronous write operations, the oe# level is a ?don't care,? and we# will override oe#. the data to be written is latched on the rising edge of ce#, we#, or lb#/ub# (whichever occurs first). asynchrono us operations (page mode disabled) can either use the adv input to latch the address, or adv can be driven low during the entire read/write operation. during asynchronous operation, the clk input should be held low. wait will be driven while the device is enabled and its state should be ignored. figure 4: read op eration (adv = low) n ote: adv must remain low for page mode operation. figure 5: write oper ation (adv = low) vcc v ccq device initialization vcc = 1.70v device ready for normal operation t pu > 150s address valid data ce# don?t car e data valid oe# we# lb#/ub# t rc = read cycle time a ddress address valid data ce# don?t car e data valid oe# we# lb#/ub# t wc = write cycle time a ddress
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 10 ?2003 micron technology, inc. all rights reserved. page mode read operation page mode is a performance-enhancing extension to the legacy asynchronous read operation. in page- mode-capable products, an initial asynchronous read access is performed, then adjacent addresses can be read quickly by simply changing the low-order address. addresses a[3:0] are used to determine the members of the 16-address cellularram page. addresses a[4] and higher must remain fixed during the entire page mode access. figure 6 shows the timing for a page mode access. page mode takes advantage of the fact that adjacent addresses can be read in a shorter period of time than random addresses. write operations do not include comparable page mode functionality. during asynchronous page mode operation, the clk input must be held low. ce# must be driven high upon completion of a page mode access. wait will be driven while the device is enabled and its state should be ignored. page mode is enabled by setting rcr[7] to high. write operations do not include comparable page mode functionality. adv must be driven low during all page mode read accesses. figure 6: page mo de read operation (adv = low) burst mode operation burst mode operations enable high-speed synchro- nous read and write operations. burst operations consist of a multiclock sequence that must be per- formed in an ordered fashion. after ce# goes low, the address to access is latched on the next rising edge of clk or adv# (whichever occurs first). during this first clock rising edge, we# indicates whether the operation is going to be a read (we# = high, figure 7 on page 11) or write (we# = low, figure 8 on page 11). the size of a burst can be specified in the bcr as either a fixed length or continuous. fixed-length bursts consist of four, eight, or sixteen words. continu- ous bursts have the ability to start at a specified address and burst through the entire memory. the latency count stored in the bcr defines the number of clock cycles that elapse before the initial data value is transferred between the processor and cellularram device. the wait output will be asserted as soon as a burst is initiated, and will be de-asserted to indicate when data is to be transferred into (or out of ) the memory. wait will again be asserted if the burst crosses a row boundary. once the cellularram device has restored the previous row's data and accessed the next row, wait will be de-asserted and the burst can continue (see figure 28 on page 38). data ce# don?t car e oe# we# lb#/ub# a ddress add[0] add[1] add[2] add[3] d[1] d[2] d[3] t aa t apa t apa t apa d[0]
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 11 ?2003 micron technology, inc. all rights reserved. figure 7: burst mode read (4-word burst) 1 figure 8: burst mode write (4-word burst) 1 n ote: 1. nondefault bcr settings: latency code two (three clocks); wait active low; hold data one clock; wait asserted during delay. a[21:0] d[0] adv# ce# oe# d[1] d[2] d[3] we# wait d q[15:0] lb#/ub# latency code 2 (3 clocks) clk don?t care read burst identified (we# = high) address valid a[21:0] d[0] adv# ce# oe# d[1] d[2] d[3] we# wait d q[15:0] lb#/ub# address valid latency code 2 (3 clocks) clk don?t car e write burst identified (we# = low)
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 12 ?2003 micron technology, inc. all rights reserved. mixed-mode operation the device can support a combination of synchro- nous read and asynchronous write operations when the bcr is configured for synchronous opera- tion. the asynchronous write operation requires that the clock (clk) remain low during the entire sequence. the adv# signal can be used to latch the target address, or it can remain low during the entire write operation. ce# must return high when transi- tioning between mixed-mode operations. note that the t cka period is the same as a read or write cycle. this time is required to ensure adequate refresh. mixed-mode operation facilitates a seamless interface to legacy burst mode flash memory controllers. see figure 36 on page 46 for the ?asynchronous write followed by burst read? timing diagram. wait operation wait output on the cellularram device is typically connected to a shared, system-level wait signal (see figure 9 below). the shared wait signal is used by the processor to coordinate tr ansactions with multiple memories on the synchronous bus. figure 9: wired or wait configuration once a read or write operation has been initi- ated, wait goes active to indicate that the cellular- ram device requires additional time before data can be transferred. for read operations, wait will remain active until valid data is output from the device. for write operations, wait will indicate to the memory controller when data will be accepted into the cellu- larram device. when wait transitions to an inactive state, the data burst will progress on successive clock edges. ce# must remain asserted at least as long as wait is asserted. bringing ce# high while wait is asserted may cause data corruption. wait output also performs an arbitration role when a read or write operation is launched while an on- chip refresh is in progress. if a collision occurs, wait pin be asserted for additional clock cycles, until the refresh has completed (see figures 10 and 11 on page 13). when the refresh operation has completed, the read or write operation will continue normally. wait is also asserted when a continuous read or write burst crosses a row boundary. the wait asser- tion allows time for the new row to be accessed, and permits any pending refresh operations to be per- formed. lb#/ub# operation the lb# enable and ub# enable signals support byte-wide data transfers. during read operations, the enabled byte(s) are driven onto the dqs. the dqs associated with a disabled byte are put into a high-z state during a read operat ion. during write opera- tions, any disabled bytes will not be transferred to the ram array and the internal value will remain unchanged. during an asynchronous write cycle, the data to be written is latched on the rising edge of ce#, we#, lb#, or ub#, whichever occurs first. when both the lb# and ub# are disabled (high) during an operation, the device will disable the data bus from receiving or transmitting data. although the device will seem to be deselected, it remains in an active mode as long as ce# remains low. cellularram external pull-up/ pull-dow n resistor processor ready other device wait other device wait wait
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 13 ?2003 micron technology, inc. all rights reserved. figure 10: refresh collision during read operation 1 n ote: 1. nondefault bcr settings: latency code two (three clocks); wait active low; hold data one cloc k; wait asserted during delay. figure 11: refresh collis ion during write operation 1 n ote: 1. nondefault bcr settings: latency code two (three clocks); wait active low; hold data one cloc k; wait asserted during delay. a[21:0] adv# ce# oe# we# wait d q[15:0] clk v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol d[2] d[1] d[3] valid address additional wait states inserted to allow refresh completion. lb#/ub# don?t care d[0] high-z a[21:0] adv# ce# oe# we# wait d q[15:0] clk d[1] d[0] d[3] d[2] valid address additional wait states inserted to allow refresh completion. lb#/ub# don?t care v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol high-z
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 14 ?2003 micron technology, inc. all rights reserved. low-power operation standby mode operation during standby, the device current consumption is reduced to the level necessary to perform the dram refresh operation. standby operation occurs when ce# is high and there are no transactions in progress. the device will enter standby operation upon com- pletion of a read or write operation, or when the address and control inputs remain static for an extended period of time. this ?active? standby mode will continue until a change occurs to the address or control inputs. temperature compensated refresh temperature compensated refresh (tcr) is used to adjust the refresh rate depending on the device operat- ing temperature. dram technology requires increas- ingly frequent refresh operations to maintain data integrity as temperatures increase. more frequent refresh is required due to increased leakage of the dram capacitive storage elements as temperatures rise. a decreased refresh rate at lower temperatures will facilitate a savings in standby current. tcr allows for adequate refresh at four different temperature thresholds (+15c, +45c, +70c, and +85c). the setting selected must be for a temperature higher than the case temp erature of the cellularram device. if the case temperatur e is +50c, the system can minimize self refresh current consumption by selecting the +70c setting. the +15c and +45c settings would result in inadequate refreshing and cause data corrup- tion. partial array refresh partial array refresh (par) restricts refresh operation to a portion of the total memory array. this feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. the refresh options are full array, three-quarters array, one-half array, one-quarter array, or none of the array. the mapping of these partitions can start at either the beginning or the end of the address map (see tables 9 and 10 on page 21). read and write operations to address ranges receiving refresh will not be affected. data stored in addresses not receiving refresh will become corrupted. deep power-do wn operation deep power-down (dpd) operation disables all refresh-related activity. this mode is used if the system does not require the storage provided by the cellular- ram device. any stored data will become corrupted when dpd is enabled. when refresh activity has been re-enabled, the cellularram device will require 150s to perform an initialization procedure before normal operations can resume. during this 150s period, the current consumption will be higher than the specified standby levels, but considerably lower than the active current specification. configuratio n registers two write-only, user-accessible configuration reg- isters have been included to define device operation. the bus configuration register (bcr) defines how the cellularram interacts with the system memory bus and is nearly identical to it s counterpart on burst mode flash devices. the refresh configuration register (rcr) is used to control how refresh is performed on the dram array. these registers are automatically loaded with default settings during power-up, and can be updated any time the devices are operating in a standby state. bus configurati on register the bcr defines how the cellularram device inter- acts with the system memory bus. page mode opera- tion is enabled by a bit contained in the rcr. the bcr is loaded using either a sy nchronous or an asynchro- nous write operation when a[19] is high and the configuration register enable (cre) input is also high (see figures 12 and 13 on page 15). when cre is low, a read or write operation will access the memory array. the values placed on address pins a[21:0] are latched into the bcr on the rising edge of adv#, ce#, or we#, whichever occurs first. lb# and ub# are ?don?t care.? table 5 on page 16 describes the control bits in the bcr. at power-up, the bcr is set to 9f4fh.
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 15 ?2003 micron technology, inc. all rights reserved. figure 12: configuration re gister write in asynchronous mode followed by read note: 1. nondefault bcr settings: latency code two (three clocks); wait active low; hold data one clock; wait asserted during del ay. 2. a[19] = low to load rcr; a[19] = high to load bcr. figure 13: configuration register write in synchrono us mode followed by read 1 note: 1. nondefault bcr settings: latency code two (three clocks); wait active low; hold data one clock; wait asserted during del ay. 2. a[19] = low to load rcr; a[19] = high to load bcr. a[21:0] ( except a19) clk opcode address address data valid a19 2 adv# ce# oe# we# lb#/ub# dq[15:0] initiate control register access write address bus value to control register cre t avs t avs t vp t vph t wc t wp t cw don?t car e select control register clk a[21:0] ( except a19) a19 2 cre adv# ce# oe# we# lb#/ub# wait dq[15:0] latch control register address t sp t sp t hd t csp t sp t hd high-z don?t care opcode address address high-z t cw t wc latch control register value
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 16 ?2003 micron technology, inc. all rights reserved. table 5: bus configuratio n register definition n ote: 1. all burst writes are continuous. a13 13 12 11 0 latency counter 3 2 1 wait polarity 4 5 wait configuration (wc) 6 clock configuration (cc) 7 8 output impedance burst wrap (bw)* 14 a12a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a 0 0 1 operation mode synchronous burst access mode asynchronous access mode (default) bcr[12] bcr[11] latency counter bcr[13] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 code 0?reserved code 1?reserved code 2 code 3 (default) code 4?reserved code 5?reserved code 6?reserved code 7?reserved 0 1 wait polarity active low active high (default) bcr[10] 0 1 wait configuration asserted during delay asserted one data cycle before delay (default) clock configuration falling edge rising edge (default) bcr[6] 0 1 output impedance full drive (default) 1/4 drive bcr[5] burst wrap (note 1) burst wraps within the burst length burst no wrap (default) bcr[3] bcr[1] bcr[0] burst length (note 2) bcr[2] 15 burst length (bl)* reserved reserved 9 10 reserved operating mode reserved 21?20 a14 a15 a[18:16] 0 1 register select select rcr select bcr must be set to "0" 19 18?16 register select reserved a19 a[21:20] reserved must be set to "0" must be set to "0" must be set to "0" must be set to "0" a ll must be set to "0" bcr[8] bcr[15] bcr[19] 0 1 0 1 0 0 0 1 0 1 1 1 1 0 1 1 4 words 8 words 16 words continuous burst (default)
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 17 ?2003 micron technology, inc. all rights reserved. burst length (bcr[2:0]) default = continuous burst burst lengths define the number of words the device outputs during a burst read operation. the device sup- ports a burst length of 4, 8, or 16 words. the device can also be set in continuous bu rst mode where data is out- put sequentially without regard to address boundaries. write bursts are always performed using continuous burst mode. burst wrap (bcr[3]) default = burst wraps within address boundaries the burst wrap option determines if a 4-, 8-, or 16- word burst read wraps within the burst length or steps through sequential addresses. if the wrap option is not enabled, the device outputs data from sequential addresses without regard to burst boundaries. when continuous burst operation is selected, the internal address wraps to 000000h if the device is read past the last address. output impedance (bcr[5]) default = outputs use full drive strength the output driver strength can be altered to adjust for different data bus loading scenarios. the reduced- strength option will be more than adequate in stacked chip (flash + cellularram) environments when there is a dedicated memory bus. the reduced-drive-strength option is included to minimize noise generated on the data bus during read operations. normal output impedance should be selected when using a discrete cellularram device in a more heavily loaded data bus environment. cellularram devices are tested using the full drive strength setting. partial drive is approxi- mately one-quarter full drive strength. outputs are configured at full drive strength during testing. table 6: sequence and burst length starting address wrap no wrap 4-word burst length 8-word burst length 16-word burst length continuous burst -- (dec) bcr[3] bcr3 linear linear linear linear 0 0 0-1-2-3 0-1-2-3-4-5-6-7 0- 1-2-3-4-5-6-7-8- 9-10-11-12-13-14-15 0-1-2-3-4-5-6-? 1 0 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8- 9-10-11-12-13-14-15-0 1-2-3-4-5-6-7-? 2 0 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12- 13-14-15-0-1 2-3-4-5-6-7-8-? 3 0 3-0-1-2 3-4-5-6-7-0-1-2 3- 4-5-6-7-8-9-10-11-12-13- 14-15-0-1-2 3-4-5-6-7-8-9-? 4 0 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11- 12-13-14-15-0-1-2-3 4-5-6-7-8-9-10-? 5 0 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11- 12-13-14-15-0-1-2-3-4 5 -6-7-8-9-10-11-? 6 0 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12- 13-14-15-0-1-2-3-4-5 6 -7-8-9-10-11-12- 7 0 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13- 14-15-0-1-2-3-4-5-6 7 -8-9-10-11-12-13-? ... ... ... ... ... ... ... 14 0 14-15-0-1-2-3-4-5-6-7-8-9-10 -11-12-13 14-15-16-17-18-19-20-.. 15 0 15-0-1-2-3-4-5-6-7-8-9-10-11 -12-13-14 15-16-17-18-19-20-21.. ... ... ... ... ... ... 0 1 0-1-2-3 0-1-2-3-4-5-6-7 0- 1-2-3-4-5-6-7-8- 9-10-11-12-13-14-15 0-1-2-3-4-5-6-? 1 1 1-2-3-4 1-2-3-4-5-6-7-8 1- 2-3-4-5-6-7-8-9- 10-11-12-13-14-15-16 1-2-3-4-5-6-7-? 2 1 2-3-4-5 2-3-4-5-6-7-8-9 2- 3-4-5-6-7-8-9-10- 11-12-13-14-15-16-17 2-3-4-5-6-7-8-? 3 1 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9- 10-11-12-13-14-15-16-17- 18 3-4-5-6-7-8-9-? 4 1 4-5-6-7-8-9-10-11 4-5-6-7-8-9-10-11- 12-13-14-15-16-17-18-19 4-5-6-7-8-9-10-? 5 1 5-6-7-8-9-10-11-12 5-6-7-8-9-10-11-12- 13-...-15-16-17-18-19- 20 5-6-7-8-9-10-11? 6 1 6-7-8-9-10-11-12-13 6-7-8-9-10-11-12-13- 14-...-16-17-18-19-20-21 6-7-8-9-10-11-12? 7 1 ... 7-8-9-10-11-12-13- 14 7-8-9-10-11-12-13-14-...-17-18- 19-20-21-22 7-8-9-10-11-12-13? ... ... ... ... ... ... 14 1 ... 14-15-16-17-18-19-...-23-24-25- 26-27-28-29 14-15-16-17-18-19-20-? 15 1 15-16-17-18-19-20-...-24-25-26- 27-28-29-30 15-16-17-18-19-20-21-?
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 18 ?2003 micron technology, inc. all rights reserved. clock configuration (bcr[6]) default = transactions processed on rising edge of clock the clock configuration bit indicates whether syn- chronous operations are dependant upon the rising or falling edge of the clock in put. all of the timing dia- grams in this data sheet show the bus interaction aligned with the rising edge of the clock. wait configuration (bcr[8]) default = wait transitions one clock before data valid/invalid the wait configuration bit is used to determine when wait transitions between the asserted and the de-asserted state with respect to valid data presented on the data bus. the memory controller will use the wait signal to coordinate data transfer during synchronous read and write operations. when bcr[8] = 0, data will be valid or invalid on the clock edge immediately after wait transitions to the de-asserted or asserted state, respectively (figure 14, below, and figure 16 on page 19). when a8 = 1, the wait signal transitions one clock period prior to the data bus going valid or invalid (figures 15 below and 16 on page 18). figure 14: wait configuration (bcr[8] = 0) n ote: data valid/invalid immediat ely after wait transitions (bcr[8] = 0). see figure 15. figure 15: wait configuration (bcr[8] = 1) n ote: valid/invalid data delayed for one clock after wait transitions (bcr[8] = 1). see figure 16 on page 19. wait polarity (bcr[10]) default = wait active high the wait polarity bit indicates whether an asserted wait output should be high or low. this bit will determine whether the wait signal requires a pull-up or pull-down resistor to maintain the de-asserted state. latency counter (bcr[13:11]) default = three-clock latency the latency counter bits determine how many clocks occur between the beginning of a read or write operation and the first data value transferred. only latency code two (three clocks) or latency code three (four clocks) is allowed (see table 7 on page 20 and figure 17 on page 20). wait d q[15:0] clk data[0] data[1] data immediately valid (or invalid ) high-z wait d [15:0] clk data[0] data valid (or invalid) after one clock dela y high-z
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 19 ?2003 micron technology, inc. all rights reserved. figure 16: wait configur ation during burst operation 1 n ote: 1. clocked on rising edge. wait wait d q[15:0] clk d[0] d[1] bcr[8] = 0 data valid in current cycl e bcr[8] = 1 data valid in next cycle don?t care d[2] d[3] d[4]
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 20 ?2003 micron technology, inc. all rights reserved. n ote: 1. clock rates below 50 mhz are allowed as long as t csp specifications are met. figure 17: latency counter operating mode (bcr[15]) default = asynchronous operation the operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation. refresh configuration register the refresh configuration register (rcr) defines how the cellularram device performs its transparent self refresh. the rcr is loaded using either a synchro- nous or an asynchronous write operation when a[19] is low and the configuration register enable (cre) input is high (see figures 12 and 13 on page 15). when cre is low, a read or write operation will access the memory array. the values placed on addresses a[21:0] are latched into the rcr on the ris- ing edge of adv#, ce#, or we#, whichever occurs first. lb# and ub# are ?don?t care.? altering the refresh parameters can dramatically reduce current consump- tion during standby mode. page mode control is also embedded into the rcr. table 8 on page 21 describes the control bits used in the rcr. at power-up, the rcr is set to 0070h. partial array refresh (rcr[2:0]) default = full array refresh the par bits restrict refresh operation to a portion of the total memory array. this feature allows the device to reduce standby current by refreshing only that part of the memory array required by the host sys- tem. the refresh options are full array, three-quarters array, one-half array, one-quarter array, or none of the array. the mapping of these partitions can start at either the beginning or the end of the address map (see tables 9 and 10 on page 21). table 7: latency configuration latency configuration code max input clk frequency (mhz) -701 -856 2 (3 clocks) 75 (13.3 ns) 44 1 (22.7 ns) 3 (4 clocks) ? default 104 (9.62 ns) 66 (15.2 ns) a[21:0] adv# d q[15:0] clk code 2 valid output valid output valid output valid output valid output valid output valid output valid output valid output code 3 (default) d q[15:0] don?t care undefined v ih v il v ih v il v ih v il v oh v ol v oh v ol valid address
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 21 ?2003 micron technology, inc. all rights reserved. table 8: refresh configuration register mapping par a4 a3 a2 a1 a0 read configuratio n register address bus 4 5 1 2 3 0 reserved reserved 6 a5 0 1 deep power-down dpd enable dpd disable (default) rcr[4] tcr rcr[6] rcr[5] 1 1 1 1 0 0 0 0 maximum case temp. +85?c (default) +70?c +45?c +15?c a6 all must be set to "0" a[18:8] 18?8 19 21?20 register select reserved a[21:20] a19 0 1 register select select rcr select bcr rcr[19] all must be set to "0" rcr[1] 0 0 1 1 rcr[0] 0 1 0 1 refresh coverage full array (default) bottom 3/4 array bottom 1/2 array bottom 1/4 array rcr[2] 0 0 0 0 00 1 0 1 1 1 0 1 11 1 none of array top 3/4 array top 1/2 array top 1/4 array dpd must be set to "0" a7 7 page 0 1 page mode enable/disable page mode disabled (default) page mode enable rcr[7] table 9: 64mb address patterns for par (a4 = 1) rcr[2] rcr[1] rcr[0] active section address space size density 0 0 0 full die 000000h?3fffffh 4 meg x 16 64mb 0 0 1 three-quarters of die 000000h?2fffffh 3 meg x 16 48mb 0 1 0 one-half of die 000000h?1fffffh 2 meg x 16 32mb 0 1 1 one-quarter of die 000000h?0fffffh 1 meg x 16 16mb 1 0 0 none of die 0 0 meg x 16 0mb 1 0 1 three-quarters of die 100000h?3fffffh 3 meg x 16 48mb 1 1 0 one-half of die 200000h?3fffffh 2 meg x 16 32mb 1 1 1 one-quarter of die 300000h?3fffffh 1 meg x 16 16mb table 10: 32mb address patterns for par (a4 = 1) rcr[2] rcr[1] rcr[0] active section address space size density 0 0 0 full die 000000h?1fffffh 2 meg x 16 32mb 0 0 1 three-quarters of die 000000h?17ffffh 1.5 meg x 16 24mb 0 1 0 one-half of die 000000h?0fffffh 1 meg x 16 16mb 0 1 1 one-quarter of die 000000h?07ffffh 512k x 16 8mb 1 0 0 none of die 0 0 meg x 16 0mb 1 0 1 three-quarters of die 080000h?1fffffh 1.5 meg x 16 24mb 1 1 0 one-half of die 100000h?1fffffh 1 meg x 16 16mb 1 1 1 one-quarter of die 180000h?1fffffh 512k x 16 8mb
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 22 ?2003 micron technology, inc. all rights reserved. deep power-down (rcr[4]) default = dpd disabled the deep power-down bit enables and disables all refresh-related activity. this mode is used if the system does not require the storage provided by the cellular- ram device. any stored data will become corrupted when dpd is enabled. when refresh activity has been re-enabled, the cellularram device will require 150s to perform an initializati on procedure before normal operations can resume. deep power-down is enabled when rcr[4] = 0, and remains enabled until rcr[4] is set to ?1.? temperature compensated refresh (rcr[6:5]) default = +85c operation the tcr bits allow for adequate refresh at four dif- ferent temperature thresholds (+15c, +45c, +70c, and +85c). the setting selected must be for a tem- perature higher than the case temperature of the cellularram device. if the case temperature is +50c, the system can mini mize self refresh current consumption by selecting the +70c setting. the +15c and +45c settings wo uld result in inadequate refreshing and cause data corruption. page mode operation (rcr[7]) default = disabled the page mode operation bit determines whether page mode is enabled for asynchronous read opera- tions. in the power-up default state, page mode is dis- abled.
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 23 ?2003 micron technology, inc. all rights reserved. absolute maximum ratings* voltage to any ball except v cc , v cc q relative to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.50v to (4.0v or vc cq + 0.3v, whichever is less) voltage on v cc supply relative to v ss . . -0.2v to +2.45v voltage on v cc q supply relative to v ss . -0.2v to +4.0v storage temperature (plastic). . . . . . . . -55oc to +150oc operating temperature (case) wireless. . . . . . . . . . . . . . . . . . . . . . . . . . -25oc to +85oc industrial . . . . . . . . . . . . . . . . . . . . . . . . -40oc to +85oc soldering temperature and time 10s (lead only) . . . . . . . . . . . . . . . . . . . . . . . . . . . +260oc *stresses greater than those listed may cause per- manent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect reliability. n ote: 1. this parameter is specified with the outputs disabl ed to avoid external loading ef fects. the user must add the cur- rent required to drive output capacita nce expected in the actual system. 2. this device assumes a standby mode if the chip is disabled (ce# high). it will also automatically go into a standby mode whenever all input signals are quiescent (not toggling), regardless of the state of c e#. in order to achieve low standby current, all inputs mu st be driven to either v cc q or v ss . 3. i sb (max) values measured with par se t to full array and tcr set to +85c. table 11: electrical characte ristics and operating conditions wireless temperature (-25oc < t c < +85oc) industrial temperature (-40oc < t c < +85oc) description conditions symbol -70 (104 mhz) -85 (66 mhz) units notes min max min max supply voltage v cc 1.70 1.95 1.70 1.95 v i/o supply voltage v cc q (1.8v) 1.70 2.25 1.70 2.25 v input high voltage v ih 1.40 v cc q + 0.2 1.40 v cc q + 0.2 v input low voltage v il -0.20 0.4 -0.20 0.4 v output high voltage i oh = -0.2ma v oh 0.80 v cc q 0.80 v cc q v output low voltage i ol = +0.2ma v ol 0.20 v cc q 0.20 v cc q v input leakage current v in = 0 to v cc qi li 11a output leakage current oe# = v ih or chip disabled i lo 11a2 read operating current v in = v cc q or 0v chip enabled, i out = 0 i cc 1ma1, 2 asynchronous random read 25 25 asynchronous page read 15 15 initial access, burst read 35 35 continuous burst read 11 11 write operating current v in = v cc q or 0v chip enabled i cc 2 25 25 ma 1, 2 standby current (32mb) v in = v cc q or 0v chip disabled i sb 90 90 a 2, 3 standby current (64mb) v in = v cc q or 0v chip disabled i sb 100 100 a 2, 3
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 24 ?2003 micron technology, inc. all rights reserved. n ote: i tcr (max) values measured wi th par set to full array. n ote: i par (max) values measured with tcr set to 85c. table 12: temperature compensated re fresh specifications and conditions description conditions symbol density max case temperatures typ max units temperature compensated refresh standby current v in = v cc or 0v chip disabled i tcr 64mb +85c 100 a +70c tbd a +45c tbd a +15c 50 a 32mb +85c 90 a +70c tbd a +45c tbd a +15c 50 a table 13: partial array refresh specifications and conditions description conditions symbol density array partition typ max units partial array refresh standby current v in = v cc or 0v, chip disabled i par 64mb full 100 a 3/4 tbd a 1/2 tbd a 1/4 tbd a 050a 32mb full 90 a 3/4 tbd a 1/2 tbd a 1/4 tbd a 050a table 14: deep power-down specifications description conditions symbol typ max units deep power-down v in = v cc or 0v; +25c i zz 10 a
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 25 ?2003 micron technology, inc. all rights reserved. n ote: 1. these parameters are verified in device characterization and are not 100% tested. figure 18: ac input/outp ut reference waveform n ote: ac test inputs are driven at v cc q for a logic 1 and v ss for a logic 0. input timing begins at v cc q/2, and output timing ends at v cc q/2. input rise and fall times (10% to 90%) < 1.6ns. figure 19: output load circuit n ote: all tests are performed with the outputs configured for full drive strength (bcr[5] = 0). table 15: capacitance description conditions symbol min max units notes input capacitance t c = +25oc; f = 1 mhz; v in = 0v c in ?6pf1 input/output capacitance (dq) c i / o ?6pf1 outpu t test points i nput v cc q v ss v cc q/2 v cc q/2 dut vccq r1 r2 30pf test poin t table 16: output load circuit v cc q r1/r2 1.8v 2.7 ? 2.5v 3.7 ? 3.0v 4.5 ?
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 26 ?2003 micron technology, inc. all rights reserved. n ote: 1. all tests are performed with the outputs conf igured for full drive strength (bcr[5] = 0). 2. see the appendix at the end of this data sheet. 3. high-z to low-z timings are tested wi th the circuit shown in figure 19 on page 25. the low-z timings measure a 100mv transition away from the high-z (v cc q/2) level toward either v oh or v ol . 4. low-z to high-z timings are tested wi th the circuit shown in figure 19 on page 25. the high-z timings measure a 100mv transition from either v oh or v ol toward v cc q/2. table 17: asynchronous read cycle timing requirements 1 parameter symbol -701, -706 -856 units notes min max min max address access time t aa 70 85 ns adv# access time t aadv 70 85 ns page access time t apa 20 25 ns address hold from adv# high t avh 55ns address setup to adv# high t avs 10 10 ns lb#/ub# access time t ba 70 85 ns lb#/ub# disable to high-z output t bhz 0808ns4 lb#/ub# enable to low-z output t blz 10 10 ns 3 ce# high between subseque nt mixed-mode operations t cbph 55ns maximum ce# pulse width t cem 10 10 s 2 ce# low to wait valid t cew 17.517.5ns chip select access time t co 70 85 ns ce# low to adv# high t cvs 10 10 ns chip disable to high-z output t hz 0808ns4 chip enable to low-z output t lz 10 10 ns 3 output enable to valid output t oe 20 20 ns output hold from output disable t oh 55ns output hold from address change t oha 55ns output disable to high-z output t ohz 0808ns4 output enable to low-z output t olz 55ns3 page cycle time t pc 20 25 ns read cycle time t rc 70 85 ns address setting time t s 10 10 s 2 adv# pulse width low t vp 10 10 ns adv# pulse width high t vph 10 10 ns
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 27 ?2003 micron technology, inc. all rights reserved. n ote: 1. all tests are performed with the outputs conf igured for full drive strength (bcr[5] = 0). 2. low-z to high-z timings are tested wi th the circuit shown in figure 19 on page 25. the high-z timings measure a 100mv transition from either v oh or v ol toward v cc q/2. 3. high-z to low-z timings are tested wi th the circuit shown in figure 19 on page 25. the low-z timings measure a 100mv transition away from the high-z (v cc q/2) level toward either v oh or v ol . 4. clock rates below 50 mhz ( t clk > 20ns) are allowed as long as t csp specifcations are met. table 18: burst read cy cle timing requirements 1 parameter symbol -701 -706, -856 units notes min max min max burst to read access time t aba 33 55 ns clk to output delay t aclk 6.5 10 ns address setup to adv# high t avs 10 10 ns burst oe# low to output delay t boe 20 20 ns ce# high between subsequent mixed-mode operations t cbph 5 5 ns ce# low to wait valid t cew 17.517.5ns clk period t clk 9.62 20 15 20 ns 4 ce# setup time to active clk edge t csp 4 20 4 20 ns hold time from active clk edge t hd 1 1 ns chip disable to high-z output t hz 0 8 0 8 ns 2 clk rise or fall time t khkl 1.6 1.6 ns clk to wait valid t khtl 6.5 10 ns clk to high-z output t khz 3838ns clk to low-z output t klz 2525ns output hold from clk t koh 2 2 ns clk high or low time t kp 3 3 ns output disable to high-z output t ohz 0 8 0 8 ns 2 output enable to low-z output t olz 5 5 ns 3 setup time to active clk edge t sp 3 3 ns
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 28 ?2003 micron technology, inc. all rights reserved. n ote: 1. see the appendix at the end of this data sheet. 2. low-z to high-z timings are tested wi th the circuit shown in figure 19 on page 25. the high-z timings measure a 100mv transition from either v oh or v ol toward v cc q/2. 3. high-z to low-z timings are tested wi th the circuit shown in figure 19 on page 25. the low-z timings measure a 100mv transition away from the high-z (v cc q/2) level toward either v oh or v ol . table 19: asynchronous write cycle timing requirements parameter symbol -701, -706 -856 units notes min max min max address hold from adv# going high t avh 55ns address setup to adv# going high t avs 10 10 ns address valid to end of write t aw 70 85 ns lb#/ub# select to end of write t bw 70 85 ns maximum ce# pulse width t cem 10 10 s 1 ce# low to wait valid t cew 1 7.5 1 7.5 ns async address-to-bur st transition time t cka 70 85 ns ce# low to adv# high t cvs 10 10 ns chip enable to end of write t cw 70 85 ns data hold from write time t dh 00ns data hold from write time t dh 00ns data to write time overlap t dw 23 23 ns 1 chip enable to low-z output t lz 10 10 ns 3 end write to low-z output t ow 55ns 3 address setup time t as 00ns1 adv# pulse width t vp 10 10 ns adv# pulse width high t vph 10 10 ns adv# setup to end of write t vs 70 85 ns write cycle time t wc 70 85 ns write to high-z output t whz 0808ns 2 write pulse width t wp 46 55 ns 1 write pulse width high t wph 10 10 ns write recovery time t wr 00ns
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 29 ?2003 micron technology, inc. all rights reserved. n ote: 1. clock rates below 50 mhz ( t clk > 20ns) are allowed as long as t csp specifications are met. table 20: burst write cycle timing requirements parameter symbol -701 -706, -856 units notes min max min max ce# high between subsequent mixed-mode operations t cbph 5 5 ns ce# low to wait valid t cew 17.517.5ns clock period t clk 9.62 20 15 20 ns 1 ce# setup to clk active edge t csp 4 20 4 20 ns hold time from active clk edge t hd 1 1 ns clk rise or fall time t khkl 1.6 1.6 ns clock to wait valid t khtl 6.5 10 ns clk high or low time t kp 33ns setup time to activate clk edge t sp 3 3 ns table 21: initialization timing requirements parameter symbol -701, -706 -856 units note min max min max initialization period (requi red before normal operations) t pu 150 150 s
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 30 ?2003 micron technology, inc. all rights reserved. burst cellularram timing diagrams figure 20: initialization period t pu v cc, vccq = 1.70v vcc (min) device ready fo r normal operatio n table 22: initializatio n timing parameters parameter symbol -701, -706 -856 units note min max min max initialization period t pu 150 150 s
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 31 ?2003 micron technology, inc. all rights reserved. figure 21: asynchronous read v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il a[21:0] adv# ce# lb#/ub# oe# we# wait d q[15:0] valid address t cbph t aa t hz t ba high-z high-z t rc t co t oh t bhz t ohz t oe t cew valid output high-z undefine d don?t care t blz t lz t olz table 23: asynchronous re ad timing parameters symbol -701, -706 -856 units symbol -701, -706 -856 units min max min max min max min max t aa 70 85 ns t hz 0808ns t ba 70 85 ns t lz 10 10 ns t bhz 0 8 0 8 ns t oe 20 20 ns t blz 10 10 ns t oh 5 5 ns t cbph 5 5 ns t ohz 0 8 0 8 ns t cew 1 7.5 1 7.5 ns t olz 5 5 ns t co 70 85 ns t rc 70 85 ns
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 32 ?2003 micron technology, inc. all rights reserved. figure 22: asynchronous read using adv# a[21:0] adv# ce# lb#/ub# oe# we# wait d q[15:0] valid address t vph t cbph t aadv t aa t vp t hz t ba high-z high-z t cvs t co t blz t oh t bhz t ohz t lz t oe t olz valid output t avh t avs high-z undefined don?t care t cew v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il table 24: asynchronous re ad timing parameters symbol -701, -706 -856 units symbol -701, -706 -856 units min max min max min max min max t aa 70 85 ns t cvs 10 10 ns t aadv 70 85 ns t hz 0808ns t avh 5 5 ns t lz 10 10 ns t avs 10 10 ns t oe 20 20 ns t ba 70 85 ns t oh 5 5 ns t bhz 0 8 0 8 ns t ohz 0 8 0 8 ns t blz 10 10 ns t olz 5 5 ns t cbph 5 5 ns t vp 10 10 ns t cew 1 7.5 1 7.5 ns t vph 10 10 ns t co 70 85 ns
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 33 ?2003 micron technology, inc. all rights reserved. figure 23: page mode read a[3:0] adv# ce# lb#/ub# oe# we# wait d q[15:0] valid address t cbph t aa t hz t ba high-z high-z t co t blz t oh t bhz t ohz t lz t oe t olz t cew high-z undefine d don?t care a[21:4] valid address valid address valid address valid address t rc valid output valid output valid output valid output t apa t cbph t pc v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il t oha table 25: asynchronous re ad timing parameters (page mode operation) symbol -701, -706 -856 units symbol -701, -706 -856 units min max min max min max min max t aa 70 85 ns t lz 10 10 ns t apa 20 25 ns t oe 20 20 ns t ba 70 85 ns t oh 5 5 ns t bhz 0 8 0 8 ns t oha 5 5 ns t blz 10 10 ns t ohz 0 8 0 8 ns t cbph 5 5 ns t olz 5 5 ns t cew 1 7.5 1 7.5 ns t pc 20 25 ns t co 70 85 ns t rc 70 85 ns t hz 0 8 0 8 ns
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 34 ?2003 micron technology, inc. all rights reserved. figure 24: single-access burst read operation 1 n ote: 1. nondefault bcr settings: latency code two (three cloc ks); wait active low; wa it asserted during delay. 2. clock rates below 50 mhz ( t clk > 20ns) are allowed as long as t csp specifications are met. a[21:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait d q[15:0] v oh v ol clk v ih v il v oh v ol t sp t clk t aclk t cew t hd t aba t avs valid output valid address high-z t koh t ohz t sp lb#/ub# v ih v il t csp high-z t olz high-z t hd t hd t sp t hz t kp t hd t sp undefined don?t care read burst identified (we# = high) t khtl t boe table 26: burst read timing parameters symbol -701 -706, -856 units symbol -701 -706, -856 units min max min max min max min max t aba 33 55 ns t hz 0 8 0 8 ns t aclk 6.5 10 ns t khtl 6.5 10 ns t avs 10 10 ns t koh 2 2 ns t boe 20 20 ns t kp 33ns t cew 17.517.5ns t ohz 0 8 0 8 ns t clk 9.62 20 15 20 ns t olz 5 5 ns t csp 4 20 4 20 ns t sp 3 3 ns t hd 1 1 ns
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 35 ?2003 micron technology, inc. all rights reserved. figure 25: 4-word burst read operation 1 n ote: 1. nondefault bcr settings: latency code two (three cloc ks); wait active low; wa it asserted during delay. 2. clock rates below 50 mhz ( t clk > 20ns) are allowed as long as t csp specifications are met. a[21:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait d q[15:0] v oh v ol clk v ih v il v oh v ol t sp t clk t hd t aba valid address high-z t koh t hz t hd t sp lb#/ub# v ih v il high-z t olz high-z t cbph t csp t sp t hd t sp t hd t ohz t avs t kp undefined don?t care read burst identified (we# = high) t cew t aclk t khtl valid output valid output valid output valid output t boe table 27: burst read timing parameters symbol -701 -706, -856 units symbol -701 -706, -856 units min max min max min max min max t aba 33 55 ns t hd 1 1 ns t aclk 6.5 10 ns t hz 0 8 0 8 ns t avs 10 10 ns t khtl 6.5 10 ns t boe 20 20 ns t koh 2 2 ns t cbph 5 5 ns t kp 33ns t cew 1 7.5 1 7.5 ns t ohz 0 8 0 8 ns t clk 9.62 20 15 20 ns t olz 5 5 ns t csp 4 20 4 20 ns t sp 3 3 ns
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 36 ?2003 micron technology, inc. all rights reserved. figure 26: 4-word burst re ad operation (with lb#/ub#) 1 n ote: 1. nondefault bcr settings: latency code two (three cloc ks); wait active low; wa it asserted during delay. 2. clock rates below 50 mhz ( t clk > 20ns) are allowed as long as t csp specifications are met. bcr configured with a burst length of four. a[21:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait d q[15:0] v oh v ol clk v ih v il v oh v ol t sp t clk t hd t aba valid address high-z t koh t khz t khz t klz t hz t hd t sp lb#/ub# v ih v il high-z t olz high-z t cbph t csp t sp t hd t sp t hd t ohz t avs t kp undefined don?t care read burst identified (we# = high) t cew high-z t aclk t khtl valid output valid output valid output t boe table 28: burst read timing parameters (with lb#/ub#) symbol -701 -706, -856 units symbol -701 -706, -856 units min max min max min max min max t aba 33 55 ns t hz 0 8 0 8 ns t aclk 6.5 10 ns t khtl 6.5 10 ns t avs 10 10 ns t khz 3838ns t boe 20 20 ns t klz 2525ns t cbph 5 5 ns t koh 2 2 ns t cew 17.517.5ns t kp 33ns t clk 9.62 20 15 20 ns t ohz 0 8 0 8 ns t csp 4 20 4 20 ns t olz 5 5 ns t hd 11ns t sp 3 3 ns
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 37 ?2003 micron technology, inc. all rights reserved. figure 27: read burst suspend 1 n ote: 1. nondefault bcr settings: latency code two (three cloc ks); wait active low; wa it asserted during delay. 2. clock rates below 50 mhz ( t clk > 20ns) are allowed as long as t csp specifications are met. a[21:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait d q[15:0] v oh v ol clk v ih v il v oh v ol t sp t hd high-z t olz t aclk lb#/ub# v ih v il t clk t sp t csp t sp t hd t avs t kp t sp t hd t koh valid output valid output undefined don?t care valid address high-z t cbph t hz t ohz valid output valid output valid output valid output t boe t ohz high-z valid address table 29: burst read timing parameters symbol -701 -706, -856 units symbol -701 -706, -856 units min max min max min max min max t aclk 6.5 10 ns t hz 0 8 0 8 ns t avs 10 10 ns t koh 22ns t boe 20 20 ns t kp 33ns t cbph 5 5 ns t ohz 0 8 0 8 ns t clk 9.62 20 15 20 ns t olz 5 5 ns t csp 4 20 4 20 ns t sp 3 3 ns t hd 1 1 ns
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 38 ?2003 micron technology, inc. all rights reserved. figure 28: continuous burst read showing an output delay with bcr[8] = 0(1) fo r end-of-row condition 1 n ote: 1. nondefault bcr settings: latency code two (three cloc ks); wait active low; wa it asserted during delay. 2. clock rates below 50 mhz ( t clk > 20ns) are allowed as long as t csp specifications are met. t aclk t koh a[21:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait d q[15:0] v oh v ol clk v ih v il v oh v ol t khtl t khtl t clk t kp t khkl lb#/ub# v ih v il wait config (bcr8) = 1 wait config (bcr8) = 0 valid output valid output valid output don?t care valid output table 30: burst read timing parameters symbol -701 -706, -856 units symbol -701 -706, -856 units min max min max min max min max t aclk 6.5 10 ns t khtl 6.5 10 ns t clk 9.62 20 15 20 ns t koh 2 2 ns t khkl 1.6 1.6 ns t kp 3 3 ns
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 39 ?2003 micron technology, inc. all rights reserved. figure 29: ce#-controll ed asynchronous write a[21:0] adv# ce# lb#/ub# oe# we# wait d q[15:0] in valid address high-z high-z t wc t cew valid input t aw don?t care t wr t cw t dw d q[15:0] out t whz t bw high-z t lz t dh t as t cem t wp t wph v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il table 31: asynchronous write timing parameters symbol -701, -706 -856 units symbol -701, -706 -856 units min max min max min max min max t as 00ns t dw 23 23 ns t aw 70 85 ns t lz 10 10 ns t bw 70 85 ns t wc 70 85 ns t cem 10 10 s t whz 0808ns t cew 1 7.5 1 7.5 ns t wp 46 55 ns t cw 70 85 ns t wph 10 10 ns t dh 00ns t wr 00ns
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 40 ?2003 micron technology, inc. all rights reserved. figure 30: lb#/ ub#-controlled asynchronous write v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il a[21:0] adv# ce# lb#/ub# oe# we# wait d q[15:0] in v ih v il valid address high-z t wc t cew valid input t aw don?t car e t wr t cw t dw d q[15:0] out v oh v ol t whz t bw t lz t dh t as t cem t wp t wph high-z high-z table 32: asynchronous write timing parameters symbol -701, -706 -856 units symbol -701, -706 -856 units min max min max min max min max t as 00ns t dw 23 23 ns t aw 70 85 ns t lz 10 10 ns t bw 70 85 ns t wc 70 85 ns t cem 10 10 s t whz 08 08 ns t cew 1 7.5 1 7.5 ns t wp 46 55 ns t cw 70 85 ns t wph 10 10 ns t dh 0 0 ns t wr 0 0 ns
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 41 ?2003 micron technology, inc. all rights reserved. figure 31: we#-controlle d asynchronous write v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il a[21:0] adv# ce# lb#/ub# oe# we# wait d q[15:0] in v ih v il valid address t wc t cew valid input t aw don?t car e t wr t dw d q[15:0] out v oh v ol t whz t bw t cw t cem t lz t wp t dh t ow t as t wph high-z high-z high-z table 33: asynchronous write timing parameters symbol -701, -706 -856 units symbol -701, -706 -856 units min max min max min max min max t as 00ns t lz 10 10 ns t aw 70 85 ns t ow 55ns t bw 70 85 ns t wc 70 85 ns t cem 10 10 s t whz 08 08 ns t cew 1 7.5 1 7.5 ns t wp 46 55 ns t cw 70 85 ns t wph 10 10 ns t dh 0 0 ns t wr 0 0 ns t dw 23 23 ns
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 42 ?2003 micron technology, inc. all rights reserved. figure 32: asynchronous write using adv# v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il a[21:0] adv# ce# lb#/ub# oe# we# wait d q[15:0] in v ih v il valid address high-z high-z t cew valid input t vs don?t car e t cw t dw d q[15:0] out v oh v ol t whz t bw t lz t wp t dh t ow t as t cem t wph t vph t avh t avs t vp t aw high-z table 34: asynchronous write timing parameters symbol -701, -706 -856 units symbol -701, -706 -856 units min max min max min max min max t as 00ns t dw 23 23 ns t avh 5 5 ns t lz 10 10 ns t avs 10 10 ns t ow 55ns t aw 70 85 ns t vp 10 10 ns t bw 70 85 ns t vph 10 10 ns t cem 10 10 s t vs 70 85 ns t cew 1 7.5 1 7.5 ns t whz 08 08 ns t cw 70 85 ns t wp 46 55 ns t dh 0 0 ns t wph 10 10 ns
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 43 ?2003 micron technology, inc. all rights reserved. figure 33: burst write operation 1 n ote: 1. nondefault bcr settings: latency code two (three cloc ks); wait active low; wa it asserted during delay. 2. clock rates below 50 mhz ( t clk > 20ns) are allowed as long as t csp specifications are met. a[21:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait d q[15:0] v oh v ol clk v ih v il v ih v il t clk t sp t csp d[3] d[2] d[1] d[0] valid address t hd t sp t hd t sp high-z high-z lb#/ub# v ih v il t sp t hd t hd don?t car e write burst identified (we# = low) t cbph t khtl t cew table 35: burst wri te timing parameters symbol -701 -706, -856 units symbol -701 -706, -856 units min max min max min max min max t cbph 5 5 ns t hd 1 1 ns t cew 17.517.5ns t khtl 6.5 10 ns t clk 9.62 20 15 20 ns t sp 3 3 ns t csp 4 20 4 20 ns
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 44 ?2003 micron technology, inc. all rights reserved. figure 34: continuous burst write showing an output delay with bcr[8] = 0(1) fo r end-of-row condition 1 n ote: 1. nondefault bcr settings: latency code two (three cloc ks); wait active low; wa it asserted during delay. 2. clock rates below 50 mhz ( t clk > 20ns) are allowed as long as t csp specifications are met. a[21:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait d q[15:0] v oh v ol clk v ih v il v ih v il t khtl t khtl t clk t kp t khkl t sp t hd valid input d[n] valid input d[n+2] end of row valid input d[n+1] valid input d[n+3] don?t care v ih v il lb#/ub# table 36: burst wri te timing parameters symbol -701 -706, -856 units symbol -701 -706, -856 units min max min max min max min max t clk 9.62 20 15 20 ns t khtl 6.5 10 ns t hd 1 1 ns t kp 3 3 ns t khkl 1.6 1.6 ns t sp 3 3 ns
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 45 ?2003 micron technology, inc. all rights reserved. figure 35: burst write followed by burst read 1 n ote: 1. nondefault bcr settings: latency code two (three cloc ks); wait active low; wa it asserted during delay. 2. to allow self-refresh operations to occur between transactions, ce# mu st remain high for at least 5ns ( t cbph) to schedule the appropriate internal refresh operation. 3. clock rates below 50 mhz ( t clk > 20ns) are allowed as long as t csp specifications are met. a[21:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait d q[15:0] in/out v oh v ol clk v ih v il v ih v il t clk t sp t csp d[3] d[2] d[1] d[0] valid address t hd t sp t hd t sp t sp t hd valid address t aba t csp t ohz t koh t aclk valid output valid output valid output valid output high-z high-z v oh v ol lb#/ub# v ih v il t hd t sp t hd t sp t hd t hd high-z undefine d don?t care t boe t cbph 1 high-z table 37: write timing parameters symbol -701 -706, -856 units symbol -701 -706, -856 units min max min max min max min max t cbph 5 5 ns t hd 1 1 ns t clk 9.62 20 15 20 ns t sp 3 3 ns t csp 4 20 4 20 ns table 38: read timing parameters symbol -701 -706, -856 units symbol -701 -706, -856 units min max min max min max min max t aba 33 55 ns t hd 11ns t aclk 6.5 10 ns t koh 2 2 ns t boe 20 20 ns t ohz 0808ns t clk 9.62 20 15 20 ns t ohz 0 8 0 8 ns t csp 420420ns t sp 33ns
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 46 ?2003 micron technology, inc. all rights reserved. figure 36: asynchronous wr ite followed by burst read 1 n ote: 1. nondefault bcr settings: latency code two (three clocks); wait active low; wait asserted during delay. 2. when transitioning between asynchronous and burst operations , ce# must go high. ce# must re main high for at least 5ns ( t cbph) to schedule the appropria te internal re fresh operation. 3. clock rates below 50 mhz ( t clk > 20ns) are allowed as long as t csp specifications are met. t clk t cbph 1 t sp t hd valid address t ohz t koh t aclk high-z high-z valid address valid address t avs t avh t aw t wr t vph t vp t vs t cka a[21:0] v ih v il adv# v ih v il oe# v ih v il we# v ih v il wait d q[15:0] in/out v oh v ol clk v ih v il v ih v il v oh v ol ce# v ih v il lb#/ub# v ih v il t cw t wph t wp t wc t dh t dw data data high-z t cvs t hd t sp t cew t sp t hd t csp t wc t wc t bw t whz valid output valid output valid output valid output don?t care undefined t aba t boe table 39: write timing parameters symbol -701, -706 -856 units symbol -701, -706 -856 units min max min max min max min max t avh 55ns t vp 10 10 ns t avs 10 10 ns t vph 10 10 ns t aw 70 85 ns t vs 70 85 ns t bw 70 85 ns t wc 70 85 ns t cka 70 85 ns t whz 08 08 ns t cvs 10 10 ns t wp 46 55 ns t cw 70 85 ns t wph 10 10 ns t dh 0 0 ns t wr 0 0 ns t dw 20 23 ns table 40: read timing parameters symbol -701 -706, -856 units symbol -701 -706, -856 units min max min max min max min max t aba 33 55 ns t csp 4 20 4 20 ns t aclk 6.5 10 ns t hd 1 1 ns t boe 20 20 ns t koh 2 2 ns t cbph 5 5 ns t ohz 0 8 0 8 ns t cew 17.517.5ns t sp 3 3 ns t clk 9.62 20 15 20 ns
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 47 ?2003 micron technology, inc. all rights reserved. figure 37: asynchronous write followed by burst read?adv# low 1 n ote: 1. nondefault bcr settings: latency code two (three clocks); wait active low; wait asserted during delay. 2. when transitioning between asynchronous and burst operations , ce# must go high. ce# must re main high for at least 5ns ( t cbph) to schedule the appropria te internal re fresh operation. 3. clock rates below 50 mhz ( t clk > 20ns) are allowed as long as t csp specifications are met. t clk t sp t hd valid address t aba t csp t koh t aclk valid output high-z valid address valid address t cka a[21:0] v ih v il adv# v ih v il oe# v ih v il we# v ih v il wait d q[15:0] in/out v oh v ol clk v ih v il v ih v il v oh v ol ce# v ih v il lb#/ub# v ih v il t cw t wph t wp t wc t dh t dw data data high-z t hd t sp t sp t hd t wc t wc t bw t whz t aw t wr t sp t kp valid output valid output valid output undefine d don?t care t boe t ohz t cew high-z t cbph 1 table 41: write timing parameters symbol -701, -706 -856 units symbol -701, -706 -856 units min max min max min max min max t aw 70 85 ns t wc 70 85 ns t bw 70 85 ns t whz 08 08 ns t cka 70 85 ns t wp 46 55 ns t cw 70 85 ns t wph 10 10 ns t dh 00ns t wr 0 0 ns t dw 23 23 ns table 42: read timing parameters symbol -701 -706, -856 units symbol -701 -706, -856 units min max min max min max min max t aba 33 55 ns t csp 420420ns t aclk 6.5 10 ns t hd 11ns t boe 20 20 ns t koh 2 2 ns t cbph 5 5 ns t kp 33ns t cew 17.517.5ns t ohz 0 8 0 8 ns t clk 9.62 20 15 20 ns t sp 33ns
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 48 ?2003 micron technology, inc. all rights reserved. figure 38: asynchronous write followed by asyn chronous read?adv# low n ote: ce# must remain high for at least 5ns ( t cbph) to schedule the appropriat e internal refresh operation. valid address valid address a[21:0] v ih v il adv# v ih v il oe# we# wait d q[15:0] in/out v oh v ol v ih v il v oh v ol ce# lb#/ub# v ih v il v ih v il v ih v il v ih v il t cw t wph t wp t wc t dh t dw data high-z valid address t aa t hz t cbph 1 t s t cem valid output high-z t oe t olz t lz t blz t ohz t bhz t aw t wr t bw t whz don?t care undefined data table 43: write timing parameters symbol -701, -706 -856 units symbol -701, -706 -856 units min max min max min max min max t aw 70 85 ns t wc 70 85 ns t bw 70 85 ns t whz 08 08 ns t cw 70 85 ns t wp 46 55 ns t dh 0 0 ns t wph 10 10 ns t dw 23 23 ns t wr 0 0 ns table 44: read timing parameters symbol -701, -706 -856 units symbol -701, -706 -856 units min max min max min max min max t aa 70 85 ns t lz 10 10 ns t bhz 0 8 0 8 ns t oe 20 20 ns t blz 10 10 ns t ohz 0 8 0 8 ns t cbph 5 5 ns t olz 5 5 ns t cem 10 10 s t s 10 10 s t hz 0 8 0 8 ns
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 49 ?2003 micron technology, inc. all rights reserved. figure 39: asynchronous write followed by asynchronous read n ote: ce# must remain high for at least 5ns ( t cbph) to schedule the appropri ate internal refresh operation. valid address valid address t avs t avh t vph t vp t vs a[21:0] v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il adv# oe# we# wait d q[15:0] in/out v oh v ol v ih v il v oh v ol ce# lb#/ub# t cw t wph t wp t wc t dh t dw data data high-z valid address t aa t hz t cbph 1 t s t cem valid output high-z t oe t cvs t olz t lz t blz t ohz t bhz t aw t wr t bw t whz undefined don?t care table 45: write timing parameters symbol -701, -706 -856 units symbol -701, -706 -856 units min max min max min max min max t avh 55ns t vp 10 10 ns t avs 10 10 ns t vph 10 10 ns t aw 70 85 ns t vs 70 85 ns t bw 70 85 ns t wc 70 85 ns t cvs 10 10 ns t whz 0808ns t cw 70 85 ns t wp 46 55 ns t dh 00ns t wph 10 10 ns t dw 23 23 ns t wr 00ns table 46: read timing parameters symbol -701, -706 -856 units symbol -701, -706 -856 units min max min max min max min max t aa 70 85 ns t lz 10 10 ns t bhz 0 8 0 8 ns t oe 20 20 ns t blz 10 10 ns t ohz 0 8 0 8 ns t cbph 5 5 ns t olz 5 5 ns t cem 10 10 s t s 10 10 s t hz 0 8 0 8 ns
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www .micron.com, customer comment line: 800-932-4992 micron, and the micron and m logos are trademarks and/or service marks of micron technology, inc. cellularram is a trademark of micron technology, inc., inside the u.s. and a trademark of infineon technologies outside the u.s . all other trademarks are the property of their respective owners. 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 50 ?2003 micron technology, inc. all rights reserved. figure 40: 54-ball fbga n ote: 1. all dimensions in millimeters; max/min, or typical, as noted. 2. package width and length do not in clude mold protrusion; allowable mold protrusion is 0.25mm per side. data sheet designation: advance this data sheet contains initial descriptions of prod- ucts still in development. 0.700 0.075 0.10 c c solder ball material: eutectic 63% sn, 37% pb or 62% sn, 36% pb, 2% ag solder ball pad: ? 0.27mm ball a1 id encapsulation material: epoxy novola c substrate: plastic laminate 0.75 typ 8.00 0.10 ball a1 id 0.75 typ 0.35 typ 54x ? 1.00 max s eating plane ball a6 solder ball diameter refers to post reflow condition. the pre-reflow diameter is ? 0.33 ball a1 6.00 3.00 0.05 1.875 0.050 3.00 0.05 6.00 0.10 4.00
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 51 ?2003 micron technology, inc. all rights reserved. appendix a how extended timings impact cellularram tm operation introduction this note describes cellularram ? timing require- ments in systems that perform extended operations. cellularram products use a dram technology that periodically requires refresh to ensure against data cor- ruption. cellularram devices include on-chip circuitry that performs the required refresh in a manner that is completely transparent in systems with normal bus timings. the refresh circuitry imposes constraints on timings in systems that take longer than 10s to com- plete an operation. write operations are affected if the device is configured for asynchronous operation. both read and write operations are affected if the device is configured for burst-mode operation. asynchronous and pag e-mode operation cellularram products require that asynchronous write operations must be completed within 10s. after completing an operation, the device must either enter standby (by transitioning ce# high), or perform a second operation using a new address. figures 41 and 42 demonstrate these constraints as they apply during an asynchronous (p age-mode-disabled) opera- tion. either the ce# active period ( t cem in figure 41) or the address valid period ( t tm in figure 42) must be less than 10s during any operation to accommodate orderly scheduling of refresh. figure 41: extended timing for t cem n ote: timing constraints when pa ge mode is disabled. figure 42: extended timing for t tm n ote: 1. timing constraints when page mode is disabled. when a cellularram device is configured for page- mode operation, the address inputs are used to accel- erate read accesses and cannot be used by the on- chip circuitry to schedule refresh. ce# must return high upon completion of all write operations when page mode is enabled (see figure 43 below). the total time taken for a write operation should not exceed 10s to accommodate orderly scheduling of refresh. figure 43: extended timing for t cem 1 n ote: 1. timing constraints when page mode is enabled. modified timings are only required during extended write operations (see figure 44 below). an extended write operation requires that both the write pulse width ( t wp) and the data valid period ( t dw) be length- ened to at least the minimum write cycle time ( t wc [min]). these increased timi ngs ensure that time is available for both a refresh and successful completion of the write operation. figure 44: extended asynchronous write operation ce# a ddress t cem 10s < ce# a ddress < t tm 10s c e# t cem 10s < data valid data-in a ddress ce# lb#/ub# we# t cem or t tm > 10s t wp t wc (min) > t dw t wc (min) >
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 52 ?2003 micron technology, inc. all rights reserved. burst-mode operation when configured for burst-mode operation, it is necessary to allow the device to perform a refresh within any 10s window. on e of two conditions will enable the device to schedule a refresh within 10s. the first condition is when all burst operations com- plete within 10s. a burst completes when the ce# sig- nal is registered high on a positive (bcr[6] = 1) or a negative (bcr[6] = 0) clock edge. the second condition that allows a refresh is wh en a burst access crosses a row boundary. the row-boundary crossing causes wait to be asserted while the next row is accessed and enables the scheduling of refresh. summary cellularram products are designed to ensure that any possible asynchronous timings do not cause data corruption due to lack of refresh. slow bus timings will only affect asynchronous write operations (reads are unaffected). the impact on asynchronous write operations is that some of the timing parameters ( t wp and t dw) are lengthened. burst mode timings must allow the device to perform a refresh within any 10s period. a burst operation must either complete (ce# registered high) or cross a row boundary within 10s to ensure successful refresh scheduling. these timing requirements are likely to have little or no impact when interfacing a cellularram device with a low- speed memory bus.
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory advance 09005aef80be2036/09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. a 7/03 en 53 ?2003 micron technology, inc. all rights reserved. table 47: revision history change date changed by description 7 07/10/03 ddb input/output leakage to 1a. added t as, removed t s. 6 06/23/03 ddb incorporated industri al temperature data where applicable. rounded initial latency and initial access to 39ns. 5 06/20/03 ddb added -706 part information where applicable. 4 06/19/03 ddb removed t sp and t hd from ce# in burst diagrams. 3 06/18/03 ddb changed standby power to 90a and 100a as marked; changed specified values to ?tbd.? 2 06/09/03 ddb absolute maximum signal input value changed. 1 06/06/03 ddb initial release.

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