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| davicom semiconductor, inc. DM9103 10/100 mbps 3-port ethernet switch controller with pci interface data sheet preliminary version: DM9103-ds-p02 september 26, 2007
DM9103 3-port switch with pci interface 2 preliminary datasheet DM9103-ds-p02 september 26, 2007 1. general description............................................................................................... 8 2. block diagram........................................................................................................... 8 3. features ...................................................................................................................... 9 4. pin configuration : 128 pin lqfp........................................................................ 10 5. pin description ........................................................................................................ 11 5.1 pci bus interface.......................................................................................................... ...................... 11 5.2 p2 mii / rmii / reverse mii interfaces ..................................................................................... .......... 12 5.2.1 mii interfaces ........................................................................................................... ................................... 12 5.2.2 rmii interfaces.......................................................................................................... .................................. 13 5.2.3 reverse mii interfaces ................................................................................................... ............................. 13 5.3 eeprom interfaces .......................................................................................................... ................. 13 5.4 led pins................................................................................................................... .......................... 14 5.5 clock interface............................................................................................................ ........................ 14 5.6 network interface .......................................................................................................... ..................... 14 5.7 miscellaneous pins......................................................................................................... .................... 15 5.8 power pins ................................................................................................................. ........................ 15 5.9 strap pins table........................................................................................................... ........................ 16 5.9.1 strap pin in 3-port mode................................................................................................. ............................. 16 5.9.2 strap pin in 2-port mode ................................................................................................. ............................. 16 6. register set ............................................................................................................. 17 6.1 pci configuration registers ................................................................................................ ............... 17 6.1.1 identification id (xxxxxx00h - pciid) .................. ......................... .......................... ............... ...................... 18 6.1.2 command & status (xxxxxx04h - pcics) ..................................................................................... ............. 18 6.1.3 revision id (xxxxxx08h - pcirv) .......................................................................................... ..................... 19 6.1.4 miscellaneous function (xxxxxx0ch - pcilt)........... .......................... .......................... ................ .............. 20 6.1.5 i/o base address (xxxxxx10h - pciio) ..................................................................................... ................. 20 6.1.6 memory mapped base address (xxxxxx14 h - pcimem) .......................... .......................... ...................... .. 20 6.1.7 subsystem identification (xxxxxx2ch - pcisid)............................................................................ .............. 21 DM9103 3-port switch with pciinterface preliminary datasheet 3 DM9103-ds-p02 september 26, 2007 6.1.8 capabilities pointer (xxxxxx34h - cap _ptr) .............................................................................. ................. 21 6.1.9 interrupt & latency configuration (xxxxxx3ch - pciint) ................................................................... ......... 21 6.1.10 device specific configuration regi ster (xxxxxx40h- pciusr).............................................................. ... 21 6.1.11 power management register (xxxxxx 50h~pcipmr) ............................................................................ ... 22 6.1.12 power management control/status (xxxxxx54h~pmcsr)....................................................................... 23 6.2 pci control and status registers (cr)...................................................................................... ........ 24 6.2.1 system control register (cr0)............................................................................................ ....................... 25 6.2.2 transmit descriptor poll demand (cr1).................................................................................... ................. 25 6.2.3 receive descriptor poll demand (cr2).................... .......................... .......................... ............. ................. 25 6.2.4 receive descriptor base address (cr3) .................................................................................... ................ 25 6.2.5 transmit descriptor base address (cr4) ................................................................................... ................ 26 6.2.6 network status report register (cr5) ..................................................................................... .................. 26 6.2.7 network operation mode register (cr6) .................................................................................... ............... 28 6.2.8 interrupt mask register (cr7) ............................................................................................ ........................ 30 6.2.9 reserved (cr8) ........................................................................................................... ............................... 31 6.2.10 management access register (c r9)................ ......................... .......................... ..................... ................ 31 6.2.11 reserved (cr10) ......................................................................................................... ............................. 32 6.2.12 reserved (cr11) ......................................................................................................... ............................. 32 6.2.13 reserved (cr12) ......................................................................................................... ............................. 32 6.2.14 (reserved cr13) ......................................................................................................... ............................. 32 6.2.15 (reserved cr14) ......................................................................................................... ............................. 32 6.2.16 checksum offload control register (cr15) ................................................................................ ............. 32 6.12.17 switch control register (cr16) ......................................................................................... ..................... 32 6.2.18 per port index register (cr17) .......................................................................................... ...................... 33 6.2.19 per port control register (cr18)........................................................................................ ...................... 33 6.2.20 per port status data register (cr19)................................................................................... ................. 36 6.2.21 per port vlan tag byte register (cr20) .................................................................................. .............. 37 6.2.22 per port mib counter index re gister (cr21) .............. ......................... .................... .................. ............ 37 6.2.23 mib counter data register (cr22) ........................................................................................ ................... 38 6.2.24 vlan priority map register (cr23) ....................................................................................... ................... 38 6.2.25 port-based vlan mapping table register 0 (cr24) ......................................................................... ......... 38 6.2.26 port-based vlan mapping table register 1 (cr25) ......................................................................... ......... 39 6.2.27 port-based vlan mapping table register 2 (cr26) ......................................................................... ......... 39 6.2.28 port-based vlan mapping table register 3 (cr27) ......................................................................... ......... 39 DM9103 3-port switch with pci interface 4 preliminary datasheet DM9103-ds-p02 september 26, 2007 6.2.29 tos priority map register 0 (cr28)...................................................................................... ................... 40 6.2.30 tos priority map register 1 (cr29)...................................................................................... ................... 40 6.2.31 tos priority map register 2 (cr30)...................................................................................... ................... 41 6.2.32 tos priority map register 3 (cr31)...................................................................................... ................... 41 6.3 descriptor list............................................................................................................ ......................... 42 6.3.1 receive descriptor format ................................................................................................ ......................... 42 6.3.1.1 receive status register (rdes0)....................................................................................... .................. 42 6.3.1.2 receive descriptor control and buffer size register (rdes1)........................................................... .. 42 6.3.1.3 buffer starting address register (rdes2) .............................................................................. .............. 43 6.3.1.4 next descriptor address register (rdes3).............................................................................. ............. 43 6.3.2 transmit descriptor format ............................................................................................... ......................... 43 6.3.2.1 transmit status register (tdes0) ...................................................................................... .................. 43 6.3.2.2 transmit buffer control and buffer size register (tdes1) .............................................................. ....... 44 6.3.2.4 next descriptor address register (tdes3) .............................................................................. ............. 44 7. pci mode eeprom format ..................................................................................... 45 8. phy registers .......................................................................................................... 47 8.1 basic mode control register (bmcr) ? 00h ................................................................................... .. 48 8.2 basic mode status register (bmsr) ? 01h.................................................................................... ... 49 8.3 phy id identifier register #1 (phyid1) ? 02h ............................................................................... ... 50 8.4 phy id identifier register #2 (phyid2) ? 03h ............................................................................... ... 50 8.5 auto-negotiation advertisement register (anar) ? 04h................................................................... 51 8.6 auto-negotiation link partner ability register (anlpar) ? 05h ....................................................... 52 8.7 auto-negotiation expansion register (aner)- 06h........................................................................... 5 3 8.8 davicom specified configuration register (dscr) ? 10h.............................................................. 53 8.9 davicom specified configuration and status register (dscsr) ? 11h......................................... 55 8.10 10base-t configuration/status (10btcsr) ? 12h ........................................................................ 56 8.11 power down control register (pwdor) ? 13h .............................................................................. 57 8.12 (specified config) register ? 14h......................................................................................... ............ 57 8.13 davicom specified receive error counter register (recr) ? 16h ............................................. 58 8.14 davicom specified disconnect counter register (discr) ? 17h ................................................ 58 9. functional description....................................................................................... 59 9.1 pci bus buffer management.................................................................................................. ............ 59 DM9103 3-port switch with pciinterface preliminary datasheet 5 DM9103-ds-p02 september 26, 2007 9.1.1. overview ................................................................................................................ .................................... 59 9.1.2. data structure and descriptor list ...................................................................................... ....................... 59 9.1.3. buffer management : ring structure method............................................................................... .............. 59 9.1.4. buffer management : chain structure method.............................................................................. ............. 59 9.1.5. descriptor list: buffer descriptor format ............................................................................... .................... 60 9.1.2. transmit data buffer processing ......................................................................................... ...................... 67 9.2 switch function: ........................................................................................................... ....................... 68 9.2.1 address learning ......................................................................................................... ............................... 68 9.2.2 address aging............................................................................................................ ................................. 68 9.2.3 packet forwarding ........................................................................................................ .............................. 68 9.2.4 inter-packet gap (ipg) ................................................................................................... ............................ 68 9.2.5 back-off algorithm....................................................................................................... ................................ 68 9.2.6 late collision ........................................................................................................... ................................... 68 9.2.7 half duplex flow control ................................................................................................. ........................... 68 9.2.8 full duplex flow control ................................................................................................. ............................ 68 9.2.9 partition mode ........................................................................................................... .................................. 68 9.2.10 broadcast storm filtering............................................................................................... ........................... 69 9.2.11 bandwidth control............ .......................... .......................... ................... .................... .............................. 69 9.2.12 port monitoring support ................................................................................................. ........................... 69 9.2.13 vlan support ............................................................................................................ ............................... 70 9.2.13.1 port-based vlan....................................................................................................... ............................ 70 9.2.13.2 802.1q-based vlan..................................................................................................... ......................... 70 9.2.13.3 tag/untag ............................................................................................................. ................................. 70 9.2.14 priority support ........................................................................................................ ................................. 70 9.2.14.1 port-based priority ................................................................................................... .............................. 71 9.2.14.2 802.1p-based priority................................................................................................. ............................ 71 9.2.14.3 diffserv-based priority............................................................................................... ............................ 71 9.3 mii interface.............................................................................................................. .......................... 72 9.3.1 mii data interface ....................................................................................................... ................................. 72 9.3.2 mii serial management ............. ......................... .......................... .................... ................ ........................... 72 9.3.3 serial management interface ....................... .......................... .......................... ................... ........................ 73 9.3.4 management interface - read frame structure..................... ................... .................... .................. ............ 73 9.3.5 management interface - write fram e structure ..................... ................... .................... ................. ............. 73 9.4 internal phy functions..................................................................................................... ................... 74 DM9103 3-port switch with pci interface 6 preliminary datasheet DM9103-ds-p02 september 26, 2007 9.4.1 100base-tx operation ..................................................................................................... .......................... 74 9.4.1.1 4b5b enc oder ........................ .......................... ................... ................... ................... ............................... 74 9.4.1.2 scrambler.............................................................................................................. ................................... 74 9.4.1.3 parallel to serial converter ........................................................................................... ........................... 74 9.4.1.4 nrz to nrzi encoder .................................................................................................... .......................... 74 9.4.1.5 mlt-3 converter ........................................................................................................ .............................. 74 9.4.1.6 mlt-3 driver ........................................................................................................... ................................. 74 9.4.1.7 4b5b code group........................................................................................................ ............................ 75 9.4.2 100base-tx receiver ...................................................................................................... ........................... 76 9.4.2.1 signal detect.......................................................................................................... .................................. 76 9.4.2.2 adaptive equalization...... .......................... .......................... .......................... .............. ............................. 76 9.4.2.3 mlt-3 to nrzi decoder.................................................................................................. ......................... 76 9.4.2.4 clock recovery module .................................................................................................. ......................... 76 9.4.2.5 nrzi to nrz ............................................................................................................ ................................ 76 9.4.2.6 serial to parallel ..................................................................................................... .................................. 76 9.4.2.7 descrambler............................................................................................................ ................................. 76 9.4.2.8 code group alignment................................................................................................... .......................... 77 9.4.2.9 4b5b decoder........................................................................................................... ............................... 77 9.4.3 10base-t operation....................................................................................................... ............................. 77 9.4.4 collision detection ...................................................................................................... ................................ 77 9.4.5 carrier sense ............................................................................................................ .................................. 77 9.4.6 auto-negotiation ......................................................................................................... ................................ 77 9.5 auto mdix hp auto-mdix functional description............................................................................. 7 7 10. dc and ac electrical characteristics......................................................... 79 10.1 absolute maximum ratings ................................................................................................. .......... 79 10.2 operating conditions ..................................................................................................... ................ 79 10.3 dc electrical characteristics ............................................................................................ ............. 79 10.3 ac characteristics........................................................................................................ ..................... 80 10.3.1 pci clock specifications timing ......................................................................................... ...................... 80 10.3.2 power on reset timing ................................................................................................... ......................... 80 10.3.3 other pci signals timing di agram ......................... .......................... ................... .................. ................... 81 10.3.4 port 2 mii interface transmit timing .................................................................................... ..................... 82 10.3.5 port 2 mii interface receive timing ..................................................................................... ..................... 82 DM9103 3-port switch with pciinterface preliminary datasheet 7 DM9103-ds-p02 september 26, 2007 10.3.6 mii management interface ti ming.................... .......................... .......................... ................. .................... 83 10.3.7 eeprom timing ........................................................................................................... ............................. 84 11. application circuit................................................................................................ 85 12. package information ........................................................................................... 88 13. ordering information .......................................................................................... 89 DM9103 3-port switch with pci interface 8 preliminary datasheet DM9103-ds-p02 september 26, 2007 1. general description the DM9103 is a fully integrated, high performance, and cost-effective fast ethernet switch controller with one general pci bus interface, two ports 10m/100mbps phy, and one port mii or rmii interface. the general pci bus connects directly to internal host mac with 32-bit data registers and internal memory. the host mac has the similar functions as other 10/100mbps phy or mii does. this makes the DM9103 act as an extended four ports switch and to shorten the latency from pci port to destination port. the internal memory of the DM9103 supports up to 1k uni-cast mac address table, and provides to three ports? and pci port?s transmit and receive buffers. for efficient memory usage algorithm, if application only uses two ports solution, the another disabled port?s memory resource can be shared to other two ports and pci port. each port of the DM9103 provides four priority transmit queues, that can be defined by port-based, 802.1p vlan, or ip packet tos field automatically, to fit the various bandwidth and latency requirement of data, voice, and video applications. each port also supports ingress and/or egress rate control to provide proper bandwidth. and up to 16 groups of 802.1q vlan with tag/un-tag functions are supported to provide efficient packet forwarding. the tcp/udp/ipv4 checksum generation and checking functions are also provided by pci port to offload the processor computing loading. besides the packet transmit and receive functions, the pci port also provides various registers to control and get status of the DM9103 functional operation. each port, including the pci port, provides the mib counters and loop-bac k capability and the build in memory self test (bist) for system and board level diagnostic. the integrated two ports phy are compliant with ieee 802.3u standards. the mii interface provides the flexibility to connect ethernet phy, and it can be configured as revers ed mii interface for soc with mii interface. an alternative interface, the rmii interface, is also provided to connect the lower pin count ethernet phy or soc with rmii interface. 2. block diagram 10/100m mac port 1 mdi/mdix mii / rmii switch controller control registers mib counters eeprom interface embedded memory memory bist memory management processor interface host mac switch engine eeprom switch fabric pci bus mac mac 10/100m 10/100m mdi/mdix port 0 port 2 10/100m 10/100m phy phy DM9103 3-port switch with pciinterface preliminary datasheet 9 DM9103-ds-p02 september 26, 2007 3. features ? ethernet switch with two 10/100mb phy, one mii/rmii, and pci bus interface ? support reverse-mii ? pci bus master architecture ? eeprom interface for power up configurations ? support tcp/udp/ipv4 checksum offload ? support hp auto-mdix ? support ieee 802.3x flow control in full-duplex mode ? support back pressure flow control in half-duplex mode ? per port support 4 priority queues by port-based, 802.1p qos, and ip tos priority ? support 802.1q vlan up-to 16 vlan group ? support vlan id tag/untag options ? per port support bandwidth, ingress and egress rate control ? support broadcast storming filter function ? support store and forward switching approach ? support up-to 1k uni-cast mac addresses ? automatic aging scheme ? support mib counters for diagnostic ? 128-pin lqfp 1.8v internal core, 3.3v i/o with 5v tolerant DM9103 3-port switch with pci interface 10 preliminary datasheet DM9103-ds-p02 september 26, 2007 4. pin configuration : 128 pin lqfp 11 DM9103 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 60 59 58 57 56 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 28 29 30 55 54 53 52 51 61 81 82 83 84 85 86 87 88 89 avddi pme# cbe3# pciclk isolate# int# req# ad31 vcci ad30 ad28 ad27 gnd ad26 ad25 ad16 ad24 ad23 ad20 ad19 ad17 gnd cbe2# frame# devsel# vcc3 vcc3 vcci perr# gnd par ad14 gnd gnd vref vcntl agnd rx1- agnd rx1+ rxd2_1 rxd2_0 agnd x2 txd2_2 txd2_1 txe2 txc2 crs2 col2 rxer2 gnd rxdv2 rxd2_3 spd0_led fdx0_led wol mdc txd2_3 spd1_led lnk1_led fdx1_led lnk0_led test3 test2 gnd vcc3 ad0 eedo pwrst# vcci eedi ad2 ad5 vcc3 eecs ad8 cbe0# gnd ad7 ad1 ad11 ad12 mdio irdy# stop# ad15 ad13 idsel vcc3 cbe1# 27 ad6 vcc3 test1 eeck ad4 rxc2 102 101 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 127 128 126 ad29 gnt# rst# bgresg avdd3 vcc3 rx0+ agnd gnd tx0- rx0- tx0+ x1 avddi tx1+ avdd3 sclk ad10 txd2_0 bgres ad3 tx1- serr# ad21 avdd3 rxd2_2 ad18 ad22 trdy# ad9 vcc3 DM9103 3-port switch with pciinterface preliminary datasheet 11 DM9103-ds-p02 september 26, 2007 5. pin description i = input, o = output, i/o = input / output, o/d = open drain, p = power, pd=internal pull-low (about 50k ohm) # = asserted low 5.1 pci bus interface pin no. pin name i/o description 2 idsel i initialization device select this signal is asserted high during the configuration space read/write access. 14 frame# i/o cycle frame this signal is driven low by the DM9103 master mode to indicate the beginning and duration of a bus transaction. 15 irdy# i/o initiator ready this signal is driven low when the master is ready to complete the current data phase of the transaction. a data phase is completed on any clock when both irdy# and trdy# are sampled asserted. 16 trdy# i/o target ready this signal is driven low when the target is ready to complete the current data phase of the transaction. during a read, it indicates that valid data is asserted. during a write, it indicates that the target is prepared to accept data. 17 devsel# i/o device select the DM9103 asserts the signal low when it recognizes its target address after frame# is asserted. as a bus master, the DM9103 will sample this signal which insures its destination address of the data transfer is recognized by a target. 19 stop# i/o stop this signal is asserted low by the target device to request the master device to stop the current transaction. 20 perr# i/o parity error the DM9103 as a master or slave will assert this signal low to indicate a parity error on any incoming data. 22 serr# i/o system error this signal is asserted low when address parity is detected with enabled pcics bit31 (detected parity error.) the system error asserts two clock cycles after the falling address if an address parity error is detected. 23 par i/o parity this signal indicates even parity across ad0~ad31 and c/be0#~c/be3# including the par pin. this signal is an output for the master and an input for the slave device. it is stable and valid one clock after the address phase. 1,13,25,36 c/be3# c/be2# c/be1# c/be0# i/o bus command/byte enable during the address phase, these signals define the bus command or the type of bus transaction that will take place. during the data phase these pins indicate which byte lanes contain valid data. c/be0# applies to bit7-0 and c/be3# applies to bit31-24. DM9103 3-port switch with pci interface 12 preliminary datasheet DM9103-ds-p02 september 26, 2007 119,121,122,123,124,126,127,128, 3,5,6,7,8,9,10,12, 26,28,29,30,31,33,34,37, 38,39,41,42,43,44,46,47 ad31~ad0 i/o address & data these are multiplexed address and data bus signals. as a bus master, the DM9103 will drive address during the first bus phase. during subsequent phases, the DM9103 will either read or write data expecting the target to increment its address pointer. as a target, the DM9103 will decode each address on the bus and respond if it is the target being addressed. 110 wol o issue a wake up signal when wake up event occurred. 111 pme# o/d power management event. the DM9103 drives it low to indicate that a power management event has occurred. 112 int# o/d interrupt request this signal will be asserted low when an interrupted condition as defined in cr5 is set, and the corresponding mask bit in cr7 is set. 113 rst# i system reset when this signal is low, the DM9103 performs the internal system reset to its initial state. 114 pciclk i pci system clock pci bus clock that provides timing for DM9103 related to pci bus transactions. 115 isolate# i isolate this pin is used to isolate the DM9103 from the pci bus. 117 gnt# i bus grant this signal is asserted low to indicate that DM9103 has been granted ownership of the bus by the central arbiter. 118 req# o bus request the DM9103 will assert this signal low to request the ownership of the bus. 5.2 p2 mii / rmii / reverse mii interfaces 5.2.1 mii interfaces pin no. pin name i/o description 55 mdc o,pd mii serial management data clock 56 mdio i/o mii serial management data 58,59,60,61 txd2_3~0 o,pd port 2 mii transmit data 4-bit nibble data outputs (synchronous to the txc2) 63 txe2 o,pd port 2 mii transmit enable 64 txc2 i/o port 2 mii transmit clock. 65 crs2 i/o port 2 mii carrier sense 66 col2 i/o port 2 mii collision detect. 67 rxer2 i port 2 mii receive error 68 rxc2 i port 2 mii receive clock 70 rxdv2 i port 2 mii receive data valid 71,72,73,74 rxd2_3~0 i port 2 mii receive data 4-bit nibble data input (synchronous to rxc2) DM9103 3-port switch with pciinterface preliminary datasheet 13 DM9103-ds-p02 september 26, 2007 5.2.2 rmii interfaces pin no. pin name i/o description 55 mdc o,pd mii serial management data clock 56 mdio i/o mii serial management data 58,59 txd2_3~2 o reserved 60,61 txd2_1~0 o,pd rmii transmit data 63 txe2 o,pd rmii transmit enable. 64 txc2 o reserved 65 crs2 i rmii crs_dv 66 col2 i reserved 67 rxer2 i reserved 68 rxc2 i 50mhz reference clock. 70 rxdv2 i reserved 71,72 rxd2_3~2 i reserved 73,74 rxd2_1~0 i rmii receive data. 5.2.3 reverse mii interfaces pin no. pin name i/o description 55 mdc o,pd reserved 56 mdio i/o reserved 58,59,60,61 txd2_3~0 o,pd port 2 mii transmit data 4-bit nibble data outputs (synchronous to the txc2) 63 txe2 o,pd port 2 mii transmit enable 64 txc2 o 25mhz clock output 65 crs2 o port 2 carrier sense output when txe2 or rxdv2 asserted. 66 col2 o port 2 collision out put when txe2 and rxdv2 asserted. 67 rxer2 i port 2 mii receive error 68 rxc2 i port 2 mii receive clock 70 rxdv2 i port 2 mii receive data valid 71,72,73,74 rxd2_3~0 i port 2 mii receive data 4-bit nibble data input (synchronous to rxc2) 5.3 eeprom interfaces pin no. pin name i/o description 49 eedi i,pd eeprom data in 50 eedo o,pd eeprom data out this pin is used serially to write op-codes, addresses and data into the eeprom. 51 eeck o,pd eeprom serial clock this pin is used as the clock for the eeprom data transfer. 52 eecs o,pd eeprom chip selection. DM9103 3-port switch with pci interface 14 preliminary datasheet DM9103-ds-p02 september 26, 2007 5.4 led pins pin no. pin name i/o description 104 lnk1_led o/d port 1 link / active led it is the combined led of link and carrier sense signal of the internal phy1 105 spd1_led o/d port 1 speed led its low output indicates that the internal phy1 is operated in 100m/s, or it is floating for the 10m mode of the internal phy1 106 fdx1_led o/d port 1 full-duplex led its low output indicates that the internal phy1 is operated in full-duplex mode, or it is floating for the half-duplex mode of the internal phy1 107 lnk0_led o/d port 0 link / active led it is the combined led of link and carrier sense signal of the internal phy0 108 spd0_led o/d port 0 speed led its low output indicates that the internal phy0 is operated in 100m/s, or it is floating for the 10m mode of the internal phy0 109 fdx0_led o/d port 0 full-duplex led its low output indicates that the internal phy0 is operated in full-duplex mode, or it is floating for the half-duplex mode of the internal phy0 5.5 clock interface pin no. pin name i/o description 101 x1 i crystal 25mhz in 102 x2 o crystal 25mhz out 116 sclk i external system clock source if strap pin eecs is pulled high, this pin is used for DM9103 system clock. the frequency range is between 20mhz and 100mhz depend on application. 5.6 network interface pin no. pin name i/o description 80,81 tx1+/- i/o port 1 tp tx these two pins are the twisted pair transmit in mdi mode or receive in mdix mode. 84,85 rx1+/- i/o port 1 tp rx these two pins are the twisted pair receive in mdi mode or transmit in mdix mode. 88,89 tx0+/- i/o port 0 tp tx these two pins are the twisted pair transmit in mdi mode or receive in mdix mode. 92,93 rx0+/- i/o port 0 tp rx DM9103 3-port switch with pciinterface preliminary datasheet 15 DM9103-ds-p02 september 26, 2007 these two pins are the twisted pair receive in mdi mode or transmit in mdix mode. 95 bgres i/o bandgap pin connect a 1.4k resistor to bggnd in application. 96 bggnd p bandgap ground 97 vcntl i/o 1.8v voltage control 98 vref o voltage reference connect a 0.1u capacitor to ground in application. 5.7 miscellaneous pins pin no. pin name i/o description 53 pwrst# i power on reset low active with minimum 1ms 76 test1 i,pd tie to high in application 77 test2 i,pd 0: 3-port mode all ports are active in this mode. 1: 2-port mode only 2 ports are active in this mode. port 1 or port 2 can be disabled by strap txen2. in this mode, the memory resource is shared by pci bus port and the other 2 ports. 78 test3 i,pd tie to ground in application 5.8 power pins pin no. pin name i/o description 4,18,32,40,48,62,75,100 vcc3 p digital 3.3v 24,57,120 vcci p internal 1.8v core power 11,21,27,35,45, 54,69,103,125 gnd p digital gnd 86,94,99 avdd3 p analog 3.3v power 79,87 avddi p analog 1.8v power 82,83,90,91 agnd p analog gnd DM9103 3-port switch with pci interface 16 preliminary datasheet DM9103-ds-p02 september 26, 2007 5.9 strap pins table 1: pull-high 1k~10k, 0: default floating. 5.9.1 strap pin in 3-port mode pin no. pin name description 52 eecs source of system clock 0: system clock is internal 50mhz clock 1: use sclk pin as system clock 50 eedo when port 2 in force status mode 0: port 2 in 100mbps 1: port 2 in 10mbps 58 txd2_3 when port 2 in force status mode 0: link on 1: link off 59 txd2_2 0: port 2 status from external phy 1: port 2 status in force mode 60,51 txd2_1,eeck 00: port 2 is mii mode (default) 01: port 2 is in reverse mii mode 10: port 2 is in rmii mode and memory bist disabled 11: port 2 is in rmii mode 61 txd2_0 when port 2 in force status mod 0: port 2 in full duplex mode 1: port 2 i half duplex mode 5.9.2 strap pin in 2-port mode pin no. pin name description 52 eecs source of system clock 0: system clock is internal 50mhz clock 1: use sclk pin as system clock 50 eedo when port 2 in force status mode 0: port 2 in 100mbps 1: port 2 in 10mbps 58 txd2_3 when port 2 in force status mode 0: link on 1: link off 59 txd2_2 0: port 2 status from external phy 1: port 2 status in force mode 60,51 txd2_1,eeck 00: port 2 is mii mode (default) 01: port 2 is in reverse mii mode 10: port 2 is in rmii mode and memory bist disabled 11: port 2 is in rmii mode 61 txd2_0 when port 2 in force status mod 0: port 2 in full duplex mode 1: port 2 i half duplex mode 63 txen2 0: port 2 disabled 1: port 1 disabled DM9103 3-port switch with pciinterface preliminary datasheet 17 DM9103-ds-p02 september 26, 2007 6. register set 6.1 pci configuration registers the definitions of pci configuration registers are based on the pci specification revision 2.2 and it provides the initialization and configuration information to operate the pci interface in the DM9103. all registers can be accessed with byte, word, or double word mode. as defined in pci specification 2.1, read accesses to reserve or unimplemented registers will return a value of ?0.? these registers are to be described in the following sections. the default value of pci configuration registers after reset. description identifier address offset value of reset identification pciid 00h 90131282h command & status pcics 04h 02100000h* revision pcirv 08h 02000010h miscellaneous pcilt 0ch bios determine i/o base address pciio 10h system allocate memory base address pcimem 14h system allocate reserved -------- 18h - 28h 00000000h subsystem identification pcisid 2ch load from eeprom reserved -------- 30h 00000000h capabilities pointer cap _ptr 34h 00000050h reserved -------- 38h 00000000h interrupt & latency pciint 3ch system allocate bit7~0 device specific configuration register pciusr 40h 00000000h** power management register pcipmr 50h c0310001h** power management control & status pmcsr 54h 00000100h * it is written to 02100007h by most bios. ** it may be changed from eeprom in application. key to default in the register description that follows, the default column takes the form DM9103 3-port switch with pci interface 18 preliminary datasheet DM9103-ds-p02 september 26, 2007 6.1.1 identification id (xxxxxx00h - pciid) bit default type description 16:31 9013h ro the field identifies the particular device. unique and fixed number for the DM9103 is 9013h. 0:15 1282h ro this field identifies the manufacturer of the device. unique and fixed number for davicom is 1282h. 6.1.2 command & status (xxxxxx04h - pcics) bit default type description 31 0 r/c detected parity error the DM9103 samples the ad[0:31], c/be[0:3]#, and the par signal to check parity and to set parity errors. in slave mode, the parity check falls on command phase and data valid phase (irdy# and trdy# both active). in master mode, the DM9103 will check each data phase, during a memory read cycle, for parity error. during a memory write cycle, if an error occurs, the perr# signal will be driven by the target. this bit is set by the DM9103 and cleared by writing "1". there is no effect by writing "0" 30 0 r/c signal for system error this bit is set when the serr# signal is driven by the DM9103. this system error occurs when an address parity is detected under the condition that bit 8 and bit 6 in command register below are set 29 0 r/c master abort detected this bit is set when the DM9103 terminates a master cycle with the master-abort bus transaction 28 0 r/c target abort detected this bit is set when the DM9103 terminates a master cycle due to a target-abort signal from other targets 27 0 r/c send target abort (0 for no implementation) the DM9103 will never assert the target-abort sequence 26:25 01 r/c devsel timing (01 select medium timing) medium timing of devsel# means the DM9103 will assert devsel# signal two clocks after frame# is sample ?asserted? 24 0 r/c data parity error detected this bit will take effect only when operating as a master and when a parity error response bit in command configuration register is set. it is set under two conditions: (i) perr# asserted by the DM9103 in memory data read error (ii) perr# sent from the target due to memory data write error 23 0 ro slave mode fast back-to-back capable (0 for no support) this bit is always reads "1" to indicate that the DM9103 is capable of accepting fast back-to-back transaction as a slave mode device 22 0 ro user-definable feature supported (0 for no support) 21 0 ro 66 mhz (0 for no capability) 20 1 ro new capability this bit indicates whether this function implements a list of extended capabilities. DM9103 3-port switch with pciinterface preliminary datasheet 19 DM9103-ds-p02 september 26, 2007 19:10 0 ro reserved 9 0 ro master mode fast back-to-back (0 for no support) the DM9103 does not support master mode fast back-to-back capability and will not generate fast back-to-back cycles 8 0 rw serr# driver enable/disable this bit controls the assertion of serr# signal output. the serr# output will be asserted on detection of an address parity error and if both this bit and bit 6 are set 7 0 ro address/data stepping (0 for no stepping) 6 0 rw parity error response enable/disable setting this bit will enable the DM9103 to assert perr# on the detection of a data parity error and to assert serr# for reporting address parity error 5 0 ro vga palette snooping (0 for no support) 4 0 ro memory write and invalid (0 for no implementation) the DM9103 only generates memory write cycle 3 0 ro special cycles (0 for no implementation) 2 1 rw master device capability enable/disable when this bit is set, DM9103 has the ability of master mode operation 1 1 rw memory space access enable/disable this bit controls the ability of memory space access. the memory access includes memory mapped i/o access and boot rom access. as the system boots up, this bit will be enabled by bios for boot rom memory access. while in normal operation, using memory mapped i/o access, this bit should be set by driver before memory access cycles 0 1 rw i/o space access enable/disable this bit controls the ability of i/o space access. it will be set by bios after power on 6.1.3 revision id (xxxxxx08h - pcirv) bit default type description 31:8 020000h ro class code (020000h) this is the standard code for ethernet lan controller 7:4 0001 ro revision major number this is the silicon-major revision number that will increase for the subsequent versions of the DM9103 3:0 0000 ro revision minor number this is the silicon-minor revision number that will increase for the subsequent versions of the DM9103 DM9103 3-port switch with pci interface 20 preliminary datasheet DM9103-ds-p02 september 26, 2007 6.1.4 miscellaneous function (xxxxxx0ch - pcilt) bit default type description 31:24 00h ro built in self test ( 00h means no implementation) 23:16 00h ro header type ( 00h means single function with predefined header type ). 15:8 00h rw latency timer for the bus master the latency timer is guaranteed by the system and measured by clock cycles. when the frame# is asserted at the beginning of a master period by the DM9103, the value will be copied into a counter and start counting down. if the frame# is de-asserted prior to count expiration, this value is meaningless. when the count expires before gnt# is de-asserted, the master transaction will be terminated as soon as the gnt# is removed while gnt# signal is removed and the counter is non-zero, the DM9103 will continue with its data transfers until the count expires. the system host will read min_gnt and max_lat registers to determine the latency requirement for the device and then initialize the latency timer with an appropriate value the reset value of latency timer is determined by bios 7:0 00h ro cache line size for memory read mode selection ( 00h means no implementation for use) 6.1.5 i/o base address (xxxxxx10h - pciio) bit default type description 31:7 undefined rw pci i/o base address this is the base address value for i/o accesses cycles. it will be compared to ad[31:7] in the address phase of bus command cycle for the i/o resource access 6:1 000000 ro pci i/o range indication it indicates that the minimum i/o resource size is 80h 0 1 ro i/o space or memory space base indicator determines that the register maps into the i/o space ( = 1 indicates i/o base) 6.1.6 memory mapped base address (xxxxxx14h - pcimem) bit default type description 31:7 undefined r/w pci memory base address this is the base address value for memory accesses cycles. it will be compared to the ad [31:7] in the address phase of bus command cycle for the memory resource access 6:1 000000 ro pci memory range indication it indicates that the minimum memory resource size is 80h 0 0 ro i/o space or memory space base indicator determines that the register maps into the memory space( = 0 indicates memory base) DM9103 3-port switch with pciinterface preliminary datasheet 21 DM9103-ds-p02 september 26, 2007 6.1.7 subsystem identification (xxxxxx2ch - pcisid) bit default type description 31:16 xxxxh ro subsystem id it can be loaded from eeprom word 1 15:0 xxxxh ro subsystem vendor id it can be loaded from eeprom word 0 6.1.8 capabilities pointer (xxxxxx34h - cap _ptr) bit default type description 31:8 000000h ro reserved 7:0 01010000 ro capability pointer the cap_ ptr provides an offset (default is 50h) into the function?s pci configuration space for the location of the first term in the capabilities linked list. the cap_ ptr offset is double word aligned so the two least significant bits are always ?0?s 6.1.9 interrupt & latency configuration (xxxxxx3ch - pciint) bit default type description 31:24 28h ro maximum latency timer that can be sustained. 23:16 14h ro minimum grant minimum length of a burst period. 15:8 01h ro interrupt pin read as 01h to indicate inta# 7:0 xxh rw interrupt line that is routed to the interrupt controller the value depends on system software. 6.1.10 device specific configuration register (xxxxxx40h- pciusr) bit default type description 31:30 0 ro reserved bits read as 0 29 0 rw when set, enables port 0 or 1 link status change wake up event 28 0 ro reserved bit read as 0 27 0 rw when set, enables magic packet wake up event 26 0 ro when set, indicates the port 0 or 1 link change and the link status change event occurred 25 0 ro reserved bit read as 0 24 0 ro when set, indicates the magic packet is received and the magic packet event occurred 23:16 00h ro reserved bits read as 0 15:8 00h rw device specific 7:0 00h ro reserved bits read as 0 DM9103 3-port switch with pci interface 22 preliminary datasheet DM9103-ds-p02 september 26, 2007 6.1.11 power management register (xxxxxx50h~pcipmr) bit default type description 31:27 11000 ro pme_ support this field indicates that the power states in which the function may assert pme#. a value of 0 for any bit indicates that the function is not capable of asserting the pme# signal while in that power state bit27 ? pme# support d0 bit28 ? pme# support d1 bit29 ? pme# support d2 bit30 ? pme# support d3(hot) bit31 ? pme# support d3(cold) DM9103?s bit31~27=11000 indicates pme# can be asserted from d3(hot) & d3(cold) these bits can be load from eeprom word 7 bit [7:3] 26:25 00 ro reserved these two bits can be load from eeprom word 7 bit [1:0] 24:22 011 ro aux_ current this field reports the 3.3vaux auxiliary current requirement for the pci function. the default value of this field is 011 means 160ma and it can be loaded from eeprom word 4 bit [15:13] if eeprom word 4 bit [9] is 1 21 0 ro reserved this bit can be load from eeprom word 7 bit [2] 20 0 ro reserved 19 0 ro pme# clock ?0? indicates that no pci clock is required for the function to generate pme# 18:16 010 ro version a default value of 010 indicates that this function complies with the revision 1.1 of the pci power management interface specification this value can be loaded from eeprom word 4 bit [12:10] if eeprom word 4 bit [9] is 1 15:8 00h ro next item pointer the offset into the function?s pci configuration space pointing to the location of next item in the function?s capability list is ?00h? 7:0 01h ro capability identifier when ?01h? indicates the linked list item as being the pci power management registers DM9103 3-port switch with pciinterface preliminary datasheet 23 DM9103-ds-p02 september 26, 2007 6.1.12 power management control/status (xxxxxx54h~pmcsr) bit default type description 31:16 0000h ro reserved 15 0 rw/c pme_ status this bit is set when the function would normally assert the pme# signal independent of the state of the pme_ en bi t. writing a ?1? to this bit will clear it. this bit defaults to ?0? if the function does not support pme# generation from d3 (cold).if the function supports pme# from d3 (cold) then this bit is sticky and must be explicitly cleared by the operating system whenever the operating system is initially loaded. 14:9 000000 ro reserved it means that the DM9103 does not support reporting power consumption. 8 1 rw pme_ en write ?1? to enables the function to assert pme#, write ?0? to disable pme# assertion this bit defaults to ?0? if the function does not support pme# generation from d3 (cold) if the function supports pme# from d3(cold) then this bit is sticky and must be explicitly cleared by the operating system each time the operating system is initially loaded. 7:2 000000 ro reserved 1:0 00 rw this two bits field is both used to determine the current power state of a function and to set the function into a new power state. the definitions given below 00: d0 11: d3 (hot) DM9103 3-port switch with pci interface 24 preliminary datasheet DM9103-ds-p02 september 26, 2007 6.2 pci control and status registers (cr) the DM9103 implements 32 control and status registers, which can be accessed by the host. these crs are double long word aligned. all crs are set to their default values by hardware or software reset unless otherwise specified. all control and status registers with their definitions and offset from io or memory base address are shown below: register description offset from csr base address default value after reset cr0 system control register 00h de000000h cr1 transmit descriptor poll demand 08h ffffffffh cr2 receive descriptor poll demand 10h ffffffffh cr3 receive descriptor base address register 18h 00000000h cr4 transmit descriptor base address register 20h 00000000h cr5 network status report register 28h fc000000h cr6 network operation mode register 30h 02040000h cr7 interrupt mask register 38h fffe0000h cr8 reserved 40h 00000000h cr9 external management access register 48h 000083f0h cr10 reserved 50h ffffffffh cr11 reserved 58h fffe0000h cr12 reserved 60h ffffffxxh cr13 reserved 68h xxxxxx00h cr14 reserved 70h unpredictable cr15 watchdog and jabber timer register 78h 00000000h cr16 switch control register 80h 00000000h cr17 per port index register 88h 00000000h cr18 per port control register 90h 00000000h cr19 per port status data register 98h 00000000h cr20 per port vlan tag byte register a0h 00000001h cr21 per port mib counter index register a8h 00000000h cr22 mib counter data register b0h 00000000h cr23 vlan priority map register b8h 0000fa50h cr24-27 port-based vlan mapping table registers x 4 c0h-d8h 0f0f0f0fh cr28-31 tos priority map register x 4 e0h-f8h xxxxxxxxh key to default in the register description that follows, the default column takes the form: DM9103 3-port switch with pciinterface preliminary datasheet 25 DM9103-ds-p02 september 26, 2007 6.2.1 system control register (cr0) bit name default description 31:24 reserved deh,ro reserved 25:22 reserved 00,ro reserved 21 mrm 0,rw memory read multiple when set, the DM9103 will use memory read multiple command (c/be3~0 1100) when it initialize the memory read burst transaction as a master device when reset, it will use memory read command (c/be3 ~ 0 = 0110) for the same master operation 20 reserved 0,rw reserved 19:1 reserved 0,ro reserved 0 sr 0,rw software reset when set, the DM9103 will make a internal reset cycle. all consequent action to DM9103 should wait at least 32 pci clock cycles for its self-cleared. 6.2.2 transmit descriptor poll demand (cr1) bit name default description 31:0 tdp ffffffffh ,wo transmit descriptor polling command writing any value to this port will force DM9103 to poll the transmit descriptor. if the acting descriptor is not available, transmit process will return to suspend state. if the descriptor shows buffer available, transmit process will begin the data transfer. 6.2.3 receive descriptor poll demand (cr2) bit name default description 31:0 rdp ffffffffh ,wo receive descriptor polling command writing any value to this port will force DM9103 to poll the receive descriptor. if the acting descriptor is not available, receive process will return to suspend state. if the descriptor shows buffer available, re ceive process will begin the data transfer. 6.2.4 receive descriptor base address (cr3) bit name default description 31:0 rdba 00000000h, rw receive descriptor base address this register defines base address of receive descriptor-chain. the receive descriptor- polling command, after cr3 is set, will make DM9103 to fetch the descriptor at the base-address. this is a working register, so the value of reading is unpredictable. DM9103 3-port switch with pci interface 26 preliminary datasheet DM9103-ds-p02 september 26, 2007 6.2.5 transmit descriptor base address (cr4) bit name default description 31:0 tdba 00000000h,r w transmit descriptor base address this register defines base address of transmit descriptor-chain. the transmit descriptor- polling command after cr4 is set to make DM9103 fetch the descriptor at the base-address. this is a working register, so the value of reading is unpredictable. 6.2.6 network status report register (cr5) note: bits [13:0] can be cleared by written 1 to them respectively. bit name default description 31:26 reserved 000000,ro reserved 25:23 sbeb 000,ro system bus error bits these bits are read only and used to indicate the type of system bus fatal error. valid only when system bus error is set. the mapping bits are shown below bit25 bit24 bit23 bus error type 0 0 0 parity error 0 0 1 master abort 0 1 0 slave abort 0 1 1 reserved 1 x x reserved 22:20 txps 000,ro transmit process state these bits are read only and used to indicate the state of transmit process the mapping table is shown below bit22 bit21 bit20 process state 0 0 0 transmit process stopped 0 0 1 fetch transmit descriptor 0 1 0 move setup frame from the host memory 0 1 1 move data from host memory to transmit fifo 1 0 0 close descriptor by clearing owner bit of descriptor 1 0 1 waiting end of transmit 1 1 0 transmit end and close descriptor by writing status 1 1 1 transmit process suspend 19:17 rxps 000,ro receive process state these bits are read only and used to indicate the state of receive process. the mapping table is shown below bit19 bit18 bit17 process state 0 0 0 receive process stopped 0 0 1 fetch receive descriptor 0 1 0 wait for receive packet under buffer available 0 1 1 move data from receive fifo to host memory 1 0 0 close descriptor by clearing owner bit of descriptor 1 0 1 close descriptor by writing status 1 1 0 receive process suspended due to buffer unavailable 1 1 1 purge the current frame from received fifo because of the unavailable received buffer DM9103 3-port switch with pciinterface preliminary datasheet 27 DM9103-ds-p02 september 26, 2007 16 nis 0,rw normal interrupt summary normal interrupt includes any of the three conditions: cr5<0> ? txci: transmit complete interrupt cr5<2> ? txdu: transmit buffer unavailable cr5<6> ? rxci: receive complete interrupt 15 ais 0,rw abnormal interrupt summary abnormal interrupt includes any interrupt condition as shown below, excluding normal interrupt conditions. they are txps (bit1), txfu (bit5), rxdu (bit7), rxps (bit8), sbe (bit13). 14 reserved 0,rw reserved 13 sbe 0,rw system bus error the pci system bus errors will set this bit. the type of system bus error is shown in cr5<25:23>. 12 links 0,ro link change status this bit is set to indicate that the link status changed in port 0 or 1 phyceiver 11 reserved 0,ro reserved 10:9 reserved 0,ro reserved 8 rxps 0,rw receive process stopped this bit is set to indicate that the receive process enters the stopped state. 7 rxdu 0,rw receive buffer unavailable this bit is set when the DM9103 fetches the next receive descriptor that is still owned by the host. receive process will be suspended until a new frame enters or the receive polling command is set. 6 rxci 0,rw receive complete interrupt this bit is set when a received frame is fully moved into host memory and receive status has been written to descriptor. receive process is still running and continues to fetch next descriptor. 5 txfu 0,rw transmit fifo underrun this bit is set when transmit fifo has underrun condition during the packet transmission. it may happen due to the heavy load on bus, cause transmit buffer unavailable before end of packet. in this case, transmit process is placed in the suspend state and underrun error tdes0<1> is set. 4 reserved 0,ro reserved 3 reserved 0,ro reserved 2 txdu 0,rw transmit buffer unavailable this bit is set when the DM9103 fetches the next transmit descriptor that is still owned by the host. transmit process will be suspended until the transmission polling command is set. 1 txps 0,rw transmit process stopped this bit is set to indicate transmit process enters the stopped state. 0 txci 0,rw transmit complete interrupt this bit is set when a frame is fully transmitted and transmit status has been written to descriptor (the tdes1<31> is also asserted). transmit process is still running and continues to fetch next descriptor. DM9103 3-port switch with pci interface 28 preliminary datasheet DM9103-ds-p02 september 26, 2007 6.2.7 network operation mode register (cr6) bit name default description 31 reserved 0,ro must be zero 30:29 reserved 0,ro reserved 28:25 reserved 0001,ro 0001: normal mode 0011: memory test mode (cr13/14 enable) 24:23 reserved 00,ro must be zero 22 reserved 0,ro reserved 21 reserved 0,ro reserved 20 reserved 0,rw reserved 19 reserved 0,rw reserved 18 reserved 0,ro reserved 17 mii_cntl 0,rw mii management pin control set this bit to enable cr9 bit 16~19 to control mii management pin (mdc,mdio) 16 1pkt 0,rw one packet mode when this bit is set, only one packet is stored at tx fifo 15:14 reserved 0,ro reserved 13 txsc 0,rw transmit start/stop command when set, the transmit process will begin by fetching the transmit descriptor for available packet data to be transmitted (running state). if the fetched descriptor is owned by the host, transmit process will enter the suspend state and transmit buffer unavailable (cr5<2>) is set. otherwise it will begin to move data from host to fifo and transmit out after reaching threshold value. when reset, the transmit process is placed in the stopped state after completing the transmission of the current frame. 12 reserved 0,ro reserved 11:10 lbm 0,rw loop-back mode these bits decide two loop-back modes, mac and phy, besides normal operation. these loop-back modes expect transmitted data back to receive path and ignore collision detection. bit11 bit10 loop-back mode 0 0 normal 0 1 internal loop-back 1 x reserved 9 reserved 0,ro reserved 8 reserved 0,ro must be zero 7 pam 0,rw pass all multicast when set, any packet with a multicast destination address is received by the DM9103. the packet with a physical address will also be filtered based on the filter mode setting 6 pm 0,rw promiscuous mode when set, any incoming valid frame is received by the DM9103, and no matter what the destination address is. the DM9103 is initialized to this mode after reset operation. 5 reserved 0,rw must be zero. DM9103 3-port switch with pciinterface preliminary datasheet 29 DM9103-ds-p02 september 26, 2007 4 iafm 0,ro inverse address filtering mode it is set to indicate the DM9103 operate in a inverse filtering mode. this is a only bit and mapped from the setup frame together with cr6<2>, cr6<0> setting. that is it is valid on ly during perfect filtering mode. 3 pbf 0,rw pass bad frame when set, the DM9103 is indicated to receive the bad frames including runt packets, truncated frames caused by the fifo overflow. the bad frame also has to pass the address filtering if the DM9103 is not set in promiscuous mode. 2 hofm 0,ro hash-only filter mode this is a read-only bit and mapped from the set-up frame together with bit4,0 of cr6.it is set to indicate the DM9103 operate in a hash-only filtering mode. 1 rxrc 0,rw receive start/stop command when set, the receive process will begin by fetching the receive descriptor for available buffer to store the new-coming packet (placed in the running state). if the fetched descriptor is owned by the host (no descriptor is owned by the DM9103), the receive process will enter the suspend state and receive buffer unavailable cr5<7> sets. otherwise it runs to wait for the packet?s income. when reset, the receive process is placed in the stopped state after completing the reception of the current frame. 0 hpfm 0,ro hash/perfect filter mode this is a read only bit and mapped from the setup frame together with cr6<4>, cr6<2>. when reset, the DM9103 does a perfect address filter of incoming frames according to the addresses specified in the setup frame. when set, the DM9103 does a imperfect address filtering for the incoming frame with a multicast address according to the hash table specified in the setup frame. the filtering mode (perfect/imperfect) for the frame with a physical address will depend on cr6<2>. DM9103 3-port switch with pci interface 30 preliminary datasheet DM9103-ds-p02 september 26, 2007 6.2.8 interrupt mask register (cr7) bit name default description 16 nise 0,rw normal interrupt summary enable this bit is set to enable the interrupt for normal interrupt summary. normal interrupt includes three conditions: cr5<0> ? txci: transmit complete interrupt cr5<2> ? txdu: transmit buffer unavailable cr5<6> ? rxci: receive complete interrupt 15 aise 0,rw abnormal interrupt summary enable this bit is set to enable the interrupt for abnormal interrupt summary. abnormal interrupt includes all interrupt conditions as shown below, excluding normal interrupt conditions. they are txps(bit1), txfu(bit5), rxdu(bit7), rxps(bit8), sbe(bit13). 14 reserved 0,rw reserved 13 sbee 0,rw system bus error enable when set together with cr7<15>, cr5<13>, it enables the interrupt for system bus error. the type of system bus error is shown in cr5<24:23>. 12 linke 0,rw link change interrupt enable when this bit and cr7<16>, cr5<12> are set together, it will enable the interrupt of link status changed from port 0 or 1 phyceiver. 11 reserved 0,rw reserved 10:9 reserved 0,ro reserved 8 rxpse 0,rw receive process stopped enable when set together with cr7<15> and cr5<8>. this bit is set to enable the interrupt of receive process stopped condition. 7 rxdue 0,rw receive buffer unavailable enable when this bit and cr7<15>, cr5<7> are set together, it will enable the interrupt of receive buffer unavailable condition. 6 rxcie 0,rw receive complete interrupt enable when this bit and cr7<16>, cr5<6> are set together, it will enable the interrupt of receive process complete condition. 5 txfue 0,rw transmit fifo underrun enable when set together with cr7<15>, cr5<5>, it will enable the interrupt of transmit fifo underrun condition. 4 reserved 0,ro reserved 3 reserved 0,ro reserved 2 txdue 0,rw transmit buffer unavailable enable when this bit and cr7<16>, cr5<2> are set together, the interrupt of transmit buffer unavailable is enabled. 1 txpse 0,rw transmit process stopped enable when this bit is set together with cr7<15> and cr5<1>, it will enable the interrupt of the transmit process to stop. 0 txcie 0,rw transmit complete interrupt enable when this bit and cr7<16>, cr5<0> are set, the transmit interrupt is enabled. DM9103 3-port switch with pciinterface preliminary datasheet 31 DM9103-ds-p02 september 26, 2007 6.2.9 reserved (cr8) 6.2.10 management access register (cr9) bit name default description 31:22 reserved 0,ro reserved 21 les 0,ro load eeprom status it is set to indicate the load of eeprom is in progress. 20 rlm 0,rw reload eeprom set to reload the content of eeprom. 19 mdin 0,ro mii management data_in this is a read-only bit to indicate the mdio input data, when bit 18 mrw is set. 18 mrw 0,rw mii management read/write mode selection this bit defines the read/write mode for phy mii management register access. 1 for read and 0 for write. 17 mdout 0,rw mii management data_out this bit is used to generate the output data signal for phy mii management register access. 16 mdclk 0,rw mii management clock this bit is used to generate the output clock signal for phy mii management register access. 15 reserved 1,ro reserved. 14 reserved 0,ro reserved. 13:12 reserved 0,ro reserved. 11 ers 0,rw eeprom selected this bit is used to enable eeprom access. 10:8 reserved 011,rw reserved 7:4 reserved fh,ro reserved 3 crdout 0,rw data_out from eeprom this bit reflects the status of eedi pin when the eeprom access is enabled. 2 crdin 0,rw data_in to eeprom this bit maps to eedo pin when the eeprom access is enabled. 1 crclk 0,rw clock to eeprom this bit maps eeck pin when the eeprom access is enabled 0 crcs 0,rw chip_select to eeprom this bit maps to eecs pin when the eeprom access is enabled DM9103 3-port switch with pci interface 32 preliminary datasheet DM9103-ds-p02 september 26, 2007 6.2.11 reserved (cr10) 6.2.12 reserved (cr11) 6.2.13 reserved (cr12) 6.2.14 (reserved cr13) 6.2.15 (reserved cr14) 6.2.16 checksum offload control register (cr15) bit name default description 31 txsumc 0,wo in transmit, generate ip/tcp/udp chksum depend-on tx desc. control 30 ipsum 0,wo in transmit, generate ip chksum to all packets 29 tcpsum 0,wo in transmit, generate tcp chksum to all packets 28 udpsum 0,wo in transmit, generate udp chksum to all packets 27 rxsum 0,wo in receiving, report ip/tcp/udp checksum status to rdes0 26:0 reserved 0,ro reserved 6.12.17 switch control register (cr16) bit name default description 31:16 reserved 0,rw reserved 15 tos6 0,rw full tos using enable 1: check most significant 6-bit of tos 0: check most significant 3-bit only of tos 14 reserved 0,ro reserved 13 unicast 0,rw unicast packet can across vlan boundary 12 vidff 0,rw replace vidff if the received packet is a tagged vlan with vid equal to ?fff?, its vlan field is replaced with vlan tag defined in cr20 bit 15~0. 11 vid1 0,rw replace vid01 if the received packet is a tagged vlan with vid equal to ?001?, its vlan field is replaced with vlan tag defined in cr20 bit 15~0. 10 vid0 0,rw replace vid0 if the received packet is a tagged vlan with vid equal to ?000?, its vlan field is replaced with vlan tag defined in cr20 bit 15~0. 9 pri 0,rw replace priority field in the tag with value define in cr20 bit 15~13. 8 vlan 0,rw vlan mode enable 1: 802.1q base vlan mode enable 0: port-base vlan 7 mem_bist 0,ro address memory test bist status 0: ok 1: fail 6 rst_sw 0,rw reset switch core and auto clear after 10us 5 rst_anlg 0,rw reset analog phy core and auto clear after 10us DM9103 3-port switch with pciinterface preliminary datasheet 33 DM9103-ds-p02 september 26, 2007 4:3 snf_port 00,rw sniffer port number define the port number to act as the sniffer port 2 crc_dis pe0,rw crc checking disable when set, the received crc error packet also accept to receive memory 1:0 age pe0,rw address table aging 00: no aging 01: 64sec 10: 128sec 11: 256sec 6.2.18 per port index register (cr17) bit name default description 31:8 reserved 0,ro reserved 7:6 monitor 00,rw reserved, 00 in application. 5 block 0,rw 1: for write cr20[31:16] block mode 4:2 reserved 0,ro reserved 1:0 index 0,rw port index for register cr17~22 write the port number to this register before write/read register cr17~22. note that the processor port index number is 3 6.2.19 per port control register (cr18) bit name default description 31 tag_out 0,rw output packet tagging enable the transmitted packets contain vlan tagged field 30 pri_dis 0,ro priority queue disable only one transmit queue is supported in this port. 29 wfque 0,rw weighted fair queuing 1: the priority weight for queue 3,2,1, and 0 is 8,4,2, and 1 respectively. 0: the queue 3 has the highest priority, and the next priorities are queue 2,1, and 0 respectively. 28 tos_pri 0,rw priority tos over vlan if a ip packet with vlan tag, the priorit y of this packet is decode from tos field. 27 tos_off 0,rw tos priority classification disable the priority information from tos field of ip packet is ignored. 26 pri_off 0,rw 802.1 p priority classification disable the priority information from vlan tag field is ignored. 25:24 p_pri 0,rw port base priority the priority queue number in port base. 00= queue 0, 01=queue 1, 10=queue 2, 11=queue 3 DM9103 3-port switch with pci interface 34 preliminary datasheet DM9103-ds-p02 september 26, 2007 23:20 bsth 0,rw broadcast storm threshold these bits define the bandwidth threshold that received broadcast packets over the threshold are discarded 0000: no broadcast storm control 0001: 8k packets/sec 0010: 16k packets/sec 0011: 64k packets/sec 0100: 5% 0101: 10% 0110: 20% 0111: 30% 1000: 40% 1001: 50% 1010: 60% 1011: 70% 1100: 80% 1101: 90% 111x: no broadcast storm control 19:16 bw ctrl 0,rw received packet length counted. bandwidth table below. these bits define the bandwidth threshold that transmitted or received packets over the threshold are discarded 000x: none 0000: none 0001: 64kbps 0010: 128kbps 0011: 256kbps 0100: 512kbps 0101: 1mbps 0110: 2mbps 0111: 4mbps 1000: 8mbps 1001: 16mbps 1010: 32mbps 1011: 48mbps 1100: 64mbps 1101: 72mbps 1110: 80mbps 1111: 88mbps DM9103 3-port switch with pciinterface preliminary datasheet 35 DM9103-ds-p02 september 26, 2007 15:12 ingress 0,rw ingress rate control these bits define the bandwidth threshold that received packets over the threshold are discarded. 0000: none 0001: 64kbps 0010: 128kbps 0011: 256kbps 0100: 512kbps 0101: 1mbps 0110: 2mbps 0111: 4mbps 1000: 8mbps 1001: 16mbps 1010: 32mbps 1011: 48mbps 1100: 64mbps 1101: 72mbps 1110: 80mbps 1111: 88mbps 11:8 egress 0,rw egress rate control these bits define the bandwidth threshold that transmitted packets over the threshold are discarded. 0000: none 0001: 64kbps 0010: 128kbps 0011: 256kbps 0100: 512kbps 0101: 1mbps 0110: 2mbps 0111: 4mbps 1000: 8mbps 1001: 16mbps 1010: 32mbps 1011: 48mbps 1100: 64mbps 1101: 72mbps 1110: 80mbps 1111: 88mbps 7 reserved 0,ro reserved 6 parti_en 0,rw enable partition detection 5 no_dis_rx 0,rw not discard rx packets when ingress bandwidth control when received packets bandwidth reach ingress bandwidth threshold, the packets over the threshold are not discarded but with flow control. 4 flow_dis 0,rw flow control in full duplex mode, or back pressure in half duplex mode enable 0 ? enable 1 ? disable 3 bandwidth 0,rw bandwidth control 0: control with ingress and egress separately in bit 15~12 and bit 11~8. 1: control with ingress or egress in bit 19~16 DM9103 3-port switch with pci interface 36 preliminary datasheet DM9103-ds-p02 september 26, 2007 2 bp_dis 0,rw broadcast packet filter 0 ? accept broadcast packets 1 ? reject broadcast packets 1 mp_dis 0,rw multicast packet filter 0 ? accept multicast packets 1 ? reject multicast packets 0 mp_storm 0,rw broadcast storm control 0 ? only broadcast packet 1 ? also multicast packet 6.2.20 per port status data register (cr19) bit name default description 31 loopback 0,rw loop-back mode 30 moni_tx 0,rw tx packet monitored the transmitted packets are also forward to sniffer port. 29 moni_rx 0,rw rx packet monitored the received packets are also forward to sniffer port 28 dis_bmp 0,rw broad/multicast not monitored the received broadcast or multicast packets are not forward to sniffer port. 27 reserved 0,ro reserved 26 tx_dis 0,rw packet transmit disabled all packets can not be forward to this port. 25 rx_dis 0,rw packet receive disabled all received packets are discarded. 24 adr_dis 0,rw address learning disabled the source address (sa) field of packet is not learned to address table. 23~6 reserved 0,ro reserved 5 lp_fcs 0,ro link partner flow control enable status 4 bist 0,ro bist status 1: sram bist fail 0: sram bist pass 3 reserved 0,ro reserved 2 speed2 ro phy speed status 0: 10mbps, 1:100mbps 1 fdx2 ro phy duplex status 0: half-duplex, 1:full-duplex 0 link2 ro phy link status 0: link fail, 1: link ok DM9103 3-port switch with pciinterface preliminary datasheet 37 DM9103-ds-p02 september 26, 2007 6.2.21 per port vlan tag byte register (cr20) bit name default description 31:28 blk_ukp 0,rw ports of unknown packet be blocked the packets with da field not found in address table are not forward to the assigned ports. these bits can be written if cr17.5=1 27:24 blk_bp 0,rw ports of broadcast packet be blocked the received broadcast packets are not forward to the assigned ports. these bits can be written if cr17.5=1 23:20 blk_mp 0,rw ports of multicast packet be blocked the received multicast packets are not forward to the assigned ports. these bits can be written if cr17.5=1 19:16 blk_up 0,rw ports of unicast packet be blocked the received unicast packets are not forward to the assigned ports. note that the assigned port definition: bit 0 for port 0, bit 1 for port 1, bit 2 for port 2, and bit 3 for processor port. these bits can be written if cr17.5=1 15:13 pri 0,rw port vlan tag [15:13] 12 cfi 0,rw port vlan tag[12] 11:0 vid118 0,rw port vlan vid[11:0] 6.2.22 per port mib counter index register (cr21) bit name default description 31:8 reserved 0,ro reserved 7 ready 0,ro mib counter data is ready when this register is written with index data, this bit is cleared and the mib counter reading is in progress. after end of read mib counter, the mib data is loaded into cr22, and this bit is set to indicate that the mib data is ready, and then the mib data of this index is cleared. 6:5 reserved 0,ro reserved 4:0 index 0,rw mib counter index 00h: rx byte counter 01h: rx uni-cast packet counter 02h: rx multi-cast packet counter 03h: rx discard packet counter 04h: rx error packet counter 05h: tx byte counter 06h: tx uni-cast packet counter 07h: tx multi-cast packet counter 08h: tx discard packet counter 09h: tx error packet counter DM9103 3-port switch with pci interface 38 preliminary datasheet DM9103-ds-p02 september 26, 2007 6.2.23 mib counter data register (cr22) bit name default description 31:0 mib_data 0,ro mib counter data 6.2.24 vlan priority map register (cr23) define the 3-bit of priority field valn mapping to 2-bit priority queue number bit name default description 31:12 reserved 0,ro reserved 15:14 tag7 3,rw vlan priority tag value = 07h 13:12 tag6 3,rw vlan priority tag value = 06h 11:10 tag5 2,rw vlan priority tag value = 05h 9:8 tag4 2,rw vlan priority tag value = 04h 7:6 tag3 1,rw vlan priority tag value = 03h 5:4 tag2 1,rw vlan priority tag value = 02h 3:2 tag1 0,rw vlan priority tag value = 01h 1:0 tag0 0,rw vlan priority tag value = 00h 6.2.25 port-based vlan mapping table register 0 (cr24) define the port member in vlan group there are 16 vlan groups that defined in (cr24) ? (cr27) group 0 defined in cr24 bit 3:0 , group 1 defined in cr24 bit 11:8, ? and group 15 defined in cr27 bit 27:24. . bit name default description 31:28 reserved 0,ro reserved 27:24 group3 f,rw group 3 member:port 3(up),2~0 23:20 reserved 0,ro reserved 19:16 group2 f,rw group 2 member:port 3(up) 2~0 15:12 reserved 0,ro reserved 11:8 group1 f,rw group 1 member:port 3(up)2~0 7:4 reserved 0,ro reserved 3:0 group0 f,rw group 0 member : port 3(up)2~0 DM9103 3-port switch with pciinterface preliminary datasheet 39 DM9103-ds-p02 september 26, 2007 6.2.26 port-based vlan mapping table register 1 (cr25) bit name default description 31:28 reserved 0,ro reserved 27:24 group7 f,rw group 7 member:port 3(up)2~0 23:20 reserved 0,ro reserved 19:16 group6 f,rw group 6 member:port 3(up)2~0 15:12 reserved 0,ro reserved 11:8 group5 f,rw group 5 member:port 3(up)2~0 7:4 reserved 0,ro reserved 3:0 group4 f,rw group 4 member : port3(up) 2~0 6.2.27 port-based vlan mapping table register 2 (cr26) bit name default description 31:28 reserved 0,ro reserved 27:24 group11 f,rw group 11 member:port 3(up) 2~0 23:20 reserved 0,ro reserved 19:16 group10 f,rw group 10 member:port 3(up) 2~0 15:12 reserved 0,ro reserved 11:8 group9 f,rw group 9 member:port 3(up) 2~0 7:4 reserved 0,ro reserved 3:0 group8 f,rw group 8 member : port 3(up) 2~0 6.2.28 port-based vlan mapping table register 3 (cr27) bit name default description 31:28 reserved 0,ro reserved 27:24 group15 f,rw group 15 member:port 3(up) 2~0 23:20 reserved 0,ro reserved 19:16 group14 f,rw group 14 member:port 3(up) 2~0 15:12 reserved 0,ro reserved 11:8 group13 f,rw group 13 member:port 3(up) 2~0 7:4 reserved 0,ro reserved 3:0 group12 f,rw group 12 member : port 3(up) 2~0 DM9103 3-port switch with pci interface 40 preliminary datasheet DM9103-ds-p02 september 26, 2007 6.2.29 tos priority map register 0 (cr28) define the 6-bit or 3-bit of tos field mapping to 2-bit priority queue number. in 6-bit type, the cr16 bit 15 is ?1?, cr28 bit [1:0] define the mapping for tos value 0, cr28 bit [3:2] define the mapping for tos value 1, ? and so on, till cr31 bit [31:30] define tos value 63. in 3-bit type, cr28 bit [1:0] define the mapping for tos value 0, cr28 bit [3:2] define the mapping for tos value 1, ? and so on, till cr28 bit [15:14] define tos value 7. bit name default description 31:30 tosf 0,rw if bit 15 of cr16 =1 :tos[7:2]=0fh 29:28 tose 0,rw if bit 15 of cr16 =1 :tos[7:2]=0eh 27:26 tosd 0,rw if bit 15 of cr16 =1 :tos[7:2]=0dh 25:24 tosc 0,rw if bit 15 of cr16 =1 :tos[7:2]=0ch 23:22 tosb 0,rw if bit 15 of cr16 =1 :tos[7:2]=0bh 21:20 tosa 0,rw if bit 15 of cr16 =1 :tos[7:2]=0ah 19:18 tos9 0,rw if bit 15 of cr16 =1 :tos[7:2]=09h 17:16 tos8 0,rw if bit 15 of cr16 =1 :tos[7:2]=08h 15:14 tos7 0/3,rw if bit 15 of cr16 =1 :tos[7:2]=07h, otherwise tos]7:5]=07h 13:12 tos6 0/3,rw if bit 15 of cr16 =1 :tos[7:2]=06h, otherwise tos]7:5]=06h 11:10 tos5 0/2,rw if bit 15 of cr16 =1 :tos[7:2]=05h, otherwise tos]7:5]=05h 9:8 tos4 0/2,rw if bit 15 of cr16 =1 :tos[7:2]=04h, otherwise tos]7:5]=04h 7:6 tos3 0/1,rw if bit 15 of cr16 =1 :tos[7:2]=03h, otherwise tos]7:5]=03h 5:4 tos2 0,/1rw if bit 15 of cr16 =1 :tos[7:2]=02h, otherwise tos]7:5]=02h 3:2 tos1 0,rw if bit 15 of cr16 =1 :tos[7:2]=01h, otherwise tos]7:5]=01h 1:0 tos0 0,rw if bit 15 of cr16 =1 :tos[7:2]=00h, otherwise tos]7:5]=00h 6.2.30 tos priority map register 1 (cr29) bit name default description 31:30 tos1f 1,rw if bit 15 of cr16 =1 :tos[7:2]=1fh 29:28 tos1e 1,rw if bit 15 of cr16 =1 :tos[7:2]=1eh 27:26 tos1d 1,rw if bit 15 of cr16 =1 :tos[7:2]=1dh 25:24 tos1c 1,rw if bit 15 of cr16 =1 :tos[7:2]=1ch 23:22 tos1b 1,rw if bit 15 of cr16 =1 :tos[7:2]=1bh 21:20 tos1a 1,rw if bit 15 of cr16 =1 :tos[7:2]=1ah 19:18 tos19 1,rw if bit 15 of cr16 =1 :tos[7:2]=19h 17:16 tos18 1,rw if bit 15 of cr16 =1 :tos[7:2]=18h 15:14 tos17 1,rw if bit 15 of cr16 =1 :tos[7:2]=17h 13:12 tos16 1,rw if bit 15 of cr16 =1 :tos[7:2]=16h 11:10 tos15 1,rw if bit 15 of cr16 =1 :tos[7:2]=15h 9:8 tos14 1,rw if bit 15 of cr16 =1 :tos[7:2]=14h 7:6 tos13 1,rw if bit 15 of cr16 =1 :tos[7:2]=13h 5:4 tos12 1,rw if bit 15 of cr16 =1 :tos[7:2]=12h 3:2 tos11 1,rw if bit 15 of cr16 =1 :tos[7:2]=11h 1:0 tos10 1,rw if bit 15 of cr16 =1 :tos[7:2]=10h DM9103 3-port switch with pciinterface preliminary datasheet 41 DM9103-ds-p02 september 26, 2007 6.2.31 tos priority map register 2 (cr30) bit name default description 31:30 tos2f 2,rw if bit 15 of cr16 =1 :tos[7:2]=2fh 29:28 tos2e 2,rw if bit 15 of cr16 =1 :tos[7:2]=2eh 27:26 tos2d 2,rw if bit 15 of cr16 =1 :tos[7:2]=2dh 25:24 tos2c 2,rw if bit 15 of cr16 =1 :tos[7:2]=2ch 23:22 tos2b 2,rw if bit 15 of cr16 =1 :tos[7:2]=2bh 21:20 tos2a 2,rw if bit 15 of cr16 =1 :tos[7:2]=2ah 19:18 tos29 2,rw if bit 15 of cr16 =1 :tos[7:2]=29h 17:16 tos28 2,rw if bit 15 of cr16 =1 :tos[7:2]=28h 15:14 tos27 2,rw if bit 15 of cr16 =1 :tos[7:2]=27h 13:12 tos26 2,rw if bit 15 of cr16 =1 :tos[7:2]=26h 11:10 tos25 2,rw if bit 15 of cr16 =1 :tos[7:2]=25h 9:8 tos24 2,rw if bit 15 of cr16 =1 :tos[7:2]=24h 7:6 tos23 2,rw if bit 15 of cr16 =1 :tos[7:2]=23h 5:4 tos22 2,rw if bit 15 of cr16 =1 :tos[7:2]=22h 3:2 tos21 2,rw if bit 15 of cr16 =1 :tos[7:2]=21h 1:0 tos20 2,rw if bit 15 of cr16 =1 :tos[7:2]=20h 6.2.32 tos priority map register 3 (cr31) bit name default description 31:30 tos3f 3,rw if bit 15 of cr16 =1 :tos[7:2]=3fh 29:28 tos3e 3,rw if bit 15 of cr16 =1 :tos[7:2]=3eh 27:26 tos3d 3,rw if bit 15 of cr16 =1 :tos[7:2]=3dh 25:24 tos3c 3,rw if bit 15 of cr16 =1 :tos[7:2]=3ch 23:22 tos3b 3,rw if bit 15 of cr16 =1 :tos[7:2]=3bh 21:20 tos3a 3,rw if bit 15 of cr16 =1 :tos[7:2]=3ah 19:18 tos39 3,rw if bit 15 of cr16 =1 :tos[7:2]=39h 17:16 tos38 3,rw if bit 15 of cr16 =1 :tos[7:2]=38h 15:14 tos37 3,rw if bit 15 of cr16 =1 :tos[7:2]=37h 13:12 tos36 3,rw if bit 15 of cr16 =1 :tos[7:2]=36h 11:10 tos35 3,rw if bit 15 of cr16 =1 :tos[7:2]=35h 9:8 tos34 3,rw if bit 15 of cr16 =1 :tos[7:2]=34h 7:6 tos33 3,rw if bit 15 of cr16 =1 :tos[7:2]=33h 5:4 tos32 3,rw if bit 15 of cr16 =1 :tos[7:2]=32h 3:2 tos31 3,rw if bit 15 of cr16 =1 :tos[7:2]=31h 1:0 tos30 3,rw if bit 15 of cr16 =1 :tos[7:2]=30h DM9103 3-port switch with pci interface 42 preliminary datasheet DM9103-ds-p02 september 26, 2007 6.3 descriptor list refer to section 9.1 ?pci bus buffer management? for the description of the descriptor list. 6.3.1 receive descriptor format 6.3.1.1 receive status register (rdes0) bit name default description 31 own 0,ro owner bit of received status 30 rau 0,ro received address unmatched 29:16 fl 0,ro frame length 15 es 0,ro error summary 14 due 0,ro descriptor unavailable error 13:12 reserved 0,ro reserved 11 rf 0,ro runt frame 10 mf 0,ro multicast frame 9 bd 0,ro begin descriptor 8 ed 0,ro end descriptor 7:6 reserved 0,ro reserved 5 ft 0,ro frame type or ip packet 4 tcp 0,ro tcp packet 3 ple 0,ro physical layer error or udp packet 2 ae 0,ro alignment error 1 crce 0,ro crc error 0 foe 0,ro fifo overflow error 6.3.1.2 receive descriptor control and buffer size register (rdes1) bit name default description 31:25 reserved 0,rw reserved 24 chain 0,rw chain mode must be set to 1 in application 23:12 reserved 0,rw reserved 10:0 bl 0,rw buffer length DM9103 3-port switch with pciinterface preliminary datasheet 43 DM9103-ds-p02 september 26, 2007 6.3.1.3 buffer starting address register (rdes2) bit name default description 31:0 n_buf 0,rw buffer start address, bit 1~0 should be set 0 6.3.1.4 next descriptor address register (rdes3) bit name default description 31:0 n_adr 0,rw next descriptor address, bit 2~0 should be set 0 6.3.2 transmit descriptor format 31 0 own status control bits buffer address next descriptor address tdes0 tdes1 tdes2 tdes3 buffer length own 6.3.2.1 transmit status register (tdes0) bit name default description 31 own 0,ro owner bit of transmit status 30:16 reserved 0,ro reserved 15 es 0,ro error summary 14:10 reserved 0,ro reserved 9 lc 0,ro late collision 8 ec 0,ro excessive collision 7 reserved 0,ro reserved 6:3 cc 0,ro collision count 2 reserved 0,ro reserved 1 fue 0,ro fifo underrun error 0 df 0,ro deferred DM9103 3-port switch with pci interface 44 preliminary datasheet DM9103-ds-p02 september 26, 2007 6.3.2.2 transmit buffer control and buffer size register (tdes1) bit name default description 31:11 ci 0,rw completion interrupt 30 ed 0,rw ending descriptor 29 bd 0,rw begin descriptor 28 fb1 0,rw filtering mode bit 1 27 sf 0,rw setup frame 26 cad 0,rw crc append disable 25 reserved 0,rw reserved 24 chain 0,rw chain mode must be set to 1 in application 23 reserved 0,rw reserved 22 fb0 0,rw filtering mode bit 0 21 ip 0,rw ip packet checksum generation 20 tcp 0,rw tcp packet checksum generation 19 udp 0,rw udp packet checksum generation 18:11 reserved 0,rw reserved 10:0 bl 0,rw buffer length bit name default description 31:0 bufadr 0,rw buffer start address bit 31:00 6.3.2.4 next descriptor address register (tdes3) bit name default description 31:0 nadr 0,ro next descriptor address, bit 2~0 should be set 0. DM9103 3-port switch with pciinterface preliminary datasheet 45 DM9103-ds-p02 september 26, 2007 7. pci mode eeprom format the first 48 words of configuration eeprom are loaded into the DM9103 after power-on-reset for the settings of the power management, system id and ethernet address. the format of the eeprom is as followed name word offset description subsystem vendor id 0 the content will be transferred into the pci configuration space 2ch bit 15~0. subsystem id 1 the content will be transferred into the pci configuration space 2ch bit 31~16. reserved 2~3 reserved auto_ load_ control 4 bit3~0: ?1010? to enable auto-load of pci vendor_ id & device_ id. pci vendor id 5 when word[4] bit 3~0=?1010?, this word will be loaded to pci configuration space address 0 bit 15~0 pci device id 6 when word[4] bit 3~0=?1010?, this word will be loaded to pci configuration space address 0 bit 31~16 pmc 7 bit2~0: directly mapping to bit[21,26:25] of the pcipmr bit7~3: directly mapping to bit[31:27] of the pcipmr. bit 15~8: reserved reserved 8~9 reserved ethernet address 10~12 word 10 low byte for address 0 word 10 high byte for address 1 word 11 low byte for address 2 word 11 high byte for address 3 word 12 low byte for address 4 word 12 high byte for address 5 reserved 13~15 reserved control 16 bit 1:0=01: acce pt setting of word 17,18 bit 3:2=01: accept setting of word 19~26 bit 5:4=01: accept setting of word 27~30 bit 7:6=01: accept setting of word 31 bit 9:8=01: accept setting of word 32~39 bit 11:10=01: accept setting of word 40~47 bit 15:12 =01: reserved switch control 1 17 when word 16 bit 1:0 is ?01?, after power on reset: this word will be loaded to cr16 bit 15~0 switch control 2 18 when word 16 bit 1:0 is ?01?, after power on reset: this word will be loaded to cr16 bit 31~16 port 0 control 1 19 when word 16 bit 3:2 is ?01?, after power on reset: this word will be loaded to port 0 cr18 bit 15~0 port 0 control 2 20 when word 16 bit 3:2 is ?01?, after power on reset: this word will be loaded to port 0 cr18 bit 31~16 port 1 control 1 21 when word 16 bit 3:2 is ?01?, after power on reset: this word will be loaded to port 1 cr18 bit 15~0 port 1 control 2 22 when word 16 bit 3:2 is ?01?, after power on reset: this word will be loaded to port 1 cr18 bit 31~16 port 2 control 1 23 when word 16 bit 3:2 is ?01?, after power on reset: this word will be loaded to port 2 cr18 bit 15~0 DM9103 3-port switch with pci interface 46 preliminary datasheet DM9103-ds-p02 september 26, 2007 port 2 control 2 24 when word 16 bit 3:2 is ?01?, after power on reset: this word will be loaded to port 2 cr18 bit 31~16 up port control 1 25 when word 16 bit 3:2 is ?01?, after power on reset: this word will be loaded to port 3 cr18 bit 15~0 up port control 2 26 when word 16 bit 3:2 is ?01?, after power on reset: this word will be loaded to port 3 cr18 bit 31~16 port 0 vlan tag 27 when word 16 bit 5:4 is ?01?, after power on reset: this word will be loaded to port 0 cr20 bit 15~0 port 1 vlan tag 28 when word 16 bit 5:4 is ?01?, after power on reset: this word will be loaded to port 1 cr20 bit 15~0 port 2 vlan tag 29 when word 16 bit 5:4 is ?01?, after power on reset: this word will be loaded to port 2 cr20 bit 15~0 up port vlan tag 30 when word 16 bit 5:4 is ?01?, after power on reset: this word will be loaded to port 3 cr20 bit 15~0 vlan priority map 31 when word 16 bit 7:6 is ?01?, after power on reset: this word will be loaded to cr23 bit 15~0 port vlan group 0,1 32 when word 16 bit 9:8 is ?01?, after power on reset: this word will be loaded to cr24 bit 15~0 port vlan group 2,3 33 when word 16 bit 9:8 is ?01?, after power on reset: this word will be loaded to cr24 bit 31~16 port vlan group 4,5 34 when word 16 bit 9:8 is ?01?, after power on reset: this word will be loaded to cr25 bit 15~0 port vlan group 6,7 35 when word 16 bit 9:8 is ?01?, after power on reset: this word will be loaded to cr25 bit 31~16 port vlan group 8,9 36 when word 16 bit 9:8 is ?01?, after power on reset: this word will be loaded to cr26 bit 15~0 port vlan group 10,11 37 when word 16 bit 9:8 is ?01?, after power on reset: this word will be loaded to cr26 bit 31~16 port vlan group 12,13 38 when word 16 bit 9:8 is ?01?, after power on reset: this word will be loaded to cr27 bit 15~0 port vlan group 14,15 39 when word 16 bit 9:8 is ?01?, after power on reset: this word will be loaded to cr27 bit 31~16 tos priority map 0 40 when word 16 bit 11:10 is ?01?, after power on reset: this word will be loaded to cr28 bit 15~0 tos priority map 1 41 when word 16 bit 11:10 is ?01?, after power on reset: this word will be loaded to cr28 bit 31~16 tos priority map 2 42 when word 16 bit 11:10 is ?01?, after power on reset: this word will be loaded to cr29 bit 15~0 tos priority map 3 43 when word 16 bit 11:10 is ?01?, after power on reset: this word will be loaded to cr29 bit 31~16 tos priority map 4 44 when word 16 bit 11:10 is ?01?, after power on reset: this word will be loaded to cr30 bit 15~0 tos priority map 5 45 when word 16 bit 11:10 is ?01?, after power on reset: this word will be loaded to cr30 bit 31~16 tos priority map 6 46 when word 16 bit 11:10 is ?01?, after power on reset: this word will be loaded to cr31 bit 15~0 tos priority map 7 47 when word 16 bit 11:10 is ?01?, after power on reset: this word will be loaded to cr31 bit 31~16 DM9103 3-port switch with pciinterface preliminary datasheet 47 DM9103-ds-p02 september 26, 2007 8. phy registers mii register description add name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset loop back speed select auto-n enable power down isolate restart auto-n full duplex coll. test reserved 00h control 0 0 1 1 0 0 0 1 0 000_0000 t4 cap. tx fdx cap. tx hdx cap. 10 fdx cap. 10 hdx cap. reserved pream. supr. auto-n compl. remote fault auto-n cap. link status jabber detect extd cap. 01h status 0 1 1 1 1 0000 1 0 0 1 0 0 1 02h phyid1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 phyid2 1 0 1 1 1 0 model no. version no. 03h 01011 0000 04h auto-neg. advertise next page flp rcv ack remote fault reserved fc adv t4 adv tx fdx adv tx hdx adv 10 fdx adv 10 hdx adv advertised protocol selector field 05h link part. ability lp next page lp ack lp rf reserved lp fc lp t4 lp tx fdx lp tx hdx lp 10 fdx lp 10 hdx link partner protocol selector field 06h auto-neg. expansion reserved pardet fault lp next pg able next pg able new pg rcv lp auton cap. 10h specified config. bp 4b5b bp scr bp align bp_adpok reserve dr tx reserve d reserved force 100lnk reserved reserved rpdctr-e n reset st. mch pream. supr. sleep mode remote loopout 11h specified conf/stat 100 fdx 100 hdx 10 fdx 10 hdx reserve d reverse d reverse d phy addr [4:0] auto-n. monitor bit [3:0] 12h 10t conf/stat rsvd lp enable hbe enable sque enable jab enable reserve d reserved polarity reverse 13h pwdor reserved pd10dr v pd100l pdchip pdcrm pdaeq pddrv pdecli pdeclo pd10 14h specified config tstse1 tstse2 force_txs d force_fe f reserved mdix_cnt l autoneg_dlp bk mdix_fixvalu e mdix_down monsel1 monsel0 reserve d pd_valu e 16h rcver receiver error counter 17h dis_conne ct reversed disconnect_counter key to default in the register description that follows, the default column takes the form: DM9103 3-port switch with pci interface 48 preliminary datasheet DM9103-ds-p02 september 26, 2007 8.1 basic mode control register (bmcr) ? 00h bit bit name default description 15 reset 0, rw/sc reset 1=software reset 0=normal operation this bit sets the status and controls the phy registers to their default states. this bit, which is self-clearing, will keep returning a value of one until the reset process is completed 14 loopback 0, rw loopback loop-back control register 1 = loop-back enabled 0 = normal operation when in 100mbps operation mode, setting this bit may cause the descrambler to lose synchronization and produce a 720ms "dead time" before any valid data appears at the mii receive outputs 13 speed selection 1, rw speed select 1 = 100mbps 0 = 10mbps link speed may be selected either by this bit or by auto-negotiation. when auto-negotiation is enabled and bit 12 is set, this bit will return auto-negotiation selected medium type 12 auto-negotiation enable 1, rw auto-negotiation enable 1 = auto-negotiation is enabled, bit 8 and 13 will be in auto-negotiation status 11 power down 0, rw power down while in the power-down state, the phy should respond to management transactions. during the transition to power-down state and while in the power-down state, the phy should not generate spurious signals on the mii 1=power down 0=normal operation 10 isolate 0,rw isolate force to 0 in application. 9 restart auto-negotiation 0,rw/sc restart auto-negotiation 1 = restart auto-negotiation. re-initiates the auto-negotiation process. when auto-negotiation is disabled (bit 12 of this register cleared), this bit has no function and it should be cleared. this bit is self-clearing and it will keep returning to a value of 1 until auto-negotiation is initiated by the DM9103. the operation of the auto-negotiation process will not be affected by the management entity that clears this bit 0 = normal operation 8 duplex mode 1,rw duplex mode 1 = full duplex operation. duplex selection is allowed when auto-negotiation is disabled (bit 12 of this register is cleared). with auto-negotiation enabled, this bi t reflects the duplex capability selected by auto-negotiation 0 = normal operation DM9103 3-port switch with pciinterface preliminary datasheet 49 DM9103-ds-p02 september 26, 2007 7 collision test 0,rw collision test 1 = collision test enabled. when set, this bit will cause the col signal to be asserted in response to the assertion of tx_en in internal mii interface. 0 = normal operation 6-0 reserved 0,ro reserved read as 0, ignore on write 8.2 basic mode status register (bmsr) ? 01h bit bit name default description 15 100base-t4 0,ro/p 100base-t4 capable 1 = DM9103 is able to perform in 100base-t4 mode 0 = DM9103 is not able to perform in 100base-t4 mode 14 100base-tx full-duplex 1,ro/p 100base-tx full duplex capable 1 = DM9103 is able to perform 100base-tx in full duplex mode 0 = DM9103 is not able to perform 100base-tx in full duplex mode 13 100base-tx half-duplex 1,ro/p 100base-tx half duplex capable 1 = DM9103 is able to perform 100base-tx in half duplex mode 0 = DM9103 is not able to perform 100base-tx in half duplex mode 12 10base-t full-duplex 1,ro/p 10base-t full duplex capable 1 = DM9103 is able to perform 10base-t in full duplex mode 0 = DM9103 is not able to perform 10base-tx in full duplex mode 11 10base-t half-duplex 1,ro/p 10base-t half duplex capable 1 = DM9103 is able to perform 10base-t in half duplex mode 0 = DM9103 is not able to perform 10base-t in half duplex mode 10-7 reserved 0,ro reserved read as 0, ignore on write 6 mf preamble suppression 1,ro mii frame preamble suppression 1 = phy will accept management frames with preamble suppressed 0 = phy will not accept management frames with preamble suppressed 5 auto-negotiation complete 0,ro auto-negotiation complete 1 = auto-negotiation process completed 0 = auto-negotiation process not completed 4 remote fault 0, ro remote fault 1 = remote fault condition detected (cleared on read or by a chip reset). fault criteria and detection method is DM9103 implementation specific. this bit will set after the rf bit in the anlpar (bit 13, register address 05) is set 0 = no remote fault condition detected 3 auto-negotiation ability 1,ro/p auto configuration ability 1 = DM9103 is able to perform auto-negotiation 0 = DM9103 is not able to perform auto-negotiation 2 link status 0,ro link status 1 = valid link is established (for either 10mbps or 100mbps operation) 0 = link is not established the link status bit is implemented with a latching function, so that DM9103 3-port switch with pci interface 50 preliminary datasheet DM9103-ds-p02 september 26, 2007 the occurrence of a link failure condition causes the link status bit to be cleared and remain cleared until it is read via the management interface 1 jabber detect 0, ro jabber detect 1 = jabber condition detected 0 = no jabber this bit is implemented with a latching function. jabber conditions will set this bit unless it is cleared by a read to this register through a management interface or a DM9103 reset. this bit works only in 10mbps mode 0 extended capability 1,ro/p extended capability 1 = extended register capable 0 = basic register capable only 8.3 phy id identifier register #1 (phyid1) ? 02h the phy identifier registers #1 and #2 work together in a single identifier of the DM9103. the identifier consists of a concatenation of the organizationally unique identifier (oui), a vendor's model number, and a model revision number. davicom semiconductor's ieee assigned oui is 00606e. bit bit name default description 15-0 oui_msb <0181h> oui most significant bits this register stores bit 3 to 18 of the oui (00606e) to bit 15 to 0 of this register respectively. the most significant two bits of the oui are ignored (the ieee standard refers to these as bit 1 and 2) 8.4 phy id identifier register #2 (phyid2) ? 03h bit bit name default description 15-10 oui_lsb <101110>, ro/p oui least significant bits bit 19 to 24 of the oui (00606e) are mapped to bit 15 to 10 of this register respectively 9-4 vndr_mdl <001011>, ro/p vendor model number five bits of vendor model number mapped to bit 9 to 4 (most significant bit to bit 9) 3-0 mdl_rev <0000>, ro/p model revision number five bits of vendor model revision number mapped to bit 3 to 0 (most significant bit to bit 4) DM9103 3-port switch with pciinterface preliminary datasheet 51 DM9103-ds-p02 september 26, 2007 8.5 auto-negotiation advertisement register (anar) ? 04h this register contains the advertised abilities of this DM9103 device as they will be transmitted to its link partner during auto-negotiation. bit bit name default description 15 np 0,ro/p next page indication 0 = no next page available 1 = next page available the DM9103 has no next page, so this bit is permanently set to 0 14 ack 0,ro acknowledge 1 = link partner ability data reception acknowledged 0 = not acknowledged the DM9103's auto-negotiation state machine will automatically control this bit in the outgoing flp bursts and set it at the appropriate time during the auto-negotiation process. software should not attempt to write to this bit. 13 rf 0, rw remote fault 1 = local device senses a fault condition 0 = no fault detected 12-11 reserved x, rw reserved write as 0, ignore on read 10 fcs 0, rw flow control support 1 = controller chip supports flow control ability 0 = controller chip doesn?t support flow control ability 9 t4 0, ro/p 100base-t4 support 1 = 100base-t4 is supported by the local device 0 = 100base-t4 is not supported the DM9103 does not support 100base-t4 so this bit is permanently set to 0 8 tx_fdx 1, rw 100base-tx full duplex support 1 = 100base-tx full duplex is supported by the local device 0 = 100base-tx full duplex is not supported 7 tx_hdx 1, rw 100base-tx support 1 = 100base-tx half duplex is supported by the local device 0 = 100base-tx half duplex is not supported 6 10_fdx 1, rw 10base-t full duplex support 1 = 10base-t full duplex is supported by the local device 0 = 10base-t full duplex is not supported 5 10_hdx 1, rw 10base-t support 1 = 10base-t half duplex is supported by the local device 0 = 10base-t half duplex is not supported 4-0 selector <00001>, rw protocol selection bits these bits contain the binary encoded protocol selector supported by this node <00001> indicates that this device supports ieee 802.3 csma/cd DM9103 3-port switch with pci interface 52 preliminary datasheet DM9103-ds-p02 september 26, 2007 8.6 auto-negotiation link partner ability register (anlpar) ? 05h this register contains the advertised abilities of th e link partner when received during auto-negotiation. bit bit name default description 15 np 0, ro next page indication 0 = link partner, no next page available 1 = link partner, next page available 14 ack 0, ro acknowledge 1 = link partner ability data reception acknowledged 0 = not acknowledged the DM9103's auto-negotiation state machine will automatically control this bit from the incoming flp bursts. software should not attempt to write to this bit 13 rf 0, ro remote fault 1 = remote fault indicated by link partner 0 = no remote fault indicated by link partner 12-11 reserved 0, ro reserved read as 0, ignore on write 10 fcs 0, ro flow control support 1 = controller chip supports flow control ability by link partner 0 = controller chip doesn?t support flow control ability by link partner 9 t4 0, ro 100base-t4 support 1 = 100base-t4 is supported by the link partner 0 = 100base-t4 is not supported by the link partner 8 tx_fdx 0, ro 100base-tx full duplex support 1 = 100base-tx full duplex is supported by the link partner 0 = 100base-tx full duplex is not supported by the link partner 7 tx_hdx 0, ro 100base-tx support 1 = 100base-tx half duplex is supported by the link partner 0 = 100base-tx half duplex is no t supported by the link partner 6 10_fdx 0, ro 10base-t full duplex support 1 = 10base-t full duplex is supported by the link partner 0 = 10base-t full duplex is not supported by the link partner 5 10_hdx 0, ro 10base-t support 1 = 10base-t half duplex is supported by the link partner 0 = 10base-t half duplex is not supported by the link partner 4-0 selector <00000>, ro protocol selection bits link partner?s binary encoded protocol selector DM9103 3-port switch with pciinterface preliminary datasheet 53 DM9103-ds-p02 september 26, 2007 8.7 auto-negotiation expansion register (aner)- 06h bit bit name default description 15-5 reserved 0, ro reserved read as 0, ignore on write 4 pdf 0, ro/lh local device parallel detection fault pdf = 1: a fault detected via parallel detection function. pdf = 0: no fault detected via parallel detection function 3 lp_np_able 0, ro link partner next page able lp_np_able = 1: link partner, next page available lp_np_able = 0: link partner, no next page 2 np_able 0,ro/p local device next page able np_able = 1: DM9103, next page available np_able = 0: DM9103, no next page DM9103 does not support this function, so this bit is always 0 1 page_rx 0, ro new page received a new link code word page received. this bit will be automatically cleared when the register (register 6) is read by management 0 lp_an_able 0, ro link partner auto-negotiation able a ?1? in this bit indicates that the link partner supports auto-negotiation 8.8 davicom specified configuration register (dscr) ? 10h bit bit name default description 15 bp_4b5b 0,rw bypass 4b5b encoding and 5b4b decoding 1 = 4b5b encoder and 5b4b decoder function bypassed 0 = normal 4b5b and 5b4b operation 14 bp_scr 0, rw bypass scrambler/descrambler function 1 = scrambler and descrambler function bypassed 0 = normal scrambler and descrambler operation 13 bp_align 0, rw bypass symbol alignment function 1 = receive functions (descrambler, symbol alignment and symbol decoding functions) bypassed. transmit functions (symbol encoder and scrambler) bypassed 0 = normal operation 12 bp_adpok 0, rw bypass adpok force signal detector (sd) active. this register is for debug only, not release to customer 1=forced sd is ok, 0=normal operation 11 reserved rw reserved force to 0 in application 10 tx 1, rw 100base-tx mode control 1 = 100base-tx operation 0 = 100base-fx operation 9 reserved 0, ro reserved DM9103 3-port switch with pci interface 54 preliminary datasheet DM9103-ds-p02 september 26, 2007 8 rmii_mode 0, rw rmii mode enable 7 f_link_100 0, rw force good link in 100mbps 0 = normal 100mbps operation 1 = force 100mbps good link status this bit is useful for diagnostic purposes 6 reserved 0, rw reserved force to 0 in application. 5 col_led 0, rw col led control (valid in phy test mode) 4 rpdctr-en 1, rw reduced power down control enable this bit is used to enable automatic reduced power down 0 = disable automatic reduced power down 1 = enable automatic reduced power down 3 smrst 0, rw reset state machine when writes 1 to this bit, all state machines of phy will be reset. this bit is self-clear after reset is completed 2 mfpsc 1, rw mf preamble suppression control mii frame preamble suppression control bit 1 = mf preamble suppression bit on 0 = mf preamble suppression bit off 1 sleep 0, rw sleep mode writing a 1 to this bit will cause phy entering the sleep mode and power down all circuit except oscillator and clock generator circuit. when waking up from sleep mode (write this bit to 0), the configuration will go back to the state before sleep; but the state machine will be reset 0 rlout 0, rw remote loopout control when this bit is set to 1, the re ceived data will loop out to the transmit channel. this is useful for bit error rate testing DM9103 preliminary datasheet 55 DM9103-ds-p02 june 01, 2007 8.9 davicom specified configuration and status register (dscsr) ? 11h bit bit name default description 15 100fdx 1, ro 100m full duplex operation mode after auto-negotiation is completed, resu lts will be written to this bit. if this bit is 1, it means the operation 1 mode is a 100m full duplex mode. the software can read bit [15:12] to see which mode is selected after auto-negotiation. this bit is invalid when it is not in the auto-negotiation mode 14 100hdx 1, ro 100m half duplex operation mode after auto-negotiation is completed, resu lts will be written to this bit. if this bit is 1, it means the operation 1 mode is a 100m half duplex mode. the software can read bit [15:12] to see which mode is selected after auto-negotiation. this bit is invalid when it is not in the auto-negotiation mode 13 10fdx 1, ro 10m full duplex operation mode after auto-negotiation is completed, resu lts will be written to this bit. if this bit is 1, it means the operation 1 mode is a 10m full duplex mode. the software can read bit [15:12] to see which mode is selected after auto-negotiation. this bit is invalid when it is not in the auto-negotiation mode 12 10hdx 1, ro 10m half duplex operation mode after auto-negotiation is completed, resu lts will be written to this bit. if this bit is 1, it means the operation 1 mode is a 10m half duplex mode. the software can read bit [15:12] to see which mode is selected after auto-negotiation. this bit is invalid when it is not in the auto-negotiation mode 11 reserved 0, ro reserved read as 0, ignore on write 10 reserved 0,rw reserved 9 reserved 0,rw reserved 8-4 phyadr[4:0 ] 1, rw phy address bit 4:0 the first phy address bit transmitted or received is the msb of the address (bit 4). a station management entity connected to multiple phy entities must know the appropriate address of each phy auto-negotiation monitor bits these bits are for debug only. the auto-negotiation status will be written to these bits. b3 b2 b1 b0 0 0 0 0 in idle state 0 0 0 1 ability match 0 0 1 0 acknowledge match 0 0 1 1 acknowledge match fail 0100consistency match 0 1 0 1 consistency match fail 0 1 1 0 parallel detects signal_link_ready 0 1 1 1 parallel detects signal_link_ready fail 3-0 anmb[3:0] 0, ro 1 0 0 0 auto-negotiation completed successfully DM9103 3-port switch with pci interface 56 preliminary datasheet DM9103-ds-p02 september 26, 2007 8.10 10base-t configuration/status (10btcsr) ? 12h bit bit name default description 15 reserved 0, ro reserved read as 0, ignore on write 14 lp_en 1, rw link pulse enable 1 = transmission of link pulses enabled 0 = link pulses disabled, good link condition forced this bit is valid only in 10mbps operation 13 hbe 1,rw heartbeat enable 1 = heartbeat function enabled 0 = heartbeat function disabled when the DM9103 is configured for full duplex operation, this bit will be ignored (the collision/heartbeat function is invalid in full duplex mode) 12 squelch 1, rw squelch enable 1 = normal squelch 0 = low squelch 11 jaben 1, rw jabber enable enables or disables the jabber function when the DM9103 is in 10base-t full duplex or 10base-t transceiver loopback mode 1 = jabber function enabled 0 = jabber function disabled 10 serial 0, rw 10m serial mode (valid in phy test mode) force to 0, in application. 9-1 reserved 0, ro reserved read as 0, ignore on write 0 polr 0, ro polarity reversed when this bit is set to 1, it indicates that the 10mbps cable polarity is reversed. this bit is automatically set and cleared by 10base-t module DM9103 3-port switch with pciinterface preliminary datasheet 57 DM9103-ds-p02 september 26, 2007 8.11 power down control register (pwdor) ? 13h bit bit name default description 15-9 reserved 0, ro reserved read as 0, ignore on write 8 pd10drv 0, rw vendor power down control test 7 pd100dl 0, rw vendor power down control test 6 pdchip 0, rw vendor power down control test 5 pdcrm 0, rw vendor power down control test 4 pdaeq 0, rw vendor power down control test 3 pddrv 0, rw vendor power down control test 2 pdedi 0, rw vendor power down control test 1 pdedo 0, rw vendor power down control test 0 pd10 0, rw vendor power down control test * when selected, the power down value is control by register 20.0 8.12 (specified config) register ? 14h bit bit name default description 15 tstse1 0,rw vendor test select control 14 tstse2 0,rw vendor test select control 13 force_txsd 0,rw force signal detect 1: force sd signal ok in 100m 0: normal sd signal. 12 force_fef 0,rw vendor test select control 11-8 reserved 0, ro reserved read as 0, ignore on write 7 mdix_cntl mdi/mdix,ro the polarity of mdi/mdix value 1: mdix mode 0: mdi mode 6 autoneg_dpbk 0,rw auto-negotiation loopback 1: test internal digital auto-negotiation loopback 0: normal. 5 mdix_fix value 0, rw mdix_cntl force value: when mdix_down = 1, mdix_cntl value depend on the register value. 4 mdix_down 0,rw mdix down manual force mdi/mdix. 0: enable hp auto-mdix 1: disable hp auto-mdix , mdix_cntl value depend on 20.5 3 monsel1 0,rw vendor monitor select 2 monsel0 0,rw vendor monitor select 1 reserved 0,rw reserved force to 0, in application. 0 pd_value 0,rw power down control value decision the value of each field register 19. 1: power down 0: normal DM9103 3-port switch with pci interface 58 preliminary datasheet DM9103-ds-p02 september 26, 2007 8.13 davicom specified receive error counter register (recr) ? 16h bit bit name default description 15-0 rcv_ err_ cnt 0, ro receive error counter receive error counter that increments upon detection of rxer. clean by read this register. 8.14 davicom specified disconnect counter register (discr) ? 17h bit bit name default description 15-8 reserved 0, ro reserved 7-0 disconnect counter 0, ro disconnect counter that increment upon detection of disconnection. clean by read this register. DM9103 3-port switch with pciinterface preliminary datasheet 59 DM9103-ds-p02 september 26, 2007 9. functional description 9.1 pci bus buffer management 9.1.1. overview the data buffers for reception and transmission of data reside in the host memory. they are directed by the descriptor lists that are located in another region of the host memory. all actions for the buffer management are operated by the DM9103 in conjunction with the driver. the data structures and processing algorithms are described in the following text. 9.1.2. data structure and descriptor list there are two types of buffers that reside in the host memory, the transmit buffer and the receive buffer. the buffers are composed of many distributed regions in the host memory. they are linked together and controlled by the descriptor lists that reside in another region of the host memory. the content of each descriptor includes pointer to the buffer, count of the buffer, command and status for the packet to be transmitted or received. each descriptor list starts from the address setting of cr3 (receive descriptor base address) and cr4 (transmit descriptor base address). the descriptor lists have two types of structure, ring structure and chain structure. 9.1.3. buffer management : ring structure method as the ring structure depicted below, the descriptors are linked directly one after another. the first and last descriptor on the list have the necessary information for the DM9103 to return to the beginning of the list after the bottom descriptor is accessed. each descriptor points to the two buffer regions and one packet may cross many descriptors boundaries. buffer 1 buffer 2 buffer 1 buffer 2 descriptor 1 descriptor n packet n control buffer address 1 buffer address 2 status own buffer 2 length buffer 1 length 9.1.4. buffer management : chain structure method as the chain structure depicted below, each descriptor contains two pointers, one point to a single buffer and the other to the next descriptor chained. the first descriptor is chained by the last descriptor under host driver?s control. with this structure, a descriptor can be allocated anywhere in DM9103 3-port switch with pci interface 60 preliminary datasheet DM9103-ds-p02 september 26, 2007 host memory and is chained to the next descriptor. the chain structure and the ring structure may combine to make the buffer structure more flexible. buffer 1 buffer 1 descriptor 1 descriptor n packet n control buffer address 1 status own not valid next descriptor address buffer 1 length 9.1.5. descriptor list: buffer descriptor format (a). receive descriptor format each receive descriptor has four doubleword entries and may be read or written by the host or the DM9103. the descriptor format is shown below with a detailed functional description. 31 0 own status control bits buffer address 1 buffer address 2 rdes0 rdes1 rdes2 rdes3 buffer 1 length buffer 2 length own receive descriptor format DM9103 3-port switch with pciinterface preliminary datasheet 61 DM9103-ds-p02 september 26, 2007 rdes0: owner bit with receive status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 own frame length ( fl ) aun own: 1=owned by DM9103, 0=owned by host this bit should be reset after packet reception is completed. it will be set by the host after received data are removed. fl: frame length indicating total byte count of received packet. aun: received address unmatched. 151413121110 9 8 7 6 5 4 3 2 1 0 es rf ce mf due lbom bd ed tlf lcs ft rwt ple ae foe efl this word-wide content includes status of received frame. they are loaded after the received buffer that belongs to the corresponding descriptor is full. all status bits are valid only when the last descriptor ( end descriptor ) bit is set. bit 15: es, error summary it is set for the following error conditions : descriptor unavailable error (due =1), runt frame (rf=1), excessive frame length (efl=1), late collision seen (lcs=1), crc error (ce=1), fifo overflow error (foe=1). valid only when ed is set. bit 14: due, descriptor unavailable error it is set when the frame is truncated due to the buffer unavailable. it is valid only when ed is set. bit 13,12: lbom, loopback operation mode these two bits show the received frame is derived from 00 --- normal operation 01 --- internal loopback 10 --- external loopback 11 --- reserved bit 11: rf, runt frame it is set to indicate the received frame has the size smaller than 64 byte s. valid only when ed is set and foe is reset. bit 10: mf, multicast frame it is set to indicate the received frame has a multicast address. valid only when ed is set. bit 9: bd, begin descriptor this bit is set for the descriptor indicating start of a received frame. bit 8: ed, ending descriptor this bit is set for the descriptor indicating end of a received frame. bit 7: efl, excessive frame length it is set to indicate the received frame length exceeds 1518 bytes. valid only when ed is set. bit 6: lcs: late collision seen it is set to indicate a late collision found during the frame reception. valid only when ed is set. bit 5: ft, frame type it is set to indicate the received frame is the ethernet-type. it is reset to indicate the received frame is the eee802.3- type. valid only when ed is set bit 4: rwt, receive watchdog time-out it is set to indicate the receive watchdog time-out during the frame reception. cr5<9> will also be set. valid only when ed is set. DM9103 3-port switch with pci interface 62 preliminary datasheet DM9103-ds-p02 september 26, 2007 bit 3: ple, physical layer error it is set to indicate a physical layer error found during the frame reception. bit 2: ae, alignment error it is set to indicate the received frame ends with a non-byte boundary. bit 1: ce, crc error it is set to indicate the received frame ends with a crc error. valid only when ed is set. bit 0: foe, fifo overflow error this bit is valid for ending descriptor is set. (ed = 1) it is set to indicate a fifo overflow error happens during the frame reception. rdes1: descriptor status and buffer size 31 30 29 28 27 26 25 24 23 22 21 ~ 11 10 ~ 0 eor ce buffer 2 length buffer 1 length bit 25: eor, end of ring set to indicate that the descriptor is located on the bottom of the descriptor list. bit 24: ce, chain enable set to indicate that the second address is the chained descriptor instead of the other buffer. used as the indication of the chain structure. bit 21-11: buffer 2 length indicates the size of the second buffer. it has no meaning in chain type descriptor. bit 10-0: buffer 1 length indicates the size of the first buffer in ring type structure and single buffer in chain type structure. rdes2: buffer 1 starting address indicates the physical starting address of buffer 1. 31 0 buffer address 1 rdes3: buffer 2 starting address indicates the physical starting address of buffer 2 under the ring structure and that of the chained descriptor under the chain descriptor structure. 31 0 buffer address 2 (b). transmit descriptor format each transmit descriptor has four doubleword content and may be read or written by the host or DM9103 3-port switch with pciinterface preliminary datasheet 63 DM9103-ds-p02 september 26, 2007 by the DM9103. the descriptor format are shown below with detailed description. 31 0 own status control bits buffer address 1 buffer address 2 tdes0 tdes1 tdes2 tdes3 buffer 2 length buffer 1 length transmit descriptor format tdes0 : owner bit with transmit status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 own bit 31: own, 1=owned by DM9103, 0=owned by host, this bit should be set when the transmitting buffer is filled with data and re ady to be transmitted. it will be reset by DM9103 after transmitting the whole data buffer. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 es ec hf cc tx jt loc nc lc lf fue df this word wide content includes status of transmitted frame. they are loaded after the data buffer that belongs to the corresponding descriptor is transmitted. bit 15: es, error summary it is set for the following error conditions : transmit jabber time-out ( txjt=1), loss of carrier (loc=1), no carrier (nc=1), late collision (lc=1), excessive collision (ec=1), fifo underrun error (fue=1). bit 14: txjt, transmit jabber time out it is set to indicate th e transmitted frame is truncated due to the transmit jabber time out condition. the transmit jabber time out interrupt cr5<3> is set. bit 11: loc, loss of carrier it is set to indicate the loss of carrier during the frame transmission. not valid in internal loopback mode. bit 10: nc, no carrier it is set to indicate that no carrier signal from transceiver is found. not valid in internal loopback mode. bit 9: lc, late collision it is set to indicate a collision occurs after the collision window of 64 bytes. not valid if fue is set. bit 8: ec, excessive collision it is set to indicate the transmission is aborted due to 16 excessive collisions. bit 7: hf, heartbeat fail it is set to indicate the heartbeat check failed after complete tr ansmission. not valid if fue is set. when tdes0<14> is set, this bit is not valid. bits 6-3: cc, collision count these bits shows the number of collision before transmission. not valid if excessive collision bit is also set. DM9103 3-port switch with pci interface 64 preliminary datasheet DM9103-ds-p02 september 26, 2007 bit 2: lf, link test fail it is set to indicate the link test fails before the frame transmission. bit 1: fue, fifo underrun error it is set to indicate the transmission aborted due to a transmit fifo underrun condition. bit 0: df, deferred it is set to indicate the frame is deferred before ready to transmit. tdes1 : transmit buffer control and buffer size 31 30 29 28 27 26 25 24 23 22 21 ~ 11 10 ~ 0 ci ed bd fmb1 setf cad eor ce pd fmb0 buffer 2 length buffer 1 length bit 31: ci, completion interrupt it is set to enable the transmit interrupt after the present frame has been transmitted. it is valid only when tdes1<30> is set or when it is a setup frame. bit 30: ed, ending descriptor it is set to indicate the pointed buffer contains the last segment of a frame. bit 29: bd, begin descriptor it is set to indicate the pointed buffer contains the first segment of a frame. bit 28: fmb1, filtering mode bit 1 this bit is used with fmb0 to indicate the filtering type when the present frame is a setup frame. bit 27: setf, setup frame it is set to indicate the current frame is a setup frame. bit 26: cad, crc append disable it is set to disable the crc appending at the end of the transmitted frame. valid only when tdes1<29> is set. bit 25: eor, end of ring descriptor it is set to indicate th e descriptor is located on the bottom of the descriptor list. bit 24: ce, chain enable this bit is set to indicate the second address ( tdes3 ) is the chained descriptor instead of the other buffer. it is used as the indication of the chain structure. when reset, it indicates the ring structure. bit 23: pd, padding disable this bit is set to disable the padding field for a packet shorter than 64 bytes. bit 22: fmb0, filtering mode bit 0 this bit is used with fmb1 to indicate the filtering type when the present frame is a setup frame. fmb1 fmb0 filtering type 0 0 perfect filtering 0 1 hash filtering 1 0 inverse filtering 1 1 hash-only filtering bits 21-11: buffer 2 length indicates the size of second buffer. it has no meaning with chain structure descriptor type. bit 10-0: buffer 1 length indicates the size of the first buffer in ring type structure and single buffer in chain type structure. DM9103 preliminary datasheet 65 DM9103-ds-p02 june 01, 2007 tdes2 : buffer 1 starting address indicates the physical starting address of buffer 1. ba1: 31 0 buffer address 1 tdes3 : buffer 2 starting address indicates the physical starting address of buffer 2 under the ring structure. ba2: 31 0 buffer address 2 initialization procedure after hardware or software reset, the transmit and receive processes are placed in the stop state. the DM9103 can accept the host commands to start operation. the general procedure for initialization is described below: (1) read/write suitable values for the pci configuration registers. (2) write cr3 and cr4 to provide the starting address of each descriptor list. (3) write cr0 to set global host bus operation parameters. (4) write cr7 to mask unnecessary interrupt causes. (5) write cr6 to set global parameters and start both the receive and transmit processes. the receive and transmit processes will enter the running state and attempt to acquire descriptors from the respective descriptor lists. (6) wait for any interrupt. data buffer processing algorithm the data buffer processing algorithm is based on the cooperation of the host and the DM9103. the host sets cr3 ( receive descriptor base address ) and cr4 ( transmit descriptor base address ) for the descriptor list initialization. the DM9103 will start the data buffer transfer af ter the descriptor polling and get the ownership. for detailed processing procedure, please see below. 1. receive data buffer processing the DM9103 always attempts to acquire an extra descriptor in anticipation of the incoming frames. any incoming frame size covers a few buffer regions and descriptors. the following conditions satisfy the descriptor acquisition attempt : z when start/stop receive sets immediately after being placed in the running state. z when the DM9103 begins writing frame data to a data buffer pointed to by the current descriptor and the buffer ends before the frame ends. z when the DM9103 completes the reception of a frame and the current receive descriptor is closed. z when the receive process is suspended due to no free buffer for the DM9103 and a new frame is received. z when the receive poll demand is issued. after acquiring the free descriptor, the DM9103 processes the incoming frame and places it in the acquired descriptor's data buffer. when the whole received frame data has been transferred, the DM9103 will write the status information to the last descriptor. the same process will repeat until it encounters a descriptor flagged as being owned by the host. if this occurs, the receive process enters the suspended state and waits the host to service. DM9103 preliminary datasheet 66 DM9103-ds-p02 june 01, 2007 stop state descriptor access datat transfer write status suspended start receive command or receive poll command buffer available ( own bit = 1 ) fifo threshold reached frame fully received buffer not full receive buffer unavailable new frame coming or receive poll command stop receive command or reset command buffer full receive buffer management state transition DM9103 3-port switch with pciinterface preliminary datasheet 67 DM9103-ds-p02 september 26, 2007 9.1.2. transmit data buffer processing when start/stop transmit command is set and the DM9103 is in running state, the transmit process polls the transmit descriptor list for frames requiring transmission. when it completes a frame transmission, the status related to the transmitted frame will be written into the transmit descriptor. if the DM9103 detects a descriptor flagged as owned by the host and no transmit buffers are available, the transmit process will be suspended. while in the running state, the transmit process can simultaneously acquire two frames. as the transmit process completes copying the first frame, it immediately polls the transmit descriptor list for the second frame. if the second frame is valid, the transmit process copies the frame before writing the status information of the first frame. both conditions below will make transmit process be suspended : (i) the DM9103 detects a descriptor owned by the host. ( ii ) a frame transmission is aborted when a locally induced error is detected. under either condition, the host driver has to service the condition before the DM9103 can resume. stop state descriptor access data transfer write status suspended buffer available ( own bit = 1 ) frame fully transmited start transmit command or transmit poll command under fifo threshold buffer not empty buffer empty transmit buffer unavailable ( owned by host ) transmit poll command stop transmit command or reset command transmit buffer management state transition DM9103 3-port switch with pciinterface 68 preliminary datasheet DM9103-ds-p02 september 26, 2007 9.2 switch function: 9.2.1 address learning the DM9103 has a self-learning mechanism for learning the mac addresses of incoming packets in real time. DM9103 stores mac addresses, port number and time stamp information in the hash-based address table. it can learn up to 1k unicast address entry. the switch engine updates address table with new entry if incoming packet?s source address (sa) does not exist and incoming packet is valid (non-error and legal length). besides, DM9103 has an option to disable address learning for individual port. this feature can be set by bit 24 of register cr19 9.2.2 address aging the time stamp information of address table is used in the aging process. the switch engine updates time stamp whenever the corresponding sa receives. the switch engine would delete the entry if its time stamp is not updated for a period of time. the period can be programmed or disabled through bit 0 & 1 of register cr16. 9.2.3 packet forwarding the DM9103 forwards the incoming packet according to following decision: (1). if da is multicast/broadcast, the packet is forwarded to all ports, except to the port on which the packet was received. (2). switch engine would look up address table based on da when incoming packets is unicast. if the da was not found in address table, the packet is treated as a multicast packet and forward to other ports. if the da was found and its destination port number is different to source port number, the packet is forward to destination port. (3). switch engine also look up vlan, port monitor setting and other forwarding constraints for the forwarding decision, more detail will discuss in later sections. the DM9103 will filter incoming packets under following conditions: (1). error packets, including crc errors, alignment errors, illegal size errors. (2). pause packets. (3). if incoming packet is unicast and its destination port number is equal to source port number. 9.2.4 inter-packet gap (ipg) ipg is the idle time between any two valid packets at the same port. the typical number is 96 bits time. in other word, the value is 9.6u sec for 10mbps and 960n sec for 100mbps. 9.2.5 back-off algorithm the DM9103 implements the binary exponential back-off algorithm in half -duplex mode compliant to ieee standard 802.3. 9.2.6 late collision late collision is a type of collision. if a collision error occurs after the first 512 bit times of data are transmitted, the packet is dropped. 9.2.7 half duplex flow control the DM9103 supports ieee standard 802.3x flow control frames on both transmit and receive sides. on the receive side, the DM9103 will defer transmitting next normal frames, if it receives a pause frame from link partner. on the transmit side, the DM9103 issues pause frame with maximum pause time when internal resources such as received buffers, transmit queue and transmit descriptor ring are unavailable. once resources are available, the DM9103 sends out a pause frame with zero pause time allows traffic to resume immediately. 9.2.8 full duplex flow control the DM9103 supports half-duplex backpressure. the inducement is the same as full duplex mode. when flow control is required, the DM9103 sends jam pattern, thus forcing a collision. the flow control ability can be set in bit 4 of register cr18. 9.2.9 partition mode the DM9103 provides a partition mode for each port, see bit 6 of register cr18. the port enters DM9103 3-port switch with pciinterface preliminary datasheet 69 DM9103-ds-p02 september 26, 2007 partition mode when more than 64 consecutive collisions are occurred. in partition mode the port continuous to transmit but it will not receive. the port returned to normal operation mode when a good packet is seen on the wire. the detail description of partition mode represent following: (1). entering partition state a port will enter the partition state when either of the following conditions occurs: z the port detects a collision on every one of 64 consecutive re-transmit attempts to the same packet. z the port detects a single collision which occurs for more than 512 bit times. z transmit defer timer time out, which indicates the transmitting packet is deferred to long. (2). while in partition state: the port will continue to transmit its pending packet, regardless of the collision detection, and will not allow the usual back-off algorithm. additional packets pending for transmission will be transmitted, while ignoring the internal collision indication. this frees up the port?s transmit buffers which would otherwise be filled up at the expense of other ports buffers. the assumption is that the partition is signifying a system failure situation (bad connection/cable/station), thus dropping packets is a small price to pay vs. the cost of halting the switch due to a buffer full condition. (3). exiting from partition state the port exits from partition state, following the end of a successful packet transmission. a successful packet transmission is defined as no collisions were detected on the first 512 bits of the transmission. 9.2.10 broadcast storm filtering the DM9103 has an option to limit the traffic of broadcast or multicast packets, to protect the switch from lower bandwidth availability. there are two type of broadcast storm control, one is throttling broadcast packet only, the other includes multicast. this feature can be set through bit 0 of register cr18. the broadcast storm threshold can be programmed by eeprom or bit 23~20 of cr18, the default setting is no broadcast storm protecting. 9.2.11 bandwidth control the DM9103 supports two type of bandwidth control for each port. one is the ingress and egress bandwidth rate can be control separately, the other is combined together, this function can be set through bit 3 of register cr18. the bandwidth control is disabled by default. for separated bandwidth control mode, the threshold rate is defined in bit 15~8 of register cr18. for combined mode, it is defined in bit 19~16 of register cr18. the behavior of bandwidth control as below: (1).for the ingress control, if flow control function is enabled, pause or jam packet will be transmitted. the ingress packets will be dropped if flow control is disabled. (2).for the egress control, the egress port will not transmit any packets. on the other hand, the ingress bandwidth of source port w ill be throttled that prevent packets from forwarding. (3).in combined mode, if the sum of ingress and egress bandwidth over threshold, the bandwidth will be throttled. 9.2.12 port monitoring support the DM9103 supports ?port monitoring? function on per port base, detail as below: (1). sniffer port and monitor port there is only one port can be selected as ?sniffer port? by bit 4~3 of register cr16, multiple ports can be set as ?receive monitor port? or ?transmit monitor port? in per-port bit 29 and 30 of register cr19 respectively. (2).receive monitor all packets received on the ?receive monitor port? are send a copy to ?sniffer port?. for example, port 0 is set as ?receive monitor port? and port 3 is selected as ?sniffer port?. if a packet is received form port 0 and predestined to port 1 after forwarding decision, the DM9103 will forward it to port 1 and port 3 in the end. (3).transmit monitor all packets transmitted on the ?transmit monitor port? are send a copy to ?sniffer port?. for example, port 1 is set as ?transmit monitor port? and port 3 is selected as ?sniffer port?. if a packet is received from port 0 and predestined to port 1 after forwarding decision, the DM9103 will forw ard it to port 1 and port 3 in the end. (4).exception DM9103 3-port switch with pciinterface 70 preliminary datasheet DM9103-ds-p02 september 26, 2007 the DM9103 has an optional setting that broadcast/multicast packets are not monitored (see bit 28 of register cr19). it?s useful to avoid unnecessary bandwidth. 9.2.13 vlan support 9.2.13.1 port-based vlan the DM9103 supports port-based vlan as default, up to 16 groups. each port has a default vid called pvid (port vid, see bit 11~0 of register cr20). the DM9103 used lsb 4-bytes of pvid as index and mapped to register cr24~27, to define the vlan groups. 9.2.13.2 802.1q-based vlan regarding ieee 802.1q standard, tag-based vlan uses an extra tag to identify the vlan membership of a frame across vlan-aware switch/router. a tagged frame is four bytes longer than an untagged frame and contains two bytes of tpid (tag protocol identifier) and two bytes of tci (tag control information). dest. src. length/type data dest. src. tpid data tci length / type priority cfi vid standard frame tagged frame 0x8100 2 bytes 3 bits 1 bits 12 bits vlan_9013.vsd the DM9103 also supports 16 802.1q-based vlan groups, as specified in bit 8 of register cr16. it?s obvious that the tagged packets can be assigned to several different vlans which are determined according to the vid inside the vlan tag. therefore, the operation is similar to port-based vlan. the DM9103 used lsb 4-bytes vid of received packet with vlan tag and vlan group mapping register (cr24~cr27) to configure the vlan partition. if the destination port of received packet is not same vlan group with received port, it will be discarded. 9.2.13.3 tag/untag user can define each port as tag port or un-tag port by bit 31 of register cr18 in 802.1q-based vlan mode. the operation of tag and un-tag can explain as below conditions: (1). receive untagged packet and forward to un-tag port. received packet will forward to destination port without modification. (2). receive tagged packet and forward to un-tag port. the DM9103 will remove the tag from the packet and recalculate crc before sending it out. (3). receive untagged packet and forward to tag port. the DM9103 will insert the pvid tag when an untagged packet enters the port, and recalculate crc before delivering it. (4). receive tagged packet and forward to tag port. received packet will forward to destination port without modification. 9.2.14 priority support DM9103 3-port switch with pciinterface preliminary datasheet 71 DM9103-ds-p02 september 26, 2007 the DM9103 supports quality of service (qos) mechanism for multimedia communication such as voip and video conferencing. the DM9103 provides three priority classifications: port-based, 802.1p-based and diffserv-based priority. see next section for more detail. the DM9103 offers four level queues for transmit on per-port based. the DM9103 provides two packet scheduling algorithms: weighted fair queuing and strict priority queuing. weighted fair queuing (wfq) based on their priority and queue weight. queues with larger weights get more service than smaller. this mechanism can get highly efficient bandwidth and smooth the traffic. strict priority queuing (spq) based on priority only. the packet on the highest priority queue is transmitted first. the next highest-priority queue is work until last queue empties, and so on. this feature can be set in bit 29 of register cr18. 9.2.14.1 port-based priority port based priority is the simplest scheme and as default. each port has a 2-bit priority value as index for splitting ingress packets to the corresponding transmit queue. this value can be set in bit 24 and 25 of register cr18. 9.2.14.2 802.1p-based priority 802.1p priority can be disabled by bit 26 of register cr18, it is enabled by default. the DM9103 extracts 3-bit priority field from received packet with 802.1p vlan tag, and maps this field against vlan priority map register cr23 to determine which transmit queue is designated. the vlan priority map is programmable. 9.2.14.3 diffserv-based priority diffserv based priority uses the most significant 6-bit of the tos field in standard ipv4 header, and maps this field against tos priority map registers (c0h~cfh) to determine which transmit queue is designated. the tos priority map is programmable too. in addition, user can only refer to most significant 3-bit of the tos field optionally, see bit 15 of register cr16. DM9103 3-port switch with pciinterface 72 preliminary datasheet DM9103-ds-p02 september 26, 2007 9.3 mii interface 9.3.1 mii data interface the DM9103 port 2 provides a media independent interface (mii) as defined in the ieee 802.3u standard (clause 22). the mii consists of a nibble wide receive data bus, a nibble wide transmit data bus, and control signals to facilitate data transfers between the DM9103 port 2 and external device (a phy or a mac in reverse mii). ? txd2 (transmit data) is a nibble (4 bits) of data that are driven by the DM9103 synchronously with respect to txc2. for each txc2 period, which txe2 is asserted, txd2 (3:0) are accepted for transmission by the external device. ? txc2 (transmit clock) from the external device is a continuous clock that provides the timing reference for the transfer of the txe2, txd2. the DM9103 can drive 25mhz clock if it is configured to reversed mii mode. ? txe2 (transmit enable) from the DM9103 port 2 mac indicates that nibbles are being presented on the mii for transmission to the external device. ? rxd2 (receive data) is a nibble (4 bits) of data that are sampled by the DM9103 port 2 mac synchronously with respect to rxc2. for each rxc2 period which rxdv2 is asserted, rxd2 (3:0) are transferred from the external device to the DM9103 port 2 mac reconciliation sublayer. ? rxc2 (receive clock) from external device to the DM9103 port 2 mac reconciliation sublayer is a continuous clock that provides the timing reference for the transfer of the rxdv2, rxd2, and rxer2 signals. ? rxdv2 (receive data valid) input from the external device to indicates that the external device is presenting recovered and decoded nibbles to the DM9103 port 2 mac reconciliation sublayer. to interpret a receive frame correctly by the reconciliation sublayer, rx dv2 must encompass the frame, starting no later than the start-of-frame delimiter and excluding any end-stream delimiter. ? rxer2 (receive error) input from the external device is synchronously with respect to rxc2. rxer2 will be asserted for 1 or more clock periods to indicate to the reconciliation sublayer that an error was detected somewhere in the frame being transmitted from the external device to the DM9103 port 2 mac. ? crs2 (carrier sense) is asserted by the external device when either the transmit or receive medium is non-idle, and de-asserted by the external device when the transmit and receive medium are idle. the crs2 can also in output mode when the DM9103 port 2 is configured to reversed mii mode. ? col2 (collision detection) is asserted by the external device, when both the transmit and receive medium is non-idle, and de-asserted by the external device when the either transmit or receive medium are idle. the col2 can also in output mode when the DM9103 port 2 is configured to reversed mii mode. 9.3.2 mii serial management the mii serial management interface consists of a data interface, basic register set in DM9103 port 0 and 1, and a serial management interface to the register set. through this in terface it is possible to control and configure multiple phy devices, include internal two ports, get status and error information, and determine the type and capabilities of the attached phy device(s). the DM9103 default is polling 3 ports basic registers 0,1,4, and 5 to get the link, duplex, and speed status automatically. alternatively, the DM9103 can be programmed to read or write any registers of 3 ports by section 6.8~11 csr b,c,d,and e. the DM9103 management functions correspond to mii specification for ieee 802.3u-1995 (clause 22) for registers 0 through 6 with vendor-specific registers 16,17, 18, 21, 22, 23 and 24~27. in read/write operation, the management data frame is 64-bits long and starts with 32 contiguous logic one bits (preamble) synchronization clock cycles on mdc. the start of frame delimiter (sfd) is indicated by a <01> pattern followed by the operation code (op):<10> indicates read operation and <01> indicates write operation. for read operation, a 2-bit turnaround (ta) filing between register address field and data field is provided for mdio to avoid contention. following the turnaround time, 16-bit data is read from or written onto management registers. DM9103 3-port switch with pciinterface preliminary datasheet 73 DM9103-ds-p02 september 26, 2007 9.3.3 serial management interface the serial control interface uses a simple two-wired serial interface to obtain and control the status of the physical layer through the mii interface. the serial control interface consists of mdc (management data clock), and mdi/o (management data input/output) signals. the mdio pin is bi-directional and may be shared by up to 32 devices. 9.3.4 management interface - read frame structure 32 "1"s 0 1 1 0 a4 a3 a0 r4 r3 r0 z 0 idle preamble sfd op code phy address register address turn around data idle read write mdc mdio read d15 d14 d1 d0 // // 9.3.5 management interface - write frame structure 32 "1"s 0 1 1 0 a4 a3 a0 r4 r3 r0 1 0 d15 d14 d1 d0 idle preamble sfd op code phy address register address turn around data idle write mdc mdio write DM9103 3-port switch with pciinterface 74 preliminary datasheet DM9103-ds-p02 september 26, 2007 9.4 internal phy functions 9.4.1 100base-tx operation the transmitter section contains the following functional blocks: - 4b5b encoder - scrambler - parallel to serial converter - nrz to nrzi converter - nrzi to mlt-3 - mlt-3 driver 9.4.1.1 4b5b encoder the 4b5b encoder converts 4-bit (4b) nibble data generated by the mac reconciliation layer into a 5-bit (5b) code group for transmission, see reference table 1. this conversion is required for control and packet data to be combined in code groups. the 4b5b encoder substitutes the first 8 bits of the mac preamble with a j/k code-group pair (11000 10001) upon transmit. the 4b5b encoder continues to replace subsequent 4b preamble and data nibbles with corresponding 5b code-groups. at the end of the transmit packet, upon the deassertion of the transmit enable signal from the mac reconciliation layer, the 4b5b encoder injects the t/r code-group pair (01101 00111) indicating the end of frame. after the t/r code-group pair, the 4b5b encoder continuously injects idles into the transmit data stream until transmit enable is asserted and the next transmit packet is detected. 9.4.1.2 scrambler the scrambler is required to control the radiated emissions (emi) by spreading the transmit energy across the frequency spectrum at the media connector and on the twisted pair cable in 100base-tx operation. by scrambling the data, the total energy presented to the cable is randomly distributed over a wide frequency range. without the scrambler, energy levels on the cable could peak beyond fcc limitations at frequencies related to the repeated 5b sequences, like the continuous transmission of idle symbols. the scrambler outp ut is combined with the nrz 5b data from the code-group encoder via an xor logic function. the result is a scrambled data stream with sufficient randomization to decrease radiated emissions at critical frequencies. 9.4.1.3 parallel to serial converter the parallel to serial conv erter receives parallel 5b scrambled data from the scrambler, and serializes it (converts it from a parallel to a serial data stream). the serialized data stream is then presented to the nrz to nrzi encoder block 9.4.1.4 nrz to nrzi encoder after the transmit data stream has been scrambled and serialized, the data must be nrzi encoded for compatibility with the tp-p md standard, for 100base -tx transmission over category-5 unshielded twisted pair cable. 9.4.1.5 mlt-3 converter the mlt-3 conversion is accomplished by converting the data stream output, from the nrzi encoder into two binary data streams, with alternately phased logic one event. 9.4.1.6 mlt-3 driver the two binary data streams created at the mlt-3 converter are fed to the twisted pair output driver, which converts these streams to current sources and alternately drives either side of the transmit transformer?s primary winding, resulting in a minimal current mlt-3 signal. DM9103 3-port switch with pciinterface preliminary datasheet 75 DM9103-ds-p02 september 26, 2007 9.4.1.7 4b5b code group symbol meaning 4b code 3210 5b code 43210 0 data 0 0000 11110 1 data 1 0001 01001 2 data 2 0010 10100 3 data 3 0011 10101 4 data 4 0100 01010 5 data 5 0101 01011 6 data 6 0110 01110 7 data 7 0111 01111 8 data 8 1000 10010 9 data 9 1001 10011 a data a 1010 10110 b data b 1011 10111 c data c 1100 11010 d data d 1101 11011 e data e 1110 11100 f data f 1111 11101 i idle undefined 11111 j sfd (1) 0101 11000 k sfd (2) 0101 10001 t esd (1) undefined 01101 r esd (2) undefined 00111 h error undefined 00100 v invalid undefined 00000 v invalid undefined 00001 v invalid undefined 00010 v invalid undefined 00011 v invalid undefined 00101 v invalid undefined 00110 v invalid undefined 01000 v invalid undefined 01100 v invalid undefined 10000 v invalid undefined 11001 table 1 DM9103 3-port switch with pciinterface 76 preliminary datasheet DM9103-ds-p02 september 26, 2007 9.4.2 100base-tx receiver the 100base-tx receiver contains several function blocks that convert the scrambled 125mb/s serial data to synchronous 4-bit nibble data. the receive section contains the following functional blocks: - signal detect - digital adaptive equalization - mlt-3 to binary decoder - clock recovery module - nrzi to nrz decoder - serial to parallel - descrambler - code group alignment - 4b5b decoder 9.4.2.1 signal detect the signal detect function meets the specifications mandated by the ansi xt12 tp-pmd 100base-tx standards for both voltage thresholds and timing parameters. 9.4.2.2 adaptive equalization when transmitting data over copper twisted pair cable at high speed, attenuation based on frequency becomes a concern. in high speed twisted pair signaling, the frequency content of the transmitted signal can vary greatly during normal operation based on the randomness of the scrambled data stream. this variation in signal attenuation, caused by frequency variations, must be compensated for to ensure the integrity of the received data. in order to ensure quality transmission when employing mlt-3 encoding, the compensation must be able to adapt to various cable lengths and cable types depending on the installed environment. the selection of long cable lengths for a given implementation requires significant compensation, which will be over-killed in a situation that includes shorter, less attenuating cable lengths. conversely, the selection of short or intermediate cable lengths requiring less compensation will cause serious under-compensation for longer length cables. therefore, the compensation or equalization must be adaptive to ensure proper conditioning of the received signal independent of the cable length. 9.4.2.3 mlt-3 to nrzi decoder the DM9103 decodes the mlt-3 information from the digital adaptive equalizer into nrzi data. 9.4.2.4 clock recovery module the clock recovery module accepts nrzi data from the mlt-3 to nrzi decoder. the clock recovery module locks onto the data stream and extracts the 125mhz reference clock. the extracted and synchronized clock and data are presented to the nrzi to nrz decoder. 9.4.2.5 nrzi to nrz the transmit data stream is required to be nrzi encoded for compatibility wi th the tp-pmd standard for 100base-tx transmission over category-5 unshielded twisted pair cable. this conversion process must be reversed on the receive end. the nrzi to nrz decoder, receives the nrzi data stream from the clock recovery module and converts it to a nrz data stream to be presented to the serial to parallel conversion block. 9.4.2.6 serial to parallel the serial to parallel converter receives a serial data stream from the nrzi to nrz converter. it converts the data stream to parallel da ta to be presented to the descrambler. 9.4.2.7 descrambler because of the scrambling process requires to control the radiated emissions of transmit data streams, the receiver must descramble the receive data streams. the descrambler receives scrambled parallel data streams from the serial to parallel converter, and it descrambles the data streams, and presents the data streams to the code group alignment block. DM9103 3-port switch with pciinterface preliminary datasheet 77 DM9103-ds-p02 september 26, 2007 9.4.2.8 code group alignment the code group alignment block receives un-aligned 5b data from the descrambler and converts it into 5b code group data. code group alignment occurs after the j/k is detected, and subsequent data is aligned on a fixed boundary. 9.4.2.9 4b5b decoder the 4b5b decoder functions as a look-up table that translates incoming 5b code groups into 4b (nibble) data. when receiving a frame, the first 2 5-bit code groups receive the start-of-frame delimiter (j/k symbols). the j/k symbol pair is stripped and two nibbles of preamble pattern are substituted. the last two code groups are the end-of-frame delimiter (t/r symbols). the t/r symbol pair is also stripped from the nibble, presented to the reconciliation layer. 9.4.3 10base-t operation the 10base-t transceiver is ieee 802.3u compliant. when the DM9103 is operating in 10base-t mode, the coding scheme is manchester. data processed for transmit is presented in nibble format, converted to a serial bit stream, then the manchester encoded. when receiving, the bit stream, encoded by the manchester, is decoded and converted into nibble format. 9.4.4 collision detection for half-duplex operation, a collision is detected when the transmit and receive channels are active simultaneously. collision detection is disabled in full duplex operation. 9.4.5 carrier sense carrier sense (crs) is asserted in half-duplex operation during transmission or reception of data. during full-duplex mode, crs is asserted only during receive operations. 9.4.6 auto-negotiation the objective of auto-negotiation is to provide a means to exchange information between linked devices and to automatically configure both devices to take maximum advantage of their abilities. it is important to note that auto-negotiation does not test the characteristics of the linked segment. the auto-negotiation function provides a means for a device to advertise supported modes of operation to a remote link partner, acknowledge the receipt and understanding of common modes of operation, and to reject un-shared modes of operation. this allows devices on both ends of a segment to establish a link at the best common mode of operation. if more than one common mode exists between the two devices, a mechanism is provided to allow the devices to resolve to a single mode of operation using a predetermined priority resolution function. auto-negotiation also provides a parallel detection function for devices that do not support the auto-negotiation feature. during parallel detection there is no exchange of information of configuration. instead, the receive signal is examined. if it is discovered that the signal matches a technology, which the receiving device supports, a connection will be automatically established using that technology. this allows devices not to support auto-negotiation but support a common mode of operation to establish a link. 9.5 auto mdix hp auto-mdix functional description the DM9103 supports the automatic detect cable connection type, mdi/mdix (straight through/cross over). a manual configuration by register bit for mdi or mdix is still accepted. when set to automatic, the polarity of mdi/mdix controlled timing is generated by a 16-bits lfsr. the switching cycle time is located from 200ms to 420ms. the polarity control is always switch until detect received signal. after selected mdi or mdix, this feature is able to detect the required cable connection type.( straight through or crossed over ) and make correction automatically DM9103 3-port switch with pciinterface 78 preliminary datasheet DM9103-ds-p02 september 26, 2007 rx + /- from DM9103 rx+/- to rj45 tx + /- from DM9103 tx+/- to rj45 * mdi : __________ * mdix : - - - - - - - - - DM9103 3-port switch with pciinterface preliminary datasheet 79 DM9103-ds-p02 september 26, 2007 10. dc and ac electrical characteristics 10.1 absolute maximum ratings symbol parameter min. max. unit conditions vcc3 3.3v supply voltage -0.3 3.6 v vcci 1.8v core power supply -0.3 1.95 v avdd3 analog power supply 3.3v -0.3 3.6 v avddi analog power supply 1.8v -0.3 1.95 v v in dc input voltage (vin) -0.5 5.5 v t stg storage temperature range -65 +150 c t c case temperature - +85 c as t a =70 c t a ambient temperature 0 +70 c l t lead temperature (tl,soldering,10 sec.). - +260 c lead-free device 10.2 operating conditions symbol parameter min. max. unit conditions vcc3 3.3v supply voltage 3.135 3.465 v vcci 1.8v core power supply 1.71 1.89 v avdd3 analog power supply 3.3v 3.135 3.465 v avddi analog power supply 1.8v 1.71 1.89 v 100base-tx - 300 ma 3.3v 10base-t tx (100% utilization) - 400 ma 3.3v auto-negotiation - 430 ma 3.3v p d (power dissipation) power down mode - 40 ma 3.3v 10.3 dc electrical characteristics symbol parameter min. typ. max. unit conditions inputs vil input low voltage - - 0.8 v vcond1 vih input high voltage 2.0 - - v vcond1 iil input low leakage current -1 - - ua vin = 0.0v, vcond1 iih input high leakage current - - 1 ua vin = 3.3v, vcond1 outputs vol output low voltage - - 0.4 v iol = 4ma voh output high voltage 2.4 - - v ioh = -4ma receiver vicm rx+/rx- common mode input voltage - 1.8 - v 100 ? termination across transmitter vtd100 100tx+/- differential output voltage 1.9 2.0 2.1 v peak to peak vtd10 10tx+/- differential output voltage 4.4 5 5.6 v peak to peak itd100 100tx+/- differential output current 19 20 21 ma absolute value itd10 10tx+/- differential output current 44 50 56 ma absolute value note: vcond1 = vcc3 = 3.3v, vcci = 1.8v, avdd3 = 3.3v, avddi = 1.8v. DM9103 3-port switch with pciinterface 80 preliminary datasheet DM9103-ds-p02 september 26, 2007 10.3 ac characteristics 10.3.1 pci clock specifications timing 2.0v t5 pci_clk_9103.vsd t1 t2 t3 t4 0.8v symbol parameter min. typ. max. unit conditions t1 pci_clk high time 12 - - ns - t2 pci_clk low time 12 - - ns - t3 pci_clk rising time - - 4 ns - t4 pci_clk falling time - - 4 ns - t5 cycle time 25 30 - ns - 10.3.2 power on reset timing pwrst# strap pins t2 t1 pwrst#.vsd symbol parameter min. typ. max. unit conditions t1 pwrst# low period 1 - - ms - t2 strap pin hold time with pwrst# 40 - - ns - DM9103 3-port switch with pciinterface preliminary datasheet 81 DM9103-ds-p02 september 26, 2007 10.3.3 other pci signals timing diagram t1 t2 t3 t4 t5 pci_signal_9103.vcd clk output input 2.5v symbol parameter min. typ. max. unit conditions t1 clk-to-signal valid delay 2 - 13 ns cload = 50 pf t2 float-to-active delay from clk 2 - - ns - t3 active-to-float delay from clk - - 28 ns - t4 input signal valid setup time before clk 7 - - ns - t5 input signal hold time from clk 0 - - ns - DM9103 3-port switch with pciinterface 82 preliminary datasheet DM9103-ds-p02 september 26, 2007 10.3.4 port 2 mii interface transmit timing txc2 txe2 txd2_3~0 t1 t2 miitx_9013.vsd symbol parameter min. typ. max. unit t1 txe2,txd2_3~0 setup time 32 ns t2 txe2,txd2_3~0 hold time 8 ns 10.3.5 port 2 mii interface receive timing rxc2 rxer2,rxdv2 rxd2_3~0 t1 t2 miirx_9013.vsd symbol parameter min. typ. max. unit t1 rxer2, rxdv2,rxd2_3~0 setup time 5 ns t2 rxer2, rxdv2,rxd2_3~0 hold time 5 ns DM9103 3-port switch with pciinterface preliminary datasheet 83 DM9103-ds-p02 september 26, 2007 10.3.6 mii management interface timing mdc mdio (drived by DM9103) t1 t2 t3 t4 t5 mdio (drived by exetrnal mii) mdio_9103.vsd symbol parameter min. typ. max. unit t1 mdc frequency 0.52 mhz t2 mdio by DM9103 setup time 955 ns t3 mdio by DM9103 hold time 960 ns t4 mdio by external mii setup time 40 ns t5 mdio by external mii hold time 40 ns DM9103 3-port switch with pciinterface 84 preliminary datasheet DM9103-ds-p02 september 26, 2007 10.3.7 eeprom timing eecs eeck eedo t1 t2 t3 t4 t5 t6 t7 eedi eeprom_9103.vcd symbol parameter min. typ. max. unit t1 eecs setup time 480 ns t2 eecs hold time 2080 ns t3 eeck frequency 0.38 mhz t4 eedo setup time 460 t5 eedo hold time 2100 ns t6 eedi setup time 8 ns t7 eedi hold time 8 ns DM9103 3-port switch with pciinterface preliminary datasheet 85 DM9103-ds-p02 september 26, 2007 11. application circuit DM9103e_evb_board 2.1 main_chip b 13 tuesday , december 19, 2006 tit le size document number rev date: sheet of dvdd_18v avdd_18v dvdd_33v dvdd_33v dvdd_33v avdd_33v avdd_18v avdd_33v dvdd_33v dvdd_33v dvdd_18v dvdd_33v avdd_18v dvdd_18v avdd_33v dvdd_33v dvdd_33v vcntl vref rxd2_3 rxd2_[0..3] rxd2_0 rxd2_1 rxd2_2 txd2_2 txd2_[0..3] txd2_1 txd2_0 txd2_3 rxdv2 rxc2 crs2 col2 rxer2 txe2 txc 2 mdi o mdc tx0+ tx0- rx0+ rx0- tx1+ rx1+ rx1- tx1- lnk0_led spd0_led fdx0_led lnk1_led spd1_led fdx1_led eedi eecs eeck eedo pwrst# test2 txe2 lnk0_led ad16 test2 rxd2_2 rx0+ cbe0# eedo ad26 txc 2 ad21 fdx1_led gnt# x1 ad5 ad29 int# serr# ad23 eeck eecs spd1_led wol pme# ad3 ad15 lnk1_led cbe3# rx0- rst# rxc2 ad27 rxd2_3 irdy# ad24 stop# ad22 rxdv2 ad12 rxd2_0 pwrst# ad9 rx1- ad2 ad28 req# cbe1# ad6 md i o fdx0_led ad31 isolate# trdy# idsel par ad10 md c crs2 vcntl ad20 txd2_1 txd2_0 cbe2# eedi x2 ad13 ad1 ad25 vref ad30 perr# devsel# ad17 ad8 tx0- rx1+ ad11 ad7 ad18 pciclk sclk tx1+ col2 tx1- tx0+ ad0 rxd2_1 rxer2 ad19 ad4 ad14 txd2_3 spd0_led txd2_2 mdi o txd2_1 eecs txe2 eeck txd2_0 txd2_2 txd2_3 eedo pme# wol int# rst# pciclk isolate# gnt# req# cbe3# idsel cbe2# frame# frame# irdy# devsel# stop# tr dy # par perr# cbe1# serr# cbe0# ad16 ad0 ad5 ad2 ad15 ad26 ad6 ad1 ad17 ad8 ad11 ad9 ad4 ad22 ad3 ad27 ad7 ad23 ad31 ad30 ad10 ad21 ad29 ad12 ad19 ad13 ad24 ad25 ad28 ad20 ad18 ad14 ad[00..31] sclk rst# pwrst# c6 0.1uf c21 0.1uf j3 header_3 1 2 3 c10 220uf c22 0.1uf c19 0.1uf l2 f.b/120/so805 c24 22pf c7 0.1uf l1 f.b/120/so805 c11 0.1uf c12 0.1uf c8 0.1uf c13 0.1uf u3 reset_ic_(ap1701dw) 1 2 3 1 2 3 c15 0.1uf c1 220uf u1 126 127 128 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 87 88 89 90 91 92 93 94 95 96 97 98 86 100 101 102 103 104 105 106 107 108 109 110 116 111 112 113 114 115 117 118 119 120 121 122 123 124 125 99 ad26 ad25 ad24 cbe3# idsel ad23 dvdd33 ad22 ad21 ad20 ad19 ad18 ad17 gnd ad16 cbe2# frame# irdy# trdy# devsel# dvdd33 stop# perr# gnd serr# par dvdd18 cbe1# ad15 gnd ad14 ad13 ad12 ad11 dvdd33 ad10 ad9 gnd cbe0# ad8 ad7 ad6 dvdd33 ad5 ad4 ad3 ad2 gnd ad1 ad0 dvdd33 eedi eedo eeck eecs pwrst# gnd md c md i o dvdd18 txd2_3 txd2_2 txd2_1 txd2_0 vcc3 txe2 txc 2 crs2 col2 rxer2 rxc2 gnd rxdv2 rxd2_3 rxd2_2 rxd2_1 rxd2_0 dvdd33 test1 test2 test3 avdd18 tx1+ tx1- agnd agnd rx1+ rx1- avdd18 tx0+ tx0- agnd agnd rx0+ rx0- avdd33 bgres bgresg vcntl vref avdd33 dvdd33 x1 x2 gnd lnk1_led spd1_led fdx1_led lnk0_led spd0_led fdx0_led wol sclk pme# int# rst# pciclk isolate# gnt# req# ad31 dvdd18 ad30 ad29 ad28 ad27 gnd avdd33 c9 0.1uf y1 25mhz/49us d1 1n4148 a c j7 test_poi n t 1 j8 test_poi n t 1 c3 0.1uf j9 test_poi n t 1 r11 10k q1 2sb1386 b e c c27 10uf c17 0.1uf r10 1.4k/1% c20 0.1uf c25 22pf j6 jumper 1 2 u2 93lc46 1 2 3 4 5 6 7 8 cs sk di do gnd org dc vcc c4 0.1uf j1 jumper 1 2 r8 nc(4.7k) r9 4.7k r1 4.7k r5 4.7k j2 jumper 1 2 r6 4.7k j4 jumper 1 2 r2 4.7k j5 jumper 1 2 r7 4.7k r3 4.7k r4 4.7k c26 0.1uf c18 220uf c16 0.1uf c5 0.1uf c23 0.1uf c2 0.1uf l3 f.b/120/so805 c14 220uf sd[00..31] rxd2_[0..3] rxdv2 rxc2 crs2 col2 rxer2 txd2_[0..3] txe2 txc 2 md c md i o pme# tx0+ tx0- rx0+ rx0- tx1+ tx1- rx1+ rx1- lnk0_led spd0_led fdx0_led lnk1_led spd1_led fdx1_led wol int# rst# pciclk isolate# gnt# req# cbe3# idsel cbe2# frame# cbe0# cbe1# par serr# perr# stop# devsel# trdy# irdy# pci interface mii interface tp / led interface eeprom DM9103e for pci interface davicom semiconductor inc. DM9103 3-port switch with pciinterface 86 preliminary datasheet DM9103-ds-p02 september 26, 2007 DM9103e_evb_board 2.1 connect_and_power b 23 tuesday , december 19, 2006 tit le size document number rev date: sheet of dvdd_5v dvdd_33v pci_5v_2 pci_5v_1 dvdd_5v pci_33v dvdd_33v dvdd_33v mii_5v pci_5v_1 pci_33v pci_5v_2 txd2_0 rxer2 mii_5v txd2_1 rxd2_3 txc2 dgnd rxd2_0 dvdd_33v rxd2_2 txd2_3 mdio dgnd rxd2_1 wol rxc2 txd2_2 dvdd_33v dvdd_33v dgnd col2 crs2 mii_5v rxdv2 txd 2_1 rxd2_[0..3] rxdv2 rxd2_2 col2 txd2_[0..3] rxd2_3 txc 2 md i o txd 2_0 rxd2_1 rxer2 txd 2_3 md c rxc2 rxd2_0 txe2 txd 2_2 crs2 mdc txe2 stop# rst# ad8 pme# cbe1# par ad19 ad4 ad22 ad7 ad12 perr# ad20 trdy# ad15 ad25 pciclk ad31 ad6 ad10 ad[00..31] ad5 ad3 ad0 irdy# devsel# wol ad18 ad9 ad29 ad11 ad14 ad21 ad17 cbe0# frame# req# ad26 ad2 idsel ad16 ad30 isolate# cbe2# int# ad27 ad1 ad24 cbe3# ad23 serr# gnt# ad28 ad13 ad0 ad30 ad19 ad6 cbe2# ad11 ad4 ad24 pciclk ad8 ad21 par ad2 idsel ad28 ad7 ad5 gnt# ad9 ad15 ad29 perr# ad16 ad1 ad14 3.3vaux req# ad13 irdy# cbe3# ad22 ad3 ad27 frame# ad31 ad26 ad12 ad17 int# stop# ad23 ad20 ad10 trdy# pci_pme# ad18 ad25 serr# rst# cbe1# cbe0# devsel# wol +5vsb 3.3vaux pci_pme# pme# isolate# r13 0 d2 1n5819 a c cn1 pciconn pcicon b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25 b26 b27 b28 b29 b30 b31 b32 b33 b34 b35 b36 b37 b38 b39 b40 b41 b42 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 a32 a33 a34 a35 a36 a37 a38 a39 a40 a41 a42 a43 a44 a45 a46 a47 a48 a49 a50 a51 a52 a53 a54 a55 a56 a57 a58 a59 a60 a61 a62 b43 b44 b45 b46 b47 b48 b49 b52 b53 b54 b55 b56 b57 b58 b59 b60 b61 b62 b50 b51 -12v tc k ground td 0 5v 5v intb* intd* prsnt1* nc prsnt2* ground ground nc ground clk ground req* 5v ad31 ad29 ground ad27 ad25 3.3v c/be3* ad23 ground ad21 ad19 3.3v ad17 c/be2* ground irdy* 3.3v devsel* ground lock* perr* 3.3v serr* tr st* 12v tms td i 5v inta* intc* 5v nc 5v nc ground ground 3.3vaux rst* 5v gnt* ground pme# ad30 3.3v ad28 ad26 ground ad24 idsel 3.3v ad22 ad20 ground ad18 ad16 3.3v frame* ground trdy* ground stop* 3.3v sdone sbo* ground par ad15 3.3v ad13 ad11 ground ad9 nc nc c/be0* 3.3v ad6 ad4 ground ad2 ad0 5v req64* 5v 5v 3.3v c/be1 ad14 ground ad12 ad10 ground ad8 ad7 3.3v ad5 ad3 ground ad1 5v ack64* 5v 5v nc nc jp1 header_3/2.5mm cn3p2.5mm 1 2 3 r12 0 d3 1n5819 a c l4 f.b/120/so803 d12 1n5819 a c d4 1n5819 a c l5 f.b/120/so803 d5 1n5819 a c jp2 header_16x2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 c29 0.1uf u4 ap1117-3.3v g o i 4 gnd out in out c28 220uf md i o txc 2 txd 2_[ 0.. 3] rxd2_[0..3] txe2 rxdv2 rxc2 crs2 col2 rxer2 md c irdy# trdy# cbe0# devsel# perr# par frame# cbe2# serr# cbe1# sd[00..31] stop# cbe3# wol pme# int# rst# pciclk isolate# gnt# req# idsel mii interface pci interface solder component (meet pci2.2 spec.) option for pc pci bus only davicom semiconductor inc. DM9103 3-port switch with pciinterface preliminary datasheet 87 DM9103-ds-p02 september 26, 2007 dm9013e_evb_board 2.1 rj45_and_led a 33 tuesday , december 19, 2006 tit le size document number rev date: sheet of avdd_18v avdd_18v dvdd_33v tx1+ rx1- fdx0_led tx1- spd1_led tx0+ lnk0_led rx1+ fdx1_led lnk1_led rx0+ rx0- tx0- spd0_led tx1+ tx1- rx1+ rx1- tx0- rx0+ tx0+ lnk0_led lnk0_led spd1_led fdx1_led rx0- rj45_link lnk1_led fdx0_led spd0_led rj45_spd spd0_led r23 330 1 2 3 4 5 6 7 8 r15 49.9/1% u5 magcom_hs9024 1 3 5 6 8 9 11 13 14 16 2 7 10 15 4 12 rd- rd+ ct td- td+ tx- tx+ mc t rx- rx+ nc nc nc nc nc nc jp4 rj-45 1 2 3 4 5 6 7 8 d11 led a c c38 0.1uf d10 led a c u7 magcom_hs9016 1 3 5 6 8 9 11 13 14 16 2 7 10 15 4 12 rd- rd+ ct td - td + tx+ tx- mc t rx+ rx- nc nc nc nc nc nc r16 49.9/1% r26 49.9/1% r14 49.9/1% d8 led a c c30 0.01uf/2kv d6 led a c d7 led a c r27 49.9/1% c31 0.1uf r22 512 u6a 74hc04 1 2 r25 49.9/1% c33 0.1uf r18 75/1% c35 0.01uf/2kv r30 75/1% u6b 74hc04 3 4 c39 0.1uf r28 49.9/1% d9 led a c r20 75/1% r31 75/1% r19 75/1% c34 0.1uf c36 0.1uf r21 512 jp3 rj-45_led 14 13 16 15 1 2 3 4 5 6 7 led1+ led1- led2+ 8 led2- c37 0.1uf c32 0.1uf r17 49.9/1% r29 75/1% r24 330 1 2 3 4 5 6 7 8 rx0+ tx0+ rx1- tx1+ tx1- rx0- tx0- rx1+ lnk0_led spd0_led fdx0_led lnk1_led spd1_led fdx1_led tp / led interface davicom semiconductor inc. DM9103 3-port switch with pciinterface 88 preliminary datasheet DM9103-ds-p02 september 26, 2007 12. package information 128 pins lqfp package outline information: dimension in mm dimension in inch symbol min nom max min nom max a - - 1.60 - - 0.063 a 1 0.05 - - 0.002 - - a 2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.13 0.18 0.23 0.005 0.007 0.009 b 1 0.13 0.16 0.19 0.005 0.006 0.007 c 0.09 - 0.20 0.004 - 0.008 c 1 0.09 - 0.16 0.004 - 0.006 d 15.85 16.00 16.15 0.624 0.630 0.636 d 1 13.90 14.00 14.10 0.547 0.551 0.555 e 15.85 16.00 16.15 0.624 0.630 0.636 e 1 13.90 14.00 14.10 0.547 0.551 0.555 e 0.40 bsc 0.016 bsc l 0.45 0.60 0.75 0.018 0.024 0.030 l 1 1.00 ref 0.039 ref r 1 0.08 - - 0.003 - - r 2 0.08 - 0.20 0.003 - 0.008 s 0.20 - - 0.008 - - 0 o 3.5 o 7 o 0 o 3.5 o 7 o 1 0 o - - 0 o - - 2 12 o typ 12 o typ 3 12 o typ 12 o typ 1. dimension d 1 and e 1 do not include resin fin. 2. all dimensions are base on metric system. 3. general appearance spec should base on its final visual inspection spec. DM9103 3-port switch with pciinterface preliminary datasheet 89 DM9103-ds-p02 september 26, 2007 13. ordering information part number pin count package DM9103ep 128 lqfp (pb-free) disclaimer the information appearing in this publication is believed to be accurate. integrated circuits sold by davicom semiconductor are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. davicom makes no warranty, express, statutory, implied or by description regarding the information in this publication or regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. further, davicom makes no warranty of merchantability or fitness for any purpose. davicom reserves the right to halt production or alter the specifications and prices at any time without notice. accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. products described herein are intended for use in normal commercial applications. applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by davicom for such applications. please note that application circuits illustrate d in this document are for reference purposes only. davicom?s terms and conditions printed on the order acknowledgment govern all sales by davicom. davicom will not be bound by any terms inconsistent with these unless davicom agrees otherwise in writing. acceptance of the buyer?s orders shall be based on these terms. company overview davicom semiconductor inc. develops and manufactures integrated circuits for integration into data communication products. our mission is to design and produce ic products that are the industry?s best value for data, audio, video, and internet/intranet applications. to achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while still delivering products that meet their cost requirements. products we offer only products that satisfy high performance requirements and which are compatible with major hardware and software standards. our currently available and soon to be released products are based on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and ethernet networking standards. contact windows for additional information about davicom products, contact the sales department at: headquarters hsin-chu office: no.6 li-hsin rd. vi, science-based park, hsin-chu city, taiwan, r.o.c. tel: + 886-3-5798797 fax: + 886-3-5646929 mail: sales@davicom.com.tw http: http://www.davicom.com.tw warning conditions beyond those listed for the absolute maximum may destroy or damage the products. in addition, conditions for sustai ned periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function . |
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