View CW001102_863252.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

db08-000123-01 september 2001 1 of 34 rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. CW001102 arm966e-s microprocessor core preliminary datasheet the CW001102 arm966e-s core integrates the arm9e-s 32-bit processor, an instruction ram, a data ram, a write buffer, and an ahb bus interface. the CW001102 supports both the 32-bit arm and 16-bit thumb instruction sets, allowing you to trade off between high performance and high code density. additionally the CW001102 supports the arm9e instruction extensions. it provides an enhanced multiplier for increased dsp performance. the CW001102 core is developed using lsi logics g12 -l low-power process. figure 1 CW001102 block diagram ahb bus interface unit and write buffer instruction sram dout addr din data sram dout addr din system control coprocessor (cp15) external coprocessor interface ia arm9e-s instr rdata da wdata system controller etm interface core
2 of 34 CW001102 arm966e-s microprocessor core db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. the ahb bus interface eases connection to cached and sram-based memory systems. the CW001102 supports the arm debug architecture and includes logic to assist in both hardware and software debug. it supports non-stopping hardware debug, which allows critical exception handlers to execute while debugging the system. the CW001102 provides real-time trace and supports external coprocessors. features this section lists the key features of the CW001102 microprocessor core: ? arm9e-s processor core ? instruction and data rams with independent sizes up to 512 kbytes ? dma interface to data ram ? arm advanced high-performance bus (ahb) interface unit with write buffer 16-word write buffer depth at up to four addresses burst transfer generation support for split transactions ? external coprocessor interface ? system controller arbitrates between instruction and data memories and ahb ? optional embedded trace module (etm) provides real-time trace capability ? g12-l low-power process ? 0.18-micron drawn gate length (0.13 effective channel length) ? system clock operates at 125 mhz tested under worst-case conditions, 1.62 v, 115 c
CW001102 arm966e-s microprocessor core 3 of 34 db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. functional description this section brie? describes the main functional blocks of the CW001102. arm9e-s processor core the arm9e-s processor core has a harvard bus architecture with separate instruction and data interfaces. this design allows concurrent instruction and data accesses, and greatly reduces the cycles per instruction of the processor. for optimal performance, single cycle memory accesses for both interfaces are required, although the core can be stalled for non-sequential accesses, or slower memory systems. the processor is implemented using a 5-stage pipeline: ? instruction fetch (f) ? instruction decode (d) ? execute (e) ? data memory access (m) ? register write (w) arm implementations are fully interlocked, so that software functions identically across different implementations without concern for pipeline effects. system controller the system controller oversees the interactions between the instruction ram, data ram, and the bus interface unit. it controls internal arbitration between the blocks and stalls the appropriate blocks when required. cp15 system control coprocessor the processor core uses a set of registers in the cp15 coprocessor to control the functionality of the rams and the write buffer. these registers are accessed using the coprocessor instructions mcr and mrc.
4 of 34 CW001102 arm966e-s microprocessor core db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. address decoders the address decoders determine whether a memory request accesses the internal ram or the ahb interface. the address decoders provide a hit/miss indication to the system controller, which then either stalls the core if an ahb read or unbuffered write access is required or allows execution to continue if the access hits the ram or is a buffered write. instruction and data rams the CW001102 incorporates internal instruction and data memories to allow high-speed operation without incurring the performance penalties of accessing the system bus. typically, the CW001102 offers lower power solutions than cached alternatives because memory is segmented to conserve power. the instruction and data rams each consist of blocks of asic library compiled ram. logically, the ram sizes can be of any size up to 64 mbytes, but the practical limit is approximately 512 kbytes for the g12 technology. the instruction and data memories can have unique sizes. dma interface the direct memory access (dma) interface provides an external device with direct access to the CW001102 data ram. when a single-port data ram is used, the dma interface stalls the CW001102 microprocessor core during the dma transfer. when a dual-port data ram is used, the dma interface does not stall the CW001102 during the dma transfer. ahb interface unit and write buffer the ahb (advanced high-performance bus) is a new generation of amba bus, which meets the requirements of high-performance synthesizable designs. the ahb interface unit arbitrates between external bus transaction sources within the CW001102. it stalls all other accesses until the current request completes. the ahb interface unit supports the following types of transactions: burst transfers, split transactions, single-cycle bus master handovers, single clock edge operations, and non-3-state implementations. the write buffer is a 12-entry fifo. it increases system performance.
CW001102 arm966e-s microprocessor core 5 of 34 db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. external coprocessor interface the CW001102 supports the connection of coprocessors via the external coprocessor interface. all types of arm coprocessor instructions are supported. coprocessors determine the instructions they need to execute using a pipeline follower in the coprocessor. jtag and debug port the CW001102 debug interface is based on ieee std. 1149.1-1990. it allows the processor core to be stopped on a given instruction fetch (breakpoint), data access (watchpoint), or external debug request. the jtag-style serial interface allows instructions to be serially inserted into the pipeline of the core without using the external data bus. embedded trace module interface this interface connects to an external embedded trace module (etm). the etm provides a high-speed port for tracing of the processor core in real time. enhanced instruction set summary ta b l e 1 lists the instruction enhancements made to the arm9e-s instruction set. the arm9e extensions improve the arm architectures performance in signal processing algorithms. table 1 arm9e instruction set summary instruction description instruction description clz count leading zeros qadd saturating add qdadd saturated double rn and saturated add qdsub saturated double rn and saturated subtract qsub saturating subtract smlaxy signed integer multiply-accumulate smlalxy signed multiply-accumulate smlawy signed integer multiply-accumulate smulxy signed integer multiply smulwy signed integer multiply
6 of 34 CW001102 arm966e-s microprocessor core db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. signal descriptions this section lists the signals that make up the external interface to the CW001102. in the descriptions that follow, the verb assert means to drive true or active. the verb deassert means to drive false or inactive. ahb interface haddr[31:0] address bus out output the CW001102 drives the ahb address on haddr[31:0]. hburst[2:0] burst type output this output indicates if the transfer forms part of a burst. both 4-beat and 8-beat bursts are supported, where a beat is a clock tick. the CW001102 generates only single word transfers or bursts of unspeci?d, 4, or 8 word lengths to drain store multiples (stms) posted in the write buffer. hbusreq bus request output hbusreq is a signal from the CW001102 core to the bus arbiter. a high in this output indicates that the core requires the bus. hgrant bus grant input a high on this signal indicates the CW001102 core is currently the highest priority master. ownership of the address/control signals changes at the end of a transfer when hready is high. a master gets access to the bus when both hready and hgrant are high. hburst[2:0] burst type description 000 single single transfer 001 incr incrementing burst of unspeci?d length 010 wrap4 4-beat wrapping burst 011 incr4 4-beat incrementing burst 100 wrap8 8-beat wrapping burst 101 incr8 8-beat incrementing burst 110 wrap16 16-beat wrapping burst 111 incr16 16-beat incrementing burst
CW001102 arm966e-s microprocessor core 7 of 34 db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. hlock locked transfer output when hlock is high, the arm9e-s core requires locked access to the bus, and no other masters should be granted the bus until hlock is low. hlock is asserted when the CW001102 is executing the swap instruction. hprot[3:0] protection control output this output provides additional information about a bus access. hprot[3:0] are primarily intended for use by any module that implements some level of protection. the signals indicate whether the transfer is an opcode fetch or data access, as well as if the transfer is a supervisor mode access or user mode access. note that for the CW001102, hprot3 is forced low (non-cacheable). hrdata[31:0] read data bus input this bus transfers data from the bus slaves to the CW001102 core during read operations. the CW001102 core has a 32-bit wide data bus. the width can be easily extended outside the core to allow for higher bandwidth operation. hready transfer done in input when high, the hready signal indicates the transfer on the bus has ?ished. drive this signal low to extend a transfer. note: slaves on the bus require hready to be both an input and an output. hresetn reset input this input is the active-low system reset. hprot3 cacheable hprot2 bufferable hprot1 supervisor hprot0 data/opcode description 0 opcode fetch 1 data access 0 user access 1 supervisor access 0 not bufferable 1 bufferable 0 not cacheable
8 of 34 CW001102 arm966e-s microprocessor core db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. hresp[1:0] transfer response in input hresp[1:0] provide additional information on the status of a transfer. when a slave must insert a number of wait states prior to decoding what response is to be given, then it must drive the response to okay. hsize[2:0] transfer size output this output indicates the size of the transfer, which is typically byte (8 bits), halfword (16 bits), or word (32 bits). the bus protocol allows for transfer sizes up to 1024 bits. hresp[1:0] transfer response description 00 okay when hready is high, the transfer has completed. 01 error this response shows an error has occurred. the error condition needs to be signaled to the bus mas- ter to make it aware that the transfer is unsuccessful. a 2-cycle response is required for an error condition. 10 retry the retry response shows the transfer has not yet completed, so the bus master needs to retry the transfer. the master continues to retry the transfer until the transfer completes. a 2-cycle retry response is required. 11 split the split response indicates the transfer has not completed successfully. the bus master must retry the transfer when it is next granted access to the bus. the slave requests access to the bus on behalf of the master when the transfer can complete. a 2-cycle split response is required. hsize[2:0] transfer size description 000 8 bits byte 001 16 bits halfword 010 32 bits word 011 64 bits 2-word line 100 128 bits 4-word line 101 256 bits 8-word line 110 512 bits 111 1024 bits
CW001102 arm966e-s microprocessor core 9 of 34 db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. htrans[1:0] transfer type out output this output indicates the type of the current transfer. hwdata[31:0] write data bus output this bus transfers data from the master to the bus slaves during write operations. the width easily can be extended external to the core to allow for higher bandwidth operation. hwrite transfer direction out output when hwrite is high, the transfer is a write. when hwrite is low, the transfer is a read. htrans[1:0] transfer type description 00 idle no data transfer required. 01 busy used to insert an idle cycle in the middle of a burst of transfers. 10 non-sequential indicates ?st transfer of a burst or single transfer. 11 sequential the control information is identical to the previous transfer. the address is equal to the address of the previous transfer plus the size (in bytes). for wrap- ping bursts, the address of the transfer wraps at the address boundary equal to the size (in bytes) multiplied by the number of beats in the transfer (either 4, 8, or 16).
10 of 34 CW001102 arm966e-s microprocessor core db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. coprocessor interface chsde[1:0] coprocessor handshake decode input these inputs are the handshake signals from the decode stage of the coprocessors pipeline follower. chsex[1:0] coprocessor handshake execute input these inputs are the handshake signals from the execute stage of the coprocessors pipeline follower. cpclken coprocessor clock enable output this clock enable controls the timing of the coprocessor interface. it is used in conjunction with clk to effectively run the coprocessor at a higher frequency than the data bus. cpdin[31:0] coprocessor data in input this 32-bit bus is the coprocessor data bus for transferring mrc and stc data from the coprocessor to the CW001102. cpdout[31:0] coprocessor data out output this 32-bit bus is the coprocessor data bus for transferring data to the coprocessor. cpinstr[31:0] coprocessor instruction output this 32-bit bus is the coprocessor instruction data bus for transferring instructions to the pipeline follower in the coprocessor. chsde[1:0] encoding 10 absent 00 wait 01 go 11 last chsex[1:0] encoding 10 absent 00 wait 01 go 11 last
CW001102 arm966e-s microprocessor core 11 of 34 db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. cplatecancel coprocessor late cancel output when cplatecancel is high during the ?st memory cycle of a coprocessor instruction execution, the coprocessor instruction must be cancelled without updating any internal state. this signal is asserted only in cycles where the previous instruction accessed memory and a data abort occurred. cppass coprocessor pass output a high on this signal indicates that there is a coprocessor instruction in the execute stage of the pipeline that needs to be executed. cptbit coprocessor interface in thumb state output when cptbit is high, the coprocessor interface is in thumb state (16-bit instructions); otherwise the interface supports 32-bit instruction execution. ncpmreq not coprocessor memory request output when ncpmreq is low on a rising clk edge and cpclken is high, the instruction on cpinstr must enter the coprocessor pipeline followers decode stage, and the instruction previously in the pipeline followers decode stage should enter its execute stage. ncptrans not coprocessor translate output when ncptrans is low, the coprocessor interface is in a non-privileged state. when ncptrans is high, the coprocessor interface is in a privileged state. the coprocessor should sample this signal on every cycle when determining the coprocessor response. instruction ram signals iaddr[23:0] instruction ram address output this 24-bit bus contains the instruction ram address. addressing is performed on word boundaries. ienable word-based instruction chip enable output assertion high of this output indicates the instruction ram data bus is enabled.
12 of 34 CW001102 arm966e-s microprocessor core db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. irdata[31:0] instruction ram read data input data to be read from the instruction ram is placed on this 32-bit bus. iwdata[31:0] instruction ram write data output this 32-bit bus contains write data to the instruction ram. iwe[3:0] byte-based instruction write enable output assertion high of this output enables bytes for writes to the instruction ram. noiram instruction ram present input the CW001102 asserts noiram high to indicate the instruction ram is not present, and thus instruction ram decoding is disabled. a low assertion of noiram indicates instruction ram is present, which enables instruction ram decoding. data ram signals the data ram interface supports both single-port and dual-port rams. when single-port rams are used, the CW001102 stalls during dma transfers. when dual-port rams are used, the CW001102 does not need to be stalled during dma transfers. the CW001102 uses the signals described below to access the data ram for both single-port and dual-port ram implementations. the dma interface shares these signals with the CW001102 for single-port ram implementations. daddr[23:0] data ram address output this 24-bit bus contains the data ram address. addressing is performed on word boundaries. denable word-based data chip enable output assertion high of this output indicates the data ram data bus is enabled. iwe bit function iwe3 write enable for iwdata[31:24] iwe2 write enable for iwdata[23:16] iwe1 write enable for iwdata[15:8] iwe0 write enable for iwdata[7:0]
CW001102 arm966e-s microprocessor core 13 of 34 db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. drdata[31:0] data ram read data input this 32-bit bus contains data read from the data ram. dwdata[31:0] data ram write data output this 32-bit bus provides write data to the data ram. dwe[3:0] byte-based data write enable output assertion high of this output enables bytes for writes to the data ram. nodram data ram present input the CW001102 asserts nodram high to indicate data ram is not present and thus data ram decoding is disabled. assertion low of nodram indicates data ram is present, which enables data ram decoding. the dma interface uses the following signals to access only the second port of a dual-port ram. daddr2[23:0] data ram address output this 24-bit bus contains the data ram address. addressing is performed on word boundaries. denable2 word-based data chip enable output assertion high of this output indicates the data ram data bus is enabled. drdata2[31:0] data ram read data input this 32-bit bus contains data read from the data ram. dwdata2[31:0] data ram write data output this 32-bit bus provides write data to the data ram. dwe bit function dwe3 write enable for dwdata[31:24] dwe2 write enable for dwdata[23:16] dwe1 write enable for dwdata[15:8] dwe0 write enable for dwdata[7:0]
14 of 34 CW001102 arm966e-s microprocessor core db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. dwe2[3:0] byte-based data write enable output assertion high of this output enables writes to the data ram. dma signals dmaa[25:0] dma address input this 26-bit address contains the byte address for dma transfers. tie all unused address bits low. dmad[31:0] dma write data input this 32-bit bus contains the dma write data to the data ram. dmaenable dma port enable input dmaenable must be asserted high for a dma transfer to proceed. assert dmaenable low to save power when the dma interface is not being used. tie dmaenable low when the dma interface is not used in the implementation. dmamas[1:0] dma memory access size input dmamas[1:0] encodes the size of dma writes. dma reads are always one word wide. dmanreq dma request input dmanreq is an active-low dma transfer request. tie this input high when the dma interface is not used. dwe2 bit function dwe2[3] write enable for dwdata[31:24] dwe2[2] write enable for dwdata[23:16] dwe2[1] write enable for dwdata[15:8] dwe2[0] write enable for dwdata[7:0] dmamas[1:0] memory access size 00 byte 01 halfword 10 word 11 reserved
CW001102 arm966e-s microprocessor core 15 of 34 db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. dmanrw dma write not read input dmanrw is the dma read/write signal. dmardata[31:0] dma read data output this 32-bit bus contains dma data read from the data ram. dmaready dma ready output dmaready is asserted high when the CW001102 is stalled due to a dma wait request. dmaready must be sampled high before a dma transfer to/from a single- port data ram can occur. dmawait dma wait request input dmawait is asserted high to stall the CW001102 before proceeding with a dma transfer to/from a single-port data ram implementation. a high on dmaready indicates when the CW001102 is stalled. only use this signal for single-port data ram implementations. tie it low for dual-port data ram implementations. debug signals commrx communications channel receive output when high, this signal indicates that the comms channel receive buffer has data that the arm9e-s cpu can read. commtx communications channel transmit output when high, this signal indicates the comms channel transmit buffer is empty. dbgack debug acknowledge output when high, dbgack indicates that the arm9e-s is in debug mode. dmanrw function 0 read 1 write
16 of 34 CW001102 arm966e-s microprocessor core db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. dbgdewpt debug watchpoint input this input halts the processor for debug purposes. if high at the end of a data memory request cycle, this input causes the arm9e-s processor core to enter the debug state. dbgen debug enable input a low on this input disables the debug features of the CW001102. tie this input low when debugging is not required. dbgext[1:0] breakpoint/watchpoint external condition input these inputs to the embeddedice logic allow breakpoints/watchpoints to be dependent on external conditions. dbgiebkpt processor execution breakpoint input assertion high of this input halts processor execution for debug purposes. if dbgiebkpt is high at the end of an instruction fetch, then the arm9e-s processor core enters the debug state if that instruction reaches the execute stage of the processors pipeline. dbginstrexec instruction executed output a high assertion of this output indicates that the instruction in the execute stage of the processors pipeline has been executed. dbgir[3:0] tap controller instruction register output these outputs re?ct the current instruction loaded into the tap controller instruction register. they change when the tap state machine is in the update_ir state on the rising edge of clk when dbgtcken is asserted. dbgntdoen dbgtdo 3-state enable output when low, this signal indicates there is serial data on the dbgtdo output. dbgntdoen can be used as part of the output enable on a packaged parts dbgtdo pin. dbgntrst not test reset input this active-low input is the internally synchronized reset signal for the embeddedice internal state.
CW001102 arm966e-s microprocessor core 17 of 34 db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. dbgrng[1:0] watchpoint register match output these outputs indicate that the corresponding embeddedice watchpoint register has matched the conditions currently present on the address, data, and control buses. these signals are independent of the state of the watchpoints enable control bit. dbgrqi internal debug request output this signal is the debug request signal presented to the processor cores debug logic. it is the anding of edbgrq as presented to the CW001102 and bit 1 of the debug control register. dbgscreg[4:0] scan chain register output these outputs re?ct the id number of the scan chain currently selected by the tap controller. they change when the tap state machine is in the update_dp state on the rising edge of clk when dbgtcken is asserted. dbgsdin boundary scan serial input data output this output contains the serial data to be applied to an external scan chain. dbgsdout boundary scan serial output data input dbgsdout is the serial data input from an external scan chain. when an external scan chain is not implemented, tie this signal low. dbgtapsm[3:0] tap controller state machine output this bus re?cts the current state of the tap controller state machine. the tap controller follows the ieee 1149.1 test access port protocol. dbgtcken test clock enable input this input is the synchronous enable for the test clock. dbgtdi test data in input dbgtdi contains data input from the boundary scan logic. dbgtdo test data out output the CW001102 outputs test data on dbgtdo from its boundary scan logic.
18 of 34 CW001102 arm966e-s microprocessor core db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. dbgtms test mode select input dbgtms is the jtag test mode select signal. the test mode follows the ieee 1149.1 test access port protocol. edbgrq external debug request input an external debugger asserts this signal high to force the processor to enter the debug state. etm interface signals these signals are part of the trace module interface. all etm outputs are registered from the corresponding core internal signals. etmbigend endian mode output this output indicates the endian mode for the etm. when this signal is high, the mode is big endian; when etmbigend is low, the mode is little endian. etmchsd[1:0] etm coprocessor handshake decode output these outputs are the handshake signals from the decode stage of the coprocessors pipeline follower. etmchse[1:0] etm coprocessor handshake execute output these outputs are the handshake signals from the execute stage of the coprocessors pipeline follower. etmda[31:0] etm data address output this 32-bit bus contains the etm data address. etmchsd[1:0] encoding 10 absent 00 wait 01 go 11 last etmchse[1:0] encoding 10 absent 00 wait 01 go 11 last
CW001102 arm966e-s microprocessor core 19 of 34 db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. etmdabort etm data abort output assertion of this signal indicates a data abort to the arm9e-s core. etmdbgack etm debug mode indication output when high, this signal indicates that the processor is in debug state. etmdmas[1:0] etm data size indicator output these signals indicate the data size of the etm. they become valid in the same cycle as the data address bus. etmdmore etm sequential data indication output the etmdmore signal is active during load and store multiple instructions and only goes high when etmdnmreq is low. this signal effectively gives the same information as etmdseq, but a cycle ahead. this information is provided to allow external logic more time to decode sequential cycles. etmdnmreq etm data memory request output this signal is asserted high when the CW001102 is making a request to etm data memory. etmdnrw etm data r/w output if this signal is low at the end of the cycle, then any data memory access in the following cycle is a read; if this signal is high, then the access is a write. etmdseq etm sequential data indication output if this signal is high at the end of the cycle, then any data memory access in the following cycle is sequential from the last data memory access. etmen etm enable input when this signal is high, the etm is enabled and the arm9e-s interface signals are driven out of this module, pipelined by one clock stage. dmas[1:0] transfer size 00 byte 01 halfword 10 word 11 reserved
20 of 34 CW001102 arm966e-s microprocessor core db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. etmhivecs exception vector location output when this output is low, the arm9e-s exception vectors start at address 0x0000.0000. when this signal is high, the arm9e-s exception vectors start at address 0xffff.0000. this output is a static con?uration signal. etmia[31:1] etm instruction address bus output this 31-bit bus contains the address for the etm. etmid31to25[31:25] bits [31:25] of the instruction data output these outputs re?ct the status of bits [31:25] of the instruction data read by the CW001102. etmid15to11[15:11] bits [15:11] of the instruction data output these outputs re?ct the status of bits [15:11] of the instruction data read by the CW001102. etminmreq etm instruction memory request output the CW001102 drives this output low to indicate that an instruction fetch is occurring. etminstrexec etm instruction execute indicator output assertion high of this output indicates that the instruction in the execute stage of the processor pipeline has been executed. etminstrvalid etm instruction valid output assertion high of this output indicates that the current instruction is valid for the etm. etmiseq etm sequential instruction output the etmiseq signal indicates whether the fetch is sequential (high) or non-sequential (low) to the previous access. etmitbit etm thumb indication output when this signal is low, the processor is in arm state, and 32-bit instructions are fetched. when etmitbit is high, the processor is in thumb state, and 16-bit instructions are fetched.
CW001102 arm966e-s microprocessor core 21 of 34 db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. etmlatecancel etm coprocessor late cancel indicator output a high on this output during the ?st memory cycle of a coprocessor instruction informs the coprocessor to cancel the instruction without changing any internal state. this signal is only asserted in cycles where the previous instruction accessed memory and a data abort occurred. etmnwait etm clock stall output driving this output low stalls the etm. etmpass etm coprocessor instruction execute indicator output a high on this signal indicates that there is a coprocessor instruction in the execute stage of the pipeline, which needs to be executed. etmprocid[31:0] etm process id output this 32-bit output contains the process id for the etm. etmprocidwr etm process id write output this output is asserted high when etmprocid is written. etmrdata[31:0] etm read data output this 32-bit bus contains etm read data. etmrngout[1:0] etm watchpoint register match output this output indicates that corresponding embeddedice watchpoint register has matched the conditions currently present on the address, data, and control buses. this signal is independent of the state of the watchpoints enable control bit. etmwdata[31:0] etm write data output this 32-bit bus contains etm write data. fifofull etm fifo full input this input is asserted high when the etm fifo is full. tie this signal low when an etm is not used.
22 of 34 CW001102 arm966e-s microprocessor core db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. tapid[31:0] boundary scan id code input this bus speci?s the id code value shifted out on dbgtdo when the idcode instruction is entered into the tap controller. miscellaneous signals bigendout big endian output when this output is high, the CW001102 is in big- endian mode (byte 0 is the most-signi?ant bit). when this output is low, the CW001102 is in little-endian mode. this input is a static con?uration signal. it must remain at one value from reset or be changed using a carefully constructed code sequence to avoid software problems. clk system clock input clk is the CW001102 system clock. clk can be stretched in either state (held high or low). hclken hclk enable input hclken is used in conjunction with clk to effectively run the CW001102 at a higher frequency than the ahb system bus. hclken is high for a single clk period and signi?s the rising edge of the ahb clock hclk. all ahb outputs transition on the clk rising edge in which hclken is asserted. nfiq not fast interrupt input this active-low input is the arm fast interrupt request. the CW001102 supports synchronous interrupts only. nirq not interrupt request input this active-low input is the arm interrupt request. the CW001102 supports synchronous interrupts only. initialization control signals initram ram enable con?uration input when initram is high, the instruction and data rams are enabled at the end of reset. when initram is low, the instruction and data rams are disabled coming out of reset.
CW001102 arm966e-s microprocessor core 23 of 34 db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. this input is a static con?uration signal. its value is sampled at reset only. vinithi high vectors con?uration input when vinithi is low at reset, the arm9 exception vectors start at address 0x0000.0000. when vinithi is high, the exception vectors start at 0xffff.0000. this signal is a static con?uration signal. its value is sampled at reset only. atpg scan control signals this section describes the automatic test pattern generation (atpg) scan control signals. scanen scan enable input assertion high of this input enables the scanning of data through the scan chain. si0 scan chain in input si0 is the input for serial scan chain 0. si1 scan chain in input si1 is the input for serial scan chain 1. si2 scan chain in input si2 is the input for serial scan chain 2. si3 scan chain in input si3 is the input for serial scan chain 3. so0 scan chain out output so0 is the output for serial scan chain 0. so1 scan chain out output so1 is the output for serial scan chain 1. so2 scan chain out output so2 is the output for serial scan chain 2. so3 scan chain out output so3 is the output for serial scan chain 3.
24 of 34 CW001102 arm966e-s microprocessor core db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. physical speci?ations the CW001102 arm966e-s core has a single 1x clock input. clock duty cycles can vary from 30% to 70% at maximum frequency. variance is greater at lower frequencies. the CW001102 operates at 125.47 mhz tested under worst-case conditions: 1.62 v, 115 c. ta b l e 2 shows the size of the CW001102 in g12-l 4-layer metal technology. ac timing all ac timing values are relative to the system clock (clk) input to the CW001102. input setup time is measured from the time the signal is valid to the rising edge of clk. input hold time is measured from the rising edge of clk to the time the signal goes invalid. for input setup times, the driver must drive the signal valid before any receivers need it. for input hold times, the driver must hold the signal valid longer than needed by any receiver. the maximum and minimum delay times for outputs are measured from the rising edge of clk to the time the signal is valid. figure 2 shows how ac timing is measured. ta b l e 3 shows the CW001102 timing conditions. table 2 CW001102 physical layout size parameter size technology g12-l width 1.17 mm height 1.75 mm
CW001102 arm966e-s microprocessor core 25 of 34 db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. figure 2 ac speci?ations ac timing parameters this section describes various parameters related to the ac timing tables below. operating conditions the core is characterized for: ? setup times: lsi_wc10 ? hold times: lsi_bc note: be sure to specify operating frequency in the design . lsitkdelspec ?e. if this frequency is not speci?d, the lsidelay default frequency causes ramp-time errors to be reported in reports/tCW001102_1_1lsi_wc.violations . table 3 CW001102 core timing conditions for g12-l process ac timing process v dd (v) junction temperature (?c) lsi_bc 0.84 1.89 ? 40 lsi_wc10 1.21 1.62 115 clk input signal max delay min delay clock period output signal setup hold
26 of 34 CW001102 arm966e-s microprocessor core db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. maximum clock frequency the maximum frequency is 125.47 mhz for lsi_wc10. maximum frequency heavily depends on the system. the estimate of maximum clock frequency is based on internal ?p-?p to ?p-?p timing. minimum and maximum duty cycles this design has been rated through static timing analysis for 30/70 and 70/30 duty cycles. the design is almost completely independent of duty cycle, because the design is fully synchronous other than the lock-up latches for scan. critical path the critical path is given below: ? startpoint: uarm9/ucoredp/ubyterot/rdatawrint_reg_20_ ? endpoint: uarm9/ucoredp/uregbank/bdata0ex_reg_5_ input ac timing ta b l e 4 shows the worst-case ac timing values for the CW001102 inputs when presented with the loading of one g12l111hs compiled memory on each of the instruction and data buses. note that all timing in ta b l e 4 is measured in nanoseconds. in ta b l e 4 , the setup margin is 0 ps @ 125.47 mhz. the hold margin is approximately 271 ps. the setup and hold times are measured with respect to clk.
CW001102 arm966e-s microprocessor core 27 of 34 db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. table 4 input signals signal setup (ns) hold (ns) notes chsde 4.84 ? 0.26 chsex 4.83 ? 0.25 cpdin 4.14 ? 0.31 to output dbgdewpt 2.06 ? 0.29 dbgen 1.97 ? 0.31 dbgext 1.52 ? 0.33 dbgiebkpt 1.72 ? 0.44 dbgntrst 4.01 ? 0.20 to cd pin dbgsdout 1.86 ? 0.50 to output dbgtcken 4.07 ? 0.54 dbgtdi 2.06 ? 0.45 dbgtms 2.28 ? 0.38 dmaa 1.63 ? 0.19 dmad 1.72 ? 0.22 dmaenable 1.20 ? 0.24 dmamas 1.53 ? 0.31 dmanreq 1.62 ? 0.36 dmanrw 1.55 ? 0.36 dmawait 1.54 ? 0.36 drdata 3.65 ? 0.44 drdata2 2.05 ? 0.38 edbgrq 1.60 ? 0.30 etmen 3.52 ? 0.49 fifofull 2.40 ? 0.64 hclken 6.53 ? 0.34 to output
28 of 34 CW001102 arm966e-s microprocessor core db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. output ac timing ta b l e 5 shows the worst-case ac timing values for the CW001102 outputs when presented with the loading of one g12l111hs compiled memory on each of the instruction and data buses. all timing in ta b l e 5 is measured in nanoseconds. in ta b l e 5 , all synchronous outputs depend on the clk input. the output load assumed for characterization is [8 * load_of(n1dfp/a)]. hgrant 2.46 ? 0.27 hrdata 3.42 ? 0.34 hready 6.42 ? 0.48 to output hresetn 3.50 ? 0.68 hresp 5.04 ? 0.42 to output initram 4.16 ? 0.56 to output irdata 3.64 ? 0.33 nfiq 2.37 ? 0.27 nirq 2.35 ? 0.25 nodram 3.40 ? 0.25 noiram 3.30 ? 0.25 scanen 6.08 ? 0.55 si0 1.75 ? 0.39 si1 1.41 ? 0.23 si2 2.18 ? 0.57 si3 1.79 ? 0.40 tapid 1.56 ? 0.22 vinithi 2.19 ? 0.32 table 4 input signals (cont.) signal setup (ns) hold (ns) notes
CW001102 arm966e-s microprocessor core 29 of 34 db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. note: the output pins of this coreware component require buffering at the periphery of the macrocell. this is to minimize loading effects on the CW001102s performance. table 5 output signals signal maximum output valid output hold time bigendout 1.98 0.49 commrx 2.26 0.57 commtx 2.70 0.78 cpclken 2.15 0.49 cpdout 1.65 0.33 cpinstr 1.74 0.38 cplatecancel 1.53 0.35 cppass 1.58 0.37 cptbit 1.60 0.37 daddr 6.61 0.51 daddr2 2.25 0.44 dbgack 3.43 0.60 dbginstrexec 2.76 053 dbgir 3.05 0.50 dbgntdoen 2.69 0.64 dbgrng 3.86 0.59 dbgrqi 3.02 0.59 dbgscreg 2.61 0.50 dbgsdin 2.46 0.63 dbgtapsm 2.64 0.40 dbgtdo 3.40 0.49 denable 6.95 0.79 denable2 3.03 0.55 dmardata 1.99 0.45
30 of 34 CW001102 arm966e-s microprocessor core db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. dmaready 2.52 0.55 dwdata 5.92 0.56 dwdata2 2.09 0.36 dwe 5.23 0.64 dwe2 3.31 0.50 etmbigend 1.72 0.40 etmchsd 1.73 0.40 etmchse 1.72 0.40 etmda 1.86 0.40 etmdabort 1.75 0.41 etmdbgack 1.70 0.39 etmdmas 1.75 0.40 etmdmore 1.72 0.40 etmdnmreq 1.74 0.40 etmdnrw 1.71 0.39 etmdseq 1.76 0.41 etmhivecs 1.75 0.41 etmia 1.91 0.39 etmid15to11 1.76 0.40 etmid31to25 1.76 0.40 etminmreq 1.74 0.40 etminstrexec 1.77 0.41 etminstrvalid 1.77 0.41 etmiseq 1.79 0.42 etmitbit 1.78 0.42 etmlatecancel 1.72 0.40 etmnwait 1.83 0.43 table 5 output signals (cont.) signal maximum output valid output hold time
CW001102 arm966e-s microprocessor core 31 of 34 db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. etmpass 1.72 0.40 etmprocid 1.81 0.39 etmprocidwr 1.77 0.41 etmrdata 1.84 0.40 etmrngout 1.78 0.42 etmwdata 2.04 0.41 haddr 2.08 0.46 hburst 1.89 0.40 hbusreq 1.78 0.42 hlock 1.88 0.44 hprot 1.88 0.44 hsize 1.85 0.39 htrans 1.94 0.40 hwdata 1.95 0.44 hwrite 1.80 0.42 iaddr 6.24 0.56 ienable 6.96 0.73 iwdata 5.81 0.80 iwe 6.03 0.61 ncpmreq 1.90 0.40 ncptrans 1.79 0.38 so0 1.13 0.19 so1 1.07 0.17 so2 1.06 0.16 so3 1.26 0.25 table 5 output signals (cont.) signal maximum output valid output hold time
32 of 34 CW001102 arm966e-s microprocessor core db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. clock tree description the clock tree begins with a single lclkbuf1250fp. the output of this buffer subsequently drives the clock buffer tree. there are 5 levels in the clock tree. clock skew and delays ta b l e 6 lists the clock timings. guidelines this section provides guidelines for the subsystem integration of the clock and sta. subsystem integration of clock guidelines the system must match the insertion delay of the coreware component. sta guidelines in the scripts provided for the static timing analysis of the CW001102, all the necessary clock de?itions, clock periods, false paths, multicycle paths, zero-cycle paths, and constants are de?ed for the developer. refer to the script for speci?s. table 6 clock timings parameter value clock skew approximately 98 ps insertion delay 1.89 ? 1.99 ns (lsi_wc10) 0.86 ? 0.90 ns (lsi_bc) minimum clock delay ubiu/uwbuf/ufifo/fifoseq_reg_5_/ cp (lsi_wc10) uarm9/ucoredp/uregbank/ uregbankmem/reg4_reg_27_/cp (lsi_bc) maximum clock delay ucp15/ucp15reg/ucp15tap/sc15shftreg_reg_20_/cp
CW001102 arm966e-s microprocessor core 33 of 34 db08-000123-01 september 2001 - rev. b copyright ? 2000, 2001 by lsi logic corporation. all rights reserved. as a qualitative analysis of the design for sta, the developer must be aware of the following: ? no generated or gated clocks are in the design. ? there are no false paths in the critical path for this design. ? no multicycle paths are identi?d for this design. ? no zero-cycle paths are identi?d for this design. ? scanen is tied low for normal operation. it is recommended that hold times be checked with scanen tied high as well as low.
eh doc. no. db08-000123-01 to receive product literature, visit us at http://www.lsilogic.com. for a current list of our distributors, sales offices, and design resource centers, view our web page located at http://www.lsilogic.com/contacts/na_salesoffices.html. lsi logic corporation reserves the right to make changes to any products and services herein at any time without notice. lsi logic does not assume any responsibility or lia- bility arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase, lease, or use of a product or service from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or of third parties. this document is preliminary. as such, it contains data derived from functional simulations and performance estimates. lsi logic has not veri?d the functional descriptions or electrical and mechanical speci?ations using production parts. the lsi logic logo design, coreware, and g12 are trade- marks or registered trademarks of lsi logic corporation. all other brand and product names may be trademarks of their respective companies. headquarters lsi logic corporation north american headquarters milpitas ca tel: 408.433.8000 fax: 408.433.8989 lsi logic europe ltd european headquarters bracknell england tel: 44.1344.426544 fax: 44.1344.481039 lsi logic k.k. headquarters tokyo japan tel: 81.3.5463.7821 fax: 81.3.5463.7820 printed on recycled paper iso 9000 certified notes

▲Up To Search▲

Price & Availability of CW001102

	To Download CW001102 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .