1 ? ISL6700 80v/1.25a peak, medium frequency, low cost, half-bridge driver the ISL6700 is an 80v/1.25a peak, medium frequency, low cost, half-bridge driver ic available in 8-lead soic and 12-lead qfn plastic packages. the low-side and high-side gate drivers are independently controlled and matched to 25ns. this gives the user maximum flexibility in dead-time selection and driver protocol. undervoltage protection on both the low-side and high-side supplies force the outputs low. non-latching, level-shift tr anslation is used to control the upper drive circuit. unlike some competitors, the high-side output returns to its correct state after a momentary undervoltage of the high-side supply. features ? drives 2 n-channel mosfets in half-bridge configuration ? space saving so8 and low r c-s qfn packages ? phase supply max voltage to 80vdc ? bootstrap supply max voltage to 96vdc ? drives 1000pf load with rise and fall times typ. 15ns ? ttl/cmos compatible input thresholds ? independent inputs for non-half-bridge topologies ? no start-up problems ? low power consumption ? wide supply range ? supply undervoltage protection ? qfn package - compliant to jedec pub95 mo-220 qfn - quad flat no leads - package outline ? pb-free available applications ? telecom/datacom power supplies ? half-bridge converters ? two-switch forward converters ? active clamp forward converters pinouts ordering information part number temp. range (c) package pkg. dwg. # ISL6700ib -40 to 125 8 ld soic m8.15 ISL6700ibz (see note) -40 to 125 8 ld soic (pb-free) m8.15 ISL6700ir -40 to 125 12 ld 4x4 qfn l12.4x4 ISL6700irz (see note) -40 to 125 12 ld 4x4 qfn (pb-free) l12.4x4 add ?-t? suffix to part number for tape and reel packaging. note: intersil pb-free products em ploy special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020b. ISL6700ib (soic) top view ISL6700ir (qfn) top view note: epad = exposed pad. 5 6 8 7 4 3 2 1 v dd hi li v ss hb hs lo ho 11 10 v dd nc hb 12 56 4 1 2 3 9 8 7 v ss nc lo ho nc hs hi nc li epad data sheet july 2004 fn9077.5 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2002-2004. all rights reserved. all other trademarks mentioned are the property of their respective owners.
2 application block diagram functional block diagram secondary circuit +48v control controller pwm li hi ho lo v dd hs hb +12v v ss ISL6700 reference and isolation drive lo drive hi level shift hb hs ho lo undervoltage detector li hi v dd v ss u/v turn-on delay epad (qfn package only) ISL6700
3 secondary ISL6700 isolation pwm +48v +12v circuit figure 1. two-switch forward converter secondary circuit ISL6700 isolation pwm +48v +12v figure 2. forward converter with an active clamp ISL6700
4 absolute maximum rati ngs thermal information supply voltage, v dd (note 1) . . . . . . . . . . . . . . . . . . . -0.3v to 16v li and hi voltages (note 1) . . . . . . . . . . . . . . . . -0.3v to v dd +0.3v voltage on hs (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to 80v voltage on hb (note 1) . . . . . . . . . . . . . . . . v hs -0.3v to v hs +v dd voltage on lo (note 1) . . . . . . . . . . . . . . . . . v ss -0.3 to v dd +0.3v voltage on ho (note 1) . . . . . . . . . . . . . . . . v hs -0.3v to v hb +0.3v phase slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20v/ns maximum recommended operating conditions supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9v to 15v voltage on hs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to 75v voltage on hs (note 2) . . . . . . . . . .(repetitive transient) -1v to 80v voltage on hb . . . . . . . . . . . . . . . . . . . . . . . . . . v hs +7.5v to v hs +v dd thermal resistance (typical) ja (c/w) jc (c/w) soic (note 3) . . . . . . . . . . . . . . . . . . . 95 n/a qfn (note 4) . . . . . . . . . . . . . . . . . . . . 49 7 max power dissipation at 25c in free air (soic, note 3). 1.316w max power dissipation at 25c in free air (qfn, note 4) . .2.976w maximum storage temperature range . . . . . . . . . .-65c to +150c maximum junction temperature range . . . . . . . . .-40c to +150c maximum lead temperature (soldering 10s) . . . . . . . . . . . +300c (soic - lead tips only) for recommended soldering condi tions see tech brief tb389. caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the recommended operating conditio ns of this specification is not implied. notes: 1. all voltages referenced to v ss unless otherwise specified. 2. based on v dd =15v. the magnitude of the allowable negative trans ient on the hs pin is a function of the v dd supply voltage. v hs <15.6v- v dd +v f , where v hs is the magnitude of the allowable negative transient and v f is the forward voltage drop of the bootstrap diode. 3. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 4. ja is measured in free air with the component mounted on a high ef fective thermal conductivity test board with ?direct attach? fe atures. jc , the ?case temp? is measured at the center of the exposed metal pad on the package underside. see tech brief tb379. electrical specifications v dd = v hb = 12v, v ss = v hs = 0v, no load on lo or ho, unless otherwise specified parameters symbol test conditions t j = 25c t j = -40c to 125c units min typ max min max supply currents & undervoltage protection v dd quiescent current i dd li = 0 or v dd - 1.9 2.2 - 2.4 ma v dd operating current i ddo f = 50khz - 2.0 2.2 - 2.5 ma v dd operating current i ddo f = 500khz - 2.5 3.0 - 4.0 ma hb off quiescent current i hbl hi = 0 - 1.25 1.5 - 1.8 ma hb on quiescent current i hbh hi = v dd - 170 240 - 250 a hb operating current i hbo f = 50khz, c l = 1000pf - 1.45 1.8 - 2.0 ma hb operating current i hbo f = 500khz, c l = 1000pf - 2.4 2.8 - 3.0 ma hs leakage current i hlk v hs = 80v v hb = 96v --1-1 a v dd rising undervoltage threshold v dduv+ 6.8 7.6 8.25 6.5 8.5 v v dd falling undervoltage threshold v dduv- 6.5 7.1 7.8 6.25 8.1 v undervoltage hysteresis uvhys 0.17 0.45 0.75 0.15 0.90 v hb undervoltage threshold vhbuv referenced to hs 4.8 5.3 6.5 4.0 7.5 v input pins: li and hi low level input voltage v il full operating conditions 0.8 1.6 - 0.8 - v high level input voltage v ih full operating conditions - 1.7 2.2 - 2.2 v input voltage hysteresis - 100 - - - mv low level input current i il v in = 0v, full operating conditions -70 -60 -30 -80 -30 a high level input current i ih v in = 5v, full operating conditions 30 115 130 30 145 a ISL6700
5 gate driver output pins: lo & ho low level output voltage v ol i out = 0a - - 0.1 - 0.1 v high level output voltage v dd -v oh i out = 0a - - 0.1 - 0.1 v peak pullup current i o +v out = 0v - 1.4 - - - a peak pulldown current i o -v out = 12v - 1.3 - - - a electrical specifications v dd = v hb = 12v, v ss = v hs = 0v, no load on lo or ho, unless otherwise specified (continued) parameters symbol test conditions t j = 25c t j = -40c to 125c units min typ max min max switching specifications v dd = v hb = 12v, v ss = v hs = 0v, no load on lo or ho, unless otherwise specified parameters symbol test conditions t j = 25c t j = -40c to 125c units min typ max min max lower turn-off propagation delay (li falling to lo falling) t lphl - 45 50 - 65 ns upper turn-off propagation delay (hi falling to ho falling) t hphl - 60 75 - 90 ns lower turn-on propagation delay (li rising to lo rising) t lplh - 75 82 - 95 ns upper turn-on propagation delay (hi rising to ho rising) t hplh - 70 75 - 95 ns deadtime, (t hplh - t lphl )dht on li, hi switched simultaneously 0 24 - 0 - ns deadtime, (t lplh - t hphl )dlt on 017 - 0 - ns rise time t r -520-25ns fall time t f -520-25ns delay matching: lower turn-on and upper turn-off t mon -820-25ns delay matching: lower turn-off and upper turn-on t moff - -15 25 - 30 ns pin descriptions symbol description v dd positive supply to control logic and lower gate drivers. de-couple this pin to v ss . connect anode of bootstrap diode to this pin. hi logic level input that controls the ho output. li logic level input that controls the lo output. v ss chip negative supply, generally will be ground. lo low-side output. connect to gate of low-side power mosfet. hs high-side source connection. connect to source of high-side pow er mosfet. connect negative side of bootstrap capacitor to thi s pin. ho high-side output. connect to gate of high-side power mosfet. hb high-side bootstrap supply. external bootstrap diode and capacitor are required. connect cathode of bootstrap diode and posit ive side of bootstrap capacitor to this pin. epad exposed pad. connect to ground or float. the epad is electrically isolated from all other pins. ISL6700
6 timing diagrams figure 3. figure 4. t hplh , t lplh t hphl , t lphl hi, li ho, lo t mon t moff li hi lo ho ISL6700
7 ISL6700 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l12.4x4 12 lead quad flat no-lead plastic package (compliant to jedec mo-220-vggc issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.23 0.28 0.38 5, 8 d 4.00 bsc - d1 3.75 bsc 9 d2 1.95 2.10 2.25 7, 8 e 4.00 bsc - e1 3.75 bsc 9 e2 1.95 2.10 2.25 7, 8 e 0.80 bsc - k0.25 - - - l 0.35 0.60 0.75 8 l1 - - 0.15 10 n122 nd 3 3 ne 3 3 p- -0.609 --129 rev. 1 5/03 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.
8 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com ISL6700 small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 o 8 o 0 o 8 o - rev. 0 12/93
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