|
If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
Datasheet File OCR Text: |
80c32/80c52 rev. g (14 jan. 97) 1 matra mhs description temic's 80c52 and 80c32 are high performance cmos versions of the 8052/8032 nmos single chip 8 bit m c. the fully static design of the temic 80c52/80c32 allows to reduce system power consumption by bringing the clock frequency down to any value, even dc, without loss of data. the 80c52 retains all the features of the 8052 : 8 k bytes of rom ; 256 bytes of ram ; 32 i/o lines ; three 16 bit timers ; a 6-source, 2-level interrupt structure ; a full duplex serial port ; and on-chip oscillator and clock circuits. in addition, the 80c52 has 2 software-selectable modes of reduced activity for further reduction in power consumption. in the idle mode the cpu is frozen while the ram, the timers, the serial port and the interrupt system continue to function. in the power down mode the ram is saved and all other functions are inoperative. the 80c32 is identical to the 80c52 except that it has no on-chip rom. temic's 80c52/80c32 are manufactured using scmos process which allows them to run from 0 up to 44 mhz with vcc = 5 v. temic's 80c52 and 80c32 are also available at 16 mhz with 2.7 v < v cc < 5.5 v. 80c32 : romless version of the 80c52 80c32/80c52-l16 : low power version vcc : 2.7 5.5 v freq : 0-16 mhz 80c32/80c52-12 : 0 to 12 mhz 80c32/80c52-16 : 0 to 16 mhz 80c32/80c52-20 : 0 to 20 mhz 80c32/80c52-25 : 0 to 25 mhz 80c32/80c52-30 : 0 to 30 mhz 80c32/80c52-36 : 0 to 36 mhz 80c32-40 : 0 to 40 mhz* 80c32-42 : 0 to 42 mhz* 80c32-44 : 0 to 44 mhz* * 0 to 70 c temperature range. for other speed and temperature range availability please consult your sales office. features power control modes 256 bytes of ram 8 kbytes of rom (80c52) 32 programmable i/o lines three 16 bit timer/counters 64 k program memory space 64 k data memory space fully static design 0.8 m cmos process boolean processor 6 interrupt sources programmable serial port temperature range : commercial, industrial, automotive, military optional secret rom : encryption secret tag : identification number cmos 0 to 44 mhz single chip 8bit microntroller
80c32/80c52 rev. g (14 jan. 97) 2 matra mhs interface figure 1. block diagram 80c32/80c52 rev. g (14 jan. 97) 3 matra mhs figure 2. pin configuration 80c32/80c52 80c32/80c52 diagrams are for reference only. package sizes are not to scale. dil lcc flat pack p1.4 p1.3 p1.2 p1.1/t2ex p1.0/t2 nc vcc p0.0/a0 p0.1/a1 p0.2/a2 p0.3/a3 p0.4/a4 p1.5 p1.6 p1.7 rst rxd/p3.0 nc txd/p3.1 int0/p3.2 int1/p3.3 t0/p3.4 t1/p3.5 p0.5/a5 p0.6/a6 p0.7/a7 ea nc ale psen p2.7/a14 p2.6/a13 p2.5/a12 wr/p3.6 rd/p3.7 xtal2 xtal1 vss nc p2.0/a7 p2.1/a8 p2.2/a9 p2.3/a10 p2.4/a11 15 p 16 p 17 p 30 rxd/p 31 txd/p 32 int0/p 33 int1/p 34 t0/p 35 t1/p 36 wr/p 37 rd/p xtal2 xtal1 ss v nc 20 p 21 p 22 p 23 p 24 p rst nc 14 p 13 p 12 p 11 p 10 p nc cc v 00 a0/p /a8 /a9 /a10 /a11 /a12 04 p /a4 05 p /a5 06 p /a6 07 p /a7 ea nc ale psen 27 p /a15 26 p /a14 25 p /a13 /t2ex /t2 01 a1/p 02 a2/p 03 a3/p 80c32/80c52 rev. g (14 jan. 97) 4 matra mhs pin description vss circuit ground potential. vcc supply voltage during normal, idle, and power down operation. port 0 port 0 is an 8 bit open drain bi-directional i/o port. port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application it uses strong internal pullups when emitting 1's. port 0 also outputs the code bytes during program verification in the 80c52. external pullups are required during program verification. port 0 can sink eight ls ttl inputs. port 1 port 1 is an 8 bit bi-directional i/o port with internal pullups. port 1 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 1 pins that are externally being pulled low will source current (iil, on the data sheet) because of the internal pullups. port 1 also receives the low-order address byte during program verification. in the 80c52, port 1 can sink/ source three ls ttl inputs. it can drive cmos inputs without external pullups. 2 inputs of port 1 are also used for timer/counter 2 : p1.0 [t2] : external clock input for timer/counter 2. p1.1 [t2ex] : a trigger input for timer/counter 2, to be reloaded or captured causing the timer/counter 2 interrupt. port 2 port 2 is an 8 bit bi-directional i/o port with internal pullups. port 2 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current (ill, on the data sheet) because of the internal pullups. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16 bit addresses (movx @dptr). in this application, it uses strong internal pullups when emitting 1's. during accesses to external data memory that use 8 bit addresses (movx @ri), port 2 emits the contents of the p2 special function register. it also receives the high-order address bits and control signals during program verification in the 80c52. port 2 can sink/source three ls ttl inputs. it can drive cmos inputs without external pullups. port 3 port 3 is an 8 bit bi-directional i/o port with internal pullups. port 3 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current (ill, on the data sheet) because of the pullups. it also serves the functions of various special features of the temic 51 family, as listed below. port pin alternate function p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 rxd (serial input port) txd (serial output port) int0 (external interrupt 0) int1 (external interrupt 1) td (timer 0 external input) t1 (timer 1 external input) wr (external data memory write strobe) rd (external data memory read strobe) port 3 can sink/source three ls ttl inputs. it can drive cmos inputs without external pullups. rst a high level on this for two machine cycles while the oscillator is running resets the device. an internal pull-down resistor permits power-on reset using only a capacitor connected to v cc . as soon as the reset is applied (vin), port 1, 2 and 3 are tied to one. this operation is achieved asynchronously even if the oscillator does not start-up. ale address latch enable output for latching the low byte of the address during accesses to external memory. ale is activated as though for this purpose at a constant rate of 1/6 the oscillator frequency except during an external data memory access at which time one ale pulse is skipped. ale can sink/source 8 ls ttl inputs. it can drive cmos inputs without an external pullup. 80c32/80c52 rev. g (14 jan. 97) 5 matra mhs psen program store enable output is the read strobe to external program memory. psen is activated twice each machine cycle during fetches from external program memory. (however, when executing out of external program memory, two activations of psen are skipped during each access to external data memory). psen is not activated during fetches from internal program memory. psen can sink/source 8 ls ttl inputs. it can drive cmos inputs without an external pullup. ea when ea is held high, the cpu executes out of internal program memory (unless the program counter exceeds 1 fffh). when ea is held low, the cpu executes only out of external program memory. ea must not be floated. xtal1 input to the inverting amplifier that forms the oscillator. receives the external oscillator signal when an external oscillator is used. xtal2 output of the inverting amplifier that forms the oscillator. this pin should be floated when an external oscillator is used. idle and power down operation figure 3 shows the internal idle and power down clock configuration. as illustrated, power down operation stops the oscillator. idle mode operation allows the interrupt, serial port, and timer blocks to continue to function, while the clock to the cpu is gated off. these special modes are activated by software via the special function register, pcon. its hardware address is 87h. pcon is not bit addressable. figure 3.idle and power down hardware. pcon : power control register (msb) (lsb) smod gf1 gf0 pd idl symbol position name and function smod pcon.7 double baud rate bit. when set to a 1, the baud rate is doubled when the serial port is being used in either modes 1, 2 or 3. pcon.6 (reserved) pcon.5 (reserved) pcon.4 (reserved) gf1 pcon.3 general-purpose flag bit. gf0 pcon.2 general-purpose flag bit. pd pcon.1 power down bit. setting this bit activates power down operation. idl pcon.0 idle mode bit. setting this bit activates idle mode operation. if 1's are written to pd and idl at the same time. pd takes, precedence. the reset value of pcon is (000x0000). idle mode the instruction that sets pcon.0 is the last instruction executed before the idle mode is activated. once in the idle mode the cpu status is preserved in its entirety : the stack pointer, program counter, program status word, accumulator, ram and all other registers maintain their data during idle. table 1 describes the status of the external pins during idle mode. 80c32/80c52 rev. g (14 jan. 97) 6 matra mhs there are three ways to terminate the idle mode. activation of any enabled interrupt will cause pcon.0 to be cleared by hardware, terminating idle mode. the interrupt is serviced, and following reti, the next instruction to be executed will be the one following the instruction that wrote 1 to pcon.0. the flag bits gf0 and gf1 may be used to determine whether the interrupt was received during normal execution or during the idle mode. for example, the instruction that writes to pcon.0 can also set or clear one or both flag bits. when idle mode is terminated by an enabled interrupt, the service routine can examine the status of the flag bits. the second way of terminating the idle mode is with a hardware reset. since the oscillator is still running, the hardware reset needs to be active for only 2 machine cycles (24 oscillator periods) to complete the reset operation. power down mode the instruction that sets pcon.1 is the last executed prior to entering power down. once in power down, the oscillator is stopped. the contents of the onchip ram and the special function register is saved during power down mode. the hardware reset initiates the special fucntion register. in the power down mode, vcc may be lowered to minimize circuit power consumption. care must be taken to ensure the voltage is not reduced until the power down mode is entered, and that the voltage is restored before the hardware reset is applied which freezes the oscillator. reset should not be released until the oscillator has restarted and stabilized. table 1 describes the status of the external pins while in the power down mode. it should be noted that if the power down mode is activated while in external program memory, the port data that is held in the special function register p2 is restored to port 2. if the data is a 1, the port pin is held high during the power down mode by the strong pullup, t1, shown in figure 4 . table 1. status of the external pins during idle and power down modes. mode program memory ale psen port0 port1 port2 port3 idle internal 1 1 port data port data port data port data idle external 1 1 floating port data address port data power down internal 0 0 port data port data port data port data power down external 0 0 floating port data port data port data stop clock mode due to static design, the temic 80c32/c52 clock speed can be reduced until 0 mhz without any data loss in memory or registers. this mode allows step by step utilization, and permits to reduce system power consumption by bringing the clock frequency down to any value. at 0 mhz, the power consumption is the same as in the power down mode. i/o ports the i/o buffers for ports 1, 2 and 3 are implemented as shown in figure 4 . figure 4.i/o buffers in the 80c52 (ports 1, 2, 3). 80c32/80c52 rev. g (14 jan. 97) 7 matra mhs when the port latch contains a 0, all pfets in figure 4 are off while the nfet is turned on. when the port latch makes a 0-to-1 transition, the nfet turns off. the strong pfet, t1, turns on for two oscillator periods, pulling the output high very rapidly. as the output line is drawn high, pfet t3 turns on through the inverter to supply the ioh source current. this inverter and t form a latch which holds the 1 and is supported by t2. when port 2 is used as an address port, for access to external program of data memory, any address bit that contains a 1 will have his strong pullup turned on for the entire duration of the external memory access. when an i/o pin on ports 1, 2, or 3 is used as an input, the user should be aware that the external circuit must sink current during the logical 1-to-0 transition. the maximum sink current is specified as itl under the d.c. specifications. when the input goes below approximately 2 v, t3 turns off to save icc current. note, when returning to a logical 1, t2 is the only internal pullup that is on. this will result in a slow rise time if the user's circuit does not force the input line high. oscillator characteristics xtal1 and xtal2 are the input and output respectively, of an inverting amplifier which is configured for use as an on-chip oscillator, as shown in figure 5. either a quartz crystal or ceramic resonator may be used. figure 5. crystal oscillator. to drive the device from an external clock source, xtal1 should be driven while xtal2 is left unconnected as shown in figure 6 . there are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. figure 6. external drive configuration. hardware description same as for the 80c51, plus a third timer/counter : timer/event counter 2 timer 2 is a 16 bit timer/counter like timers 0 and 1, it can operate either as a timer or as an event counter. this is selected by bit c/t2 in the special function register t2con (figure 1). it has three operating modes : acaptureo, aautoloado and abaud rate generatoro, which are selected by bits in t2con as shown in table 2 . in the capture mode there are two options which are selected by bit exen2 in t2con; if exen2 = 0, then timer 2 is a 16 bit timer or counter which upon overflowing sets bit tf2, the timer 2 overflow bit, which can be used to generate an interrupt. if exen2 = 1, then timer 2 still does the above, but with the added feature that a 1-to-0 transition at external input t2ex causes the current value in the timer 2 registers, tl2 and th2, to be captured into registers rcap2l and rcap2h, respectively, (rcap2l and rcap2h are new special function register in the 80c52). in addition, the transition at t2ex causes bit exf2 in t2con to be set, and exf2, like tf2, can generate an interrupt. table 2. timer 2 operating modes. rclk + tclk cp/rl2 tr2 mode 0 0 1 x 0 1 x x 1 1 1 0 16 bit auto-reload 16 bit capture baud rate generator (off) 80c32/80c52 rev. g (14 jan. 97) 8 matra mhs the capture mode is illustrated in figure 7 . figure 7. timer 2 in capture mode. in the auto-reload mode there are again two options, which are selected by bit exen2 in t2con.if exen2 = 0, then when timer 2 rolls over it does not only set tf2 but also causes the timer 2 register to be reloaded with the 16 bit value in registers rcap2l and rcap2h, which are preset by software. if exen2 = 1, then timer 2 still does the above, but with the added feature that a 1-to-0 transition at external input t2ex will also trigger the 16 bit reload and set exf2. the auto-reload mode is illustrated in figure 8 . figure 8. timer in auto-reload mode. (msb) (lsb) tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 the baud rate generator mode is selected by : rclk = 1 and/or tclk = 1. symbol position name and significance tf2 t2con.7 timer 2 overflow flag set by a timer 2 overflow and must be cleared by software. tf2 will not be set when either rclk = 1 or tclk = 1. exf2 t2con.6 timer 2 external flag set when either a capture or reload is caused by a negative transition on t2ex and exen2 = 1. when timer 2 interrupt is enabled, exf2 = 1 will cause the cpu to vector to the timer 2 interrupt routine. exf2 must be cleared by software. rclk t2con.5 receive clock flag. when set, causes the serial port to use timer2 overflow pulses for its receive clock in modes 1 and 3. rclk = 0 causes timer 1 overflow to be used for the receive clock. tclk t2con.4 transmit clock flag. when set, causes the serial port to use timer 2 overflow pulses for its transmit clock in modes 1 and 3. tclk = 0 causes timer 1 overflows to be used for the transmit clock. exen2 t2con.3 timer 2 external enable flag. when set, allows capture or reload to occur as a result of a negative transition on t2ex if timer 2 is not being used to clock the serial port. exen2 = 0 causes timer 2 to ignore events at t2ex. tr2 t2con.2 start/stop control for timer 2. a logic 1 starts the timer. c/t2 t2con.1 timer or counter select. (timer 2) 0 = internal timer (osc/12) 1 = external event counter (falling edge triggered). cp/rl2 t2con.0 capture/reload flag. when set, captures will occur on negative transitions at t2ex if exen 2 = 1. when cleared, auto reloads will occur either with timer 2 overflows or negative transition at t2ex when exen2 = 1. when either rclk = 1 or tclk = 1, this bit is ignored and the timer is forced to auto-reload on timer 2 overflow. 80c32/80c52 rev. g (14 jan. 97) 9 matra mhs 80c52 with secret rom temic offers 80c52 with the encrypted secret rom option to secure the rom code contained in the 80c52 microcontrollers. the clear reading of the program contained in the rom is made impossible due to an encryption through several random keys implemented during the manufacturing process. the keys used to do such encryption are selected randomwise and are definitely different from one microcontroller to another. this encryption is activated during the following phases : everytime a byte is addressed during a verify of the rom content, a byte of the encryption array is selected. movc instructions executed from external program memory are disabled when fetching code bytes from internal memory. ea is sampled and latched on reset, thus all state modification are disabled. for further information please refer to the application note (anm053) available upon request. 80c52 with secret tag temic offers special 64-bit identifier called asecret tago on the microcontroller chip. the secret tag option is available on both romless and masked microcontrollers. the secret tag feature allows serialization of each microcontroller for identification of a specific equipment. a unique number per device is implemented in the chip during manufacturing process. the serial number is a 64-bit binary value which is contained and addressable in the special function registers (sfr) area. this secret tag option can be read-out by a software routine and thus enables the user to do an individual identity check per device. this routine is implemented inside the microcontroller rom memory in case of masked version which can be kept secret (and then the value of the secret tag also) by using a rom encryption. for further information, please refer to the application note (anm031) available upon request. 80c32/80c52 rev. g (14 jan. 97) 10 matra mhs electrical characteristics absolute maximum ratings* ambiant temperature under bias : c = commercial 0 to 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i = industrial 40 to 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature 65 to + 150 . . . . . . . . . . . . . . . . . . . . . . . voltage on vcc to vss 0.5 v to + 7 v . . . . . . . . . . . . . . . . . . . . . . . . voltage on any pin to vss 0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . power dissipation 1 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . * this value is based on the maximum allowable die temperature and the thermal resistance of the package * notice stresses at or above those listed under a absolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. dc parameters ta = 0 c to 70 c ; vss = 0 v ; vcc = 5 v 10 % ; f = 0 to 44 mhz ta = 40 c + 85 c ; vss = 0 v ; vcc = 5 v 10 % ; f = 0 to 36 mhz symbol parameter min max unit test conditions vil input low voltage 0.5 0.2 vcc 0.1 v vih input high voltage (except xtal and rst) 0.2 vcc + 1.4 vcc + 0.5 v vih1 input high voltage (for xtal and rst) 0.7 vcc vcc + 0.5 v vol output low voltage (port 1, 2 and 3) 0.3 0.45 1.0 v v v iol = 100 m a iol = 1.6 ma (note 2) iol = 3.5 ma vol1 output low voltage (port 0, ale, psen ) 0.3 0.45 1.0 v v v iol = 200 m a iol = 3.2 ma (note 2) iol = 7.0 ma voh output high voltage port 1, 2, 3 vcc 0.3 v ioh = 10 m a vcc 0.7 v ioh = 30 m a vcc 1.5 v ioh = 60 m a vcc = 5 v 10 % voh1 output high voltage (port 0, ale, psen ) vcc 0.3 v ioh = 200 m a vcc 0.7 v ioh = 3.2 ma vcc 1.5 v ioh = 7.0 ma vcc = 5 v 10 % iil logical 0 input current (ports 1, 2 and 3) 50 m a vin = 0.45 v ili input leakage current 10 m a 0.45 < vin < vcc itl logical 1 to 0 transition current (ports 1, 2 and 3) 650 m a vin = 2.0 v ipd power down current 50 m a vcc = 2.0 v to 5.5 v (note 1) rrst rst pulldown resistor 50 200 kohm cio capacitance of i/o buffer 10 pf fc = 1 mhz, ta = 25 c icc power supply current freq = 1 mhz icc op icc idle freq = 6 mhz icc op icc idle freq 12 mhz icc op = 1.25 freq (mhz) + 5 ma icc idle = 0.36 freq (mhz) + 2.7 ma 1.8 1 10 4 ma ma ma ma vcc = 5.5 v 80c32/80c52 rev. g (14 jan. 97) 11 matra mhs absolute maximum ratings* ambient temperature under bias : a = automotive 40 to +125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature 65 to + 150 . . . . . . . . . . . . . . . . . . . . . . . voltage on vcc to vss 0.5 v to + 7 v . . . . . . . . . . . . . . . . . . . . . . . . voltage on any pin to vss 0.5 v to vcc + 0.5 v . . . . . . . . . . . . . . . power dissipation 1 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . * this value is based on the maximum allowable die temperature and the thermal resistance of the package * notice stresses above those listed under a absolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc parameters ta = 40 c + 125 c ; vss = 0 v ; vcc = 5 v 10 % ; f = 0 to 36 mhz symbol parameter min max unit test conditions vil input low voltage 0.5 0.2 vcc 0.1 v vih input high voltage (except xtal and rst) 0.2 vcc + 1.4 vcc + 0.5 v vih1 input high voltage (for xtal and rst) 0.7 vcc vcc + 0.5 v vol output low voltage (port 1, 2 and 3) 0.3 0.45 1.0 v v v iol = 100 m a iol = 1.6 ma (note 2) iol = 3.5 ma vol1 output low voltage (port 0, ale, psen ) 0.3 0.45 1.0 v v v iol = 200 m a iol = 3.2 ma (note 2) iol = 7.0 ma voh output high voltage port 1, 2 and 3 vcc 0.3 v ioh = 10 m a vcc 0.7 v ioh = 30 m a vcc 1.5 v ioh = 60 m a vcc = 5 v 10 % voh1 output high voltage (port 0, ale, psen ) vcc 0.3 v ioh = 200 ma vcc 0.7 v ioh = 3.2 ma vcc 1.5 v ioh = 7.0 ma vcc = 5 v 10 % iil logical 0 input current (ports 1, 2 and 3) 75 m a vin = 0.45 v ili input leakage current 10 m a 0.45 < vin < vcc itl logical 1 to 0 transition current (ports 1, 2 and 3) 750 m a vin = 2.0 v ipd power down current 75 m a vcc = 2.0 v to 5.5 v (note 1) rrst rst pulldown resistor 50 200 kohm cio capacitance of i/o buffer 10 pf fc = 1 mhz, ta = 25 c icc power supply current freq = 1 mhz icc op icc idle freq = 6 mhz icc op icc idle freq 12 mhz icc op = 1.25 freq (mhz) + 5 ma icc idle = 0.36 freq (mhz) + 2.7 ma 1.8 1 10 4 ma ma ma ma vcc = 5.5 v 80c32/80c52 rev. g (14 jan. 97) 12 matra mhs absolute maximum ratings* ambient temperature under bias : m = military 55 to +125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature 65 to + 150 . . . . . . . . . . . . . . . . . . . . . . . voltage on vcc to vss 0.5 v to + 7 v . . . . . . . . . . . . . . . . . . . . . . . . voltage on any pin to vss 0.5 v to vcc + 0.5 v . . . . . . . . . . . . . . . power dissipation 1 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . * this value is based on the maximum allowable die temperature and the thermal resistance of the package * notice stresses at or above those listed under a absolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. dc parameters ta = 55 c + 125 c ; vss = 0 v ; vcc = 5 v 10 % ; f = 0 to 36 mhz symbol parameter min max unit test conditions vil input low voltage 0.5 0.2 vcc 0.1 v vih input high voltage (except xtal and rst) 0.2 vcc + 1.4 vcc + 0.5 v vih1 input high voltage (for xtal and rst) 0.7 vcc vcc + 0.5 v vol output low voltage (port 1, 2 and 3) 0.45 v iol = 1.6 ma (note 2) vol1 output low voltage (port 0, ale, psen) 0.45 v iol = 3.2 ma (note 2) voh output high voltage (port 1, 2 and 3) 2.4 v ioh = 60 m a vcc = 5 v 10 % 0.75 vcc v ioh = 25 m a 0.9 vcc v ioh = 10 m a voh1 output high voltage (port 0 in external bus mode, ale, pen) 2.4 v ioh = 400 m a vcc = 5 v 10 % 0.75 vcc v ioh = 150 m a 0.9 vcc v ioh = 40 m a iil logical 0 input current (ports 1, 2 and 3) 75 m a vin = 0.45 v ili input leakage current +/ 10 m a 0.45 < vin < vcc itl logical 1 to 0 transition current (ports 1, 2 and 3) 750 m a vin = 2.0 v ipd power down current 75 m a vcc = 2.0 v to 5.5 v (note 1) rrst rst pulldown resistor 50 200 k w cio capacitance of i/o buffer 10 pf fc = 1 mhz, ta = 25 c icc power supply current freq = 1 mhz icc op icc idle freq = 6 mhz icc op icc idle freq 12 mhz icc op = 1.25 freq (mhz) + 5 ma icc idle = 0.36 freq (mhz) + 2.7 ma 1.8 1 10 4 ma ma ma ma vcc = 5.5 v 80c32/80c52 rev. g (14 jan. 97) 13 matra mhs absolute maximum ratings* ambient temperature under bias : c = commercial 0 to 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |