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MAX7472/max7473 hdtv anti-aliasing filters with triple-input mux ________________________________________________________________ maxim integrated products 1 ordering information 19-0619; rev 0; 8/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. continuously variable anti-aliasing filter 5mhz to 34mhz in 256 steps 3:1 input mux on each video filter supports all standard video and computer input formats 480i, 480p, 720p, 1080i qvga, vga, svga, xga, sxga, uxga y p b p r , gsbr, rgbhv, y/c, cvbs accepts any input sync format sync on y, sync on g, external sync (positive or negative) sync on all channels buffered outputs drive standard 150 ? video load 0db (MAX7472) +6db (max7473) dc- or ac-coupled outputs single +5v analog and +3.3v digital supplies 5mw power-down mode lead (pb)-free 28-pin tqfn package general description the MAX7472/max7473 triple-channel anti-aliasing fil- ters and buffers with triple-input mux are ideal for high- definition (hd) and standard-definition (sd) television (tv) applications. compatible with 1080i, 720p, 480p, and 480i scanning system standards as well as com- puter format signals, the MAX7472/max7473 support component video (y p b p r , gsbr, and rgbhv) as well as composite (cvbs) and s-video (y/c). the MAX7472/max7473 limit the input bandwidth for anti-aliasing and out-of-band noise reduction prior to digital conversion by an adc or video decoder. the frequency response of the MAX7472/max7473 can be continuously varied in 256 linear steps from below sd response to beyond hd response through an i 2 c ? inter- face. the adjustable cutoff frequency allows filter opti- mization for sampling rate and noise reduction. the MAX7472/max7473 also include 3:1 multiplexers for selection of three complete sets of video inputs through the i 2 c interface. the MAX7472/max7473 drive a 2v p-p video signal into a standard 150 ? load. the inputs are ac-coupled and the outputs can be either dc- or ac-coupled. the MAX7472 has a gain of 0db and the max7473 has a gain of +6db. both devices are available in a 28-pin tqfn package and are fully specified over the upper- commercial (0? to +85?) temperature range. features evaluation kit available note: all devices are specified over the 0? to +85? operat- ing temperature range. +indicates lead-free packaging. *ep = exposed pad. ** future product?ontact factory for availability. part pin-package pkg code buffer gain (db) MAX7472 uti+ 28 tqfn-ep* t2855-8 0 max7473 uti+** 28 tqfn-ep* t2855-8 +6 26 27 25 24 10 9 11 agnd inb2 inc2 agnd ina3 12 inc1 av dd av dd out3 out1 dv dd sda 12 agnd 4567 20 21 19 17 16 15 agnd ina1 syncb synca dgnd inc3 MAX7472 max7473 ina2 out2 3 18 28 + 8 inb1 inb3 a1 23 13 syncc a0 22 14 scl av dd tqfn 5mm x 5mm *exposed pad. top view ep* pin configuration hdtv (lcd, pdp, dlp, crt) set-top boxes personal video recorders home theaters applications ? purchase of i 2 c components from maxim integrated products, inc., or one of its sublicensed associated companies, conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. typical operating circuit appears at end of data sheet.
MAX7472/max7473 hdtv anti-aliasing filters with triple-input mux 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av dd = +5v ?%, dv dd = 2.7v to 3.6v, r load = 150 ? to agnd, c in = 0.1?, t a = 0? to +85?, unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to agnd .........................................................-0.3v to +6v dv dd to dgnd.........................................................-0.3v to +4v agnd to dgnd.....................................................-0.3v to +0.3v ina_, inb_, inc_ to agnd........................................................... ............................-0.3v to the lower of (av dd + 0.3v) and +6v out_ to agnd.?.-0.3v to the lower of (av dd + 0.3v) and +6v sync_, a_ to agnd..................................................................... ...............................-0.3v to the lower of (av dd + 0.3v) and +6v scl, sda to dgnd .................................................-0.3v to + 6v maximum current into any pin (except av dd , dv dd , and out) ...................................?0ma continuous power dissipation (t a = +70?) 28-pin tqfn (derate 34.5mw/? above +70?) ........2758mw operating temperature range.............................. 0? to +85? storage temperature range ............................-65? to +150? junction temperature ......................................................+150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units hd: f = 100khz to 30mhz, relative to 100khz (note 1) -3 -0.6 +1 filter passband response a pb sd: f = 100khz to 5.75mhz, relative to 100khz (note 2) ?.1 ?.0 db hd: f = 74mhz (note 1) 57 filter stopband attenuation a sb sd: f = 27mhz (note 2) 63 db hd: 100khz to 30mhz, relative to 100khz (note 1) 20 group-delay deviation ? t g sd: 100khz to 5.75mhz, relative to 100khz (note 2) 15 ns hd: channel to channel, 100khz to 2mhz (note 1) 5 group-delay matching t g ( match ) sd: channel to channel, 100khz to 500khz (note 2) 1.5 ns bypass frequency response -3db, bypass mode, independent of filter setting 100 mhz sd differential gain dg 5-step modulated staircase (note 2) 0.25 % sd differential phase d 5-step modulated staircase (note 2) 0.25 d egr ees signal-to-noise ratio snr output signal (2v p-p ) to rms noise (100khz to 30mhz) (note 1) 69 db sd line-time distortion h dist deviations in a line with an 18?, 100 ire bar, 1 line = 63.5? (note 2) 0.3 % sd field-time distortion v dist deviations in 130 lines with 18?, 100 ire bars (note 2) 0.3 %
MAX7472/max7473 hdtv anti-aliasing filters with triple-input mux _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd = +5v ?%, dv dd = 2.7v to 3.6v, r load = 150 ? to agnd, c in = 0.1?, t a = 0? to +85?, unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units positive 350 clamp settling time to 1% with 100 ire step (note 3) negative 650 h minimum functional input sync amplitude 125 mv t a = +25?, MAX7472 (note 1) -0.5 0 +0.5 low-frequency gain t a = +25?, max7473 (note 1) 5.5 6 6.5 db low-frequency gain matching 100khz 0.05 db MAX7472 2.4 maximum input voltage amplitude max7473 1.2 v p-p maximum output voltage amplitude dc to 30mhz 2.4 v p-p output clamping level variation (notes 1, 4) ?20 mv mux crosstalk -80 db channel-to-channel isolation 62 db power-supply rejection ratio psrr 50 db digital inputs (a1, a0, sync_) input logic high voltage v ih 2.0 v input logic low voltage v il 0.8 v input leakage current i in v in = 0 to dv dd ? ?0 ? input capacitance c in 6pf digital inputs (sda, scl) input logic high voltage v ih 0.7 x dv dd v input logic low voltage v il 0.3 x dv dd v input hysteresis v hyst 0.05 x dv dd v input leakage current i in v in = 0 to dv dd ?.1 ?0 ? input capacitance c in 6pf digital output (sda) output logic low voltage v ol i sink = 3ma 0.4 v tri-state leakage current i l v in = 0 to dv dd ?.1 ?0 ? tri-state output capacitance c out 6pf power requirements analog supply voltage range av dd 4.75 5 5.25 v digital supply voltage range dv dd 2.7 3.3 3.6 v normal operation, no load 180 200 analog supply current i avdd power-down mode, no load 1 1.5 ma digital supply current i dvdd 25 ?
MAX7472/max7473 hdtv anti-aliasing filters with triple-input mux 4 _______________________________________________________________________________________ timing characteristics (av dd = +5v ?%, dv dd = 2.7v to 3.6v, t a = 0? to +85?, unless otherwise noted. typical values are at t a = +25?.) (figure 1) parameter symbol conditions min typ max units serial clock frequency f scl 0 400 khz bus free time between stop (p) and start (s) conditions t buf 1.3 ? hold time (repeated) start (sr) condition t hd;sta after this period, the first clock pulse is generated 0.6 ? scl pulse-width low t low 1.3 ? scl pulse-width high t high 0.6 ? setup time for a repeated start (sr) condition t su;sta 0.6 ? data hold time t hd;dat (note 5) 0 0.9 ? data setup time t su;dat 100 ns rise time of both sda and scl signals, receiving t r 0 300 ns fall time of both sda and scl signals, receiving t f 0 300 ns fall time of sda signal, transmitting t f (note 6) 20 + 0.1c b 300 ns setup time for stop (p) condition t su;sto 0.6 ? capacitive load for each bus line c b 400 pf pulse width of spikes suppressed by the input filter t sp (note 7) 0 50 ns note 1: the filter passband edge is set to code 255. note 2: the filter passband edge is set to code 40. note 3: 1h is the total line period, depending on the video standard. for ntsc, this is 63.5?, for hdtv, the line period is 29.64?. note 4: the clamp level is at the sync tip for signals with sync pulses, and is at the blanking level otherwise. note 5: a master device must provide a hold time of at least 300ns for the sda signal (referred to v il of the scl signal) to bridge the undefined region of scl? falling edge. note 6: c b = total capacitance of one bus line in pf. t r and t f measured between 0.3v dd and 0.7v dd . note 7: input filters on the sda and scl inputs suppress noise spikes less than 50ns. sda scl t r t f s r t sp t r ps t low t hd;sta t hd;dat t su;sta t high t su;dat t hd;sta t su;sto t buf t f s figure 1. 2-wire serial-interface timing diagram
MAX7472/max7473 hdtv anti-aliasing filters with triple-input mux _______________________________________________________________________________________ 5 -80 -60 -70 -30 -40 -50 0 -10 -20 10 0.1 10 1 100 1000 frequency response (MAX7472) MAX7472/73 toc01 frequency (mhz) response (db) code 40 code 90 code 220 code 255 -40 -50 -60 -70 -30 -10 -20 0 10 0.1 10 1 100 1000 frequency response (max7473) MAX7472/73 toc02 frequency (mhz) response (db) code 40 code 90 code 220 code 255 -1.5 -2.0 -2.5 -3.0 -1.0 0 -0.5 0.5 1.0 0.1 10 1100 passband flatness (MAX7472) MAX7472/73 toc03 frequency (mhz) response (db) code 40 code 255 code 220 code 90 4.5 4.0 3.5 3.0 5.0 6.0 5.5 6.5 7.0 0.1 10 1 100 passband flatness (max7473) MAX7472/73 toc04 frequency (mhz) response (db) code 40 code 255 code 220 code 90 40 30 20 10 0 50 70 60 80 90 0.1 1 10 100 group delay MAX7472/73 toc05 frequency (mhz) delay (ns) sd hd 2t response (1 ire = 7.14mv) MAX7472/73 toc06 100ns/div modulated 12.5t response MAX7472/73 toc07 400ns/div 0.2 0.3 0.1 0 -0.1 -0.2 -0.3 -0.2 differential gain differential phase -0.1 differential phase ( ) differential gain (%) 0.1 0.2 0 MAX7472/73 toc08 134 2567 -3db frequency vs. control code control code measured cutoff frequency (mhz) MAX7472/73 toc09 0 51 102 153 204 255 5 10 15 20 25 30 35 typical operating characteristics (av dd = +5v, dv dd = 3.3v, r load = 150 ? to gnd, c in = 0.1?, t a = +25?.)
MAX7472/max7473 hdtv anti-aliasing filters with triple-input mux 6 _______________________________________________________________________________________ -40 -10 -15 -20 -25 -30 -35 0 -5 5 10 0.1 10 1 100 1000 bypass-mode frequency response MAX7472/73 toc10 frequency (mhz) response (db) max7473 MAX7472 0 4 12 8 16 20 0.1 10 1100 bypass-mode group delay MAX7472/73 toc11 frequency (mhz) delay (ns) typical operating characteristics (continued) (av dd = +5v, dv dd = 3.3v, r load = 150 ? to gnd, c in = 0.1?, t a = +25?.) pin description pin name function 1 inc1 channel c input 1. ac-couple inc1 with a series 0.1? capacitor. 2, 6, 25, 26 agnd analog ground. connect all agnd pins to the ground plane. see the power-supply bypassing and layout considerations section. 3 ina2 channel a input 2. ac-couple ina2 with a series 0.1? capacitor. 4 inb2 channel b input 2. ac-couple inb2 with a series 0.1? capacitor. 5 inc2 channel c input 2. ac-couple inc2 with a series 0.1? capacitor. 7 ina3 channel a input 3. ac-couple ina3 with a series 0.1? capacitor. 8 inb3 channel b input 3. ac-couple inb3 with a series 0.1? capacitor. 9 inc3 channel c input 3. ac-couple inc3 with a series 0.1? capacitor. 10 dgnd digital ground. see the power-supply bypassing and layout considerations section. 11 synca channel a external sync input. connect to ground if not used. 12 syncb channel b external sync input. connect to ground if not used. 13 syncc channel c external sync input. connect to ground if not used. 14 scl i 2 c-compatible serial clock input 15 sda i 2 c-compatible serial data input/output 16 dv dd digital power supply. bypass to dgnd with a 0.1? capacitor. see the power-supply bypassing and layout considerations section. 17 out3 video output 3. out3 can be either ac- or dc-coupled. 18, 20, 22 av dd analog power supply. bypass each av dd input to agnd using a 0.1? capacitor. see the power- supply bypassing and layout considerations section.
MAX7472/max7473 hdtv anti-aliasing filters with triple-input mux _______________________________________________________________________________________ 7 pin description (continued) pin name function 19 out2 video output 2. out2 can be either ac- or dc-coupled. 21 out1 video output 1. out1 can be either ac- or dc-coupled. 23 a0 address bit 0 24 a1 address bit 1 27 ina1 channel a input 1. ac-couple ina1 with a series 0.1? capacitor. 28 inb1 channel b input 1. ac-couple inb1 with a series 0.1? capacitor. ?p exposed pad. the exposed pad is located on the package bottom and is internally connected to agnd. connect ep to the analog ground plane. do not route any pc board traces under the package. see the power-supply bypassing and layout considerations section. clamp level input signal format channel 1 channel 2 channel 3 y p b p r low high high gsbr low high high cvbs y c low low high y p b p r (sync on all signals) low low low r g b h v high high high detailed description the MAX7472/max7473 are complete video anti-alias- ing solutions ideal for fixed-pixel hdtv display tech- nologies such as plasma and lcd, which digitize the input video signal and then scale the resolution to match the native pixel format of the display. with a soft- ware-selectable corner frequency ranging from 5mhz to 34mhz, the MAX7472/max7473 support both sd and hd video signals including 1080i, 720p, 720i, 480p, and 480i. higher bandwidth computer resolution signals are also supported. integrated lowpass filters limit the analog video input bandwidth for anti-aliasing and out-of-band noise reduction prior to sampling by an adc or video decoder. by allowing the corner frequency to be adjust- ed from below sd resolution to beyond hd resolutions in 256 steps, the filter? corner frequency can be opti- mized dynamically for a specific input video signal and the sampling frequency of the adc or video decoder. the MAX7472/max7473 provide a filter-bypass mode to support applications requiring a passband greater than 34mhz. an i 2 c interface allows a microcontroller to configure the MAX7472/max7473s?performance and functionality including the mux, the clamp voltage, the filter? corner frequency, the sync source (internal/external), and filter bypassing. the typical operating circuit shows the block diagram and typical external connections of the MAX7472/ max7473. sync detector and clamp levels the MAX7472/max7473 use a video clamp circuit to establish a dc offset for the incoming video signal after the ac-coupling capacitor. this video clamp sets the dc bias level of the circuit at the optimum operating point. the MAX7472/max7473 support both internal and external sync detection. selection of internal vs. exter- nal detection is achieved by programming the com- mand byte (see table 3). after extracting the sync information from channel 1 or an external sync (synca, syncb, or syncc), the MAX7472/max7473 clamp the video signal during the sync tip portion of the video. select one of two possible clamp levels according to the input signal format. use the low level when the input signal contains sync information such as y (luma) or cvbs signals. use the high level for bipolar signals such as c (chroma) or p b /p r . see table 1. table 1. clamp levels
MAX7472/max7473 component/composite selection the MAX7472/max7473 accept component or com- posite inputs. the sync detection path provides an additional selectable color burst filter to improve sync detection. external sync detection when filtering a video signal without embedded sync information, such as computer formats (rgbhv) with separate sync signals, use the external sync mode (see table 3) and apply the horizontal sync source to the synca, syncb, or syncc pin. the sync detector determines when the clamp circuit is turned on. the MAX7472/max7473 can detect positive or nega- tive polarity external syncs with ttl logic levels. use the i 2 c interface to program the polarity of the external sync signal. filter the internal video filter delivers an optimized response with a steep transition band to achieve a wide pass- band along with excellent stopband rejection. in addi- tion, the filter is optimized to provide an excellent time- domain response with low overshoot. setting the filter frequency the frequency response (-3db cutoff frequency) of the filter in the MAX7472/max7473 can be varied from less than the sd passband to beyond the hd passband in 256 linear steps through the i 2 c interface. use the com- mand byte to write to the frequency register followed by the 8-bit data word that corresponds to the desired frequency. see table 6. the frequency register sets the -3db point. set this fre- quency accordingly to achieve the desired flat pass- band response. optimizing the frequency response select the frequency according to the resolution of the video-signal format. high-definition signals require higher bandwidth and standard-definition signals require less bandwidth. the actual bandwidth con- tained in the video signal is a function of the visual res- olution of the signal. this bandwidth is typically less than what is indicated by the format resolution (1080i, 720p, 480p, and 480i). for more information on this topic, see application note 750: bandwidth vs. video resolution on the maxim website (www.maxim-ic.com). see table 6. the frequency response can be optimized to improve the overall performance. there are a number of consid- erations, one of the most important being the sampling rate of the subsequent adc or video decoder in the system. in oversampled systems, the sampling rate is significantly more than the desired passband response. the extra frequency span between the passband and the sampling rate contains noise that can be eliminated by setting the corner frequency of the filter to just pass the desired bandwidth. this results in a higher signal- to-noise ratio of the overall system. filter bypass the MAX7472/max7473 offer selectable filter bypass- ing that allows the input video signals to bypass the internal filters reaching the output buffers unfiltered. the filter-bypass mode is enabled/disabled through the command byte (see table 3). output buffer each output buffer can drive a 2v p-p signal into a 150 ? video load. the MAX7472/max7473 can drive a dc- or ac-coupled load. the output dc level is controlled to limit the dc voltage on the cable so that the blanking level of the video signal is always less than 1v, meeting the digital tv specification. as a result, output ac-cou- pling capacitors can be eliminated when driving a cable, thus eliminating the normal adverse effects caused by these capacitors such as line- and field-time distortion, otherwise known as droop. see the output considerations section for more information. gain options the MAX7472 features an overall gain of 0db, while the max7473 features an overall gain of +6db. use the +6db option (max7473) when driving a back-matched cable. use the 0db option (MAX7472) when driving an adc or video decoder with an input range the same as the input to the MAX7472. to add flexibility, the MAX7472 accepts input signals up to 2v p-p , twice the standard video-signal range. output clamp level the MAX7472/max7473 output can be dc- or ac-cou- pled. the nominal output clamp level in the dc-cou- pled case depends on the clamp voltage setting and can be determined according to table 2. hdtv anti-aliasing filters with triple-input mux 8 _______________________________________________________________________________________ table 2. output clamp level clamp setting output clamp level (mv) (typ) low ?00 high ?00
as shown in the sync detector and clamp levels sec- tion, the low clamp level is used for signals with sync information and determines the voltage level of the sync tip, while the high clamp level is used for signals without sync information and sets the blanking level. the absolute voltage level of the output signal is rela- tive to the output clamp level. a video signal containing sync information (i.e., cvbs or y) is unipolar above the clamp level and conversely, a video signal without sync (i.e., p b , p r , or c) is bipolar around the clamp level. multiplexers the MAX7472/max7473 provide four 3:1 multiplexers programmable through the i 2 c interface to select which of three separate channels (channels a, b, c) is to be connected to each video input. the fourth multiplexer is used in conjunction with external sync detection and determines which channel? external sync is to be con- nected to the external sync input. see table 3 and the serial interface section for more information on how to select a particular channel. after selecting a channel with a command byte, bits cs7 and cs6 of the channel selection register reflect the channel setting (table 7). power-down mode the MAX7472/max7473 include a power-down mode that reduces the supply current from 180ma (typ) to 1ma (typ) by powering down the analog circuitry. the i 2 c interface remains active allowing the device to return to full-power operation. the clamp settling time (see the electrical characteristics table) limits the wake-up time of the MAX7472/max7473. after exiting the power-down mode, the MAX7472/max7473 resume normal operation using the settings stored prior to power-down. the command byte controls the power- down and wake-up modes (see table 3). a software reset sets the control/status register to its default con- ditions. the frequency register and the channel selection register are not affected. power-on reset (por) the MAX7472/max7473 include a power-on reset (por) circuit that resets the internal registers and i 2 c interface to their default condition (see tables 4?). serial interface the MAX7472/max7473 feature an i 2 c-compatible, 2-wire serial interface consisting of a bidirectional serial data line (sda) and a serial clock line (scl). sda and scl facilitate bidirectional communication between the MAX7472/max7473 and the master at rates up to 400khz. once a command byte is written to the MAX7472/ max7473, the command interpreter changes the control/status register and the channel selection regis- ter accordingly. see the control/status register and channel-selection register sections for more informa- tion. the command interpreter also controls access to the frequency register (see the command byte (write cycle) section). the MAX7472/max7473 are transmit/receive slave-only devices, relying upon a master to generate a clock sig- nal. the master (typically a microcontroller) initiates data transfer on the bus and generates scl. a master device communicates to the MAX7472/ max7473 by transmitting the proper address (see the slave address section) followed by a command and/or data words. each transmit sequence is framed with a start (s) or repeated start (sr) condition and a stop (p) condition. the sda driver is an open-drain output, requiring a pullup resistor (2.4k ? or greater) to generate a logic- high voltage. optional resistors (24 ? ) in series with sda and scl protect the device inputs from high-volt- age spikes on the bus lines. series resistors also mini- mize crosstalk and undershoot of the bus signals. bit transfer each scl rising edge transfers 1 data bit. nine clock cycles are required to transfer the data into or out of the MAX7472/max7473. the data on sda must remain stable during the high period of the scl clock pulse. changes in sda while scl is high are read as control signals (see the start and stop conditions section). when the serial interface is inactive, sda and scl idle high. start and stop conditions a master device initiates communication by issuing a start condition (s), a high-to-low transition on sda with scl high (figure 2). the master terminates transmission by a stop condition (p) (see the acknowledge bit (ack) and not-acknowledge bit (nack) section). a stop con- dition is a low-to-high transition on sda while scl is high (figure 2). the stop condition frees the bus. if a repeat- ed start condition (s r ) is generated instead of a stop condition, the bus remains active. when a stop condi- tion or incorrect address is detected, the MAX7472/ max7473 then ignore all communication on the i 2 c bus until the next start or repeated start condition, minimizing digital noise and feedthrough. MAX7472/max7473 hdtv anti-aliasing filters with triple-input mux _______________________________________________________________________________________ 9
MAX7472/max7473 early stop conditions the MAX7472/max7473 recognize a stop condition at any point during transmission except when a stop condition occurs in the same high pulse as a start condition (figure 3). this condition is not a legal i 2 c format; at least one clock pulse must separate any start and stop conditions. the MAX7472/max7473 discard any data received during a data transfer abort- ed by an early stop condition. repeated start (s r ) conditions an s r condition is used to indicate a change in direc- tion of data flow (see the read cycle section). s r can also be used when the bus master is writing to several i 2 c devices and does not want to relinquish control of the bus. the MAX7472/max7473 serial interface sup- ports continuous write operations with (or without) an s r condition separating them. acknowledge bit (ack) and not-acknowledge bit (nack) successful data transfers are acknowledged with an acknowledge bit (ack) or a not-acknowledge bit (nack). both the master and the MAX7472/max7473 (slave) generate acknowledge bits. to generate an acknowledge, the receiving device must pull sda low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse (figure 4). to generate a not acknowl- edge, the receiver allows sda to be pulled high before the rising edge of the acknowledge-related clock pulse (ninth pulse) and leaves it high during the high period of the clock pulse. monitoring the acknowledge bits allows for detection of unsuccessful data transfers. an unsuc- cessful data transfer happens if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the master should reattempt communication at a later time. the MAX7472/max7473 generate an acknowledge bit when receiving an address or data by pulling sda low during the ninth clock pulse. when transmitting data during a read, the MAX7472/max7473 do not drive sda during the ninth clock pulse (i.e., the external pullups define the bus as a logic high) so that the receiver of the data can pull sda low to acknowledge receipt of data. slave address a bus master initiates communication with a slave device by issuing a start condition followed by the 7-bit slave address (figure 5). when idle, the MAX7472/max7473 wait for a start condition followed by its slave address. the serial interface compares each address bit by bit, allowing the interface to power down and disconnect from scl immediately if an incorrect address is detect- ed. after recognizing a start condition followed by the correct address, the MAX7472/max7473 are ready to accept or send data. the least significant bit (lsb) of the address byte (r/ w ) determines whether the master is writing to or reading from the MAX7472/max7473 (r/ w = 0 selects a write condition, r/ w = 1 selects a read condi- hdtv anti-aliasing filters with triple-input mux 10 ______________________________________________________________________________________ scl sda sp s r start start stop illegal stop legal stop condition illegal stop condition scl sda scl sda figure 2. start/stop conditions figure 3. early stop conditions 189 s sda scl not acknowledge acknowledge figure 4. acknowledge and not-acknowledge bits
tion). after receiving the proper address, the MAX7472/max7473 (slave) issue an ack by pulling sda low for one clock cycle. the MAX7472/max7473 slave address consists of 5 fixed bits a6?2 (set to 10010) followed by 2 pin-pro- grammable bits a1 and a0. the most significant address bit (a6) is transmitted first, followed by the remaining bits. addresses a1 and a0 can also be driven dynami- cally if required, but the values must be stable when they are expected in the address sequence. command byte (write cycle) a write cycle begins with the bus master issuing a start condition followed by 7 address bits (figure 5) and a write bit (r/ w = 0). after successfully receiving its address, the MAX7472/max7473 (slave) issue an ack. the MAX7472/max7473 recognize the next byte after a successfully received address as the command byte (table 3). use the command byte to configure the MAX7472/ max7473. while most of the commands listed in table 3 modify the functionality of the MAX7472/ max7473, some commands prepare the device for fur- ther data transfers (see the control/status register , frequency register , and channel-selection register sections.) when the write cycle is prematurely aborted, the register is not updated. figures 6 and 7 show examples of write sequences. MAX7472/max7473 hdtv anti-aliasing filters with triple-input mux ______________________________________________________________________________________ 11 sda scl 1 0 1 0 a1 a0 0 r/w msb lsb ack figure 5. slave-address byte definition sda scl 1 0 0 1 0 a1 a0 r/w c7 c6 c5 c4 c3 c2 c1 c0 ack ack out in out in to MAX7472/max7473 sda (cont) sda direction sda direction scl (cont) f7 f6 f5 f4 f3 f2 f1 ack out f0 in in start stop command word c7?0 is 00010010. 00010010 figure 6. write sequence to update the frequency register
MAX7472/max7473 hdtv anti-aliasing filters with triple-input mux 12 ______________________________________________________________________________________ command byte: individual bit definitions c7 c6 c5 c4 c3 c2 c1 c0 description 0 0 0 0 0 0 0 0 power-down. 00000001 wake-up; resume normal operation using the frequency/status previously stored (unless power has been cycled). 0 0 0 0 0 0 1 0 set clamp voltage level for in1 to low. 0 0 0 0 0 0 1 1 set clamp voltage level for in1 to high. 0 0 0 0 0 1 0 0 set clamp voltage level for in2 to low. 0 0 0 0 0 1 0 1 set clamp voltage level for in2 to high. 0 0 0 0 0 1 1 0 set clamp voltage level for in3 to low. 0 0 0 0 0 1 1 1 set clamp voltage level for in3 to high. 0 0 0 0 1 0 0 0 select component input, color-burst filter disabled. 0 0 0 0 1 0 0 1 select composite input, color-burst filter enabled. 0 0 0 0 1 0 1 0 select internal sync. 0 0 0 0 1 0 1 1 select external sync. 0 0 0 0 1 1 0 0 select positive polarity for the external sync. 0 0 0 0 1 1 0 1 select negative polarity for the external sync. 0 0 0 0 1 1 1 0 enable filters. 0 0 0 0 1 1 1 1 disable filters. enter bypass mode. 00010000 reset status to the default status as outlined in the control/status register table. this command does not affect the frequency register and the channel selection register. 00010001 request reading the control/status register. the interface expects an s r condition to follow with address and read/write set to read so that data can be driven onto the bus. 0 0 0 1 0 0 1 0 load the frequency register with the data byte following the command word. 00010011 request reading the frequency register. the interface expects an s r condition to follow with address and read/write set to read so that data can be driven onto the bus. 0 0 0 1 0 1 0 0 select input a. 0 0 0 1 0 1 0 1 select input b. 0 0 0 1 0 1 1 0 select input c. 00010111 request reading the channel selection register. the interface expects an s r condition to follow with address and read/write set to read so that data can be driven onto the bus. table 3. command byte definition
read cycle in read mode (r/ w = 1), the MAX7472/max7473 write the contents of the status, channel selection, or frequency register to the bus. when the command byte indicates a read operation of either the status or the frequency register, the serial interface expects an sr condition to follow the command byte. after sending an sr, the master sends the MAX7472/max7473 slave address byte followed by the r/ w bit (set to 1 to indi- cate a read). the slave device (MAX7472/max7473) generates an ack for the second address word and immediately after the ack clock pulse, the direction of data flow reverses. the slave (MAX7472/max7473) then transmits 1 byte of data containing the value of the register that was selected in the command byte. figure 8 shows a basic read sequence. note: to read the contents of the status, channel selection, or frequency register, the master must first write a command byte, requesting to read the status, channel selection, or frequency register. MAX7472/max7473 hdtv anti-aliasing filters with triple-input mux ______________________________________________________________________________________ 13 sda scl 1 0 0 1 0 a1 a0 r/w c7 c6 c5 c4 c3 c2 c1 c0 ack ack out in in out in to MAX7472/max7473 command bite is for power-down. sda direction start 00000000 stop figure 7. write sequence for a command bite r/w sda scl 1 0 0 1 0 a1 a0 r/w c7 c6 c5 c4 c3 c2 c1 c0 ack ack ack out in out in to MAX7472/max7473 sda (cont) sda direction sda direction scl (cont) d7 1 d6 d5 d4 d3 d2 d1 ack out d0 00 0 1 a1 a0 in in start sr stop 0 0 0 1 0 0 1/0 1 figure 8. basic read sequence
MAX7472/max7473 control/status register the MAX7472/max7473 store their status in an 8-bit register that can be read back by the master. the indi- vidual bits of the control/status register are summa- rized in tables 4 and 5. the power-on default value of this register is 03h. frequency register the frequency response (-3db passband edge) of the MAX7472/max7473 can be continuously varied in 256 linear steps by changing the codes in the frequency register (table 6). see the command byte ( write cycle) section for a write sequence to update the frequency register. hdtv anti-aliasing filters with triple-input mux 14 ______________________________________________________________________________________ table 4. control/status register table 5. control/status register bit description control/status register s7 s6 s5 s4 s3 s2 s1 s0 bit description s7 0 = component input signal selected (default). 1 = composite input signal selected. s6 0 = internal sync enabled (default). 1 = external sync enabled. s5 0 = external sync: positive polarity (default). 1 = external sync: negative polarity. s4 0 = normal operation mode (default). 1 = power-down mode. s3 0 = filters enabled (default). 1 = bypass mode?o filtering. s2 0 = clamp voltage for in1 set to low (default). 1 = clamp voltage for in1 set to high. s1 0 = clamp voltage for in2 set to low. 1 = clamp voltage for in2 set to high (default). s0 0 = clamp voltage for in3 set to low. 1 = clamp voltage for in3 set to high (default). table 6. suggested frequency register setting for various video-signal formats video-signal format f7 f6 f5 f4 f3 f2 f1 f0 code number approximate frequency (-3db) (mhz) standard-definition interlaced 00101000 40 10 standard-definition progressive 01011010 90 15 high-definition low bandwidth 11011100 220 30 high-definition high bandwidth 11111111 255 34 (default)
channel-selection register the MAX7472/max7473 store channel selection in an 8-bit register that can be read back by the master. the individual bits of the channel selection register are summarized in table 7. the power-on default selects channel a. i 2 c compatibility the MAX7472/max7473 are compatible with existing i 2 c systems supporting standard i 2 c 8-bit communica- tions. the general call address is ignored, and cbus formats are not supported. the devices?address is compatible with 7-bit i 2 c addressing protocol only. ten-bit address formats are not supported. applications information input considerations use 0.1? ceramic capacitors to ac-couple the inputs. the input cannot be dc-coupled. the internal clamp circuit stores a dc voltage across the input capacitors to obtain the appropriate output dc voltage level. increasing the value of these capacitors to improve line-time distortion is not necessary due to the extreme- ly low input leakage current yielding a very low line-time distortion performance. the MAX7472/max7473 provide a high input imped- ance to allow a nonzero source impedance to be used such as when the input is connected directly to a back- matched video cable, ensuring the external resistance determines the termination impedance. output considerations the MAX7472/max7473 outputs can be dc- or ac- coupled. the max7473, with +6db gain, is typically connected to a 75 ? series back-match resistor fol- lowed by the video cable. because of the inherent divide-by-two of this configuration, the blanking level of the video signal is always less than 1v, which complies with digital tv requirements. the MAX7472, with 0db gain, is typically connected to an adc or video decoder. this can be a dc or ac con- nection. if a dc connection is used, ensure that the dc input requirements of the adc or video decoder are compatible. when using an ac connection, choose an ac-coupling capacitor value that ensures that the lowest frequency content in the video signal is passed and the line-time distortion is kept within desired limits. the selection of this value is a function of the input impedance and more importantly, the input leakage of the circuit being driven. use a video clamp to reestablish the dc level if not already included in the subsequent circuit. the outputs of the MAX7472/max7473 are fully protect- ed against short-circuit conditions either to ground or to the positive supply of the device. MAX7472/max7473 hdtv anti-aliasing filters with triple-input mux ______________________________________________________________________________________ 15 table 7. channel-selection register channel-selection register cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 description 00xxxxxxchannel a selected (defau lt). 01xxxxxx channel b selected. 10xxxxxx channel c selected. x = don? care.
MAX7472/max7473 power-supply bypassing and layout considerations the MAX7472/max7473 operate from a single +5v analog supply and +3.3v digital supply. bypass each av dd to agnd with a 0.1? capacitor with an addition- al 1? capacitor in parallel for low-frequency decou- pling. determine the proper power-supply bypassing necessary by taking into account the desired distur- bance level tolerable on the output, the power-supply rejection of the MAX7472/max7473, and the amplitude and frequency of the disturbance signals present in the vicinity of the MAX7472/max7473. use an extensive ground plane to ensure optimum performance. the three av dd inputs (pins 18, 20, and 22) that supply the individual channels can be connected together and bypassed as one provided the components are close to the pins. bypass dv dd to dgnd with a 0.1? capac- itor. connect all ground pins to a low-impedance ground plane as close to the device as possible. place the input termination resistors as close to the device as possible. alternatively, the terminations can be placed further from the device if the pc board traces are designed to be a controlled impedance of 75 ? . minimize parasitic capacitance as much as possi- ble to avoid performance degradation in the upper fre- quency range possible with the MAX7472/max7473. refer to the MAX7472/max7473 evaluation kit for a proven pc board layout. exposed pad and heat dissipation the MAX7472/max7473 tqfn package provides an exposed pad on the bottom side of the package. this pad is electrically connected to agnd and must be soldered to the ground plane for proper thermal con- ductivity. do not route any pc board traces under the package. the MAX7472/max7473 typically dissipate 900mw of power; therefore, pay attention to heat dispersion. use at least a two-layer board with a good ground plane. to maximize heat dispersion, place copper directly under the MAX7472/max7473 package to match the outline of the plastic encapsulated area. repeat the same with the bottom ground plane layer and place as many vias as possible connecting the top and layers to thermally connect to the ground plane. maxim has evaluated a four-layer board using fr-4 material and 1oz copper with equal areas of metal on the top and bottom side coincident with the plastic encapsulated areas of the package. the two middle layers are used as power and ground planes. the board has 21, 15-mil, plated-through via holes between top, bottom, and ground plane layers. thermocouple measurements confirm device temperatures to be safe- ly within maximum limits. hdtv anti-aliasing filters with triple-input mux 16 ______________________________________________________________________________________
MAX7472/max7473 hdtv anti-aliasing filters with triple-input mux ______________________________________________________________________________________ 17 programmable lpf filter 5mhz?4mhz MAX7472 (max7473) adc clamp out1 2 out2 bypass clamp level out3 i 2 c interface 0.1 f 0.1 f 0.1 f 0.1 f programmable lpf filter 5mhz?4mhz adc clamp/ bias 0db (6db) buffer 0db (6db) buffer 0db (6db) buffer programmable lpf filter 5mhz?4mhz adc clamp/ bias scl agnd ina1 av dd ina2 ina3 hd vga sd synca inb1 inb2 inb3 syncb inc1 inc2 inc3 syncc dgnd sda a1 a0 mux mux ext sync enable mux mux 3 dv dd () indicates the max7473 typical operating circuit chip information process: bicmos
MAX7472/max7473 hdtv anti-aliasing filters with triple-input mux 18 ______________________________________________________________________________________ 24l qfn thin.eps package outline, 21-0139 2 1 e 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)
MAX7472/max7473 hdtv anti-aliasing filters with triple-input mux maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 19 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. package outline, 21-0139 2 2 e 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)

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