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| T6K41 2002-01-08 1 toshiba cmos digital integrated circuit silicon monolithic T6K41 column and row driver lsi for a dot matrix graphic lcd the T6K41 is a driver for a small-to-medium-sized dot matrix graphic lcd, especially for four-gray-scale monochromatic stn lcds. this driver can be interfaced to the mpu via an 8-bit (80/68-series) or a serial interface, and is operated asynchronously with the mpu. since the T6K41 contains a cr oscillator, it can generate the timing signals required for the lcd. the T6K41 has 128 outputs for the lcd drive (segment) signals that constitute the display data, 128 outputs for the lcd drive (common) signals that constitute the scanning signals and 16 bits of static-lcd drive (icon) signals. furthermore, the T6K41 has 128 128 2 bits display ram and 16-bit register. thus, this single device allows you to drive an lcd panel comprised of up to 128 128 + 16 dots with a minimize of power requirement. it also incorporates a gray-scale function. the display ram of the T6K41 is a two-port ram so that the mpu access it without any wait time. to minimize power consumption, the T6K41 has a display change mode (power save mode) in which only a 16-dot icon can be displayed. furthermore, it has various built-in analog circuits such as a voltage regulator, voltage divider resistors, power supply op-amp, dc-dc converters (2 to 6) and a contrast control (electronic volume) circuit. all these circuits enable the lcd panel to be driven with a single power supply. tcp (tape carrier package) lead pitch in out T6K41 unit: mm please contact your nearest toshiba dealer for individual package dimensions. no idea preliminar y
T6K41 2002-01-08 2 features lcd drive outputs : 128 rows (common) 128 columns (segment) + 16 icons display ram : 128 128 2 = 32,768 bits, 2-port ram gray scales : 4 gray-scale levels (palette function) word length : 8-bit/word display duty cycle : 1/72, 1/80, 1/100 or 1/128 duty during normal mode. (duty cycles in normal mode are set in software by the mpu.) display modes : normal mode: full display power save mode: icon display partial display mode: partial display standby mode: clock stopped (all internal circuits turned off) mpu : 8-bit (68/80 series) parallel or serial interface oscillator : built-in cr oscillator with external resistors power supply circuits : resistors to divide bias voltage, op-amp for lcd drive power supply, dc-dc converters (2 to 6), contrast control circuit. operating voltage : v dd = 2.4 v to 3.3 v, v in = 2.7 v to 3.3 v lcd drive voltage : v cc = 16.5 v (max) v out = 15.4 v (typ.) or v out = 13.0 v (typ.) (for internal voltage regulator) these voltages can be selected in software. cmos process low power consumption : i ss = 300 a (typ.) conditions: v dd = v in = 3.0 v, when dc-dc converter is used (6 mode), lcd non-loaded, ta = 25c, 1/128 duty, 1/12 bias, fosc = 82 khz (when internal oscillator is used), voltage regulator on, op-amp on, display data = all 4-gray-scale checker pattern, no data access from mpu. temperature coefficient of voltage regulator: ? 0.05%/c package : product package T6K41 (, ) tcp (tape carrier package) jbT6K41-as gold bump chip T6K41 2002-01-08 3 block diagram m/s blnk sync ck cl pm fr stb lcd driver circuit(128) com1 seg1 com64 seg128 display ram128 128 2 32,768 bits input/output gate circuit y-address counter/decoder decoder x-address counter z-address counter frs control register contrast control register z- address register display control register x/y counter select register x/y counter up/down register input/output buffer input register interface control circuit duty cycle control register timing signals generating circuit op-amp dc-dc converter bias control circuit contrast control circuit lcd driver circuit (64) 32 bit shift register oscillator multiplexer 8 3 6 8 4 vlc1 vlc2 vlc3 vlc4 vlc5 vout vref cna cnb vin 128 2 8 latch circuit 3 output register register select circuit analog control register osc2 osc3 n 1 to 5 vcc vdd vss 68/80 rst p/s 1 cs cs2 wr rd rs db0 to db7 frc frc circuit si so d/i sck osc1 oscillator control register static icon control register grayscale control register static icon driver circuit com65 com128 s1 to s16 coms lcd driver circuit (64) 32 bit shift register T6K41 2002-01-08 4 pin assignment note 1: the above diagram shows the pin configuration of the lsi chip, not that of the tape carrier package. db7 db6 db5 db4 db3 db2 db1 db0 1 cs cs2 rs rd wr d/i rst p/s 68/80 so si sck m/s blnk sync ck cl pm fr stb v dd osc3 osc2 osc1 v ss vref v in c1a c1b c2a c2b c3a c3b c4a c4b c5a c5b v out v cc vlc0 vlc1 vlc2 vlc3 vlc4 vlc5 (hvss) s1 s2 s3 s14 s15 s16 coms com64 com63 com62 com61 com4 com3 com2 com1 seg1 seg2 seg3 seg4 seg125 seg126 seg127 seg128 com65 com66 com67 com68 com125 com126 com127 com128 coms T6K41 (top view) T6K41 2002-01-08 5 pad specification note 2: please refer to the T6K41 technical datasheet for pad specification. item size unit chip size 12300 2610 m (1) 6150, 1305 (2) 6150, 1305 (3) 6150, 1305 chip tip coordinates (4) 6150, 1305 m bump pitch 52 m bump height 14 4 m item number of pins input pin 105 pins (including dummy pins) output pin 283 pins (including dummy pins) test pin 2 pins (note 3) fuse pin 17 pins (note 3) note 3: test and fuse pins are lsi test pins, leave these pins open. T6K41 2002-01-08 6 pad layout chip size: 12.3 2.61 mm note 4: please refer to the T6K41 technical datasheet for pad layout and coordinates values. no. 1 no. 407 (0, 0) T6K41 2002-01-08 7 pad coordinates (1) [unit: m] no. name x-point y-point no. name x-point y-point no. name x-point y-point 1 vcl5 5871 1124 46 tdummy8 1328 1124 91 tdummy19 2986 1124 2 vlc5 5769 1124 47 dmyvss 1249 1124 92 /stb 3072 1124 3 vlc5 5667 1124 48 v ss 1170 1124 93 fr 3161 1124 4 vlc5 5565 1124 49 v ss 1084 1124 94 pm 3252 1124 5 vlc4 5463 1124 50 v ss 998 1124 95 cl 3343 1124 6 vlc4 5361 1124 51 v ss 912 1124 96 ck 3434 1124 7 vlc3 5259 1124 52 v ss 826 1124 97 sync 3525 1124 8 vlc3 5157 1124 53 test3 740 1124 98 blnk 3616 1124 9 vlc2 5055 1124 54 osc1 654 1124 99 m/s 3705 1124 10 vlc2 4953 1124 55 dmyvss 568 1124 100 sck 3791 1124 11 vlc1 4851 1124 56 osc2 482 1124 101 si 3877 1124 12 vlc1 4749 1124 57 dmyvss 396 1124 102 so 3963 1124 13 vlc0 4647 1124 58 osc3 310 1124 103 dmyvdd 4049 1124 14 vlc0 4545 1124 59 fuse31 210 1124 104 68/80 4135 1124 15 vlc0 4443 1124 60 fuse32 111 1124 105 dmyvss 4221 1124 16 vlc0 4341 1124 61 fuse3g 12 1124 106 p/s 4307 1124 17 vcc1 4239 1124 62 fuse33 87 1124 107 dmyvdd 4393 1124 18 vcc1 4137 1124 63 fuse34 186 1124 108 /rst 4479 1124 19 vcc1 4035 1124 64 fuse21 285 1124 109 d/i 4565 1124 20 vcc1 3933 1124 65 fuse22 384 1124 110 /wr 4651 1124 21 test2 3831 1124 66 fuse23 483 1124 111 /rd 4737 1124 22 vout 3729 1124 67 fuse2g 582 1124 112 rs 4823 1124 23 vout 3627 1124 68 fuse24 681 1124 113 cs2 4909 1124 24 c5b 3525 1124 69 fuse25 780 1124 114 /cs1 4995 1124 25 c5a 3423 1124 70 fuse11 879 1124 115 dmyvss 5081 1124 26 c4b 3321 1124 71 fuse12 978 1124 116 db0 5167 1124 27 c4a 3219 1124 72 fuse13 1077 1124 117 db1 5253 1124 28 c3b 3117 1124 73 fuse1g 1176 1124 118 db2 5339 1124 29 c3a 3015 1124 74 fuse14 1275 1124 119 db3 5425 1124 30 c2b 2913 1124 75 fuse15 1374 1124 120 db4 5511 1124 31 c2a 2811 1124 76 v dd 1486 1124 121 db5 5597 1124 32 c1b 2709 1124 77 v dd 1587 1124 122 db6 5683 1124 33 c1a 2607 1124 78 v dd 1688 1124 123 db7 5769 1124 34 dmyvss 2514 1124 79 v dd 1789 1124 124 dmyvdd 5871 1124 35 vin 2421 1124 80 v dd 1890 1124 125 dummy1 5934 803 36 vin 2319 1124 81 tdummy9 1976 1124 126 dummy2 5934 721 37 dmyvss 2231 1124 82 tdummy10 2077 1124 127 dummy3 5934 669 38 vreg 2142 1124 83 tdummy11 2199 1124 128 dummy4 5934 617 39 tdummy1 2056 1124 84 tdummy12 2279 1124 129 dummy5 5934 565 40 tdummy2 1955 1124 85 tdummy13 2380 1124 130 dummy6 5934 513 41 tdummy3 1833 1124 86 tdummy14 2502 1124 131 s1 5934 461 42 tdummy4 1732 1124 87 tdummy15 2582 1124 132 s2 5934 409 43 tdummy5 1652 1124 88 tdummy16 2662 1124 133 s3 5934 357 44 tdummy6 1551 1124 89 tdummy17 2805 1124 134 s4 5934 305 45 tdummy7 1429 1124 90 tdummy18 2885 1124 135 s5 5934 253 T6K41 2002-01-08 8 pad coordinates (2) [unit: m] no. name x-point y-point no. name x-point y-point no. name x-point y-point 136 s6 5934 201 181 com33 4419 1087 226 seg13 2079 1087 137 s7 5934 149 182 com32 4367 1087 227 seg14 2027 1087 138 s8 5934 97 183 com31 4315 1087 228 seg15 1975 1087 139 s9 5934 45 184 com30 4263 1087 229 seg16 1923 1087 140 s10 5934 8 185 com29 4211 1087 230 seg17 1871 1087 141 s11 5934 60 186 com28 4159 1087 231 seg18 1819 1087 142 s12 5934 112 187 com27 4107 1087 232 seg19 1767 1087 143 s13 5934 164 188 com26 4055 1087 233 seg20 1715 1087 144 s14 5934 216 189 com25 4003 1087 234 seg21 1663 1087 145 s15 5934 268 190 com24 3951 1087 235 seg22 1611 1087 146 s16 5934 320 191 com23 3899 1087 236 seg23 1559 1087 147 coms2 5934 372 192 com22 3847 1087 237 seg24 1507 1087 148 dummy7 5934 425 193 com21 3795 1087 238 seg25 1455 1087 149 dummy8 5934 477 194 com20 3743 1087 239 seg26 1403 1087 150 com64 5934 529 195 com19 3691 1087 240 seg27 1351 1087 151 com63 5934 581 196 com18 3639 1087 241 seg28 1299 1087 152 com62 5934 633 197 com17 3587 1087 242 seg29 1247 1087 153 com61 5934 685 198 com16 3535 1087 243 seg30 1195 1087 154 com60 5934 767 199 com15 3483 1087 244 seg31 1143 1087 155 com59 5801 1087 200 com14 3431 1087 245 seg32 1091 1087 156 com58 5719 1087 201 com13 3379 1087 246 seg33 1039 1087 157 com57 5667 1087 202 com12 3327 1087 247 seg34 987 1087 158 com56 5615 1087 203 com11 3275 1087 248 seg35 935 1087 159 com55 5563 1087 204 com10 3223 1087 249 seg36 883 1087 160 com54 5511 1087 205 com9 3171 1087 250 seg37 831 1087 161 com53 5459 1087 206 com8 3119 1087 251 seg38 779 1087 162 com52 5407 1087 207 com7 3067 1087 252 seg39 727 1087 163 com51 5355 1087 208 com6 3015 1087 253 seg40 675 1087 164 com50 5303 1087 209 com5 2963 1087 254 seg41 623 1087 165 com49 5251 1087 210 com4 2911 1087 255 seg42 571 1087 166 com48 5199 1087 211 com3 2859 1087 256 seg43 519 1087 167 com47 5147 1087 212 com2 2807 1087 257 seg44 467 1087 168 com46 5095 1087 213 com1 2755 1087 258 seg45 415 1087 169 com45 5043 1087 214 seg1 2703 1087 259 seg46 363 1087 170 com44 4991 1087 215 seg2 2651 1087 260 seg47 311 1087 171 com43 4939 1087 216 seg3 2599 1087 261 seg48 259 1087 172 com42 4887 1087 217 seg4 2547 1087 262 seg49 207 1087 173 com41 4835 1087 218 seg5 2495 1087 263 seg50 155 1087 174 com40 4783 1087 219 seg6 2443 1087 264 seg51 103 1087 175 com39 4731 1087 220 seg7 2391 1087 265 seg52 51 1087 176 com38 4679 1087 221 seg8 2339 1087 266 seg53 1 1087 177 com37 4627 1087 222 seg9 2287 1087 267 seg54 53 1087 178 com36 4575 1087 223 seg10 2235 1087 268 seg55 105 1087 179 com35 4523 1087 224 seg11 2183 1087 269 seg56 157 1087 180 com34 4471 1087 225 seg12 2131 1087 270 seg57 209 1087 T6K41 2002-01-08 9 pad coordinates (3) [unit: m] no. name x-point y-point no. name x-point y-point no. name x-point y-point 271 seg58 261 1087 317 seg104 2653 1087 363 com86 5045 1087 272 seg59 313 1087 318 seg105 2705 1087 364 com87 5097 1087 273 seg60 365 1087 319 seg106 2757 1087 365 com88 5149 1087 274 seg61 417 1087 320 seg107 2809 1087 366 com89 5201 1087 275 seg62 469 1087 321 seg108 2861 1087 367 com90 5253 1087 276 seg63 521 1087 322 seg109 2913 1087 368 com91 5305 1087 277 seg64 573 1087 323 seg110 2965 1087 369 com92 5357 1087 278 seg65 625 1087 324 seg111 3017 1087 370 com93 5409 1087 279 seg66 677 1087 325 seg112 3069 1087 371 com94 5461 1087 280 seg67 729 1087 326 seg113 3121 1087 372 com95 5513 1087 281 seg68 781 1087 327 seg114 3173 1087 373 com96 5565 1087 282 seg69 833 1087 328 seg115 3225 1087 374 com97 5617 1087 283 seg70 885 1087 329 seg116 3277 1087 375 com98 5669 1087 284 seg71 937 1087 330 seg117 3329 1087 376 com99 5721 1087 285 seg72 989 1087 331 seg118 3381 1087 377 com100 5803 1087 286 seg73 1041 1087 332 seg119 3433 1087 378 com101 5934 767 287 seg74 1093 1087 333 seg120 3485 1087 379 com102 5934 685 288 seg75 1145 1087 334 seg121 3537 1087 380 com103 5934 633 289 seg76 1197 1087 335 seg122 3589 1087 381 com104 5934 581 290 seg77 1249 1087 336 seg123 3641 1087 382 com105 5934 529 291 seg78 1301 1087 337 seg124 3693 1087 383 com106 5934 477 292 seg79 1353 1087 338 seg125 3745 1087 384 com107 5934 425 293 seg80 1405 1087 339 seg126 3797 1087 385 com108 5934 373 294 seg81 1457 1087 340 seg127 3849 1087 386 com109 5934 321 295 seg82 1509 1087 341 seg128 3901 1087 387 com110 5934 269 296 seg83 1561 1087 342 com65 3953 1087 388 com111 5934 217 297 seg84 1613 1087 343 com66 4005 1087 389 com112 5934 165 298 seg85 1665 1087 344 com67 4057 1087 390 com113 5934 113 299 seg86 1717 1087 345 com68 4109 1087 391 com114 5934 61 300 seg87 1769 1087 346 com69 4161 1087 392 com115 5934 9 301 seg88 1821 1087 347 com70 4213 1087 393 com116 5934 43 302 seg89 1873 1087 348 com71 4265 1087 394 com117 5934 95 303 seg90 1925 1087 349 com72 4317 1087 395 com118 5934 147 304 seg91 1977 1087 350 com73 4369 1087 396 com119 5934 199 305 seg92 2029 1087 351 com74 4421 1087 397 com120 5934 251 306 seg93 2081 1087 352 com75 4473 1087 398 com121 5934 303 307 seg94 2133 1087 353 com76 4525 1087 399 com122 5934 355 308 seg95 2185 1087 354 com77 4577 1087 400 com123 5934 407 309 seg96 2237 1087 355 com78 4629 1087 401 com124 5934 459 310 seg97 2289 1087 356 com79 4681 1087 402 com125 5934 511 311 seg98 2341 1087 357 com80 4733 1087 403 com126 5934 563 312 seg99 2393 1087 358 com81 4785 1087 404 com127 5934 615 313 seg100 2445 1087 359 com82 4837 1087 405 com128 5934 667 314 seg101 2497 1087 360 com83 4889 1087 406 dummy9 5934 719 315 seg102 2549 1087 361 com84 4941 1087 407 coms1 5934 801 316 seg103 2601 1087 362 com85 4993 1087 T6K41 2002-01-08 10 pin functions pin name i/o functions seg1 to seg128 output lcd drive segment signals com1 to com128 output lcd drive common signals s1 to s16 output lcd driver segment signals for static icons coms output lcd driver common signals for static icons db0 to db7 i/o data bus 1 cs input chip select signal 1 write data: data on db0 to db7 is latched on the rising edge of 1 cs . read data: data appears on db0 to db7 while 1 cs is low. cs2 input chip select signal 2 write data: data on db0 to db7 is latched on the falling edge of cs2. read data: data appears on db0 to db7 while 1 cs is high. d/i input input for data/instruction select signal d/i high indicates that the data on db0 to db7 or si is display data. d/i low indicates that the data on db0 to db7 or si is an instruction. wr (r/w) input input or write select signal (input for read/write select signal) if 80 series mpu is selected, data on db0 to db7 is latched on the rising edge of wr if 68 series mpu is selected, data read is selected if r/w high and data write is selected if r/w low. rd (e) input input for read select signal (input for enable signal) if 80 series mpu is selected, data appears on db0 to db7 while rd low. if 68 series mpu is selected, this pin is used for the input enable signal. rs input input for register mode select signal if rs low, this input is recognized as a register number. if rs high, this input is recognized as the data to be written to the register. p/s input input for parallel/serial interface select signal p/s high parallel interface is selected. si and sck must be connected to v dd or v ss . p/s low serial interface is selected. db0 to db7 must be open. wr and rd must be connected to v ss . 68/80 input input for 68/80 series parallel mpu select signal 68/80 high 68 series parallel mpu is selected. 68/80 low 80 series parallel mpu is selected. so output output for serial data si input input for serial data sck input input for serial clock rst input input for reset signal rst low reset state stb input input for standby signal usually connected to v dd . stb low T6K41 is in standby state. column drive signals and row drive signals are at the v ss level and the on-chip oscillator is stopped. in standby state T6K41 can be accessed by the mpu. osc1 input input for cr oscillator when using an external clock, input the clock to osc1 and leave osc2 and osc3 open. T6K41 2002-01-08 11 pin name i/o functions osc2, osc3 output output for cr oscillator when using the internal clock oscillator, connect a resistor between osc1 and osc2 or between osc1 and osc3. osc1 and osc2: oscillator for normal display mode osc1 and osc3: oscillator for partial display mode v in power supply for dc-dc converter usually connected to v dd the condition v dd v in must always be met. c1a, c1b external capacitor-connecting pin for 2 dc-dc converter c2a, c2b external capacitor-connecting pin for 3 dc-dc converter c3a, c3b external capacitor-connecting pin for 4 dc-dc converter c4a, c4b external capacitor-connecting pin for 5 dc-dc converter c5a, c5b external capacitor-connecting pin for 6 dc-dc converter v out dc-dc converter output pin vref lv regulator output pin v cc lcd driver power supply pin vlc0 to vlc5 lcd drive power supply pin v dd , v ss logic circuit power supply pin m/s input input for master/save select signal m/s high T6K41 is a master chip. m/s low T6K41 is a slave chip. cl i/o input/output for shift clock pulse master mode (m/s high) output slave mode (m/s low) input pm i/o input/output for frame signal master mode (m/s high) output slave mode (m/s low) input fr i/o input/output for display alternating signal master mode (m/s high) output slave mode (m/s low) input ck i/o input/output for system clock signal master mode (m/s high) output slave mode (m/s low) input sync i/o input/output for gray-scale data synchronous signal master mode (m/s high) output slave mode (m/s low) input blnk i/o input/output for static icons blinking synchronous signal master mode (m/s high) output slave mode (m/s low) input T6K41 2002-01-08 12 function each block mpu interface unit the T6K41 can be operated with an 80-series mpu, 68-series mpu or a serial interface. figure 1 shows an example of interface. figure 1 the T6K41 selects an 8-bit parallel or serial interface, allowing for data to transferred from the mpu. p/s 68/80 interface type 1 cs cs2 d/i rs wr rd so si sck db0 to 7 80-series mpu ( 1 cs ) an 2 h an an 1 wr rd open l/h l/h db0 to 7 l 80-series mpu (cs2) l an 2an an 1 wr rd open l/h l/h db0 to 7 h h 68-series mpu l h an an 1 r/w e open l/h l/h db0 to 7 l l serial l h l/h l/h l/h l/h so si sck open note 5: h denotes the v dd level; l denotes the v ss level. rst db0 to 7 rd wr d/i rs 1 cs case of 80-series mpu (using 1 cs signal) (cs2 v dd ) 80-series mpu reset d0 to 7 rd wr an an 1 an 2 T6K41 rst db0 to 7 rd wr d/i rs 1 cs case of 68-series mpu (cs2 v dd /cs1 v ss ) 68-series mpu reset d0 to7 rd wr an an 1 an 2 T6K41 rst si sck so case of serial interface (cs2 v dd /cs1 v ss ) mpu reset so sck si T6K41 T6K41 2002-01-08 13 T6K41 2002-01-08 14 register select circuit this circuit transfers a register chosen by command to the data. T6K41 has r0 to r31 registers. the r23 to r31 registers are provided for test. do not choose these registers. input register this register stores 8-bit data from the mpu. the d/i signal discriminate between command data and display data. x-address counter the x-address counter is a 128-up/down counter. it holds the row address of the display ram. when this counter is selected by a command, it is automatically incremented or decremented each time data is read or written to the display ram. y (page) -address counter the y (page) -address counter is a 32-up/down counter. it holds the column address of the display ram. when this counter is selected by a command, it is automatically incremented or decremented each time data is read or written to the display ram. z-address counter the z-address counter is a 128-up counter used to supply the display data stored in the display ram to the lcd drive circuit. this counter is incremented by cl signal. the data held in the z-address register is loaded into this counter as z-address. for instance, when z start address is 16, the counter increment like this: 16, 17, ,18 , 127, 128, 1, 2 , 14,15,16. therefore, the display start line is 16-line of the display ram. x/y counter up/down register this register holds the data that selects the up-count or down-count mode for the x and y counters. x/y counter select register the register holds the data that selects the x or y counter to be used. display on/off register this register holds the data that determines whether the display be turned on or off. when turned off, the output data turns to default level. when turned on, the display data appears according to the display ram data. the display on or off state does not affect the data of display ram. duty cycle control register this register holds the data that sets one of the four duty cycles that can be used. frs control register this register holds frs control data. contrast control register this register holds contrast control data. oscillator control register this register holds the data that controls oscillator. static icon control register this register holds the data that controls static icons. the static icons are usually independent of the lcd drive circuit for a normal display, and holds contrast control data, display on/off data, and blink control data. T6K41 2002-01-08 15 analog circuit on/off register this register holds the data that determines whether the internal analog circuit be turned on or off. z-address register this register holds the data that determines the display start line. by setting z-address in this register successively, it is possible to scroll the display up or down. shift register T6K41 has two 64-bit shift registers necessary to shift the turn-on data required for the lcd drive common signals. latch circuit the circuit latches the data from the display ram. lcd drive circuit (segment) the segment driver circuit consists of 128 driver circuits. one of the four lcd driving level is selected by the combination of m (internal signal) and the display data transferred from the latch circuit. details of segment driver circuit are shown in figure 3. figure 3 lcd driver circuit (common) the common driver circuit consists of 128 driver circuits. one of the four lcd driving level is selected by the combination of m (internal signal) and the data from the shift register. details of common driver circuit are shown in figure 4. figure 4 vcon vcoff display data seg1 to seg128 vlc5 vlc0 vlc3 vlc2 m vcon vcoff display data seg1 to seg128 vlc0 vlc5 vlc4 vlc1 m T6K41 2002-01-08 16 frc (frame rate control) circuit the circuit controls on/off of pwm data in each frame for generating the gray scale level. pwm (pulse width modulation) is performed by gray scale data (the 2-bit display ram data correspond to gray scale data). the gray scale data also determines whether pwm data is assigned to which frame. timing generation circuit the circuit divides the signals from the oscillator and generates display timing signals and operating clock. op-amp, bias control circuit and voltage divider resistors the T6K41 has five op-amp for supplying lcd driving levels. to maintain good lcd contrast, connect a capacitor between the op-amp output and v ss . the value of the capacitor should normally be 0.1 f. one of four biases can be selected by a bias control command. figure 5 db0 to 7 rs bias control register decoder v cc vlc0 vlc1 vlc2 output circuit vlc3 vlc4 vlc5 rb rb rb 5rb 6rb 7rb 8rb rb 1400k rb T6K41 2002-01-08 17 oscillator the T6K41 has two oscillators for normal display mode and partial display mode. when using internal oscillators, connect an external resistor for normal display mode between ocs1 and osc2 and connect an external resistor for partial display mode between osc1 and osc3. when using external clock, input the clock to osc1 after setting up oscillation control resister data, as shown in figure 7. T6K41 2002-01-08 18 dc-dc converter T6K41 contains a 4/5/6 dc-dc converter. this circuit boosts by an external capacitor (charge pump system). by supping voltage to v in , this circuit can generate the boosted voltage selected by the command, and outputs the voltage from v out . the boosted voltage is fed back to dc-dc converter circuit and the voltage adjusted by contrast control circuit is again outputted from v out . when using a dc-dc converter, short v out and v cc . as for the output voltage of v out , 15.4 v or 13.0 v is the maximum value after a contrast control setup. since more than 15.4 v or more than 13.0 v is not outputted, please be careful. in partial display mode, the dc-dc converter automatically changes to 2 or 3 mode. the output voltage of v out is v in level in a standby state (/stb ?l?) or a reset state (/rst ?l?). refer to figure 9 for the capacitor connection. note 6: please set the capacitor value of c1 and c2 as the following ratio to suit the circuit characteristic. c1:c2 1:more than 20 figure 9 contrast control circuit the contrast control circuit feeds back the voltage outputted from v out through built-in variable resistance, and outputs again contrast adjustment voltage to v out . therefore, the output voltage of v out is the maximum of lcd drive voltage adjusted by contrast control circuit. figure 10 dc-dc converter v cc vlc0 v out contrast control c1: 0.1 f c2: 2.2 f when using 6 moder c1a c1b c2a c2b c3a c3b c4a c4b c5a c5b v ss v dd v in v cc v out c2 c1 c1 c1 c1 c1 when using 5 booster c1 a c1b c2 a c2b c3 a c3b c4 a c4b c5 a c5b v ss v dd v in v cc v out c2 c1 c1 c1 c1 when using 4 booster c1a c1b c2a c2b c3a c3b c4a c4b c5a c5b v ss v dd v in v cc v out c2 c1 c1 c1 T6K41 2002-01-08 19 command definition command reg. no. d/i rs wr rd db7 db6 db5 db4 db3 db2 db1 db0 set register 0 0 0 1 0 0 0 register (0 to 31) status read 0 0 1 0 * * pd n/f si dp y/x u/d counter mode r0 0 1 0 1 0 0 0 0 0 0 y/x u/d display mode r1 0 1 0 1 0 cdr sdr 0 pd si n/f dp set power control r2 0 1 0 1 6/ 5/ 4 3/ 2 0 0 hi/lo op dc set duty/bias r3 0 1 0 1 0 0 bias 0 0 duty oscillator control r4 0 1 0 1 0 0 0 0 0 0 ext osc 0 1 0 1 1 x-address (0 to 127) set x/y-address r5 0 1 0 1 0 0 0 y-address (0 to 31) set z-address r6 0 1 0 1 0 z-address (0 to 127) set normal display contrast r7 0 1 0 1 contrast control for normal display (0 to 255) set static icon contrast r8 0 1 0 1 0 0 contrast control for static icon display (0 to 63) set static icon register (1) r9 0 1 0 1 s4 state s3 state s2 state s1 state set static icon register (2) r10 0 1 0 1 s8 state s7 state s6 state s5 state set static icon register (3) r11 0 1 0 1 s12 state s11 state s10 state s9 state set static icon register (4) r12 0 1 0 1 s16 state s15 state s14 state s13 state set partial display mode r13 0 1 0 1 bias partial area size partial start area (0 to 15) set alternating period r14 0 1 0 1 0 0 0 0 0 frs control (0 to 7) r15 0 1 0 1 r16 0 1 0 1 gray scale data for normal display (1) gs data to ram data ?00? r17 0 1 0 1 r18 0 1 0 1 gray scale data for normal display (2) gs data to ram data ?01? r19 0 1 0 1 r20 0 1 0 1 gray scale data for normal display (3) gs data to ram data ?10? r21 0 1 0 1 gray scale pallet for normal display r22 0 1 0 1 gray scale data for normal display (4) gs data to ram data ?11? test mode r23 to r31 0 1 0 1 test mode (do not access these registers.) data write 1 1 0 1 write data data read 1 1 1 0 read data T6K41 2002-01-08 20 set register T6K41 has registers for command (r0 to r31). but, r23 to r31 registers are provided for lsi test. do not access these registers. if you access these registers inadvertently, you must be execute a re-setup of a register after executing reset function of T6K41. r0: counter mode d/i rs wr rd db7 db6 db5 db4 db3 db2 db1 db0 code 0 1 0 1 0 0 0 0 0 0 y/x u/d y/x: selects y-counter or x-counter. y/x 1: y-counter is selected. y/x 0: x-counter is selected. u/d: selects up mode or down mode. u/d 1: up mode is selected. u/d 0: down mode is selected. r1: display mode d/i rs wr rd db7 db6 db5 db4 db3 db2 db1 db0 code 0 1 0 1 0 cdr sdr 0 pd si n/f dp cdr: sets the common data scanning direction. cdr 1: data is scanned in the direction com1 com128. cdr 0: data is scanned in the direction com128 com1. sdr: sets the segment data direction. sdr 1: seg1 seg4 with respect to the data direction db7 db0. sdr 0: seg1 seg4 with respect to the data direction db0 db7. note 7: for details, see figure 11 on function description. pd: turns partial display on or off. dp 1: partial display is turned on dp 0: partial display is turned off. (normal display) si: turns static icons on or off. si 1: static icons are turned on. si 0: static icons are turned off. n/f: selects between normal display and icon display modes. n/f 1: normal display mode is selected. n/f 0: icon display mode is selected. display mode display mode normal display static icons normal display mode valid valid power save mode invalid valid note 8: when power save mode (icon display mode) is selected, only static icon can be displayed. dp: turns display on or off. dp 1: display is turned on. dp 0: display is turned off. T6K41 2002-01-08 21 r2: set power control d/i rs wr rd db7 db6 db5 db4 db3 db2 db1 db0 code 0 1 0 1 6/ 5/ 4 3/ 2 0 0 hi/lo op dc 6/ 5/ 4: selects booster level in normal display mode db7 db6 booster 1 0 6 0 1 5 0 0 4 3/ 2: selects booster level in partial display mode. 3/ 2 1: 3 booster 3/ 2 0: doubler hi/lo: selects lcd drive voltage (v out ). hi/lo 1: v out 15.4 v (typ.) hi/lo 0: v out 13.0 v (typ.) op: controls op-amp for driving lcd. op 1: op-amp for driving lcd on op 0: op-amp for driving lcd off (externally supply v cc and vlc1 to vlc4 via op-amp.) dc: controls booster (dc-dc converter). dc 1: booster on dc 0: booster off r3: set duty/bias sets duty/bias in normal display mode. d/i rs wr rd db7 db6 db5 db4 db3 db2 db1 db0 code 0 1 0 1 0 0 bias (0 to 3) 0 0 duty (0 to 3) bias: sets a power supply bias for lcd drive. db5 db4 1 1 set to 1/12 bias. 1 0 set to 1/11 bias. 0 1 set to 1/10 bias. 0 0 set to 1/9 bias. duty : sets a display duty cycle. db1 db0 1 1 set to 1/128 duty 1 0 set to 1/100 duty 0 1 set to 1/80 duty 0 0 set to 1/72 duty T6K41 2002-01-08 22 r4: oscillation control d/i rs wr rd db7 db6 db5 db4 db3 db2 db1 db0 code 0 1 0 1 0 0 0 0 0 0 ext osc ext: switches input. ext 1: inputs external clock. ext 0: uses internal oscillator. osc: controls internal oscillator. osc 1: internal oscillator on osc 0: internal oscillator off switching between normal display and partial display modes switches oscillator resistor when an internal oscillator is used (ext 0). normal display mode: resistor between osc1 and osc2 partial display mode: resistor between osc1 and osc3 divides the frequency from the selected oscillator to obtain the static icon clock. to switch between normal display and partial display modes using external clock input, the clock frequency must be changed according to the display mode. T6K41 2002-01-08 23 r5: set x/y-address d/i rs wr rd db7 db6 db5 db4 db3 db2 db1 db0 1 x-address (0 to 127) code 0 1 0 1 0 0 0 y-address (0 to 31) (1) set x-address setting db7 to 1 acknowledges an x-address. the address is controlled as a vertical address of the screen image. using the x-up/down counter automatically enables write and read. the x-up/down counter counts addresses on the specified horizontal line only. (2) set y-address setting db7 to 0 acknowledges a y-address. the address is controlled as a horizontal address of the screen image. using the y-up/down counter automatically enables write and read. the y-up/down counter counts addresses on the specified vertical line only. r6: set z-address d/i rs wr rd db7 db6 db5 db4 db3 db2 db1 db0 code 0 1 0 1 0 z-address (0 to 127) sets the start line of display ram. setting this address enables vertical scrolling. for the scroll function, see the detailed description. r7: set normal display contrast d/i rs wr rd db7 db6 db5 db4 db3 db2 db1 db0 code 0 1 0 1 contrast control (0 to 255) sets contrast control of the normal display area. when set to 0, contrast is the minimum. when set to 255, contrast is the maximum. note 9: that if a doubler is selected in partial display mode, set db7 1 and set a step from 1 to 128. r8: set static icon contrast d/i rs wr rd db7 db6 db5 db4 db3 db2 db1 db0 code 0 1 0 1 0 0 contrast control (0 to 63) sets contrast control of the static icon area. when set to 0, contrast is the minimum. when set to 63, contrast is the maximum. the on period ratio of the drive voltage for the static icon area is adjusted by changing the phase of the waveform between the coms pin and pins s1 to s16. T6K41 2002-01-08 24 r9: set static icon register (1) d/i rs wr rd db7 db6 db5 db4 db3 db2 db1 db0 code 0 1 0 1 s4 state s3 state s2 state s1 state sets on/off of static icons s1 to s4. when a static icon is on (r1: si 1), s1 to s4 are turned on according to the setting of this register. when a static icon is off (r1: si 0), the display is off regardless of the setting of this register. static icon states vary as shown below according to the 2-bit data. s1 to s16 state 0 0 off 0 1 on (blinks at intervals of about 1 second) 1 0 on (blinks at intervals of about 0.5 seconds) 1 1 on r10: set static icon register (2) d/i rs wr rd db7 db6 db5 db4 db3 db2 db1 db0 code 0 1 0 1 s8 state s7 state s6 state s5 state sets on/off of the static icons s5 to s8. when a static icon is on (r1: si 1), s5 to s8 are turned on according to the setting of this register. when a static icon is off (r1: si 0), the display is off regardless of the setting of this register. r11: set static icon register (3) d/i rs wr rd db7 db6 db5 db4 db3 db2 db1 db0 code 0 1 0 1 s12 state s11 state s10 state s9 state sets on/off of the static icon s9 to s12. when a static icon is on (r1: si 1), s9 to s12 are turned on according to the setting of this register. when a static icon is off (r1: si 0), the display is off regardless of the setting of this register. r12: set static icon register (4) d/i rs wr rd db7 db6 db5 db4 db3 db2 db1 db0 code 0 1 0 1 s16 state s15 state s14 state s13 state sets on/off of the static icon s13 to s16. when a static icon is on (r1: si 1), s13 to s16 are turned on according to the setting of this register. when a static icon is off (r1: si 0), the display is off regardless of the setting of this register. turned off turned on turned off turned on turned off turned on approx. 1 s T6K41 2002-01-08 25 r13: set partial display mode d/i rs wr rd db7 db6 db5 db4 db3 db2 db1 db0 code 0 1 0 1 bias partial area size partial start area set partial start area db3 db2 db1 db0 start area 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 1 0 1 1 1 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 sets the partial display start area. the partial display start area can be specified in units of 8 lines (8 coms). set partial area size db5 db4 partial area size 0 0 8 lines mode 0 1 16 lines mode 1 0 24 lines mode 1 1 32 lines mode sets the partial display area size. a partial display area of the set size is displayed from the partial display start area. set bias db7 db6 bias 0 0 1/4 bias 0 1 1/5 bias 1 0 1/6 bias 1 1 1/7 bias sets bias in partial display mode. area 0 area 1 area 2 area 15 com1 com9 com17 com121 com128 seg1 seg128 T6K41 2002-01-08 26 r14: set alternating period d/i rs wr rd db7 db6 db5 db4 db3 db2 db1 db0 code 0 1 0 1 0 0 0 0 0 frs control (0 to 7) this command sets the number of lines at which intervals the polarity of the frame signal (alternating signal) is switched over. db2 db1 db0 1 1 1 fr signal inverts on every 19 lines. 1 1 0 fr signal inverts on every 17 lines. 1 0 1 fr signal inverts on every 13 lines. 1 0 0 fr signal inverts on every 11 lines. 0 1 1 fr signal inverts on every 7 lines. 0 1 0 fr signal inverts on every 5 lines. 0 0 1 fr signal inverts on every 3 lines. 0 0 0 in case 1/n duty is selected by r3, fr signal inverts on every n lines. r15 to r22: gray scale pallet for normal display d/i rs wr rd db7 db6 db5 db4 db3 db2 db1 db0 r15/16: gray scale data for normal display (1) r17/18: gray scale data for normal display (2) r19/20: gray scale data for normal display (3) code 0 1 0 1 r21/22: gray scale data for normal display (4) this register stores the data for generating the gray scale level. the gray scale is created by pulse width modulation (pwm) and frame rate control (frc). use two registers for each gray scale level. set the pwm data for the first to fourth frames in these registers. four bits of pwm data are eliminated from a frame. four frames are used to display one gray scale level. frames (1) to (4) above correspond to display data 00, 01, 10 and 11, respectively. any gray scale level is assigned to the display data values (00, 01, 10 and 11). frame rate control (frc) setting the T6K41 determines the gray scale level by specifying the pwm to be performed in the four frames. the correspondence between frame control order and the registers is shown in the table below. data bus register db7 db6 db5 db4 db3 db2 db1 db0 r15/r17/r19/r21 data eliminated from second frame data eliminated from first frame r16/r18/r20/r22 data eliminated from fourth frame data eliminated from third frame note 10: eliminated data are pwm data. T6K41 2002-01-08 27 pwm (pulse width modulation) setting the T6K41 determines the gray scale level by dividing the segment data on waveform by nine. the data to be written to the register are selected from the gray scale levels listed below. bin hex pwm (on width) note 0000 00 0 (0/9) 0001 01 1/9 0010 02 2/9 0011 03 3/9 0100 04 4/9 0101 05 5/9 0110 06 6/9 0111 07 7/9 1000 08 8/9 1001 09 1 (9/9) 1010 to 1111 0a to 0f 0 (0/9) these data select off level (0 level). note 11: optimization by combination of pwm and frc data depends on the characteristics of the lcd. r23 to r31: test mode d/i rs wr rd db7 db6 db5 db4 db3 db2 db1 db0 code 0 1 0 1 test mode this command selects a test mode, so do not use it. if you?ve used this test command inadvertently, deassert it by pulling the rst input low data write d/i rs wr rd db7 db6 db5 db4 db3 db2 db1 db0 code 0 1 0 1 write data writes 8-bit data to display ram. using the x/y counter automatically counts up/down addresses after specifying the start address so that data can be written. data read d/i rs wr rd db7 db6 db5 db4 db3 db2 db1 db0 code 1 1 1 0 read data reads 8-bit data from display ram. using the x/y counter automatically counts up/down addresses after specifying the start address so that data can be read. T6K41 2002-01-08 28 status read d/i rs wr rd db7 db6 db5 db4 db3 db2 db1 db0 code 0 0 1 0 * * * n/f si dp y/x u/d n/f (db4): identifies normal display mode or power save mode. n/f 1: indicates normal display mode. n/f 0: indicates power save mode. si (db3): identifies static icon on/off. si 1: static icon on si 0: static icon off dp (db2): identifies display on/off. dp 1: display on dp 0: display off y/x (db1): identifies y or x counter. y/x 1: y counter is selected. y/x 0: x counter is selected. u/d (db0): identifies counter up or down mode. u/d 1: counter up mode u/d 0: counter down mode T6K41 2002-01-08 29 reset function the T6K41 has a rst pin. when input to this pin is pulled low, the T6K41 is reset, with its internal circuits (register contents) initialized as shown below. command reg. no. d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 1 1 counter mode r0 * * * * * * y/x u/d 0 1 1 0 0 0 1 0 display mode r1 * cdr sdr * pd si n/f dp 1 0 0 0 0 1 0 0 power control r2 6/ 5/ 4 3/ 2 * * hi/lo op dc 0 0 1 1 0 0 1 1 set duty/bias r3 * * bias * * duty 0 0 0 0 0 0 1 1 oscillator setting r4 * * * * * * ext osc 0 0 0 0 0 0 0 0 set x/y-address r5 * x-address/y-address 0 0 0 0 0 0 0 0 set z-address r6 * z-address 0 0 0 0 0 0 0 0 contrast setting in normal display mode r7 contrast control data for normal display 0 0 0 0 0 0 0 0 contrast setting for static icon r8 * * contrast control for static icon 0 0 0 0 0 0 0 0 static icon setting r9 to r12 s1 to s16 states (specify in two bits) 0 0 0 0 0 0 0 0 partial display setting r13 bias area size display start area 0 0 0 0 0 0 0 0 alternating current signal setting r14 * * * * * alternating current signal 0 0 0 0 0 0 0 0 setting of gray scale pallet for normal display r15 to r22 gray scale data for normal display T6K41 2002-01-08 30 function description display data bit (1) when sdr 1 (2) when sdr 0 figure 11 seg7 seg8 seg6 seg5 seg3 seg4 seg2 seg1 1 1 1 0 0 1 0 0 gs3 gs2 gs1 gs0 1 1 1 0 0 1 0 0 gs3 gs2 gs1 gs0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 lcd display lcd control display ram bit 0 page 1 page seg122 seg121 seg123 seg124 seg126 seg125 seg127 seg128 1 1 1 0 0 1 0 0 gs3 gs2 gs1 gs0 1 1 1 0 0 1 0 0 gs3 gs2 gs1 gs0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 lcd display lcd control display ram bit 0 page 1 page T6K41 2002-01-08 31 the relationship between the duty and the lcd drive common signal output T6K41 can change duty by command setup. when cdr 1, assignment of lcd drive common signal output (com) pins are as shown below. duty assignment of com pins number of using pins 1/128 duty com1 com 128 128 1/100 duty com1 com50, com65 com114 100 1/80 duty com1 com40, com65 com104 80 1/72 duty com1 com36, com65 com100 72 partial display function the T6K41 has the partial display function for displaying arbitrary area by command setup. the partial display area size can be selected from 8 lines, 16 lines, 24 lines, or 32 lines. the partial start area (start line) can be selected from the following table. r13 partial start area no display start line r13 partial start area display start line x0h 0 com1 x8h 8 com65 x1h 1 com9 x9h 9 com73 x2h 2 com17 xah 10 com81 x3h 3 com25 xbh 11 com89 x4h 4 com33 xch 12 com97 x5h 5 com41 xdh 13 com105 x6h 6 com49 xeh 14 com113 x7h 7 com57 xfh 15 com121 z address determines the effective display ram area. for instance, when the partial display area size is set to 16 lines and the partial start area no. is set to 0, the data of effective display ram area shown below by z-address setup is displayed on 16 lines from com1. when z-address (zad) is set to 0, the range of xad 0 to xad 15 are effective when z-address (zad) is set to 30, the range of xad 30 to xad 46 are effective. note 12: x: invalid T6K41 2002-01-08 32 expansion function the T6K41's expansion function, allows two, T6K41s to drive an lcd panel of up to 256 by 128 dots. the table below shows the timing signals state by using m/s pin. timing signal output/input for expansion m/s cl pm fr ck sync blnk h output output output output output output l input input input input input input the table below shows the selectable function by using m/s pin. m/s h l ? single-chip mode disable expansion mode ? two-chip mode (master chip) timing signals and power voltage supply to slave chip. ? two-chip mode (slave chip) timing signals and power voltage are supplied from master chip. T6K41 2002-01-08 33 lcd drive waveform (normal display mode) lcd drive timing chart (1/128 duty) maximum ratings characteristics symbol rating unit power supply voltage (1) v dd , v in (note 13) 0.3 to 6.0 v power supply voltage (2) vlc0, 1, 2, 3, 4, 5, v cc , v out v ss 18.0 to v ss 0.3 v input voltage vinp (note 13, 14) 0.3 to v dd 0.3 v operating temperature t opr 30 to 85 c storage temperature t stg 55 to 125 c note 13: value based on v ss 0 v note 14: applies to input and data bus excluding v cc , v out , vlc0, vlc1, vlc2, vlc3, vlc4 and vlc5. v4 com1 v4 v4 v4 v5 v1 v1 v1 v0 v5 v0 v0 v4 v5 v5 v1 v1 v3 on v0 v4 v0 v2 v2 v5 v5 v3 v3 v0 v0 off on off com2 com12 seg1 seg128 v0 v3 T6K41 2002-01-08 34 electrical characteristics (1) (test conditions: unless otherwise noted, v ss 0 v, v dd 2.7 to 3.3 v, v cc 15.5 v, ta 25c) characteristics symbol test circuit test condition min typ. max unit applicable operating voltage (1) v dd 2.4 3.3 v v dd operating voltage (2) v in 2.7 3.3 v v in normal display v cc 6.0 v ss 16.5 v ss v v cc , v out operating voltage (3) partial display v cc 4.0 v ss 16.5 v ss v v cc , v out high level v ih 0.8 v dd v dd v input voltage low level v il 0 0.2 v dd v db0 to db7, d/i, wr , rd , 1 cs , cs2, rs, p/s, 68/80, si, sck, rst , stb , cl, pm, fr, sync, ck, blnk high level v oh i oh 400 a v dd 0.2 v dd v output voltage low level v ol i ol 400 a 0 0.2 v db0 to db7, so, cl, pm, fr, sync, ck segment driver on-resistance normal display mode rcol (note 15) 7.5 k seg1 to seg128 common driver on-resistance normal display mode rrow (note 15) 1.5 k com1 to com128 static icon on-resistance low power consumption mode ricon (note 16) 7.5 k coms, s1 to s16 input leakage current i il vinp v dd to gnd 1 1 a db0 to db7, d/i, wr , rd , 1 cs , cs2, rs, p/s, 68/80, si, sck, rst , stb , cl, pm, fr, sync, ck, blnk operating frequency fosc (note 22) 80.64 khz osc1 external clock input frequency fex (note 22) 80.64 khz osc1 external clock duty fduty 45 50 55 % osc1 external clock rise/fall time t r /t f 50 ns osc1 current consumption (1) i ss1 (note 17) 300 450 a v ss current consumption (2) i ss2 (note 18) 60 90 a v ss current consumption (3) i ss3 (note 19) 4 6 a v ss current consumption (4) i ss4 (note 20) 500 700 a v ss current consumption (5) i ssstb (note 21) 1 1 a v ss note 15: v cc 10.3 v, load current 100 a, 1/9 bias note 16: v dd 3.0 v, load current 100 a, 1/4 bias note 17: v dd 3.0 v, v out 15.4 v ( 6 booster), no data access, internal clock (osc 80.64 khz), no load, 1/12 bias, 1/128 duty, op-amp on, regulator on, normal display mode (gray scale), display pattern: check note 18: v dd 3.0 v, v out 5.2 v (doubler), no data access, internal clock (osc 5 khz), no load, 1/4 bias, 1/8 duty, op-amp on, regulator on, partial display mode, display pattern: check note 19: v dd 3.0 v, no data access, internal clock (osc 5.04 khz), no load, op-amp off, regulator off, low power consumption mode note 20: v dd 3.0 v, v out 6 booster, data access cycle (f/ce 1 mhz), internal clock (osc 82 khz), no load, 1/12 bias, 1/128 duty, op-amp on, regulator on note 21: v dd 3.3 v, v cc v ss 16.0 v, stb ?l? note 22: 1/128 duty, ffr 70 hz T6K41 2002-01-08 35 electrical characteristics (2) (test conditions: unless otherwise noted, v ss 0 v, v dd v in 2.7 to 3.3 v, v cc 15.5 v, ta 25c) characteristics symbol test circuit test condition min typ. max unit applicable regulator reference high voltage (1) (hi/lo 1) vhr1 ta 25c (note 23) 15.3 15.4 15.5 v v out regulator reference high voltage (2) (hi/lo 0) vhr2 ta 25c (note 24) 12.9 13.0 13.1 v v out regulator reference high voltage (3) (partial display mode) vhr3 ta 25c (note 24) 7.9 8.0 8.1 v v out regulator reference high voltage temperature gradient vhrinc ta 20 to 60c (note 23) tbd 0.05 tbd %/c v out note 23: v dd v in 3.0 v, contrast max, no display load, normal display mode note 24: v dd v in 3.0 v, contrast max, no display load, partial display mode electrical characteristics (3) (test conditions: unless otherwise specified, v ss 0 v, v dd 2.7 to 3.3 v, v cc 15.5 v, ta 25c) characteristics symbol test circuit test condition min typ. max unit applicable op-amp output voltage offset (1) vopoff (note 25) 100 100 mv vlc0, vlc1, vlc2, vlc3, vlc4 op-amp output voltage offset (2) vopoffs1 (note 26) 100 100 mv vlc0, vlc1, vlc2, vlc3, vlc4 op-amp output voltage offset (3) vopoffs2 iload 100 a 130 130 mv vlc0, vlc1, vlc2, vlc3, vlc4 note 25: v dd 2.7 to 3.3 v, v ss 0 v, 1/12 bias, 1/128 duty, v cc 15.4 v, op-amp on, no load vlc0: vlc0 vopoff vlc1: (vlc0 11/12) vlc1 vopoff vlc2: (vlc0 10/12) vlc2 vopoff vlc3: (vlc0 2/12) vlc3 vopoff vlc4: (vlc0 1/12) vlc4 vopoff note 26: v dd 2.7 to 3.3 v, v ss 0 v, 1/12 bias, 1/128 duty, v cc 16.0 v, op-amp on, no load vopoff1 ((vlc1 vlc2) (vlc0 vlc1)) ((vlc3 vlc4) (vlc4 vlc5)) vopoff2 ((vlc1 vlc2) (vlc0 vlc1)) ((vlc3 vlc4) (vlc4 vlc5)) T6K41 2002-01-08 36 test circuit (1) with doubler (2) with 3 booster a v in v dd osc1 c1a c1b v out v cc osc3 v ss c1 r2 iload external power supplied c2 osc 5.04 khz c1 c2 1.0 f iload 100 a a v in v dd osc1 c1a c1b v out v cc osc3 v ss c1 r2 iload external power supplied c2 osc 20.16 khz c1 c2 1.0 f iload 100 a c2a c2b c1 T6K41 2002-01-08 37 (3) with 4 booster (4) with 5 booster a v in v dd osc1 c1a c1b v out v cc osc2 v ss c1 r1 iload external power supplied c2 osc 40.32 khz c1 c2 1.0 f iload 200 a c2a c2b c1 c3a c3b c1 a v in v dd osc1 c1a c1b v out v cc osc2 v ss c1 r1 iload external power supplied c2 osc 63 khz c1 c2 1.0 f iload 200 a c2a c2b c1 c3a c3b c1 c4a c4b c1 T6K41 2002-01-08 38 (5) with 6 booster a v in v dd osc1 c1a c1b v out v cc osc2 v ss c1 r1 iload external power supplied c2 osc 80.64 khz c1 c2 1.0 f iload 200 a c2a c2b c1 c3a c3b c1 c4a c4b c1 c5a c5b c1 T6K41 2002-01-08 39 switching characteristics (1) (8-bit 80 series mpu interface) test conditions (unless otherwise noted, v ss 0 v, v dd 2.7 to 3.3 v, v cc 15.5 v, ta 25c) note 27: when the load circuit shown is added characteristics symbol min max unit enable cycle time t cyce 500 enable pulse width p wel 410 enable rise/fall time t er , t ef 25 address setup time t as 20 address hold time t ah 0 data setup time t ds 100 write data hold time t dhw 20 data delay time t dd (note 27) 300 read data hold time t dhr (note 27) 20 ns v ih v il t ah v ih v il t as p wel t er t ef t ds t dhw t er t cyce t dhr t ef t dd v il v il v il v il v ih v ih v ih v ih v il v ih v il v oh v ol v oh v ol v il v il v ih v ih v ih valid data valid data d/i 1 cs (cs2 h) wr data write rd data read db0 to 7 cl 100 pf (including wiring capacitance) load circuit cl T6K41 2002-01-08 40 switching characteristics (2) (8-bit 68 series mpu interface) test conditions (unless otherwise noted, v ss 0 v, v dd 2.7 to 3.3 v, v cc 15.5 v, ta 25c) characteristics symbol min max unit enable cycle time t cyce 500 enable pulse width p weh 410 enable rise/fall time t er , t ef 25 address setup time t as 20 address hold time t ah 0 data setup time t ds 100 write data hold time t dhw 20 data delay time t dd (note 28) 300 read data hold time t dhr (note 28) 20 ns note 28: when the load circuit shown is added v ih v il t ah v ih v il t as p weh t ef t er t ds t dhw t cyce t dhr t dd v il v il v il v il v ih v ih v ih v ih v il v ih v il v oh v ol v oh v ol valid data valid data d/i r/w ( wr ) data write data read e ( rd ) db0 to 7 cl 100 pf (including wiring capacitance) load circuit cl T6K41 2002-01-08 41 switching characteristics (3) (serial interface) test conditions (unless otherwise noted, v ss 0 v, v dd 2.7 to 3.3 v, v cc 15.5 v, ta 25c) characteristics symbol min max unit enable cycle time t cycc 2000 enable pulse width p wcl , p wch 900 enable rise/fall time t cr , t cf 25 data setup time t ds 250 data hold time t dh 100 data delay time t dd 200 ns p wcl t cf t cr t ds t dh t cycc v il v il v ih v ih v ih v il v ih v il v oh v ol sck si v il p wch t dd so T6K41 2002-01-08 42 switching characteristics (4) test conditions (unless otherwise noted, v ss 0 v, v dd 2.7 to 3.3 v, v cc 15.5 v, ta 25c) characteristics symbol min max unit v dd rise time v dst 1 ms reset hold v rst 1 s reset pulse width r stw 1 s v dst v il v ih v dd rst r stw v il v ih v rst T6K41 2002-01-08 43 application circuit T6K41 one chip (master) mode v dd 3.0 v using dc-dc converter ( 6) using internal cr oscillator using op-amp 80-series parallel interface 16 dot static icons 128 128 dot lcd T6K41 com1 to com64 vlc0 vlc1 vlc2 vlc3 vlc4 vlc5 v ref v cc v out cs2 68/80 mpu s1 to s16, coms 128 com65 to com128 64 64 16 1 seg1 to seg128 cs1 rs di wr rd db0 to db7 rst decoder iorq ax ay am an wr rd db0 to db7 reset reset circuit 8 p/s si sck stb v ss v dd v in m/s osc1 osc2 osc3 cna cnb v ss v dd 0.1 f 0.1 f 0.1 f 2.2 f T6K41 2002-01-08 44 toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. polyimide base film is hard and thin. be careful not to injure yourself on the film or to scratch any other parts with the film. try to design and manufacture products so that there is no chance of users touching the film after assembly, or if they do , that there is no chance of them injuring themselves. when cutting out the film, try to ensure that the film shavings do not cause accidents. after use, treat the leftover film and reel spacers as industrial waste. light striking a semiconductor device generates electromotive force due to photoelectric effects. in some cases this can cause the device to malfunction. this is especially true for devices in which the surface (back), or side of the chip is exposed. when designing circuits, make sure that devices are protected against incident light from external sources. exposure to light both during regular operation and during inspection must be taken into account. the products described in this document are subject to the foreign exchange and foreign trade laws. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. the information contained herein is subject to change without notice. 000707ebe restrictions on product use |
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