md1811 high speed quad mosfet driver 1 nr090105 initial release features 6ns rise and fall time 2 a peak output source/sink current 1.2v to 5v input cmos compatible 5v to 12v total supply voltage smart logic threshold low jitter design quad matched channels drives two n and two p channel mosfets outputs can swing below ground low inductance quad ? at no-lead package high-performance thermally-enhanced applications medical ultrasound imaging piezoelectric transducer drivers nondestructive evaluation pin diode driver clock driver/buffer high speed level translator general description the supertex md1811 is a high speed, quad mosfet driver designed to drive high voltage p/n-channel mosfets for medical ultrasound applications and other applications requiring a high output current for a capacitive load. the high-speed input stage of the md1811 can operate from a 1.2 to 5.0 volt logic interface with an optimum operating input signal range of 1.8 to 3.3 volts. an adaptive threshold circuit is used to set the level translator switch threshold to the average of the input logic 0 and logic 1 levels. the input logic levels may be ground referenced, even though the driver is putting out bipolar signals. the level translator uses a proprietary circuit, which provides dc coupling together with high-speed operation. the output stage of the md1811 has separate power connections enabling the output signal l and h levels to be chosen independently from the supply voltages used for the majority of the circuit. as an example, the input logic levels may be 0 and 1.8 volts, the control logic may be powered by +5 and C5 volts, and the output l and h levels may be varied anywhere over the range of C5 to +5 volts. the output stage is capable of peak currents of up to 2 amps, depending on the supply voltages used and load capacitance present. the oe pin serves a dual purpose. first, its logic h level is used to compute the threshold voltage level for the channel input level translators. secondly, when oe is low, the outputs are disabled, with the a & c output high and the b & d output low. this assists in properly pre-charging the ac coupling capacitors that may be used in series in the gate drive circuit of an external pmos and nmos transistor pair. typical application circuit 3.3v cmos logic inputs outa outb outc outd +10v 0.22 f v dd v h +10v 0.47 f v ss v l gnd ina inb inc ind oe +pls1 -pls1 enab +pls2 -pls2 10nf 10nf 10nf +100v 1f to piezoelectric transducer #1 -100v 1f supertex tc6320 supertex tc6320 10nf +100v 1f -100v 1f to p ie zo e l e ct r i c transducer #2 #1 #2 supertex md1811
2 nr090105 md1811 v dd -v ss logic supply voltage 4.5 13 v v ss low side supply voltage -5.5 0 v v h output high supply voltage v ss +2 v dd v v l output low supply voltage v ss v dd -2 v i ddq v dd quiescent current 0.8 ma no input transitions, oe = 1 i hq v h quiescent current 10 a i dd v dd average current 8.0 ma one channel on at 5.0mhz, no load i h v h average current 26 ma v ih input logic voltage high v oe -0.3 5 v for logic inputs ina, inb, inc, and ind v il input logic voltage low 0 0.3 v i ih input logic current high 1.0 a i il input logic current low 1.0 a v ih oe input logic voltage high 1.2 5 v for logic input oe v il oe input logic voltage low 0 0.3 v r in input logic impedance to gnd 12 20 30 k ? c in logic input capacitance 5 10 pf r sink output sink resistance 12.5 ? i sink = 50ma r source output source resistance 12.5 ? i source = 50ma i sink peak output sink current 2.0 a i source peak output source current 2.0 a outputs (v h = v dd = 12v, v l = v ss = gnd = 0v, v oe = 3.3v, t j = 25c) sym. parameter min. typ. max. units conditions ordering information device package options 16-lead 4x4x0.9 qfn md1811 MD1811K6-G ja 45c/w (1oz. 4-layer 3x4inch pcb) dc electrical characteristics (v h = v dd = 12v, v l = v ss = gnd = 0v, v oe = 3.3v, t j = 25c) sym. parameter min. typ. max. units conditions product marking information 1 st line device number 1811 2 nd line year, week code, lot number ywll example: 5a88 means lot #88 of ? rst or second week in 2005 absolute maximum ratings* v dd -v ss , logic supply voltage -0.5v to +13.5v v h , output high supply voltage v l -0.5v to v dd +0.5v v l , output low supply voltage v ss -0.5v to v h +0.5v vss, low side supply voltage -7v to +0.5v logic input levels v ss -0.5v to v ss +7v maximum junction temperature +125c storage temperature -65c to 150c soldering temperature 235c package power dissipation 2.2w pin 1 1811 ywll top view -g indicates package is rohs compliant (green) *absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground.
3 nr090105 md1811 ac electrical characteristics (v h = v dd = 12v, v l = v ss = gnd = 0v, v oe = 3.3v, t j = 25c) sym. parameter min. typ. max. units conditions t irf input or oe rise & fall time 10 ns logic input edge speed requirement t plh propagation delay when output is from low to high 7ns c load = 1000pf, see timing diagram input signal rise/fall time 2ns t phl propagation delay when output is from high to low 7ns t poe propagation delay oe to output 9 ns t r output rise time 6 ns t f output fall time 6 ns l t r - t f l rise and fall time matching 1.0 ns for each channel l t plh -t phl l propagation low to high and high to low matching 1.0 ns ? t dm propagation delay matching 2.0 ns device to device delay match logic truth table logic inputs output oe ina inb outa outb hllv h v h hlhv h v l hh lv l v h hhhv l v l lxxv h v l oe inc ind outc outd hllv h v h hlhv h v l hh lv l v h hhhv l v l lxxv h v l timing diagram and v th / v oe curve v oe v th 0 0.5 1.0 1.5 2.0 1.0 2.0 3.0 4.0 5.0 0 0.6v v oe/2 0 v 1. 8 v in t plh 1 0 % 9 0 % 5 0 % 0 v 1 2 v 5 0 % out t phl t r 9 0 % 1 0 % t f v th vs v oe
4 nr090105 md1811 simpli? ed block diagram detailed block diagram o e i n a i n b o u t a o u t b v d d v h i n c i n d o u t c o u t d g n d v s s v l md1811 inb level shifter v dd outc outd gnd v l level shifter v h level shifter v l v ss v dd v dd v h v h oe ina level shifter v ss level shifter v l outb outa v dd v h inc ind v ss sub v ss v l
5 nr090105 md1811 application information for proper operation of the md1811, low inductance bypass capacitors should be used on the various supply pins. the gnd pin should be connected to the logic ground. the ina, inb inc, ind, and oe pins should be connected to a logic source with a swing of gnd to v ll , where v ll is 1.2 to 5.0 volts. good trace practices should be followed corresponding to the desired operating speed. the internal circuitry of the md1811 is capable of operating up to 100mhz, with the primary speed limitation being the loading effects of the load capacitance. because of this speed and the high transient currents that result with capacitive loads, the bypass capacitors should be as close to the chip pins as possible. unless the load speci? cally requires bipolar drive, the v ss , and v l pins should have low inductance feed-through connections directly to a ground plane. if these voltages are not zero, then they need bypass capacitors in a manner similar to the positive power supplies. the power connection v dd should have a ceramic bypass capacitor to the ground plane with short leads and decoupling components to prevent resonance in the power leads. the voltages of v h and v l decide the output signal levels. these two pins can draw fast transient currents of up to 2a, so they should be provided with an appropriate bypass capacitor located next to the chip pins. a ceramic capacitor of up to 1.0f may be appropriate, with a series ferrite bead to prevent resonance in the power supply lead coming to the capacitor. pay particular attention to minimizing trace lengths, current loop area and using suf? cient trace width to reduce inductance. surface mount components are highly recommended. since the output impedance of this driver is very low, in some cases it may be desirable to add a small series resistance in series with the output signal to obtain better waveform transitions at the load terminals. this will of course reduce the output voltage slew rate at the terminals of a capacitive load. pay particular attention that parasitic couplings are minimized from the output to the input signal terminals. the parasitic feedback may cause oscillations or spurious waveform shapes on the edges of signal transitions. since the input operates with signals down to 1.2v even small coupled voltages may cause problems. use of a solid ground plane and good power and signal layout practices will prevent this problem. be careful that a circulating ground return current from a capacitive load cannot react with common inductance to cause noise voltages in the input logic circuitry. pin description v dd high side analog circuit, level shifter and gate drive supply voltage. v ss low side analog circuit, level shifter and gate drive supply voltage. v ss must be connected to the most negative potential of voltage supplies and powered-up ? rst. v h supply voltage for p-channel output stage v l supply voltage for n-channel output stage gnd logic input ground reference oe output-enable logic input. when oe is high, (v oe +v gnd )/2 sets the logic threshold level for inputs, when oe is low, outa and outc are at v h , outb and outd are at v l , regardless of the inputs ina, inb, inc or ind. keep oe low until ic powered up ina, inb, inc, ind logic input. controls output when oe is high. input logic high will cause the output to swing to v l . input logic low will cause the output to swing to v h . keep all logic inputs low until ic powered up. outa output driver. swings from v h to v l . intended to drive the gate of an external p-channel mosfet via a series capacitor. when oe is low, the output is disabled. outa will swing to v h turning off the external p-channel mosfet. outb output driver. swings from v h to v l . intended to drive the gate of an external n-channel mosfet via a series capacitor. when oe is low, the output is disabled. outb will swing to v l turning off the external n-channel mosfet. outc output driver. swings from v h to v l . intended to drive the gate of an external p-channel mosfet via a series capacitor. when oe is low, the output is disabled. outc will swing to v h turning off the external p-channel mosfet. outd output driver. swings from v h to v l . intended to drive the gate of an external n-channel mosfet via a series capacitor. when oe is low, the output is disabled. outd will swing to v l turning off the external n-channel mosfet. substrate the ic substrate is internally connected to the thermal pad. thermal pad and v ss must be connected externally.
6 doc.# dsfp - md1811 nr090105 md1811 pin con? guration pin # function 1inb 2v l 3gnd 4v l 5inc 6ind 7v ss 8outd 9outc 10 v h 11 v h 12 outb 13 outa 14 v dd 15 ina 16 oe note thermal pad, and pin #7 (v ss ), must be connected externally qfn-16 4x4x0.9 1 9 16 (top view, mm) 13 0.325 0.65 2.64 2.64 0.28 4 12 58
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