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lg semicon 8-bit microcontrollers gms81604/08 revision history rev 1.2 (dec. 1998) red r a w pa c kage dim e nsion on pag e 5~6. rev 1.1 (nov. 1998) ope r ating v oltage, 2.7~5.5 v is e xtend e d w ith 2.4~5.5v. operating te m perature, -20~80 c is ext e nd e d with - 20 ~ 8 5 c. add the "typic a l ch a r a cte r isti c s" on page 16, 17. add the unused port guidance on pag e 48. revision the information for the otp programming guidance, recommand using "intelligent mode" on page 49. add the chapter for otp programming specification as an appendix. rev 1.0 (nov. 1997) first edition
second edition published by mcu application team 1998 lg semicon co., ltd. all right reserved. additional information of this manual may be served by lg semicon offices in korea or dist ributors and representatives listed at address directory. lg semicon reserves the right to make changes to any information here in at any time without n otice. the information, diagrams and other data in this manual are correct and reliable; however, lg semicon co,. ltd. is in no way responsible for any violations of patents or other rights of the third party gene rated by the use of this manual.
table of contents overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 port structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 basic interval timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 timer/counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8-bit timer/counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 16-bit timer/counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8-bit capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 16-bit capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 analog to digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 how to use a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 buzzer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 brk interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 multiple interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 release stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 minimizing current consumption in stop mode . . . . . . . . . . . . . . . . . . . . . . . . 43 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 power fail processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 unused ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 GMS81608t (otp) programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 1. using the universal programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2. using the general eprom(27c256) programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 GMS81608t programming manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 appendix a. instruction set b. mask order sheet
gms81604 / GMS81608 cmos single-chip 8-bit microcontroller overview memory proliferation device rom bytes ram bytes gms81604 4k 256 GMS81608 8k 256 GMS81608t 8k eprom 256 development tools the gms800 family is supported by a full-featured macro assembler, an in-circuit emulators choice- jr. tm , socket adapters for otp device. the availability of otp devices are especially useful for customers expecting frequent code changes and updates. the otp devices, packaged in plastic pack - ages permit the user to program them once. in addition to the program memory, the configuration fuses must be programmed. gms81604, GMS81608 in-circuit emulators choice-jr. tm otp devices GMS81608t (40 dip) GMS81608t k (42 sdip) GMS81608t pl (44 pin plcc) socket adapters for otp devices oa816a-40pd (40 dip) oa816a-42sd (42 sdip) oa816a-44pl (44 plcc) assembler lgs macro assembler 4k/ 8k on-chip program memory 256 bytes of on-chip data ram instruction execution time: 0.5us at 8mhz 2.4v to 5.5v operating range 1~8 mhz operating frequency basic interval timer four 8-bit timer/ counters (can be used as two 16-bit) four external interrupt ports two programmable clock out one buzzer driving port 31 programmable i/o, 4 input pins, twelve interrupt sources all led direct drive output ports 8-channel 8-bit on-chip analog to digital converter power fail processor (noise immunity circuit) power down mode (stop mode) description the gms81604/08 is a high-performance cmos 8-bit microcontroller with 4k or 8k bytes of rom. the device is one of gms800 family. the lg semicon gms81604/08 is a powerful microcontroller which pr ovides a highly flexible and cost effective solution to many embedded control applications. the gms81604 /08 provides the following standard features: 8k bytes of rom, 256 bytes of ram, 35 i/o lines(33 lines for 40pd ip), 16-bit or 8-bit timer/counter, a precision analog to digital converter, on-chip oscillator and clock circuitry. in addition, the gms81604/08 supports power saving modes to reduce power consumption. the stop mode saves the ram contents but freezes the oscillator disabling all other chip functions until the next hardwa re reset or external interrupt. feature s lg semicon gms81604/08 1
device selection guide rom size package ordering code 4k bytes 40dip gms81604 42sdip gms81604 k 44plcc gms81604 pl 8k bytes 40dip GMS81608 42sdip GMS81608 k 44plcc GMS81608 pl 8k bytes (otp) 40dip GMS81608t 42sdip GMS81608t k 44plcc GMS81608t pl gms81604/08 lg semicon 2
block diagram figure 1. block diagram lg semicon gms81604/08 3
pin assignment packages part package type gms8160x gms8160x k gms8160x pl 40dip 42sdip 44plcc ? "x" means 4(4k bytes) or 8(8k bytes). 42 sdip 40 pdip 44 plcc figure 2. pin connections gms81604/08 lg semicon 4
lg semicon gms81604/08 package unit: inch 1.470 1.450 0.020 0.016 0.045 0.035 0.070 bsc 0.550 0.530 0.600 bsc 0-15 0 . 0 1 2 0 . 0 0 8 42sdip 0.140 0.120 min. 0.015 0.190 max. unit: inch 2.075 2.045 0.200 max. 0.022 0.015 0.065 0.045 0.100 bsc 0.550 0.530 0.600 bsc 0-15 0 . 0 1 2 0 . 0 0 8 40dip 0.140 0.120 min. 0.015 5
gms81604/08 lg s e mi co n 0.180 0.165 unit: inch 44plcc 0. 0 12 0. 0 075 0.120 0.090 0. 032 0. 026 0. 63 0 0. 59 0 min. 0.02 0 0. 6 56 0. 6 50 0. 6 95 0. 6 85 0. 656 0. 650 0. 695 0. 685 0.050 bsc 6
pin descriptions v dd : supply voltage. v ss : circuit ground. test : for test purposes only. connect it to v dd . reset : reset the mcu. x in : input to the inverting oscillator amplifier and input to the internal clock operating circuit. x out : output from the inverting oscillator amplifier. r00~r07 : r0 is an 8-bit, cmos, bidirectional i/o port. as an output port each pin can sink several ls ttl inputs. r0 pins that have 1 or 0 written to their port direction mode register, can be used as outputs or inputs. r10~r17 : r1 is an 8-bit, cmos, bidirectional i/o port. as an output port each pin can sink several ls ttl inputs. r1 pins that have 1 or 0 written to their port direction mode register, can be used as outputs or inputs. r40~r47 : r4 is an 8-bit, cmos, bidirectional i/o port. as an output port each pin can sink several ls ttl inputs. r4 pins that have 1 or 0 written to their port direction mode register, can be used as outputs or inputs. in addition, port 4 serves the functions of the various following special features. port pin alternate function r40 int0 (external interrupt 0) r41 int1 (external interrupt 1) r42 r43 int2 (external interrupt 2) int3 (external interrupt 3) r44 r45 ec0 (external count input to timer/ counter 0) ec2 (external count input to timer/ counter 2) r46 r47 t1o (timer 1 clock-out) t3o (timer 3 clock-out) r50, r51, r55 : r5 is a 3-bit, cmos, bidirectional i/o port. as an output port each pin can sink several ls ttl inputs. r5 pins that have 1 or 0 written to their port direction mode register, can be used as outputs or inputs. r50 and r51 differs in having internal pull-ups. port r55 serves the functions of special features. port pin alternate function r55 buz (square wave output for buzzer driving) r60~r67 : r6 is an 8-bit, cmos, i/o port. r60~r63 can be used as only input, can not be output, r64~r67 are bidirectional i/o port. as an output port each pin can sink several ls ttl inputs. r64~r67 pins that have 1 or 0 written to their port direction mode register, can be used as outputs or inputs. r6 serves the functions of following special features. port pin alternate function r60 r61 r62 r63 r64 r65 r66 r67 an0 (adc input 0) an1 (adc input 1) an2 (adc input 2) an3 (adc input 3) an4 (adc input 4) an5 (adc input 5) an6 (adc input 6) an7 (adc input 7) av dd : supply voltage to the ladder resistor of adc circuit. to enhance the resolution of analog to digital converter, use independent power source as well as possible, other than digital power source. lg semicon gms81604/08 7
port pin i/o descriptions pull-up/ pull-down reset stop mode primary functions secondary functions v dd - power supply to mcu - - - - v ss - ground - - - - av dd - power supply for adc - - - - test i test mode - - - - reset i reset the mcu - pull-up low last state x in i oscillation input - - oscillation low x out o oscillation output - - oscillation high r00~r07 i/o general i/o - - input 3) last state r10~r17 i/o general i/o - - input 3) last state r40/int0 r41/int1 r42/int2 r43/int3 r44/ ec0 r45/ ec2 r46/t1o r47/t3o i/o i/o i/o i/o i/o i/o i/o i/o general i/o " " " " " " " external interrupt 0 external interrupt 1 external interrupt 2 external interrupt 3 external count input 0 external count input 2 timer 1 output timer 3 output - input 3) last state r50 1) r51 1) r55/buz i/o i/o i/o general i/o " " - - buzzer driving output pull-up 2) pull-up 2) - input 3) last state r60/an0 r61/an1 r62/an2 r63/an3 r64/an4 r65/an5 r66/an6 r67/an7 i i i i i/o i/o i/o i/o general input " " " general i/o " " " analog input 0 analog input 1 analog input 2 analog input 3 analog input 4 analog input 5 analog input 6 analog input 7 - input 3) last state notes: 1. r50 and r51 are not physically served on 40 pin package. 2. when input mode is selected, pull-up is activated. in output mode, pull-up is de-activated . 3. in reset status, status of r50,r51 are weak high (typ. impedance 50~100k w ). other pin impedance is very high(high-z). gms81604/08 lg semicon 8
port structures data bus data bus data bus mux rd. protect diode protect diode v ss v dd direction reg. data reg. r00~r07, r10~r17 data bus data bus data bus pmr4 alternate function ex) int0 rd. mux data reg. direction reg. r40/int0, r41/int1, r42/int2, r43/int3, r44/ ec0 , r45/ ec2 data bus data bus selection (pmr4 or pmr5) alternate function ex) t1o direction reg. rd. data reg. data bus mux mux r46/t1o, r47/t3o, r55/buz lg semicon gms81604/08 9
data bus to a/d converter rd. rd. ch. select r60/an0, r61/an1, r62/an2, r63/an3 data reg. direction reg. rd. mux data bus data bus data bus to a/d converter ch. select rd. 0: output 1: reset, input, ad ch. select r64/an4, r65/an5, r66/an6, r67/an7 data reg. direction reg. rd. mux data bus data bus data bus pull-up resistor input mode: pull-up resistor is activated. output mode: pull-up resistor is de-activated. r50, r51 gms81604/08 lg semicon 10
pull-up resister reset otp: no p-ch diode test x in x out stop x in , x out lg semicon gms81604/08 11
electrical characteristics absolute maximum ratings recommended operating conditions parameter symbol condition specifications unit min. max. supply voltage v dd f xin = 8 mhz f xin = 4 mhz 4.5 2.4 5.5 5.5 v operating frequency f xin v dd = 4.5~5.5v v dd = 2.4~5.5v 1 1 8 4.2 mhz operating temperature t opr -20 85 c supply voltage . . . . . . . . . . . . . . . -0.3 to +6.0 v storage temperature . . . . . . . . . . . . -40 to +125 c voltage on any pin with respect to ground (v ss ) . . . . . . -0.3 to v dd +0.3 v maximum current out of v ss pin . . . . . . . . . 150 ma maximum current into v dd pin . . . . . . . . . 100 ma maximum current sunk by (i ol per i/o pin) . . . . 20 ma maximum output current sourced by (i oh per i/o pin) . . . . . . . . . . . . . . . 8 ma maximum current ( s i ol ) . . . . . . . . . . . . 120 ma maximum current ( s i oh ) . . . . . . . . . . . . . 50 ma notice: stresses above those listed under "absolute maxi - mum ratings" may cause permanent damage to the device. this is a stress rating only and func - tional operation of the device at these of any other conditions above those indicated in the op - erational sections of this specification is not im - plied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. gms81604/08 lg semicon 12
dc characteristics ( 5v ) (v dd = 5.0v 10%, v ss = 0v, t a = -20 ~ 85 c, f xin = 8 mhz) parameter pin symbol test condition specifications unit min. typ.* max. input high voltage x in , reset , r40~r45 v ih1 - 0.8v dd - v dd v r0,r1,r46,r47 r5,r6 v ih2 - 0.7v dd - v dd v input low voltage x in, reset , r40~r45 v il1 - 0 - 0.2v dd v r0,r1,r46,r47 r5,r6 v il2 - 0 - 0.3v dd v output high voltage r0,r1,r4,r5,r6 v oh v dd = 5v i oh = -2ma v dd -1.0 v dd -0.4 - v output low voltage r0,r1,r4,r5,r6 v ol v dd = 5v i ol = 10ma - 0.6 1.0 v power fail detect voltage v dd v pfd v dd =3~4v 3.0 - 4.0 v input leakage current reset , r0, r1, r4, r5, r6 i ih v i = v dd -5.0 - 5.0 ua i il v i = 0v -5.0 - 5.0 ua input pull-up current reset i p1 v dd = 5v -180 -120 -30 ua r50, r51 i p2 v dd = 5v -90 -60 -15 ua power current operating mode i dd f xin =4mhz f xin =8mhz - 4.5 8 8 15 ma stop mode i stop v dd = 5v - 2 20 ua hysteresis reset , r40~r45 v t + ~v t - v dd = 5v 0.5 0.8 - v * : data in "typ" column is at 5 v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. a/d converter characteristics ( 5v ) (v dd = 5.0v 10%, v ain = 5.0v, v ss = 0v, t a = 25 c ) parameter symbol specifications unit min. typ.* max. analog input range v ain v ss - v avdd v non-linearity error n le - 0.7 1.5 lsb differential non-linearity error n dif - 0.1 0.5 lsb zero offset error n off - 1.5 2.5 lsb full scale error n fs - 1.0 1.5 lsb accuracy a cc - 2.0 3.0 lsb av dd input current i avdd - 0.5 1.0 ma conversion time t conv - - 40 us analog power supply input range v avdd 4.5 5.0 5.5 v * : data in "typ" column is at 5 v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. lg semicon gms81604/08 13
dc characteristics ( 3v ) (v dd = 3.0v 10%, v ss = 0v, t a = -20 ~ 85 c, f xin = 4 mhz) parameter pin symbol test condition specifications unit min. typ.* max. input high voltage x in , reset , r40~r45 v ih1 - 0.8v dd - v dd v r0,r1,r46,r47 r5,r6 v ih2 - 0.7v dd - v dd v input low voltage x in , reset , r40~r45 v il1 - 0 - 0.2v dd v r0,r1,r46,r47 r5,r6 v il2 - 0 - 0.3v dd v output high voltage r0,r1,r4,r5,r6 v oh v dd = 3v i oh = -1ma v dd -0.5 v dd -0.3 - v output low voltage r0,r1,r4,r5,r6 v ol v dd = 3v i ol = 5ma - 0.5 0.7 v power fail detect voltage** - - - - - - v input leakage current reset , r0, r1, r4, r5, r6 i ih v i = v dd -3.0 - 3.0 ua i il v i = 0v -3.0 - 3.0 ua input pull-up current reset i p1 v dd = 3v -60 -40 -15 ua r50, r51 i p2 v dd = 3v -30 -20 -7.5 ua power current operating mode i dd f xin =4mhz - 2 5 ma stop mode i stop v dd = 3v - 1 10 ua hysteresis reset , r40~r45 v t + ~v t - v dd = 3v 0.3 0.6 - v * : data in "typ" column is at 3 v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. **: power fail detection function is not available on 3v operation. a/d converter characteristics ( 3v ) (v dd = 3.0v 10%, v ain = 3.0v, v ss = 0v, t a = 25 c) parameter symbol specifications unit min. typ.* max. analog input range v ain v ss - v avdd v non-linearity error n le - 0.2 1.0 lsb differential non-linearity error n dif - 0.1 0.5 lsb zero offset error n off - 2.0 2.5 lsb full scale error n fs - 1.0 1.5 lsb accuracy a cc - 2.0 3.0 lsb av dd input current i avdd - 0.3 0.5 ma conversion time t conv - - 40 us analog power supply input range v avdd 2.7 3.0 3.3 v * : data in "typ" column is at 3 v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. gms81604/08 lg semicon 14
ac characteristics (v dd = 2.7~5.5v, v ss = 0v, t a = -20 ~ 85 c) parameter pin symbol specifications unit min. typ. max. main clock frequency x in f xin 1 - 8 mhz oscillation stabilization time x in , x out t st 20 - - ms external clock pulse width x in t cpw 80 - - ns external clock transition time x in t rcp , t fcp - - 20 ns interrupt pulse width int0, int1, int2, int3 t iw 2 - - t sys * reset input low width reset t rst 8 - - t sys * event counter input pulse width ec0 , ec2 t ecw 2 - - t sys * event counter transition time ec0 , ec2 t rec , t fec - - 20 ns *: t sys is 2/f xin . timing chart x in 1 / f xin t rcp t fcp t cpw t cpw 0.1v dd 0.9v dd t iw 0.8v dd 0.2v dd t iw int0, int1 int2, int3 reset t rst 0.2v dd ec0 , ec2 t rec t fec t ecw t ecw 0.8v dd 0.2v dd lg semicon gms81604/08 15
typical characteristics these parameters are for design guidance only and are not tested. 1 2 3 4 0 i ol - v ol 6 12 18 24 i ol (ma) v dd =5.0v t a =25 c v ol (v) v dd =5v 1 2 3 4 0 i oh - v oh 6 12 18 24 i oh (ma) v dd =5.0v t a =25 c v dd -v oh (v) 2 3 4 5 0 6 (v) i dd - v dd 2 4 6 8 i dd (ma) t a =25 c v dd f xin = 4mhz f xin = 8mhz 2 3 4 5 0 6 (v) i stop 2 4 6 8 i stop (ua) t a =25 c v dd 1 0 operating area 2 4 6 8 f xin (mhz) t a = -20~80 c v dd (v) 2 3 4 5 gms81604/08 lg semicon 16
0.5 1.0 1.5 2.0 0 i ol - v ol 5 10 15 20 i ol (ma) v dd =3.0v t a =25 c v ol (v) v dd =3.0v 0.5 1.0 1.5 2.0 0 i oh - v oh -2 -4 -6 -8 i oh (ma) v dd -v oh (v) v dd =3.0v t a =25 c lg semicon gms81604/08 17
memory organization the gms81604 has separate address spaces for pro - gram and data memory. program memory can only be read, not written to. it can be up to 4k (8k for GMS81608) bytes of program memory. data mem - ory can be read and written to up to 256 bytes including the stack area. registers this device has six registers that are the program counter (pc), a accumulator (a), two index registers (x,y), the stack pointer (sp) and the program status word (psw). the program counter consists of 16-bit register. accumulator : the accumulator is the 8-bit general purpose register, used for data operation such as trans - fer, temporary saving and conditional judgment, etc. the accumulator can be used as a 16-bit register with y register as shown below. x register, y register : in the addressing modes which use these index registers, the register contents are added to the specified address and this becomes the actual address. these modes are extremely effective for referencing subroutine tables and memory tables. the index registers also have increment, decrement, compare and data transfer functions and they can be used as simple accumulators. stack pointer : the stack pointer is an 8-bit register used for occurrence interrupts and calling out subrou - tines. the stack can be located at any position within 100 h to 13f h of the internal data memory. data store and restore sequence to(from) stack area is shown in figure 0. caution: the stack pointer must be initialized by software because its value is undefined after reset. ex) ldx #03fh txsp ; sp ? 3f h program counter: the program counter is a 16-bit wide which consists of two 8-bit registers, pch, pcl. this counter indicates the address of the next instruc - tion to be executed. in reset state, the program counter has reset routine address (pch: ff h , pcl: fe h ). . program status word : the program status word (psw) contains several status bits that reflect the cur - rent state of the cpu. the psw shown in figure 6. it contains the negative flag, the overflow flag, the direct page flag, the break flag, the half carry (for bcd operations), the interrupt enable flag, the zero flag and the carry bit. [carry flag c] this flag stores any carry or borrow from the alu of cpu after an arithmetic operation and is also changed by the shift instruction or rotate instruction. [zero flag z] this flag is set when the result of an arithmetic opera - tion or data transfer is "0" and is cleared by any other result. [interrupt disable flag i] this flag enables/disables all interrupts except interrupt caused by reset or software pch pcl a x sp y psw accumulator program counter x register y register stack pointer program status word figure 3. configuration of registers y a y a two 8-bit registers one "ya" 16-bit register figure 4. configuration of ya 16-bit register 1 sp hardware fixed. 15 8 7 0 stack address (100 h ~13f h ) figure 5. stack pointer gms81604/08 lg semicon 18
brk instruction. all interrupts are disabled when cleared to "0". this flag immediately becomes "0" when an interrupt is served. it is set by the ei instruc - tion, cleared by the di instruction. [half carry flag h] after operation, set when there is a carry from bit 3 of alu or there is not a borrow from bit 4 of alu. this bit can not be set or cleared except clrv instruction, clearing with overflow flag (v). [break flag b] this flag set by software brk instruction to distin - guish brk from tcall instruction which as the same vector address. [direct page flag g] this flag assign direct page for direct addressing mode. in the direct addressing mode, addressing area is within zero page 00 h to ff h when this flag is "0". if it is set to "1", addressing area is 100 h to 1ff h . it is set by setg instruction, and cleared by clrg. [overflow flag v] this flag is set to "1" when an overflow occurs in the result of an arithmetic operation involving signs. an overflow occurs when the result of an addition or subtraction exceeds +127(7f h ) or -128(80 h ). the clrv instruction clears the overflow flag. there is no set instruction. when the bit instruction is executed, for other than the above, bit 6 of memory is copy to this flag. [negative flag n] this flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. when the bit instruction is executed, bit 7 of memory is copy to this flag. n carry flag receives carry out v g b h i z c zero flag interrupt enable flag half carry flag receives carry out from bit 1 of addition operands brk flag g flag to select direct page overflow flag negative flag psw msb lsb reset value: 00h figure 6. psw (program status word) register m(sp) ? (pch) 1) interrupt sp ? sp - 1 m(sp) ? (pcl) sp ? sp - 1 m(sp) ? (psw) sp ? sp - 1 (pch) ? m(sp) 2) reti sp ? sp + 1 (pcl) ? m(sp) sp ? sp + 1 (psw) ? m(sp) sp ? sp + 1 m(sp) ? (pch) 3) call sp ? sp - 1 m(sp) ? (pcl) sp ? sp - 1 4) ret sp ? sp + 1 (pch) ? m(sp) sp ? sp + 1 (pcl) ? m(sp) m(sp) ? acc. 5) push a (x,y,psw) sp ? sp - 1 m(sp) ? (pch) 6) pop a (x,y,psw) sp ? sp + 1 figure 7. stack operation lg semicon gms81604/08 19
program memory a 16-bit program counter is capable of addressing up to 64k bytes, but this devices have 4k bytes (8k for GMS81608) program memory space only the physi - cally implemented. accessing a location above ffff h will cause a wrap-around to 0000 h . figure 8, shows a map of the upper part of the program memory. after reset, the cpu begins execution from reset vector which is stored in address fffe h , ffff h . as shown in figure 8, each area is assigned a fixed location in program memory. program memory area contains the user program, page call (pcall) area contains subroutine program, to reduce program byte length because of using by 2 bytes pcall instead of 3 bytes call instruction. if it is frequently called, more useful to save program byte length. table call (tcall) causes the cpu to jump to each tcall address, where it commences execution of the service routine. the table call service locations are spaced at 2-byte interval : ffc0 h for tcall15, ffc2 h for tcall14, etc. address tcall name ffc0h ffc2h ffc4h ffc6h ffc8h ffcah ffcch ffceh ffd0h ffd2h ffd4h ffd6h ffd8h ffdah ffdch ffdeh tcall15 tcall14 tcall13 tcall12 tcall11 tcall10 tcall9 tcall8 tcall7 tcall6 tcall5 tcall4 tcall3 tcall2 tcall1 tcall0/ brk 1) 1) the brk software interrupt is using same address with tcall0. the interrupt causes the cpu to jump to specific location, where it commences execution of the service routine. the external interrupt 0, for example, is as - signed to location fffa h . the interrupt service loca - tions are spaced at 2-byte interval : fff8 h for external interrupt 1, fffa h for external interrupt 0, etc. any area from ff00 h to ffff h , if it not going to be used, its service location is available as general pur - pose program memory. address vector name ffe0h ffe2h ffe4h ffe6h ffe8h ffeah ffech ffeeh fff0h fff2h fff4h fff6h fff8h fffah fffch fffeh - - - basic interval timer watch dog timer analog to digital converter timer/ counter 3 timer/ counter 2 timer/ counter 1 timer/ counter 0 external interrupt 3 external interrupt 2 external interrupt 1 external interrupt 0 - reset f000h ffffh feffh ff00h program memory pcall area ffbfh ffc0h tcall area interrupt vector area ffdfh ffe0h GMS81608 e000h gms81604 figure 8. program memory gms81604/08 lg semicon 20
data memory figure 9 shows the internal data memory space avail - able. data memory are divided into three groups, a user ram, control registers and stack. internal data memory addresses are always one byte wide, which implies an address space of 256 bytes including the stack area. to access above ff h , g-flag should be set to "1" before, because after mcu reset, g-flag is "0". the stack pointer should be initialized within 00 h to 3f h by software because of implemented area of internal data memory. the control registers are used by the cpu and periph - eral functions for controlling the desired operation of the device. therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters, i/o ports. the control registers are in address c0 h to ff h . note that unoccupied addresses may not be imple - mented on the chip. read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. more detail informations of each register are explained in each peripheral sections. caution: write only registers can not be accessed by bit manipulation instruction. address symbol r/w power-on reset value c0 h c1 h c2 h c3 h c8 h c9 h ca h cb h cc h cd h d0 h d1 h d3 h 2) d3 h 2) e0 h e2 h e3 h e4 h e5 h e6 h e7 h e8 h e9 h ec h ed h f4 h f5 h f6 h f7 h f8 h r0 r0dd r1 r1dd r4 r4dd r5 r5dd r6 r6dd pmr4 pmr5 bitr ckctlr wdtr tm0 tm2 + note 3 + note 3 + note 3 + note 3 adcm adr bur pfdr ienl irql ienh irqh ieds r/w w 1) r/w w 1) r/w w 1) r/w w 1) r/w w 1) w 1) w 1) r w 1) w 1) r/w r/w r/w r/w r/w r/w r/w 4) r w 1) r/w r/w r/w r/w r/w w 1) x 00000000 x 00000000 x 00000000 x --0---00 x 00000000 00000000 --0----- 00000000 --010111 -0111111 00000000 00000000 x x x x --000001 x x -----100 000----- 000----- 00000000 00000000 00000000 legend - = unimplemented locations. x= undefined value. notes: 1) the all write only registers can not be accessed by bit manipulation instruction. 2) the register bitr and ckctlr are located at same address. address d3h is read as bitr, as written to ckctlr. 3) several names are given at same address. refer to below table. address when read when write timer mode capture mode e4h e5h e6h e7h t0 t1 t2 t3 cdr0 cdr1 cdr2 cdr3 tdr0 tdr1 tdr2 tdr3 4) only bit 0 of adcm can be read. 13f h data memory (ram) control registers bf h c0 h 00 h stack area ff h 100 h 256 bytes figure 9. data memory lg semicon gms81604/08 21
control registers for the gms81604/08 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c0 h r0 r0 port data register c1 h r0dd r0 port direction register c2 h r1 r1 port data register c3 h r1dd r1 port direction register c8 h r4 r4 port data register c9 h r4dd r4 port direction register ca h r5 r5 port data register cb h r5dd r5 port direction register cc h r6 r6 port data register cd h r6dd r6 port direction register d0 h pmr4 t3s t1s ec2s ec0s int3s int2s int1s int0s d1 h pmr5 - - buzs - - - - - d3 h 1) bitr basic interval timer data register d3 h 1) ckctlr - - wdton enpck btcl bts2 bts1 bts0 e0 h wdtr - wdtcl 6-bit watch dog counter register e2 h tm0 cap0 t1st t1sl1 t1sl0 t0st t0cn t0sl1 t0sl0 e3 h tm2 cap2 t3st t3sl1 t3sl0 t2st t2cn t2sl1 t2sl0 e4 h t0/ tdr0/ cdr0 timer 0 register/ timer data register 0/ capture data register 0 e5 h t1/ tdr1/ cdr1 timer 1 register/ timer data register 1/ capture data register 1 e6 h t2/ tdr2/ cdr2 timer 2 register/ timer data register 2/ capture data register 2 e7 h t3/ tdr3/ cdr3 timer 3 register/ timer data register 3/ capture data register 3 e8 h adcm - - aden ads2 ads1 ads0 adst adsf e9 h adr adc result data register ec h bur buck1 buck0 bu5 bu4 bu3 bu2 bu1 bu0 ed h 2) pfdr - - - - - pfd pfr pfs f4 h ienl ae wdte bite - - - - - f5 h irql aif wdtif bitif - - - - - f6 h ienh int0e int1e int2e int3e t0e t1e t2e t3e f7 h irqh int0if int1if int2if int3if t0if t1if t2if t3if f8 h ieds ied3h ied3l ied2h ied2l ied1h ied1l ied0h ied0l legend - = unimplemented locations. notes: 1) the register bitr and ckctlr are located at same address. address d3 h is read as bitr, written to ckctlr. 2) the register pfdr only be implemented on device, not on in-circuit emulator. gms81604/08 lg semicon 22
i/o ports the gms81604/08 have five ports, r0, r1, r4, r5, r6. these ports pins may be multiplexed with an alternate function for the peripheral features on the device. in general, when a initial reset state, all ports are used as a general purpose input port. all pins have data direction registers which can con - figure these pins as output or input. a "1" in the port direction register configures the corresponding port pin as output. conversely, write "0" to the corresponding bit to specify as an input pin. for example, to use the even numbered bit of r1 as output ports and the odd numbered bits as input ports, write "55 h " to address c1 h (r0 direction register) during initial setting as shown in figure 10. reading data register reads the status of the pins whereas writing to it will write to the port latch. r0 and r0dd registers: r0 is a 8-bit bidirectional i/o port (address c0 h ). each pin is individually con - figurable as input and output through the r0dd regis - ter (address c1 h ). r1 and r1dd registers: r1 is an 8-bit bidirectional i/o port (address c2 h ). each pin is individually con - figurable as input and output through the r1dd regis - ter (address c3 h ). r4 and r4dd registers: r4 is an 8-bit bidirectional i/o port (address c8 h ). each pin is individually con - figurable as input and output through the r4dd regis - ter (address c9 h ). in addition, port r4 is multiplexed with various special features. the control register pmr4 (address d0 h ) controls to select alternate function. after reset, this value is "0", port may be used as general i/o ports. to select alternate function such as external interrupt or external counter or timer clock out, write "1" to the corresponding bit of pmr4. port pin alternate function r40 r41 r42 r43 int0 (external interrupt 0) int1 (external interrupt 1) int2 (external interrupt 2) int3 (external interrupt 3) r44 r45 ec0 (external count input to timer/ counter 0) ec2 (external count input to timer/ counter 2) r46 r47 t1o (timer 1 clock-out) t3o (timer 3 clock-out) regardless of the direction register r4dd, pmr4 is selected to use as alternate functions, port pin can be used as a corresponding alternate features. 0 1 0 1 0 1 0 1 i i o i o i o o write "55 h " to port r0 direction register 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 port r0 data r0 direction r1 data r1 direction c0h c1h c2h c3h i: input port o: output port figure 10. example port i/o assignment r07 r06 r05 r04 r03 r02 r01 r00 port 0 data register address: c0 h reset value: undefined r07 r06 r05 r04 r03 r02 r01 r00 r0dd address: c1 h reset value: 00000000 direction select 0: input 1: output input/ output data r0 port 0 direction register r17 r16 r15 r14 r13 r12 r11 r10 port 1 data register address: c2 h reset value: undefined r17 r16 r15 r14 r13 r12 r11 r10 r1dd address: c3 h reset value: 00000000 direction select 0: input 1: output input/ output data r1 port 1 direction register lg semicon gms81604/08 23
r5 and r5dd registers: r5 is a 3-bit bidirectional i/o port (address ca h ). r50, r51 and r55 only are physically implemented on this device. r50, r51 have internal pullups which is activated on input but deactivated on output. as input, these pins that are externally pull low will source current (i p2 on the dc characteristics) because of the internal pullups. caution: pins r50, r51 are present on 42sdip, 44plcc package only, but not on 40dip . refer to pin as - signment. each pin is individually configurable as input and output through the r5dd register (address cb h ). port pin alternate function r55 buz (square-wave output for buzzer driving) the control register pmr5 (address d1 h ) controls the selection alternate function. after reset, this value is "0", port may be used as general i/o ports. to use buzzer function, write "1" to the pmr5. r47 r46 r45 r44 r43 r42 r41 r40 port 4 data register address: c8 h reset value: undefined r47 r46 r45 r44 r43 r42 r41 r40 r4dd address: c9 h reset value: 00000000 direction select 0: input 1: output input/ output data r4 port 4 direction register t3s t1s ec2s ec0s int3s int2s int1s int0s pmr4 address: d0 h reset value: 00000000 0: r41 1: int1 0: r47 1: t3o 0: r45 1: ec2 0: r46 1: t1o 0: r44 1: ec0 0: r43 1: int3 0: r42 1: int2 0: r40 1: int0 msb lsb ieds address: f8 h reset value: 00000000 edge selection register external interrupt edge select 00: reserved 01: falling (1-to-0 transition) 10: rising (0-to-1 transition) 11: both (rising & falling) int3 int2 int1 int0 port 4 mode register - - r55 - - - r51 r50 port 5 data register address: ca h reset value: undefined - - r55 - - - r51 r50 r5dd address: cb h reset value: --0---00 direction select 0: input 1: output input/ output data r5 port 5 direction register - - buzs - - - - - pmr5 address: d1 h reset value: --0----- port 5 mode register 0: r55 1: buz (buzzer port) gms81604/08 lg semicon 24
r6 and r6dd registers: r6 is an 8-bit port (address cc h ). pins r64~r67 are individually configurable as input and output through the r6dd register (address cd h ), but pins r60~r63 are input only. port pin alternate function r60 r61 r62 r63 r64 r65 r66 r67 an0 (adc input 0) an1 (adc input 1) an2 (adc input 2) an3 (adc input 3) an4 (adc input 4) an5 (adc input 5) an6 (adc input 6) an7 (adc input 7) r6dd (address cd h ) controls the direction of the r6 pins, even when they are being used as analog inputs. the user must make sure to keep the pins configured as inputs when using them as analog inputs. on the initial reset, r60 can not be used digital input port, because this port is selected as an ana- log input port by adcm register. to use this port as a digital i/o port, change the value of lower 4 bits of adcm (address 0e8 h ). on the other hand, r6 port, all eight pins can not be used as digital i/o port simultaneousely. at least one pin is used as an analog input. r67 r66 r65 r64 r63 r62 r61 r60 port 6 data register address: cc h reset value: undefined r67 r66 r65 r64 r63 r62 r61 r60 r6dd address: cd h reset value: 0000---- direction select 0: input 1: output input/ output data r6 port 6 direction register fixed as input. can not write. lg semicon gms81604/08 25
basic interval timer the gms81604 has one 8-bit basic interval timer that is free-run, can not stop. block diagram is shown in figure 11. the 8-bit basic interval timer register (bitr) is incre - mented every internal count pulse which is divided by prescaler. since prescaler has divided ratio by 16 to 2048, the count rate is 1/16 to 1/2048 of the oscillator frequency. as the count overflows from ff h to 00 h , this overflow causes to generate the basic interval timer interrupt. the bitr is interrupt request flag of basic interval timer. caution: all control bits of basic interval timer are in ckctlr register which is located at same ad - dress of bitr (address d3 h ). address d3 h is read as bitr, written to ckctlr. when write "1" to bit btcl of ckctlr, data register is cleared to "0" and restart to count-up. it becomes "0" after one machine cycle by hardware. ? 16 ? 32 ? 64 ? 128 ? 256 ? 512 ? 1024 ? 2048 bitr (8 bits) basic interval timer interrupt btcl bitif bts[2:0] clear x in pin prescaler mux 3 8 figure 11. block diagram of the basic interval timer symbol position name and significance wdton ckctlr.5 wdton=1, enables watch dog timer operation, wdton=0, operates as a 6-bit timer enpck ckctlr.4 enable peripheral clock. btcl ckctlr.3 btcl is set to "1", bitr is cleared. btcl becomes "0" automatically after one machine cycle, and starts counting. basic interval timer clock selection bts2 bts1 bts0 prescale value 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 16 32 64 128 256 512 1024 2048 wdton - enpck btcl bts1 bts2 bts0 - ckctlr address: d3 h reset value: --010111 figure 12. ckctlr: control clock register gms81604/08 lg semicon 26
timer/counter the gms81604 has four timer/counter registers. each module can generate an interrupt to indicate that an event has occurred (i.e. timer match). timer 0 and timer 1 are can be used either the two 8-bit timer/counter or one 16-bit timer/counter to combine them. also timer 2 and timer 3 are same. in the "timer" function, the register is incremented every internal clock input. thus, one can think of it as counting internal clock input. since a least clock con - sists of 4 and most clock consists of 64 oscillator periods, the count rate is 1/4 to 1/64 of the oscillator frequency. in the "counter" function, the register is incremented in response to a 1-to-0 (falling edge) transition at its corresponding external input pin, ec0 or ec2 . in addition the "capture" function, the register is incre - mented in response external or internal clock sources same with timer or counter function. when external clock edge input, the count register is captured into timer data register correspondingly. it has four operating modes: "8-bit timer/counter", "16-bit timer/counter", "8-bit capture", "16-bit cap - ture" which are selected by bit in timer mode register tm0 and tm2 as shown in right table. in operation of timer 2, timer 3, their operations are same with timer 0, timer 1, respectively. tm0 for timer 0, timer 1 cap0 t1sl1 t1sl0 timer 0 timer 1 0 0 0 16-bit timer/counter 1 0 0 16-bit capture 0 x x 8-bit timer 8-bit timer 1 x x 8-bit capture 8-bit timer tm2 for timer 2, timer 3 cap2 t3sl1 t3sl0 timer 2 timer 3 0 0 0 16-bit timer/counter 1 0 0 16-bit capture 0 x x 8-bit timer 8-bit timer 1 x x 8-bit capture 8-bit timer timer 1 timer 0 t1sl1 t1sl0 input clock t0sl1 t0sl0 input clock 0 0 1 1 0 1 0 1 16-bit timer mode (note 1) 8-bit timer, ? 4 ? prescaler 8-bit timer, ? 16 8-bit timer, ? 64 0 0 1 1 0 1 0 1 timer or counter select ? 4 ? prescaler ? 16 ? 64 tm0 lsb msb t1sl1 t1st t1sl0 t0st t0sl1 t0cn t0sl0 cap0 capture mode selection flag, when set, timer operate as one 16-bit capture timer combine two 8-bit timers. cap0 when set, timer 1 count register is cleared and start again. when cleared, stop the counting. t1st start/stop control for timer 0. a logic 1 starts the timer. t0cn when set, the timer 0 count register is cleared and start again. when cleared, stop the counting. t0st timer 1 timer 0 tm2 is in figure 14. note: if this mode selected, the timer 0 are used as a 16-bit timer mode. the timer 1 is engaged to the ti mer 0. the source clock is selected by bits t0sl1 and t0sl0. address: e2 h reset value: 00h figure 13. tm0: timer 0, timer 1 mode register lg semicon gms81604/08 27
timer 3 timer 2 t3sl1 t3sl0 input clock t2sl1 t2sl0 input clock 0 0 1 1 0 1 0 1 16-bit timer mode (note 1) 8-bit timer, ? 4 ? prescaler 8-bit timer, ? 16 8-bit timer, ? 64 0 0 1 1 0 1 0 1 timer or counter select ? 4 ? prescaler ? 16 ? 64 lsb msb t3sl1 t3st t3sl0 t2st t2sl1 t2cn t2sl0 cap2 tm2 capture mode selection flag, when set, timer operate as one 16-bit timer combine two 8-bit timers. see figure 21 and figure 22. cap2 when set, timer 3 count register is cleared and start again. when cleared, stop the counting. t3st start/stop control for timer 2. a logic 1 starts the timer. t2cn when set, timer 2 count register is cleared and start again. when cleared, stop the counting. t2st note: if this mode selected, the timer 2 and timer 3 are used as a 16-bit timer mode. the timer 3 is engag ed to the timer 2. the source clock is selected by bits t2sl1 and t2sl0. timer 3 timer 2 address: e3 h reset value: 00 h figure 14. tm2: timer 2, timer 3 mode register lsb msb tdr0 tdr1 tdr2 tdr3 address: e4 h reset value: 00 h address: e5 h reset value: 00 h address: e6 h reset value: 00 h address: e7 h reset value: 00 h figure 15. tdrx : timer x data register gms81604/08 lg semicon 28
8-bit timer/counter mode the gms81604 has four 8-bit timer/counters, timer 0, timer 1, timer 2, timer 3. the timer 0, timer 1 only as shown in figure 16. because other timer/count - ers are same with timer 0 and timer 1. the "timer" or "counter" function is selected by control registers tm0, tm2 as shown in figure 13 and figure 14. to use as an 8-bit timer/counter mode, bit cap 0 of tm0 is cleared to "0" and bits t1sl1, t1sl0 of tm0 or bits t3sl1, t3sl0 of tm2 should not set to zero (figure 16). these timers have each 8-bit count register and data register. the count register is incremented by every internal or external clock input. the internal clock has a prescaler divide ratio option of 4, 16, 64 (selected by control bits txsl1, txsl0 of register tmx). in the timer 0, timer register t0 increments from 00 h until it matches tdr0 and then reset to 00 h . the match output of timer 0 generates timer 0 interrupt (latched in t0if bit) as tdrx and tx register are in same address, when reading it as a tx, written to tdrx. caution: the contents of timer data register tdrx should be initialized 1 h ~ff h except 0 h , because it is un - defined after reset. in counter function, the counter is incremented every 1-to 0 (falling edge) transition of ec0 or ec2 pin. in order to use counter function, the bit ec0s, ec2s of the port mode register pmr4 are set to "1". the timer 0 can be used as a counter by pin ec0 input, but timer 1 can not. similarly, timer 2 can be used by pin ec2 input but timer 3 can not. tm0 cap0 t1st t1sl1 t1sl0 t0st t0cn t0sl1 t0sl0 0 x 1 0 1 0 x x x x ? 4 ? 16 ? 64 tdr0 (8-bits) timer 0 interrupt t0sl[1:0] x in pin ec0 pin t0 (8-bits) t0cn comparator t0st clear timer 1 interrupt t1o pin t1if f/f t0if mux t1sl[1:0] mux tdr1 (8-bits) t1 (8-bits) t1st prescaler comparator clear timer 0 timer 1 msb lsb edge detector 0: stop 1: clear and start 0: stop 1: clear and start address: e2 h reset value: 00 h 1 0 figure 16. 8-bit timer/counter mode lg semicon gms81604/08 29
to pulse out, the timer match can goes to port pin as shown in figure 16. thus, pulse out is generated by the timer match. these operation is implemented to pin, t1o and t3o. the pin t1o is output from timer 1, the t3o is from timer 3. operation of t3o is omitted in this document, but still presents and same architecture with t1o. f txo ( hz ) = oscillator frequency 2 prescaler tdr t3s 0: r47 1: t3o (timer 3 output) int3s 0: r43 1: int3 (external interrupt 3) t1s 0: r46 1: t1o (timer 1 output) int2s 0: r42 1: int2 (external interrupt 2) ec2s 0: r45 1: ec2 (external input pin for timer 2 int1s 0: r41 1: int1 (external interrupt 1) ec0s 0: r44 1: ec0 (external input pin for timer 0 int0s 0: r40 1: int0 (external interrupt 0) lsb msb ec2s t1s ec0s int3s int1s int2s int0s t3s pmr4 address: d0 h reset value: 00 h figure 17. pmr4: r4 port mode register tdr0 match (tdr0 = t0) 00 h timer 0 interrupt time clear clear occur interrupt clear occur interrupt f1 f2 f3 f5 interrupt period occur interrupt 1 2 3 f0 count pulse period when tm0: 00110111 (prescaler= 16) tdr0: f9 h = 249 d oscillator freq.= 4mhz interrupt period = 1 4 10 6 hz 16 ( 249 + 1 ) = 1ms f6 f7 f8 f9 f4 ex) 4 us figure 18. timer count example gms81604/08 lg semicon 30
16-bit timer/counter mode the timer register is being run with all 16 bits. a 16-bit timer/counter register t0, t1 are incremented from 0000 h until it matches tdr0, tdr1 and then resets to 0000 h . the match output generates timer 0 inter - rupt. the clock source of the timer 0 is selected either internal or external clock by bit t0sl1, t0sl0. even if the timer 0 (including the timer 1) is used as a 16-bit timer, the timer 2 and timer 3 can still be used as either two 8-bit timer or one 16-bit timer by setting the tm2. reversely, even if the timer 2 (including the timer 3) is used as a 16-bit timer, the timer 0 and timer 1 can still be used as 8-bit timer independently. tm0 cap0 t1st t1sl1 t1sl0 t0st t0cn t0sl1 t0sl0 0 x 0 0 x x x x msb lsb ? 4 ? 16 ? 64 tdr0 (8-bits) timer 0 interrupt t0sl[1:0] xin pin ec0 pin t0 (8-bits) t0cn comparator t0st clear t0if mux prescaler timer 0 tdr1 (8-bits) t1 (8-bits) this figure is a example of the timer 0 and timer 1. in the timer 2, each registers and flags may be changed correspondingly. (not timer 1 interrupt) edge detector 0: stop 1: clear and start address: e2 h reset value: 00 h higher lower (+timer1) 1 0 do not care figure 19. 16-bit timer/counter mode tdr0 match 00 h timer interrupt time clear clear clear occur interrupt occur interrupt match clear and start stop stop txst txcn restart count up high low high low figure 20. timer count operation lg semicon gms81604/08 31
8-bit capture mode the timer 0 capture mode is set by bit cap0 of timer mode register tm0 (bit cap2 of timer mode register tm2 for timer 2) as shown in figure 21. in this mode, timer 1 still operates as an 8-bit timer/counter. as mentioned above, not only timer 0 but timer 2 can also be used as a capture mode. in 8-bit capture mode, timer 1 and timer 3 are can not be used as a capture mode. the timer/counter register is incremented in response internal or external input. this counting function is same with normal timer mode, but timer interrupt is not generated. timer/counter still does the above, but with the added feature that a edge transition at external input intx pin causes the current value in the timer x register (t0,t2), to be captured into registers cdrx (cdr0, cdr2), respectively. after captured, timer x register is cleared and restarts by hardware. caution: the cdrx and tdrx are in same address. in the capture mode, reading operation is read the cdrx, not tdrx because path is opened to the cdrx. it has three transition modes: "falling edge", "rising edge", "both edge" which are selected by interrupt edge selection register ieds (refer to external inter - rupt section). in addition, the transition at intx pin generate an interrupt. tm0 cap0 t1st t1sl1 t1sl0 t0st t0cn t0sl1 t0sl0 1 x 1 0 1 0 x x x x ? 4 ? 16 ? 64 t0sl[1:0] xin pin ec0 pin t0 (8-bits) t0cn t0st mux int0 pin cdr0 (8-bits) int0 interrupt int0if ieds[1:0] this figure is a example of the timer 0. in the timer 2, each registers and flags may be changed correspondingly. edge detector prescaler msb lsb 0: stop 1: clear and start capture address: e2 h reset value: 00 h 1 0 figure 21. 8-bit capture mode gms81604/08 lg semicon 32
16-bit capture mode 16-bit capture mode is the same as 8-bit capture, except that the timer register is being run will 16 bits. tm0 cap0 t1st t1sl1 t1sl0 t0st t0cn t0sl1 t0sl0 1 x 0 0 x x x x msb lsb ? 4 ? 16 ? 64 t0sl[1:0] xin pin ec0 pin t1 (8-bits) t0cn t0st mux int0 pin cdr1 (8-bits) int 0 interrupt int0if ieds[1:0] t0 (8-bits) cdr0 (8-bits) prescaler edge detector this figure is a example of using timer 0 and timer 1. in the timer 2 and timer 3 each registers and flags may be changed. timer 0 + timer 1 address: e2 h reset value: 00 h 0: stop 1: clear and start higher lower 1 0 do not care figure 22. 16-bit capture mode lg semicon gms81604/08 33
analog to digital converter the analog-to-digital converter (a/d) allows conver - sion of an analog input signal to a corresponding 8-bit digital value. the a/d module has eight analog inputs, which are multiplexed into one sample and hold. the output of the sample and hold is the input into the converter, which generates the result via successive approximation. the analog supply voltage is con - nected to av dd of ladder resistance of a/d module. the a/d module has two registers which are the con - trol register adcm and a/d result register adr. the register adcm, shown in figure 24, controls the operation of the a/d converter module. the port pins can be configured as analog inputs or digital i/o. to use analog inputs, i/o is selected input mode by r6dd direction register. how to use a/d converter the processing of conversion is start when the start bit adst is set to "1". after one cycle, it is cleared by hardware. the register adr contains the results of the a/d conversion. when the conversion is completed, the result is loaded into the adr, the a/d conversion status bit adsf is set to "1", and the a/d interrupt flag aif is set. the block diagram of the a/d module is shown in figure 23. the a/d status bit adsf is set automatically when a/d conversion is completed, cleared when a/d conversion is in process. the con - version time takes maximum 40 us (at f xin =4 mhz). r61/an1 ladder resistor decoder av dd pin r60/an0 r63/an3 r62/an2 r65/an5 r64/an4 r67/an7 r66/an6 successive approximation circuit adr a/d interrupt s/h ads[2:0] v in 001 010 011 100 101 110 111 input channel selection a/d result register 3 aden address: e9 h reset value: undefined aif sample & hold "0" "1" 000 figure 23. a/d block diagram gms81604/08 lg semicon 34
lsb msb aden - ads2 ads1 adst ads0 adsf - adcm a/d status bit 0: a/d conversion is in process. 1: a/d conversion is completed, not in process. a/d start bit 1: setting this bit starts an a/d conversion. after one cycle, bit is cleared to "0". 0: bit force to zero. analog channel select 000: channel 0 (r60/an0) 001: channel 1 (r61/an1) 010: channel 2 (r62/an2) 011: channel 3 (r63/an3) 100: channel 4 (r64/an4) 101: channel 5 (r65/an5) 110: channel 6 (r66/an6) 111: channel 7 (r67/an7) a/d converter enable bit 0: a/d converter module shut off and consumes no operating current. 1: enable a/d converter reserved address: e8 h reset value: --00001 r/w r/w r/w r/w r/w r figure 24. adcm: a/d converter control register lg semicon gms81604/08 35
buzzer function the buzzer driver consists of 6-bit binary counter, the buzzer register bur and the clock selector. it gener - ates square-wave which is very wide range frequency (250 hz~125 khz at f xin =4 mhz) by user program - mable counter. pin r55 is assigned for output port of buzzer driver by setting the bit 5 of pmr5 (address d1 h ) to "1". at this time, the pin r55 must be defined as output mode (the bit 5 of r5dd=1) the bit 0 to 5 of bur determines output frequency for buzzer driving. frequency calculation is following below. f buz ( hz ) = f xin 2 prescaler ratio bur value f buz : buzzer frequency f xin : min oscillator frequency prescaler: prescaler divide ratio by buck1, buck0 bur:lower 6-bit of bur. buzzer period data value the bits buck1, buck0 of bur selects the source clock from prescaler output. the 6-bit buzzer counter is cleared and start the count - ing by writing signal to the register bur. it is incre - ment from 00 h until it matches 6-bit register bur. caution: the register bur contains undefined value after reset. it must be initialized none 0 h (1 h ~3f h ). ? 16 ? 32 ? 64 ? 128 counter (6 bit) bur[5:0] (6 bit) mux bur[7:6] f/f x in pin prescaler bur register buz pin figure 25. buzzer driver lsb msb bu5 buck0 bu4 bu3 bu1 bu2 bu0 buck1 bur address: ec h reset value: undefined buzzer source clock selection 00: fx in ? 16 01: fx in ? 32 10: fx in ? 64 11: fx in ? 128 buzzer period data figure 26. bur: buzzer period data register lsb msb buzs - - - - - - - pmr5 address: d1 h reset value: --0----- r55/ buz port selection 0: r55 1: buz figure 27. pmr5: port 5 mode register gms81604/08 lg semicon 36
interrupts the gms81604/08 interrupt circuits consist of inter - rupt enable register (ienh, ienl), interrupt request flags of irqh, irql, priority circuit and master en - able flag(i flag of psw). the configuration of interrupt circuit is shown in figure 28. 12 interrupt sources are provided including the reset. interrupt source symbol priority hardware reset external interrupt 0 external interrupt 1 external interrupt 2 external interrupt 3 timer/counter 0 timer/counter 1 timer/counter 2 timer/counter 3 ad converter watch dog timer basic interval timer rst int0if int1if int2if int3if t0if t1if t2if t3if aif wdtif bitif 1 2 3 4 5 6 7 8 9 10 11 12 *vector addresses are shown in program memory section. the external interrupts int0~int3 can each be tran - sition-activated, depending on interrupt edge selection register. the timer 0~timer 3 interrupts are generated by t0if ~t3if, which are set by a match in their respective timer/counter register. the ad converter interrupt is generated by aif which is set by finishing the analog to digital conversion. the watch dog timer interrupt is generated by wdtif which set by a match in watch dog timer register. the basic interval timer interrupt is generated by bitif which are set by a overflow in the timer/counter register. the interrupts are controlled by the interrupt master enable flag i-flag (bit 2 of psw), the interrupt enable register (ienh, ienl) and the interrupt request flags (in irqh, irql) except power-on reset and software brk interrupt. interrupt enable registers are shown in figure 29. these registers are composed of interrupt enable flags of each interrupt source, these flags determines int0if int1if int2if int3if t0if t1if t2if t3if aif wdtif bitif priority control int2 reset brk (software interrupt) i-flag 1 0 i-flag is in psw, it is cleared by "di", set by "ei" instruction. when it goes interrupt service, i-flag is cleared by hardware, thus any other interrupt are inhibited. when interrupt service is completed by "reti" instruction, i-flag is set to "1" by hardware. ienh ienl irqh irql int1 int0 int3 timer 0 timer 1 timer 2 timer 3 adc wdt basic interval timer to cpu msb lsb bit 7 bit 6 bit 5 release the stop (if in stop mode) master enable flag 0 1 figure 28. block diagram of interrupt function lg semicon gms81604/08 37
whether an interrupt will be accepted or not. when enable flag is "0", a corresponding interrupt source is prohibited. note that psw contains also a master en - able bit, i-flag, which disables all interrupts at once. when an interrupt is responded to, the i-flag is cleared to disable any further interrupt, the return address is pushed into the stack and the pc is vectored to. once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit(s) must be cleared in software before reenabling interrupts to avoid recursive inter - rupts. the interrupt request flags are able to be read and write. external interrupt external interrupt on int0~int3 pins are edge trig - gered depending the edge selection register ieds. the edge detection of external interrupt has three transition activated mode: rising edge, falling edge, both edge. int0~int3 are multiplexed with general i/o ports (r40~r43). to use external interrupt pin, set bit 0 to bit 3 of the port mode register pmr4. the pmr4 and ieds registers are shown in figure 32. msb lsb lsb msb int2e int1e int3e t0e t2e t1e t3e int0e ienh enables or disables the interrupt individually. if flag is cleared, the interrupt is disabled. 0: disable 1: enable bite wdte - - - - - ae ienl address: f6 h reset value: 00 h address: f4 h reset value: 000----- figure 29. ienh, ienl: interrupt enable registers int0 int1 int2 int3 int0 interrupt int1 interrupt int2 interrupt int3 interrupt ieds[1:0] ieds[5:4] ieds[7:6] ieds[3:2] edge detector int0if int1if int2if int3if figure 30. external interrupt gms81604/08 lg semicon 38
interrupt active f xin 8 f osc max. 13 f osc instruction execution (interrupt holding) interrupt processing interrupt routine figure 31. int pin interrupt timing relation with timer/counter function t3s 0: r47 1: t3o (timer/counter 3 output) int3s 0: r43 1: int3 (external interrupt 3) t1s 0: r46 1: t1o (timer/counter 1 output) int2s 0: r42 1: int2 (external interrupt 2) ec2s 0: r45 1: ec2 (external input pin for timer/counter 2 int1s 0: r41 1: int1 (external interrupt 1) ec0s 0: r44 1: ec0 (external input pin for timer/counter 0 int0s 0: r40 1: int0 (external interrupt 0) lsb msb ec2s t1s ec0s int3s int1s int2s int0s t3s pmr4 relation with external interrupt function lsb msb ied2h ied3l ied2l ied1h ied0h ied1l ied0l ied3h ieds address: d0 h reset value: 00 h address: f8 h reset value: 00 h int3 int2 int1 int0 edge selection register 00: reserved 01: falling (1-to-0 transition) 10: rising (0-to-1 transition) 11: both (rising & falling) figure 32. pmr4 and ieds registers lg semicon gms81604/08 39
brk interrupt software interrupt can be invoked by brk instruction, which is the lowest priority order. interrupt vector address of brk is shared with the vector of tcall0 (refer to program memory sec - tion). when brk interrupt is generated, b-flag of psw is set to distinguish brk from tcall0. each processing step is determined by b-flag as shown below. multiple interrupt if two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. if requests of the same priority level are received simultaneously, an internal polling sequence determines by hardware which request is serviced. hardware interrupt priority is shown in page 37. however, multiple processing through software for special features is possible. generally when an inter - rupt is accepted, the i-flag is cleared to disable any further interrupt. but as user set i-flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress. b-flag reti brk or tcall0 brk interrupt routine tcall0 routine ret = 0 = 1 figure 33. execution of brk/ tcall0 mov ienh,#80h mov ienl,#00h ei reti occur timer 0 interrupt int0 routine reti main routine timer 0 routine mov ienh,#ffh mov ienl,#ffh int 0 routine in this example, the int0 interrupt can be serviced without any pending, even timer 0 is in progress. because of re-setting the interrupt enable registers ienh, ienl and master enable flag "ei" in the timer/counter 0 routine. figure 34. execution of multi-interrupt gms81604/08 lg semicon 40
watchdog timer the purpose of the watchdog timer is to detect the malfunction (runaway) of program due to external noise or other causes and return the operation to the normal condition. the watchdog timer consists of 6-bit binary counter, 6-bit comparator and the watchdog timer data register. when the value of 6-bit binary counter is equal to the lower 6 bits of wdtr, the match is generated to go to reset the cpu. the 6-bit binary counter is cleared by wdtcl=1. caution: because the watchdog timer counter is enabled af - ter clearing basic interval timer . after the bit wdton set to "1", maximum error of timer is depend on prescaler ratio of basic interval timer. this watchdog timer can also be used as a simple 6-bit timer by interrupt wdtif. the interval of watchdog timer interrupt is decided by basic interval timer. interval equation is as below. t wdt = wdtr interval of bit wdtr[5:0] (6-bits) watch-dog timer interrupt count source watchdog counter (6-bits) wdton comparator clear basic interval timer overflow wdtcl note: the bit wdton is in register ckctlr. see figure 12. wdtif to reset cpu "0" "1" watchdog timer register figure 35. block diagram of watch-dog timer lsb msb wdtcl - wdtr address: ec h reset value: undefined wdtcl 0: free-run watch-dog timer 1: wdtcl is set to "1", counter is cleared. wdtcl becomes "0" automatically after one machine cycle, and counter starts counting. 6-bit watch-dog count register reserved figure 36. wdtr: watch-dog timer data register lg semicon gms81604/08 41
stop mode for applications where power consumption is a critical factor, device provides reduced power of stop. an instruction that stop causes that to be the last instruction executed before going into the stop mode. in the stop mode, the on-chip oscillator is stopped. with the clock frozen, all functions are stopped, but the on-chip ram and control registers are held. the port pins out the values held by their respective port data register rx, port direction register rxdd. the status of peripherals during stop mode is shown below. peripheral status ram retain control registers retain i/o retain oscillation stop x in low x out high in the stop mode of operation, v dd can be reduced to minimize power consumption. care must be taken, however, to ensure that v dd is not reduced before the stop mode is invoked, and that v dd is restored to its normal operating level, before the stop mode is termi - nated. the reset should not be activated before v dd is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize (minimum 20 msec). caution: the nop instruction have to be written more than two to next line of the stop instruction. ex) stop nop nop release stop mode the exit from stop mode is hardware reset or external interrupt. reset redefines all the control registers but does not change the on-chip ram. external interrupts allow both on-chip ram and control registers to retain their values. if i-flag = 1, the normal interrupt response takes place. if i-flag = 0, the chip will resume execution starting with the instruction following the stop instruction. it will not vector to interrupt service routine. when exit from stop mode by external interrupt from stop mode, enough oscillation stabilization time is required to normal operation. figure 37 shows the timing diagram. when release the stop mode, the external interrupt internal clock oscillator t st > 20 ms normal operation basic interval timer counter clear basic interval timer n+2 00 01 fe ff 00 n n+1 stabilization time 01 02 03 normal operation stop mode stop instruction execution figure 37. timing of stop release by external interrupt gms81604/08 lg semicon 42
basic interval timer is activated on wake-up. it is incremented from 00 h until ff h then 00 h . the count overflow is set to start normal operation. therefore, before stop instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). this guarantees that crystal oscillator has started and stabilized. by reset, exit from stop mode is shown in figure 38. minimizing current consumption in stop mode the stop mode is designed to reduce power consump - tion. to minimize current drawn during stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical. weak pull-ups on port pins should be turned off, if possible. all inputs should be either as v ss or at v dd (or as close to rail as possible). an intermediate voltage on an input pin causes the input buffer to draw a significant amount of current. wake-up and reset function table event chip status before event chip function after event pc oscillator circuit reset do not care vector on stop instruction normal operation n+1 off external interrupt normal operation vector on external interrupt wake-up stop, i-flag = 1 stop, i-flag = 0 vector n+1 on on pc: program counter contents after the event. n: address of stop instruction. stop mode reset internal clock oscillator stop instruction execution t st = 64 ms at 8 mhz stabilization time time can not be control by software. figure 38. timing of stop mode release by reset lg semicon gms81604/08 43
reset the reset input is the reset pin, which is the input to a schmitt trigger. a reset in accomplished by holding the reset pin low for at least 8 oscillator periods, while the oscillator running. after reset, 64ms (at 8 mhz) plus 7 oscillator periods are required to start execution as shown in figure 40. internal ram is not affected by reset. when v dd is turned on, the ram content is indeterminate. initial state of each register is as follow. therefore, this ram should be initialized before reading or testing it. register content a x y psw pc sp x x x 00h x x r0 r0dd r1 r1dd r4 r4dd r5 r5dd r6 r6dd pmr4 pmr5 x 00000000 x 00000000 x 00000000 x --0---00 x 00000000 00000000 --0----- bitr ckctlr wdtr tm0 tm2 tdr0/ t0/ cdr0 tdr1/ t1/ cdr1 tdr2/ t2/ cdr2 tdr3/ t3/ cdr3 00h --010111 -0111111 00h 00h x x x x adcm adr bur pfdr --000001 x x -----100 ienh ienl irqh irql ieds 00h 000----- 00h 000----- 00h - = unimplemented bit x= unknown reset +5v 4.2v reset ic 7042 10k w 10uf + 4.2v reset ic ex) 5v operation figure 39. example of reset circuit reset oscillator 1 2 3 4 5 6 7 ? ? ? ? ? fffe ffff start reset process step address bus ? ? data bus ? ? fe adl adh op code main program t st = 64 ms at 8 mhz stabilization time figure 40. timing diagram after reset gms81604/08 lg semicon 44
power fail processor the gms81604/08 have on-chip power fail detection circuitry to immunize against power noise. a configu - ration register, pfdr, can enable (if clear/pro - grammed) or disable (if set) the power-fail detect circuitry. if v dd falls below 3.0~4.0v range for longer than 100 ns, the power fail situation may reset mcu according to pfr bit of pfdr. caution: power fail processor function is not available on 3v operation, because this function will detect power fail all the time. as below pfdr register is not implemented on the in-circuit emulator, user can not experiment with it. therefore, after final development of user program, this function may be experimented. r/w msb - - - - pfr pfd pfs - pfdr address: ed h reset value: -----100 power fail status 0: normal operate 1: this bit force to "1" when power fail was detected. reserved operation mode 0: normal operation regardless of power fail. 1: mcu will be reset during power fail. disable flag 0: power fail detection enable 1: power fail detection disable r/w r/w lsb figure 41. pfdr: power fail detector register reset vector no pfs = 1 ? ram clear initialize ram data yes function execution initialize all ports initialize registers skip the initial routine. pfs = 0 figure 42. example s/w of reset flow by power fail lg semicon gms81604/08 45
pfv dd max. pfv dd min. v dd internal reset v dd internal reset v dd internal reset pfv dd max. pfv dd min. pfv dd max. pfv dd min. 64 ms t < 64 ms 64 ms 64 ms when pfr = 1 figure 43. power fail processor situations gms81604/08 lg semicon 46
oscillator circuit x in and x out are the input and output, respectively, of a inverting amplifier which can be configured for use as an on-chip oscillator, as shown in figure 44. to drive the device from an external clock source, x out should be left unconnected while x in is driven as shown in figure 45. there are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. since each crys - tal and ceramic resonator have their own charac - teristics, the user should consult the crystal manufacturer for appropriate values of external com - ponents. in addition, see figure 46. for the layout of the crystal. in all cases, an external clock operation is available. x out x in v ss recommend: c1,c2 = 30 pf 10 pf for crystals. c1 c2 figure 44. oscillator connections x out x in v ss n/c external oscillator signal figure 45. external clock drive configuration v ss x in x out reset r00 r01 figure 46. layout of crystal lg semicon gms81604/08 47
unused ports all unused ports should be set properly that current flow through the port does not exist. first conseider the setting to input mode. be sure that there is no current flow after considering its relation - ship with external circuit. in input mode, the pin im - pedance viewing from external mcu is very high that the current does not flow. but input voltage level should be v ss or v dd . be careful that if unspecified voltage, i.e. if unfirmed voltage level is applied to input pin, there can be little current ( max. 1ma at around 2v) flow. if it is not appropriate to set to input mode, then set to output mode considering there is no current flow. setting to high or low is decided considering its relationship with external circuit. for example, if there is external pull-up resistor then it is set to output mode, i.e. to high, and if there is external pull-down register, it is set to low. gms81604/08 lg semicon 48
GMS81608t (otp) programming the GMS81608t is one-time prom (otp) micro - controller with 8k bytes electrically programmable read only memory for the gms81604/08 system evaluation, first production and fast mass production. the programming to the otp device, user can have two way. one is using the universal programmer which is support lgs microcontrollers, other is using the general eprom programmer. 1. using the universal programmer third party universal programmer support to program the GMS81608t microcontrollers and lists are shown as below. manufacturer: advantech web site: http://www.aec.com.tw programmer: labtool-48 manufacturer: hi-lo systems web site: http://www.hilosystems.com.tw programmer: all-11, gang-08 socket adapters are supported by third party program - mer manufacturer. 2. using the general eprom(27c256) programmer the programming algorithm is simmilar with the stan - dart eprom 27c256. it give some convience that user can use standard eprom programmer. make sure that 1ms programming pulse must be used, it gener - ally called "intelligent mode". do not use 100us programming pulse mode, "quick pulse mode". when user use general eprom programmer, socket adaper is essencially required. it convert pin to fit the pin of general 27c256 eprom. three type socket adapters are provided according to package variation as below table. socket adapter package type oa816a-40sd 40 pin dip oa816a-42sd 42 pin sdip oa816a-42pl 44 pin plcc with these socket adapters, the GMS81608t can easy be programming and verifying using 27c256 eprom mode on general-purpose prom programmer. in assembler and file type, two files are generated after compiling. one is "*.hex", another is "*.otp". the "*.hex" file is used for emulation in circuit emulator (choice-dr tm or choice-jr tm ) and "*.otp" file is used for programming to the otp device. programming procedure 1. select the eprom device and manufacturer on eprom programmer (intel 27c256). 2. select the programming algorithm as an intelligent mode (apply 1ms writing pulse), not a quick pulse mode. 3. load the file (*.otp) to the programmer. 4. set the programming address range as below table. address set value buffer start address 6000 h buffer end address 7fff h device start address 6000 h 5. mount the socket adapter with the GMS81608t on the prom programmer. 6. start the prom programmer to programming/ verifying. lg semicon gms81604/08 49
GMS81608t programming manual
gms815045t package device name package GMS81608t 40dip GMS81608t k 42sdip GMS81608t pl 44plcc pin configuration 40dip lg semicon GMS81608t programming specification 5 1
44plcc 42sdip GMS81608t programming specification lg semicon 5 2
pin no. mcu mode otp mode 1 test i v pp - 2 av dd - (1) - 3 r67/an7 i/o (1) - 4 r66/an6 i/o (1) - 5 r65/an5 i/o (1) - 6 r64/an4 i/o (1) - 7 r63/an3 i (1) - 8 r62/an2 i (1) - 9 r61/an1 i (1) - 10 r60/an0 i (1) - 11 r47/t3o i/o a4 i 12 r46/t1o i/o (1) - 13 r45/ ec2 i/o ce i 14 r44/ ec0 i/o oe i 15 r43/int3 i/o a3 i 16 r42/int2 i/o a2 i 17 r41/int1 i/o a1 i 18 r40/int0 i/o a0 i 19 r55/buz i/o (1) - 20 v dd - v dd - notes: (1) pins must be connected to v ss , because these pins are input ports during programming, program verify and reading (2) pins must be connected to v dd . (3) x out pin must be opened during programming. pin no. mcu mode otp mode 21 r17 i/o a12 i 22 r16 i/o a11 i 23 r15 i/o a10 i 24 r14 i/o a9 i 25 r13 i/o a8 i 26 r12 i/o a7 i 27 r11 i/o a6 i 28 r10 i/o a5 i 29 r07 i/o o7 o 30 r06 i/o o6 o 31 r05 i/o o5 o 32 r04 i/o o4 o 33 r03 i/o o3 o 34 r02 i/o o2 o 35 r01 i/o o1 o 36 r00 i/o o0 o 37 reset i (1) - 38 x out o (3) - 39 x in i (1) - 40 v ss - (1) - i/o: input/output pin i: input pin o: output pin 40dip package for GMS81608t lg semicon GMS81608t programming specification 5 3
pin no. mcu mode otp mode 1 test i v pp - 2 av dd - (1) - 3 r67/an7 i/o (1) - 4 r66/an6 i/o (1) - 5 r65/an5 i/o (1) - 6 r64/an4 i/o (1) - 7 r63/an3 i (1) - 8 r62/an2 i (1) - 9 r61/an1 i (1) - 10 r60/an0 i (1) - 11 r47/t3o i/o a4 i 12 r46/t1o i/o (1) - 13 r45/ ec2 i/o ce i 14 r44/ ec0 i/o oe i 15 r43/int3 i/o a3 i 16 r42/int2 i/o a2 i 17 r41/int1 i/o a1 i 18 r40/int0 i/o a0 i 19 r55/buz i/o (1) - 20 v dd - v dd - 21 r51 i/o (2) - notes: (1) pins must be connected to v ss , because these pins are input ports during programming, program verify and reading (2) pins must be connected to v dd . (3) x out pin must be opened during programming. pin no. mcu mode otp mode 22 r50 i/o (2) - 23 r17 i/o a12 i 24 r16 i/o a11 i 25 r15 i/o a10 i 26 r14 i/o a9 i 27 r13 i/o a8 i 28 r12 i/o a7 i 29 r11 i/o a6 i 30 r10 i/o a5 i 31 r07 i/o o7 o 32 r06 i/o o6 o 33 r05 i/o o5 o 34 r04 i/o o4 o 35 r03 i/o o3 o 36 r02 i/o o2 o 37 r01 i/o o1 o 38 r00 i/o o0 o 39 reset i (1) - 40 x out o (3) - 41 x in i (1) - 42 v ss - (1) - i/o: input/output pin i: input pin o: output pin 42sdip package for GMS81608t GMS81608t programming specification lg semicon 5 4
pin no. mcu mode otp mode 1 n.c. - n.c. - 2 test i v pp - 3 av dd - (1) - 4 r67/an7 i/o (1) - 5 r66/an6 i/o (1) - 6 r65/an5 i/o (1) - 7 r64/an4 i/o (1) - 8 r63/an3 i (1) - 9 r62/an2 i (1) - 10 r61/an1 i (1) - 11 r60/an0 i (1) - 12 r47/t3o i/o a4 i 13 r46/t1o i/o (1) - 14 r45/ ec2 i/o ce i 15 r44/ ec0 i/o oe i 16 r43/int3 i/o a3 i 17 n.c. - n.c. - 18 r42/int2 i/o a2 i 19 r41/int1 i/o a1 i 20 r40/int0 i/o a0 i 21 r55/buz i/o (1) - 22 v dd - v dd - notes: (1) pins must be connected to v ss , because these pins are input ports during programming, program verify and reading (2) pins must be connected to v dd . (3) x out pin must be opened during programming. pin no. mcu mode otp mode 23 r51 i/o (2) - 24 r50 i/o (2) - 25 r17 i/o a12 i 26 r16 i/o a11 i 27 r15 i/o a10 i 28 r14 i/o a9 i 29 r13 i/o a8 i 30 r12 i/o a7 i 31 r11 i/o a6 i 32 r10 i/o a5 i 33 r07 i/o o7 o 34 r06 i/o o6 o 35 r05 i/o o5 o 36 r04 i/o o4 o 37 r03 i/o o3 o 38 r02 i/o o2 o 39 r01 i/o o1 o 40 r00 i/o o0 o 41 reset i (1) - 42 x out o (3) - 43 x in i (1) - 44 v ss - (1) - i/o: input/output pin i: input pin o: output pin 44plcc package for GMS81608t lg semicon GMS81608t programming specification 5 5
pin function (otp mode) v pp (program voltage) v pp is the input for the program voltage for programming the eprom. ce ( chip enable) ce is the input for programming and verifying internal eprom. oe (output enable) oe is the input of data output control signal for verify. a 0 ~a 12 (address bus) a 0 ~a 12 are address input pins for internal eprom. o 0 ~o 7 (eprom data bus) these are data bus for internal eprom. programming the GMS81608t has address a 0 ~a 12 pins. therefore, the programmer just program 8k bytes data of addresses 6000 h to 7fff h into the GMS81608t otp device. during the programming addresses a 13 , a 14 , a 15 of programmer must be pulled to a logic high. when the programmer write the data from 6000 h to 7fff h , consequently, the data actually will be written into addresses e000 h to ffff h of the otp device. programming flow 1. the data format to be programmed is made up of motorola s1 format. ex) "motorola s1" format; s00b00005741544348363038df s1246000e1ff3bff04a13f8f06e1c1711bff3f1b003e1b00371b00361bff3d1b003c1bff3385 s12460211bff321bff351b92131b7fcc1bf3d61b17fd1bfcfc1b821b1be01d1b8e191bfd18b1 : : s1057ff2941fd6 s1057ffeff1f5f s9030000fc 2. down load above data into programmer from pc. 3. programming the data from address 6000 h to 7fff h into the otp mcu, the data must be turned over respectively, and then record the data into the otp device. when read the data, it also must be turned over. ex) 00(00000000) ? ff(11111111), 76(01110110) ? 89(10001001), ff (11111111)? 00(00000000) etc. 4. of course, the check sum is result of the sum of whole data from address 6000 h to 7fff h in the file (not reverse data of the otp mcu). * when GMS81608t shipped, the blank data of GMS81608t is initially 00 h (not ff h ). GMS81608t programming specification lg semicon 5 6
address GMS81608t device file xxxxxxxx.otp e1 ff 3b ff 04 a1 3f 8f : : : : 94 1f : ff 1f down loadin g program 6000 h 6001 h 6002 h 6003 h 6004 h 6005 h 6006 h 6007 h : : : : 7ff2 h 7ff3 h : 7ffe h 7fff h e1 ff 3b ff 04 a1 3f 8f : : : : 94 1f : ff 1f 6000 h 6001 h 6002 h 6003 h 6004 h 6005 h 6006 h 6007 h : : : : 7ff2 h 7ff3 h : 7ffe h 7fff h 1e 00 c4 00 fc 5e c0 70 : : : : 6a e0 : 00 e0 e000 h e001 h e002 h e003 h e004 h e005 h e006 h e007 h : : : : fff2 h fff3 h : fffe h ffff h reading verify up loading data addres s data addres s data programmer buffer checksum = e1+ff+3b+ff+04+a1+3f+8f+ + 94+1f+ +ff+1f programming example program area 8 k bytes e000 h ffff h address file type: motorola s-format GMS81608t 6000 h 7fff h address xxxxxxxx.otp universal programmer down loading program verify reading buffer start address: 6000 h buffer end address: 7fff h device start address: e000 h programming flow lg semicon GMS81608t programming specification 5 7
device operation mode (t a = 25 c 5 c) mode ce oe a 0 ~a 15 v pp v dd o 0 ~o 7 read x x v dd 5.0v d out output disable v ih v ih x v dd 5.0v hi-z programming v il v ih x v pp v dd d in program verify x x v pp v dd d out notes: 1. x = either v il or v ih 3. see dc characteristics table for v dd and v pp voltages during programming. dc characteristics (v ss =0 v, t a = 25 c 5 c) symbol item min typ max unit test condition v pp v pp supply voltage 12.0 - 13.0 v v dd (1) v dd supply voltage 5.75 - 6.25 v i pp (2) v pp supply current 50 ma ce =v il i dd (2) v dd supply current 30 ma v ih input high voltage 0.8 v dd v v il input low voltage 0.2 v dd v v oh output high voltage v dd -1.0 v i oh = -2.5 ma v ol output low voltage 0.4 v i ol = 2.1 ma i il input leakage current 5 ua notes: 1. v dd must be applied simultaneously or before v pp and removed simultaneously or after v pp . 2. the maximum current value is with outputs o 0 to o 7 unloaded. GMS81608t programming specification lg semicon 5 8
notes: 1. the input timing reference level is 1.0 v for a v il and 4.0v for a v ih at v dd =5.0v 2. to read the output data, transition requires on the oe from the high to the low after address setup time t as . address valid t oe valid output t dh addresses oe output high-z v ih v il v ih v il v ih v il t as (2) reading waveforms waveform inputs outputs must be steady may change from h to l may change from l to h do not care any change permitted does not apply w ill be steady w ill be changing from h to l w ill be changing from l to h changing state unknown center line is high impedance "off" state switching waveforms lg semicon GMS81608t programming specification 5 9
notes: 1. the input timing reference level is 1.0 v for a v il and 4.0v for a v ih at v dd =5.0v t dfp addresses data high-z v ih v il 12.5v v dd v pp v dd ce oe 6.0v 5.0v t as t ds t vps t vds t opw t pw t oes program program verify t dh v ih v il v ih v il v ih v il t ah address stable data in stable data out valid t oe programming algorithm waveforms GMS81608t programming specification lg semicon 6 0
ac reading characteristics (v ss =0 v, t a = 25 c 5 c) symbol item min typ max unit test condition t as address setup time 2 us t oe data output delay time 200 ns t dh data hold time 0 ns notes: 1. v dd must be applied simultaneously or before v pp and removed simultaneously or after v pp . ac programming characteristics (v ss =0 v, t a = 25 c 5 c; see dc characteristics table for v dd and v pp voltages.) symbol item min typ max unit condition* (note 1) t as address set-up time 2 us t oes oe set-up time 2 us t ds data setup time 2 us t ah address hold time 0 us t dh data hold time 1 us t dfp output disable delay time 0 us t vps v pp setup time 2 us t vds v dd setup time 2 us t pw program pulse width 0.95 1.0 1.05 ms t opw ce pulse width when over programming 2.85 78.75 ms (note 2) t oe data output delay time 200 ns *ac conditions of test input rise and fall times (10% to 90%) . . . . 20 ns input pulse levels . . . . . . . . . . . . . . . 0.45v to 4.55v input timing reference level . . . . . . . . . 1.0v to 4.0v output timing reference level . . . . . . . . 1.0v to 4.0v notes: 1. v dd must be applied simultaneously or before v pp and removed simultaneously or after v pp . 2. the length of the overprogram pulse may vary from 2.85 msec to 78.75 msec as a function of the iteration counter value x (intelligent programming algorithm).refer to flow chart of page 13. lg semicon GMS81608t programming specification 6 1
start v dd = 6.0v v pp = 12.5v x = 0 program one 1 ms pulse increment x verify byte verify one byte last address ? v dd = v pp = 5.0v compare all bytes to original data device passed increment address yes no fail pass fail pass no yes fail pass device failed program one pulse of 3x msec duration x = 25 ? address= first location intelligent programming algorithm GMS81608t programming specification lg semicon 6 2
appendix
gms800 series i a. instruction a.1 terminology list terminology description a accumulator x x - register y y - register psw program status word #imm 8-bit immediate data dp direct page offset address !abs absolute address [ ] indirect expression { } register indirect expression { }+ register indirect expression, after that, register auto-increment .bit bit position a.bit bit position of accumulator dp.bit bit position of direct page memory m.bit bit position of memory data (000 h ~0fff h ) rel relative addressing data upage u-page (0ff00 h ~0ffff h ) offset address n table call number (0~15) + addition x upper nibble expression in opcode y upper nibble expression in opcode - subtraction multiplication / division ( ) contents expression and or ? exclusive or ~not ? assignment / transfer / shift left ? shift right ? exchange = equal 1 not equal 0 bit position 1 bit position
gms800 series ii a.2 instruction map low high 00000 00 00001 01 00010 02 00011 03 00100 04 00101 05 00110 06 00111 07 01000 08 01001 09 01010 0a 01011 0b 01100 0c 01101 0d 01110 0e 01111 0f 000 - set1 dp.bit bbs a.bit,rel bbs dp.bit,re l adc #imm adc dp adc dp+x adc !abs asl a asl dp tcall 0 seta1 .bit bit dp pop a push a brk 001 clrc sbc #imm sbc dp sbc dp+x sbc !abs rol a rol dp tcall 2 clra1 .bit com dp pop x push x bra rel 010 clrg cmp #imm cmp dp cmp dp+x cmp !abs lsr a lsr dp tcall 4 not1 m.bit tst dp pop y push y pcall upage 011 di or #imm or dp or dp+x or !abs ror a ror dp tcall 6 or1 or1b cmpx dp pop psw push psw ret 100 clrv and #imm and dp and dp+x and !abs inc a inc dp tcall 8 and1 and1b cmpy dp cbne dp+x txsp inc x 101 setc eor #imm eor dp eor dp+x eor !abs dec a dec dp tcall 10 eor1 eor1b dbne dp xma dp+x tspx dec x 110 setg lda #imm lda dp lda dp+x lda !abs txa ldy dp tcall 12 ldc ldcb ldx dp ldx dp+y xcn das 111 ei ldm dp,#im m sta dp sta dp+x sta !abs tax sty dp tcall 14 stc m.bit stx dp stx dp+y xax stop low high 10000 10 10001 11 10010 12 10011 13 10100 14 10101 15 10110 16 10111 17 11000 18 11001 19 11010 1a 11011 1b 11100 1c 11101 1d 11110 1e 11111 1f 000 bpl rel clr1 dp.bit bbc a.bit,rel bbc dp.bit,rel adc {x} adc !abs+y adc [dp+x] adc [dp]+y asl !abs asl dp+x tcall 1 jmp !abs bit !abs addw dp ldx #imm jmp [!abs] 001 bvc rel sbc {x} sbc !abs+y sbc [dp+x] sbc [dp]+y rol !abs rol dp+x tcall 3 call !abs test !abs subw dp ldy #imm jmp [dp] 010 bcc rel cmp {x} cmp !abs+y cmp [dp+x] cmp [dp]+y lsr !abs lsr dp+x tcall 5 mul tclr1 !abs cmpw dp cmpx #imm call [dp] 011 bne rel or {x} or !abs+y or [dp+x] or [dp]+y ror !abs ror dp+x tcall 7 dbne y cmpx !abs ldya dp cmpy #imm reti 100 bmi rel and {x} and !abs+y and [dp+x] and [dp]+y inc !abs inc dp+x tcall 9 div cmpy !abs incw dp inc y tay 101 bvs rel eor {x} eor !abs+y eor [dp+x] eor [dp]+y dec !abs dec dp+x tcall 11 xma {x} xma dp decw dp dec y tya 110 bcs rel lda {x} lda !abs+y lda [dp+x] lda [dp]+y ldy !abs ldy dp+x tcall 13 lda {x}+ ldx !abs stya dp xay daa 111 beq rel sta {x} sta !abs+y sta [dp+x] sta [dp]+y sty !abs sty dp+x tcall 15 sta {x}+ stx !abs cbne dp xyx nop
gms800 series iii a.3 instruction set arithmetic / logic operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 adc #imm 04 2 2 add with carry. 2 adc dp 05 2 3 a ? ( a ) + ( m ) + c 3 adc dp + x 06 2 4 4 adc !abs 07 3 4 nv--h-zc 5 adc !abs + y 15 3 5 6 adc [ dp + x ] 16 2 6 7 adc [ dp ] + y 17 2 6 8 adc { x } 14 1 3 9 and #imm 84 2 2 logical and 10 and dp 85 2 3 a ? ( a ) ( m ) 11 and dp + x 86 2 4 12 and !abs 87 3 4 n-----z- 13 and !abs + y 95 3 5 14 and [ dp + x ] 96 2 6 15 and [ dp ] + y 97 2 6 16 and { x } 94 1 3 17 asl a 08 1 2 arithmetic shift left 18 asl dp 09 2 4 n-----zc 19 asl dp + x 19 2 5 20 asl !abs 18 3 5 21 cmp #imm 44 2 2 compare accumulator contents with memory con- tents ( a ) - ( m ) 22 cmp dp 45 2 3 23 cmp dp + x 46 2 4 24 cmp !abs 47 3 4 n-----zc 25 cmp !abs + y 55 3 5 26 cmp [ dp + x ] 56 2 6 27 cmp [ dp ] + y 57 2 6 28 cmp { x } 54 1 3 29 cmpx #imm 5e 2 2 compare x contents with memory contents 30 cmpx dp 6c 2 3 ( x ) - ( m ) n-----zc 31 cmpx !abs 7c 3 4 32 cmpy #imm 7e 2 2 compare y contents with memory contents 33 cmpy dp 8c 2 3 ( y ) - ( m ) n-----zc 34 cmpy !abs 9c 3 4 35 com dp 2c 2 4 1s complement : ( dp ) ? ~( dp ) n-----z- 36 daa df 1 3 decimal adjust for addition n-----zc 37 das cf 1 3 decimal adjust for subtraction n-----zc 38 dec a a8 1 2 decrement n-----zc ? ? ? ? ? ? ? ? 76543210 ? 0 ? c
gms800 series iv 39 dec dp a9 2 4 m ? ( m ) - 1 n-----z- 40 dec dp + x b9 2 5 n-----z- 41 dec !abs b8 3 5 n-----z- 42 dec x af 1 2 n-----z- 43 dec y be 1 2 n-----z- 44 div 9b 1 12 divide : ya / x q: a, r: y nv--h-z- 45 eor #imm a4 2 2 exclusive or 46 eor dp a5 2 3 a ? ( a ) ? ( m ) 47 eor dp + x a6 2 4 48 eor !abs a7 3 4 n-----z- 49 eor !abs + y b5 3 5 50 eor [ dp + x ] b6 2 6 51 eor [ dp ] + y b7 2 6 52 eor { x } b4 1 3 53 inc a 88 1 2 increment n-----zc 54 inc dp 89 2 4 m ? ( m ) + 1 n-----z- 55 inc dp + x 99 2 5 n-----z- 56 inc !abs 98 3 5 n-----z- 57 inc x 8f 1 2 n-----z- 58 inc y 9e 1 2 n-----z- 59 lsr a 48 1 2 logical shift right 60 lsr dp 49 2 4 n-----zc 61 lsr dp + x 59 2 5 62 lsr !abs 58 3 5 63 mul 5b 1 9 multiply : ya ? y a n-----z- 64 or #imm 64 2 2 logical or 65 or dp 65 2 3 a ? ( a ) ( m ) 66 or dp + x 66 2 4 67 or !abs 67 3 4 n-----z- 68 or !abs + y 75 3 5 69 or [ dp + x ] 76 2 6 70 or [ dp ] + y 77 2 6 71 or { x } 74 1 3 72 rol a 28 1 2 rotate left through carry 73 rol dp 29 2 4 n-----zc 74 rol dp + x 39 2 5 75 rol !abs 38 3 5 76 ror a 68 1 2 rotate right through carry 77 ror dp 69 2 4 n-----zc 78 ror dp + x 79 2 5 79 ror !abs 78 3 5 80 sbc #imm 24 2 2 subtract with carry no. mnemonic op code byte no cycle no operation flag nvgbhizc ? ? ? ? ? ? ? ? 76543210 0 ? ? c ? ? ? ? ? ? ? ? 76543210 c ? ? ? ? ? ? ? ? 76543210 c
gms800 series v 81 sbc dp 25 2 3 a ? ( a ) - ( m ) - ~( c ) 82 sbc dp + x 26 2 4 83 sbc !abs 27 3 4 nv--hzc 84 sbc !abs + y 35 3 5 85 sbc [ dp + x ] 36 2 6 86 sbc [ dp ] + y 37 2 6 87 sbc { x } 34 1 3 88 tst dp 4c 2 3 test memory contents for negative or zero, ( dp ) - 00 h n-----z- 89 xcn ce 1 5 exchange nibbles within the accumulator a 7 ~a 4 ? a 3 ~a 0 n-----z- no. mnemonic op code byte no cycle no operation flag nvgbhizc
gms800 series vi register / memory operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 lda #imm c4 2 2 load accumulator 2 lda dp c5 2 3 a ? ( m ) 3lda dp + x c6 2 4 4 lda !abs c7 3 4 5 lda !abs + y d5 3 5 n-----z- 6 lda [ dp + x ] d6 2 6 7 lda [ dp ] + y d7 2 6 8lda { x } d4 1 3 9 lda { x }+ db 1 4 x- register auto-increment : a ? ( m ) , x ? x + 1 10 ldm dp,#imm e4 3 5 load memory with immediate data : ( m ) ? imm -------- 11 ldx #imm 1e 2 2 load x-register 12 ldx dp cc 2 3 x ? ( m ) n-----z- 13 ldx dp + y cd 2 4 14 ldx !abs dc 3 4 15 ldy #imm 3e 2 2 load y-register 16 ldy dp c9 2 3 y ? ( m ) n-----z- 17 ldy dp + x d9 2 4 18 ldy !abs d8 3 4 19 sta dp e5 2 4 store accumulator contents in memory 20 sta dp + x e6 2 5 ( m ) ? a 21 sta !abs e7 3 5 22 sta !abs + y f5 3 6 -------- 23 sta [ dp + x ] f6 2 7 24 sta [ dp ] + y f7 2 7 25 sta { x } f4 1 4 26 sta { x }+ fb 1 4 x- register auto-increment : ( m ) ? a, x ? x + 1 27 stx dp ec 2 4 store x-register contents in memory 28 stx dp + y ed 2 5 ( m ) ? x -------- 29 stx !abs fc 3 5 30 sty dp e9 2 4 store y-register contents in memory 31 sty dp + x f9 2 5 ( m ) ? y -------- 32 sty !abs f8 3 5 33 tax e8 1 2 transfer accumulator contents to x-register : x ? a n-----z- 34 tay 9f 1 2 transfer accumulator contents to y-register : y ? a n-----z- 35 tspx ae 1 2 transfer stack-pointer contents to x-register : x ? sp n-----z- 36 txa c8 1 2 transfer x-register contents to accumulator: a ? x n-----z- 37 txsp 8e 1 2 transfer x-register contents to stack-pointer: sp ? x n-----z- 38 tya bf 1 2 transfer y-register contents to accumulator: a ? y n-----z- 39 xax ee 1 4 exchange x-register contents with accumulator :x ? a --------
gms800 series vii 16-bit operation bit manipulation 40 xay de 1 4 exchange y-register contents with accumulator :y ? a -------- 41 xma dp bc 2 5 exchange memory contents with accumulator 42 xma dp+x ad 2 6 ( m ) ? a n-----z- 43 xma {x} bb 1 5 44 xyx fe 1 4 exchange x-register contents with y-register : x ? y -------- no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 addw dp 1d 2 5 16-bits add without carry ya ? ( ya ) ( dp +1 ) ( dp ) nv--h-zc 2cmpw dp 5d 2 4 compare ya contents with memory pair contents : (ya) - (dp+1)(dp) n-----zc 3 decw dp bd 2 6 decrement memory pair ( dp+1)( dp) ? ( dp+1) ( dp) - 1 n-----z- 4 incw dp 9d 2 6 increment memory pair ( dp+1) ( dp) ? ( dp+1) ( dp ) + 1 n-----z- 5ldya dp 7d 2 5 load ya ya ? ( dp +1 ) ( dp ) n-----z- 6 stya dp dd 2 5 store ya ( dp +1 ) ( dp ) ? ya -------- 7 subw dp 3d 2 5 16-bits subtract without carry ya ? ( ya ) - ( dp +1) ( dp) nv--h-zc no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 and1 m.bit 8b 3 4 bit and c-flag : c ? ( c ) ( m .bit ) -------c 2 and1b m.bit 8b 3 4 bit and c-flag and not : c ? ( c ) ~( m .bit ) -------c 3 bit dp 0c 2 4 bit test a with memory : mm----z- 4 bit !abs 1c 3 5 z ? ( a ) ( m ) , n ? ( m 7 ) , v ? ( m 6 ) 5 clr1 dp.bit y1 2 4 clear bit : ( m.bit ) ? 0 -------- 6 clra1 a.bit 2b 2 2 clear a bit : ( a.bit ) ? 0 -------- 7 clrc 20 1 2 clear c-flag : c ? 0 -------0 8 clrg 40 1 2 clear g-flag : g ? 0 --0----- 9 clrv 80 1 2 clear v-flag : v ? 0 -0--0--- 10 eor1 m.bit ab 3 5 bit exclusive-or c-flag : c ? ( c ) ? ( m .bit ) -------c 11 eor1b m.bit ab 3 5 bit exclusive-or c-flag and not : c ? ( c ) ? ~(m .bit) -------c 12 ldc m.bit cb 3 4 load c-flag : c ? ( m .bit ) -------c 13 ldcb m.bit cb 3 4 load c-flag with not : c ? ~( m .bit ) -------c 14 not1 m.bit 4b 3 5 bit complement : ( m .bit ) ? ~( m .bit ) -------- 15 or1 m.bit 6b 3 5 bit or c-flag : c ? ( c ) ( m .bit ) -------c 16 or1b m.bit 6b 3 5 bit or c-flag and not : c ? ( c ) ~( m .bit ) -------c
gms800 series viii 17 set1 dp.bit x1 2 4 set bit : ( m.bit ) ? 1 -------- 18 seta1 a.bit 0b 2 2 set a bit : ( a.bit ) ? 1 -------- 19 setc a0 1 2 set c-flag : c ? 1 -------1 20 setg c0 1 2 set g-flag : g ? 1 --1----- 21 stc m.bit eb 3 6 store c-flag : ( m .bit ) ? c -------- 22 tclr1 !abs 5c 3 6 test and clear bits with a : a - ( m ) , ( m ) ? ( m ) ~( a ) n-----z- 23 tset1 !abs 3c 3 6 test and set bits with a : a - ( m ) , ( m ) ? ( m ) ( a ) n-----z-
gms800 series ix branch / jump operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 bbc a.bit,rel y2 2 4/6 branch if bit clear : -------- 2 bbc dp.bit,rel y3 3 5/7 if ( bit ) = 0 , then pc ? ( pc ) + rel 3 bbs a.bit,rel x2 2 4/6 branch if bit set : -------- 4 bbs dp.bit,rel x3 3 5/7 if ( bit ) = 1 , then pc ? ( pc ) + rel 5 bcc rel 50 2 2/4 branch if carry bit clear if ( c ) = 0 , then pc ? ( pc ) + rel -------- 6bcs rel d0 2 2/4 branch if carry bit set if ( c ) = 1 , then pc ? ( pc ) + rel -------- 7 beq rel d0 2 2/4 branch if equal if ( z ) = 1 , then pc ? ( pc ) + rel -------- 8 bmi rel 90 2 2/4 branch if minus if ( n ) = 1 , then pc ? ( pc ) + rel -------- 9bne rel 70 2 2/4 branch if not equal if ( z ) = 0 , then pc ? ( pc ) + rel -------- 10 bpl rel 10 2 2/4 branch if minus if ( n ) = 0 , then pc ? ( pc ) + rel -------- 11 bra rel 2f 2 4 branch always pc ? ( pc ) + rel -------- 12 bvc rel 30 2 2/4 branch if overflow bit clear if (v) = 0 , then pc ? ( pc) + rel -------- 13 bvs rel b0 2 2/4 branch if overflow bit set if (v) = 1 , then pc ? ( pc ) + rel -------- 14 call !abs 3b 3 8 subroutine call 15 call [dp] 5f 2 8 m( sp) ? ( pc h ), sp ? sp - 1, m(sp) ? (pc l ), sp ? sp - 1, if !abs, pc ? abs ; if [dp], pc l ? ( dp ), pc h ? ( dp+1 ) . -------- 16 cbne dp,rel fd 3 5/7 compare and branch if not equal : -------- 17 cbne dp+x,rel 8d 3 6/8 if ( a ) 1 ( m ) , then pc ? ( pc ) + rel. 18 dbne dp,rel ac 3 5/7 decrement and branch if not equal : -------- 19 dbne y,rel 7b 2 4/6 if ( m ) 1 0 , then pc ? ( pc ) + rel. 20 jmp !abs 1b 3 3 unconditional jump 21 jmp [!abs] 1f 3 5 pc ? jump address -------- 22 jmp [dp] 3f 2 4 23 pcall upage 4f 2 6 u-page call m(sp) ? ( pc h ), sp ? sp - 1, m(sp) ? ( pc l ), sp ? sp - 1, pc l ? ( upage ), pc h ? 0ff h . -------- 24 tcall n na 1 8 table call : (sp) ? ( pc h ), sp ? sp - 1, m(sp) ? ( pc l ),sp ? sp - 1, pc l ? (table vector l), pc h ? (table vector h) --------
gms800 series x control operation & etc. no. mnemonic op code byte no cycle no operation flag nvgbhizc 1brk 0f 1 8 software interrupt : b ? 1, m(sp) ? (pc h ), sp ? sp-1, m(s) ? (pc l ), sp ? sp - 1, m(sp) ? (psw), sp ? sp -1, pc l ? ( 0ffde h ) , pc h ? ( 0ffdf h ) . ---1-0-- 2 di 60 1 3 disable all interrupts : i ? 0 -----0-- 3 ei e0 1 3 enable all interrupt : i ? 1 -----1-- 4 nop ff 1 2 no operation -------- 5 pop a 0d 1 4 sp ? sp + 1, a ? m( sp ) 6 pop x 2d 1 4 sp ? sp + 1, x ? m( sp ) -------- 7 pop y 4d 1 4 sp ? sp + 1, y ? m( sp ) 8 pop psw 6d 1 4 sp ? sp + 1, psw ? m( sp ) restored 9 push a 0e 1 4 m( sp ) ? a , sp ? sp - 1 10 push x 2e 1 4 m( sp ) ? x , sp ? sp - 1 -------- 11 push y 4e 1 4 m( sp ) ? y , sp ? sp - 1 12 push psw 6e 1 4 m( sp ) ? psw , sp ? sp - 1 13 ret 6f 1 5 return from subroutine sp ? sp +1, pc l ? m( sp ), sp ? sp +1, pc h ? m( sp ) -------- 14 reti 7f 1 6 return from interrupt sp ? sp +1, psw ? m( sp ), sp ? sp + 1, pc l ? m( sp ), sp ? sp + 1, pc h ? m( sp ) restored 15 stop ef 1 3 stop mode ( halt cpu, stop oscillator ) --------
mask order & verification sheet gms81604-hc 1. customer information company name 2. device information 3. marking specification 4. delivery schedule customer sample date yyyy mm dd risk order yyyy mm dd quantity lg confirmation application order date yyyy mm dd te l : fax: name & signature: package 40dip 42sdip 5. rom code verification verification date: yyyy mm dd approval date: yyyy mm dd please confirm our verification data. i agree with your verification data and confirm you to make mask set. check sum: te l : fax: name & signature: te l : fax: name & signature: set ff in this area 0000h 7000h 7fffh rom (4k) 6fffh mask data hitel chollian internet file name: ( .otp) (please check mark into ) lg semicon pcs pcs check sum: ( ) customer should write inside thick line box. this box is written after 5.verification. lgs yyw w korea gms81604 -hc customers part number 44plcc
mask order & verification sheet GMS81608-hc 1. customer information company name 2. device information 3. marking specification 4. delivery schedule customer sample date yyyy mm dd risk order yyyy mm dd quantity lg confirmation application order date yyyy mm dd te l : fax: name & signature: package 40dip 42sdip 5. rom code verification verification date: yyyy mm dd approval date: yyyy mm dd please confirm our verification data. i agree with your verification data and confirm you to make mask set. check sum: te l : fax: name & signature: te l : fax: name & signature: set ff in this area 0000h 6000h 7fffh rom (8k) 5fffh mask data hitel chollian internet file name: ( .otp) (please check mark into ) lg semicon pcs pcs check sum: ( ) customer should write inside thick line box. this box is written after 5.verification. lgs yyw w korea GMS81608 -hc customers part number 44plcc

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