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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. a ad9883a one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. 110 msps/140 msps analog interface for flat panel displays functional block diagram r ain r outa g ain g outa b ain b outa midscv sync processing and clock generation hsync coast clamp filt dtack hsout vsout sogout ref ref bypass serial register and power management scl sda a 0 ad9883a clamp 8 a/d clamp 8 a/d clamp 8 a/d features industrial temperature range operation 140 msps maximum conversion rate 300 mhz analog bandwidth 0.5 v to 1.0 v analog input range 500 ps p-p pll clock jitter at 110 msps 3.3 v power supply full sync processing sync detect for hot plugging midscale clamping power-down mode low power: 500 mw typical 4:2:2 output format mode applications rgb graphics processing lcd monitors and projectors plasma display panels scan converters microdisplays digital tv general description the ad9883a is a complete 8-bit, 140 msps, monolithic analog interface optimized for capturing rgb graphics signals from personal computers and workstations. its 140 msps encode rate capability and full power analog bandwidth of 300 mhz supports resolutions up to sxga (1280 1024 at 75 hz). th e ad9883a includes a 140 mhz triple adc with internal 1.25 v reference, a pll, and programmable gain, offset, and clamp control. the user provides only a 3.3 v power supply, analog input, and hsync and coast signals. three- state cmos outputs may be powered from 2.5 v to 3.3 v. the ad9883a? on-chip pll generates a pixel clock from the h sync input. pixel clock output frequencies range from 12 mhz to 140 mhz. pll clock jitter is 500 ps p-p typical at 140 msps. when the coast signal is presented, the pll maintains its output frequency in the absence of hsync. a sampling phase adjustment is provided. data, h sync, a nd c lock output phase relationships are maintained. the ad9883a also offers full sync processing for composite sync and sync-on-green applica tions. a clamp signal is generated internally or may be provided by the user through the clamp input pin. this interface is fully programmable via a 2-wire serial interface. fabricated in an advanced cmos process, the ad9883a is pro- vided in a space-saving 80-lead lqfp surface-mount plastic package and is specified over the ?0 c to +85 c temperature range.
rev. b e2e ad9883aespecifications test ad9883akst-110 ad9883akst-140 parameter temp level min typ max min typ max unit resolution 8 8 bits dc accuracy differential nonlinearity 25 ci 0.5 +1.25/e1.0 0.5 +1.35/e1.0 lsb full vi +1.35/e1.0 +1.45/e1.0 lsb integral nonlinearity 25 ci 0.5 1.85 0.5 2.0 lsb full vi 2.0 2.3 lsb no missing codes full vi guaranteed guaranteed analog input input voltage range minimum full vi 0.5 0.5 v p-p maximum full vi 1.0 1.0 v p-p gain tempco 25 cv 100 100 ppm/ c input bias current 25 civ 1 1 a full iv 1 1 a input offset voltage full vi 7 50 7 70 mv input full-scale matching full vi 1.5 6.0 1.5 8.0 % fs offset adjustment range full vi 46 49 52 46 49 52 % fs reference output output voltage full vi 1.20 1.25 1.32 1.20 1.25 1.32 v temperature coefficient full v 50 50 ppm/ c switching performance maximum conversion rate full vi 110 140 msps minimum conversion rate full iv 10 10 msps data to clock skew full iv e0.5 +2.0 e0.5 +2.0 ns t buff full vi 4.7 4.7 s t stah full vi 4.0 4.0 s t dho full vi 0 0 s t dal full vi 4.7 4.7 s t dah full vi 4.0 4.0 s t dsu full vi 250 250 ns t stasu full vi 4.7 4.7 s t stosu full vi 4.0 4.0 s hsync input frequency full iv 15 110 15 110 khz maximum pll clock rate full vi 110 140 mhz minimum pll clock rate full iv 12 12 mhz pll jitter 25 civ 400 700 1 400 700 1 ps p-p full iv 1000 1 1000 1 ps p-p sampling phase tempco full iv 15 15 ps/ c digital inputs input voltage, high (v ih ) full vi 2.5 2.5 v input voltage, low (v il ) full vi 0.8 0.8 v input voltage, high (v ih ) full v e1.0 e1.0 a input voltage, low (v il ) full v +1.0 +1.0 a input capacitance 25 cv 3 3 pf analog interface (v d = 3.3 v, v dd = 3.3 v, adc clock = maximum conversion rate, unless otherwise noted.)
rev. b e3e ad9883a test ad9883akst-110 ad9883akst-140 parameter temp level min typ max min typ max unit digital outputs output voltage, high (v oh ) full vi v d e 0.1 v d e 0.1 v output voltage, low (v ol ) full vi 0.1 0.1 v duty cycle datack full iv 45 50 55 45 50 55 % output coding binary binary power supply v d supply voltage full iv 3.0 3.3 3.6 3.15 3.3 3.6 v v dd supply voltage full iv 2.2 3.3 3.6 2.2 3.3 3.6 v p vd supply voltage full iv 3.0 3.3 3.6 3.0 3.3 3.6 v i d supply current (v d )25 cv 132 180 ma i dd supply current (v dd ) 2 25 cv 19 26 ma ip vd supply current (p vd )25 cv 8 11 ma total power dissipation full vi 525 650 650 800 mw power-down supply current full vi 5 10 5 10 ma power-down dissipation full vi 16.5 33 16.5 33 mw dynamic performance analog bandwidth, full power 25 cv 300 300 mhz transient response 25 cv 2 2 ns overvoltage recovery time 25 cv 1.5 1.5 ns signal-to-noise ratio (snr) 25 cv 44 43 db (without harmonics) full v 43 42 db f in = 40.7 mhz crosstalk full v 55 55 dbc thermal characteristics jc junction-to-case thermal resistance v 16 16 c/w ja junction-to-ambient thermal resistance v 35 35 c/w notes 1 vco range = 10, charge pump current = 110, pll divider = 1693. 2 datack load = 15 pf, data load = 5 pf. specifications subject to change without notice.
rev. b ad9883a e4e test ad9883abste110 ad9883abste140 parameter temp level min typ max min typ max unit resolution 8 8 bits dc accuracy differential nonlinearity 25 ci 0.5 +1.25/e1.0 0.5 +1.5/e1.0 lsb full vi +1.5/e1.0 +1.81/e1.0 lsb integral nonlinearity 25 ci 0.5 1.85 0.5 1.85 lsb full vi 3.2 3.2 lsb analog input input voltage range minimum full vi 0.5 0.5 v p-p maximum full vi 1.0 1.0 v p-p gain tempco 25 cv 100 100 ppm/ c input bias current 25 civ 1 1 a full iv 2 2 a input offset voltage full vi 7 75 7 75 mv input full-scale matching full vi 1.5 8.0 1.5 10.0 % fs offset adjustment range full vi 46 49 52 46 49 52 % fs reference output output voltage full vi 1.19 1.25 1.33 1.19 1.25 1.33 v temperature coefficient full v 100 100 ppm/ c switching performance maximum conversion rate full vi 110 140 msps minimum conversion rate full iv 10 10 msps data to clock skew full iv e0.5 +2.0 e0.5 +2.0 ns t buff full vi 4.7 4.7 s t stah full vi 4.0 4.0 s t dho full vi 0 0 s t dal full vi 4.7 4.7 s t dah full vi 4.0 4.0 s t dsu full vi 250 250 s t stasu full vi 4.7 4.7 s t stosu full vi 4.0 4.0 s hsync input frequency full iv 15 110 15 110 khz maximum pll clock rate full vi 110 140 mhz minimum pll clock rate full iv 12 12 mhz pll jitter 25 civ 400 700 1 400 700 1 ps p-p full iv 1100 1 1100 1 ps p-p sampling phase tempco full iv 15 15 ps/ c digital inputs input voltage, high (v ih ) full vi 2.5 2.5 v input voltage, low (v il ) full vi 0.8 0.8 v input current, high (i ih ) full v e1.0 e1.0 a input current, low (i il ) full v 1.0 1.0 a input capacitance +25 cv 3 3 pf digital outputs output voltage, high (v oh ) full vi v d e 0.1 v d e 0.1 v output voltage, low (v ol ) full vi 0.1 0.1 v duty cycle, datack full iv 45 50 55 45 50 55 % output coding binary binary analog interface (v d = 3.3 v, v dd = 3.3 v, adc clock = maximum conversion rate, unless otherwise noted.)
rev. b ad9883a e5e test ad9883abste110 ad9883abste140 parameter temp level min typ max min typ max unit power supply v d supply voltage full iv 3.0 3.3 3.6 3.0 3.3 3.6 v v dd supply voltage full iv 2.2 3.3 3.6 2.2 3.3 3.6 v p vd supply voltage full iv 3.0 3.3 3.6 3.0 3.3 3.6 v i d supply current (v d )25 cv 132 163 ma i dd supply current (v dd ) 2 25 cv 19 24 ma ip vd supply current (p vd )25 cv 8 10 ma total power dissipation full vi 525 700 650 850 mw power-down supply current full vi 5 15 5 15 ma power-down dissipation full vi 16.5 33 16.5 33 mw dynamic performance analog bandwidth, full power 25 cv 300 300 mhz transient response 25 cv 2 2 ns overvoltage recovery time 25 cv 1.5 1.5 ns signal-to-noise ratio (snr) 25 cv 44 43 db (without harmonics) full v 43 42 db f in = 40.7 mhz crosstalk full v 55 55 dbc thermal characteristics jc junction-to-case 16 16 thermal resistance v c/w ja junction-to-ambient 35 35 thermal resistance v c/w notes 1 vco range = 10, charge pump current = 110, pll divider = 1693. 2 datack load = 15 pf, data load = 5 pf. specifications subject to change without notice.
rev. b ad9883a e6e absolute maximum ratings * v d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 v v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 v analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . v d to 0.0 v vref in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v d to 0.0 v digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 v to 0.0 v digital output current . . . . . . . . . . . . . . . . . . . . . . . . 20 ma operating temperature . . . . . . . . . . . . . . . . . e40 c to +85 c storage temperature . . . . . . . . . . . . . . . . . . e65 c to +150 c maximum junction temperature . . . . . . . . . . . . . . . . . 150 c maximum case temperature . . . . . . . . . . . . . . . . . . . . 150 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. explanation of test levels test level i. 100% production tested. ii. 1 00% production tested at 25 c and sample tested at specified temperatures. iii. sample tested only. iv. parameter is guaranteed by design and characterization testing. v. parameter is a typical value only. vi. 100% production tested at 25 c; guaranteed by design and characterization testing. ordering guide temperature package package model range description option ad9883akst-140 0 c to 70 c lqfp st-80 ad9883akst-110 0 c to 70 c lqfp st-80 ad9883akstz-110 * 0 c to 70 c lqfp st-80 ad9883akstz-140 * 0 c to 70 c lqfp st-80 ad9883abst-110 e40 c to +85 c lqfp st-80 ad9883abst-140 e40 c to +85 c lqfp st-80 ad9883abst-rl110 e40 c to +85 c lqfp st-80 ad9883abst-rl140 e40 c to +85 c lqfp st-80 ad9883a/pcb 25 ce valuation board * lead-free product caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9883a features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. b e7e ad9883a pin configuration gnd green <7> green <6> green <5> green <4> green <3> green <2> green <1> green <0> gnd v dd blue <7> blue <6> blue <5> blue <4> blue <3> blue <2> blue <1> blue <0> gnd gnd gnd gnd gnd gnd gnd v d v d v d v d v d v d ref bypass sda scl a0 r ain g ain b ain sogin 80 79 78 77 76 71 70 69 68 67 66 65 75 74 73 72 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 12 17 18 20 19 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 pin 1 identifier top view (not to scale) ad9883a 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 gnd v dd v dd red <0> red <1> red <2> red <3> red <4> red <5> red <6> red <7> v dd gnd datack hsout sogout gnd v d gnd vsout gnd v dd v dd gnd gnd pv d pv d gnd midscv clamp v d gnd coast hsync vsync gnd filt pv d pv d gnd table i. complete pinout list pin type mnemonic function value pin no. i nputs r ain analog input for converter r 0.0 v to 1.0 v 54 g ain analog input for converter g 0.0 v to 1.0 v 48 b ain analog input for converter b 0.0 v to 1.0 v 43 hsync horizontal sync input 3.3 v cmos 30 vsync vertical sync input 3.3 v cmos 31 sogin input for sync-on-green 0.0 v to 1.0 v 49 clamp clamp input (external clamp signal) 3.3 v cmos 38 coast pll coast signal input 3.3 v cmos 29 outputs red [7:0] outputs of converter red, bit 7 is the msb 3.3 v cmos 70e77 green [7:0] outputs of converter green, bit 7 is the msb 3.3 v cmos 2e9 blue [7:0] outputs of converter blue, bit 7 is the msb 3.3 v cmos 12e19 datack data output clock 3.3 v cmos 67 hsout hsync output (phase-aligned with datack) 3.3 v cmos 66 vsout vsync output (phase-aligned with datack) 3.3 v cmos 64 sogout sync-on-green slicer output 3.3 v cmos 65 references ref bypass internal reference bypass 1.25 v 58 midscv internal midscale voltage bypass 37 filt connection for external filter components for internal pll 33 power supply v d analog power supply 3.3 v 39, 42, 45, 46, 51, 52, 59, 62 v dd output power supply 3.3 v 11, 22, 23, 69, 78, 79 pv d pll power supply 3.3 v 26, 27, 34, 35 gnd ground 0 v 1, 10, 20, 21, 24, 25, 28, 32, 36, 40, 41, 44, 47, 50, 53, 60, 61, 63, 68, 80 control sda serial port data i/o 3.3 v cmos 57 scl serial port data clock (100 khz maximum) 3.3 v cmos 56 a0 serial port address input 1 3.3 v cmos 55
rev. b ad9883a e8e pin function descriptions pin name function outputs hsout horizontal sync output a reconstructed and phase-aligned version of the hsync input. both the polarity and duration of this output can be pro- grammed via serial bus registers. by maintaining alignment with datack and data, data timing with respect to horizontal sync can always be determined. vsout vertical sync output a reconstructed and phase-aligned version of the video vsync. the polarity of this output can be controlled via a serial bus bit. the place ment and duration in all modes is set by the graphics transmitter. sogout sync-on-green slicer output th is pin outputs either the signal from the sync-on-green slicer comparator or an unpr ocessed but delayed version of the hsync input. see the sync processing block diagram (figure 12) to view how this pin is connected. (note: besides slicing off sog, the output from this pin gets no other additional processing on the ad9883a. vsync separation is performed via the sync separator.) serial port (2-wire) sda serial port data i/o scl serial port data clock a0 serial port address input 1 for a full description of the 2-wire serial register and how it works, refer to the 2-wire serial control port section. data outputs red data output, red channel green data output, green channel blue data output, blue channel the main data outputs. bit 7 is the msb. the delay from pixel sampling time to output is fixed. when the sampling time is changed by adjusting the phase register, the output timing is shifted as well. the datack and hsout outputs are also moved, so the timing relationship among the signals is maintained. for exact t iming information, refer to figures 7, 8, and 9. data clock output datack data output clock this is the main clock output signal used to strobe the output data and hsout into external logic. it is produced by the internal clock generator and is synchronous with the internal pixel sampling clock. when the sampling time is changed by adjusting the phase register, the output timing is shifted as well. the data, datack, and hsout outputs are all moved, so the timing relationship among the signals is maintained. inputs r ain analog input for red channel g ain analog input for green channel b ain analog input for blue channel high impedance inputs that accept the red, green, and blue channel graphics signals, respectively. (the three channels are identical, and can be used for any colors, but colors are assigned for convenient reference.) they accommodate input signals ranging from 0.5 v to 1.0 v full scale. signals should be ac-coupled to these pins to support clamp operation. hsync horizontal sync input this input receives a logic signal that establis hes the horizontal timing reference and provides the frequency reference f or pi xel clock generation. the logic sense of this pin is controlled by serial register 0eh bit 6 (hsync polarity). only the leading edge of hsync is active; the trailing edge is ignored. when hsync polarity = 0, the falling edge of hsync is used. when hsync polarity = 1, the rising edge is active. the input includes a schmitt trigger for noise immunity, with a nominal input threshold of 1.5 v. vsync vertical sync input this is the input for vertical sync. sogin sync-on-green input this input is provided to assist with processing signals with embedded sync, typically on the green channel. the pin is connected to a high speed comparator with an internally generated threshold. the threshold level can be programmed in 10 mv steps to any voltage between 10 mv and 330 mv above the negative peak of the input signal. the default voltage threshold is 150 mv. when connected to an ac-coupled graphics signal with embedded sync, it will produce a noninverting digital output on sogout. (this is usually a composite sync signal, containing both vertical and horizontal sync infor mation that must be separated before passing the horizontal sync signal to hsync.) when not used, this input should be left unconnected. for more details on this function and how it should be configured, refer to the sync-on-green section.
rev. b ad9883a e9e design guide general description the ad9883a is a fully integrated solution for capturing analog rgb signals and digitizing them for display on flat panel monitors or projectors. the circuit is ideal for providing a computer interface for hdtv monitors or as the front end to high performance video scan converters. implemented in a high performance cmos process, the interface can capture signals with pixel rates up to 110 mhz. the ad9883a includes all necessary input buffering, signal dc restoration (clamping), offset and gain (brightness and contrast) adjustment, pixel clock generation, sampling phase control, and output data formatting. all controls are programmable via a 2-wire serial interface. full integration of these sensitive analog functions makes system design straightforward and less sensitive to the physical and electrical environment. with a typical power dissipation of only 500 mw and an operating temperature range of 0 c to 70 c, the device requires no special environmental considerations. digital inputs all digital inputs on the ad9883a operate to 3.3 v cmos levels. however, all digital inputs are 5 v tolerant. applying 5 v to them will not cause any damage. input signal handling t he ad9883a has three high impedance analog input pins for the red, green, and blue channels. they will accommodate signals ranging from 0.5 v to 1.0 v p-p. signals are typically brought onto the interface board via a dvi-i connector, a 15-pin d connector, or via bnc connectors. the ad9883a should be located as close as practical to the input connector. signals should be routed via matched-impedance traces (normally 75 ) to the ic input pins. pin function descriptions (continued) pin name function clamp external clamp input this logic input may be used to define the time during which the input signal is clamped to ground. it should be exer- cised when the reference dc level is known to be present on the analog input channels, typically during the back porch of the graphics signal. the clamp pin is enabled by setting control bit clamp function to 1, (register 0fh, bit 7, default is 0). when disabled, this pin is ignored and the clamp timing is determined internally by counting a delay and duration from the trailing edge of the hsync input. the logic sense of this pin is controlled by clamp polarity register 0fh, bit 6. when not used, this pin must be grounded and clamp function programmed to 0. coast clock generator coast input (optional) this input may be used to cause the pixel clock generator to stop synchronizing with hsync and continue producing a clock at its current frequency and phase. this is useful when processing signals from sources that fail to produce horizontal sync pulses during the vertical interval. the coast signal is generally not required for pc-generated signals. the logic sense of this pin is controlled by coast polarity (register 0fh, bit 3). when not used, this pin may be grounded and coast polarity programmed to 1, or tied high (to v d through a 10 k resistor) and coast polarity programmed to 0. coast polarity defaults to 1 at power-up. ref bypass internal reference bypass bypass for the internal 1.25 v band gap reference. it should be connected to ground through a 0.1 f capacitor. the absolute accuracy of this reference is 4%, and the temperature coefficient is 50 ppm, which is adequate for most ad9883a applications. if higher accuracy is required, an external reference may be employed instead. midscv midscale voltage reference bypass bypass for the internal midscale voltage reference. it should be connected to ground through a 0.1 f capacitor. the exact voltage varies with the gain setting of the blue channel. filt external filter connection for proper operation, the pixel clock generator pll requires an external filter. connect the filter shown in figure 6 to this pin. for optimal performance, minimize noise and parasitics on this node. power supply v d main power supply these pins supply power to the main elements of the circuit. they should be filtered and as quiet as possible. v dd digital output power supply a large number of output pins (up to 25) switching at high speed (up to 110 mhz) generates a lot of power supply transients (noise). these supply pins are identified separately from the v d pins so special care can be taken to minimize output noise transferred into the sensitive analog circuitry. if the ad9883a is interfacing with lower voltage logic, v dd may be connected to a lower supply voltage (as low as 2.5 v) for compatibility. pv d clock generator power supply the most sensitive portion of the ad9883a is the clock generation circuitry. these pins provide power to the clock pll and help the user design for optimal performance. the designer should provide quiet, noise-free power to these pins. gnd ground the ground return for all circuitry on-chip. it is recommended that the ad9883a be assembled on a single solid ground plane, with careful attention given to ground current paths.
rev. b ad9883a e10e at that point the signal should be resistively terminated (75 to the signal ground return) and capacitively coupled to the ad9883a inputs through 47 nf capacitors. these capacitors form part of the dc restoration circuit. in an ideal world of perfectly matched impedances, the best perfor- mance can be obtained with the widest possible signal bandwidth. the ultrawide bandwidth inputs of the ad9883a (300 mhz) can track the input signal continuously as it moves from one pixel level to the next, and digitize the pixel during a long, flat pixel t ime. in many systems, however, there are mismatches, reflections, and noise, which can result in excessive ringing and distortion of the input waveform. this makes it more difficult to establish a sampling phase that provides good image quality. it has been shown that a small inductor in series with the input is effec tive in rolling off the input bandwidth slightly and providing a high quality signal over a wider range of conditions. using a fair- rite #2508051217z0 high speed signal chip bead inductor in the circuit of figure 1 gives good results in most applications. rgb input r ain g ain b ain 47nf 75 figure 1. analog input interface circuit hsync, vsync inputs the interface also takes a horizontal sync signal, which is used to generate the pixel clock and clamp timing. this can be either a sync signal directly from the graphics source, or a prepro cessed ttl or cmos level signal. the hsync input includes a schmitt trigger buffer for immunity to noise and signals with long rise times. in typical pc based graphic systems, the sync signals are simply ttl-level drivers feeding unshielded wires in the monitor cable. as such, no ter- mination is required. serial control port the serial control port is designed for 3.3 v logic. if there are 5 v drivers on the bus, these pins should be protected with 150 series resistors placed between the pull-up resistors and the input pins. output signal handling the digital outputs are designed and specified to operate from a 3.3 v power supply (v dd ). they can also work with a v dd as low as 2.5 v for compatibility with other 2.5 v logic. clamping rgb clamping to properly digitize the incoming signal, the dc offset of the input must be adjusted to fit the range of the on-b oard a/d converters. most graphics systems produce rgb signals with black at ground and white at approximately 0.75 v. however, if sync signals are embedded in the graphics, the sync tip is often at ground and black is at 300 mv. then white is at approximately 1.0 v. some common rgb line amplifier boxes use emitter-follower buffers to split signals and increase drive capability. this intro- duces a 700 mv dc offset to the signal, which must be removed for proper capture by the ad9883a. the key to clamping is to identify a portion (time) of the signal when the graphic system is known to be producing black. an off s et is then introduced which results in the a/d c onverters pr o ducing a black output (code 00h) when the known black input is present. the offset then remains in place when other signal levels are processed, and the entire signal is shifted to elimi- nate offset errors. in most pc graphics systems, black is transmitted between active video lines. with crt displays, when the electron beam has completed writing a horizontal line on the screen (at the right side), the beam is deflected quickly to the left side of the screen (called horizontal retrace) and a black signal is provided to prevent the beam from disturbing the image. in systems with embedded sync, a blacker-than-black signal (hsync) is produced briefly to signal the crt that it is time to begin a retrace. for obvious reasons, it is important to avoid clamping on the tip of hsync. fortunately, there is virtually always a period following hsync, called the back porch, where a good black reference is provided. this is the time when clamp- ing should be done. the clamp timing can be established by simply exercising the clamp pin at the appropriate time (with external clamp = 1). the polarity of this signal is set by the clamp polarity bit. a simpler method of clamp timing employs the ad9883a internal clamp timing generator. the clamp placement register is pro- grammed with the number of pixel times that should pass after the trailing edge of hsync before clamping starts. a se cond register (clamp duration) sets the duration of the clamp. these are both 8-bit values, providing considerable flexibility in clamp generation. the clamp timing is referenced to the trailing edge of hsync because, though hsync duration can vary widely, the back porch (black reference) always follows hsync. a good starting point for establishing clamping is to set the clamp place- ment to 09h (providing 9 pixel periods for the graphics signal to stabilize after sync) and set the clamp duration to 14h (giving the clamp 20 pixel periods to reestablish the black reference). clamping is accomplished by placing an appropriate charge on the external input coupling capacitor. the value of this capaci- tor affects the performance of the clamp. if it is too small, there will be a significant amplitude change during a horizontal line time (between clamping intervals). if the capacitor is too large, then it will take excessively long for the clamp to recover from a large change in incoming signal offset. the recommended value (47 nf) results in recovering from a step error of 100 mv to within 1/2 lsb in 10 lines with a clamp duration of 20 pixel periods on a 60 hz sxga signal. yuv clamping yuv graphic signals are slightly different from rgb signals in that the dc reference level (black level in rgb signals) can be at the midpoint of the graphics signal rather than at the bottom. for these signals, it can be necessary to clamp to the midscale range of the a/d converter range (80h) rather than at the bottom of the a/d converter range (00h). clamping to midscale rather than to ground can be accom plished by setting the clamp select bits in the serial bus register. each of the three converters has its own selection bit so that they can be clamped to either midscale or ground independently. these bits are located in register 10h and are bits 0e2. the midscale refer ence voltage that each a/d converter clamps to is provided on the midscv pin, (pin 37). this pin should be bypassed to ground with a 0.1 f capacitor, (even if midscale clamping is not re quired).
rev. b ad9883a e11e gain 1.0 0. 0 00h ffh input range e v 0.5 offset = 00h offset = 3fh offset = 7fh offset = 00h offset = 7fh offset = 3fh figure 2. gain and offset control gain and offset control the ad9883a can accommodate input signals with inputs ranging from 0.5 v to 1.0 v full scale. the full-scale range is set in three 8-bit registers (red gain, green gain, and blue gain). note that increasing the gain setting results in an image with less contrast. the offset control shifts the entire input range, resulting in a change in image brightness. three 7-bit registers (red offset, green offset, blue offset) provide independent settings for each channel. the offset controls provide a 63 lsb adjust- ment range. this range is connected with the full-scale range, so if the input range is doubled (from 0.5 v to 1.0 v) then the offset step size is also doubled (from 2 mv per step to 4 mv per step). figure 2 illustrates the interaction of gain and offset controls. the magnitude of an lsb in offset adjustment is proportional to the full-scale range, so changing the full-scale range also changes the offset. the change is minimal if the offset setting is near midscale. when changing the offset, the full-scale range is n ot affected, but the full-scale level is shifted by the same amount as the zero scale level. sync-on-green the sync-on-green input operates in two steps. first, it sets a ba seline clamp level off of the incoming video signal w ith a negative peak detector. second, it sets the sync trigger level to a programmable level (typically 150 mv) above the negative peak. th e sync-on-green input must be ac-coupled to the g reen an alog input through its own capacitor, as shown in f igure 3. the value of the capacitor must be 1 nf 20%. if sync-on- green is not used, this connection is not required. note that the sync- on-green signal is always negative polarity. r ain b ain g ain sog 47nf 47nf 47nf 1nf figure 3. typical clamp configuration clock generation a phase locked loop (pll) is employed to generate the pixel clock. in this pll, the hsync input provides a reference fre- quency. a voltage controlled oscillator (vco) generates a much higher pixel clock frequency. this pixel clock is divided by the pll divide value (registers 01h and 02h) and phase compared with the hsync input. any error is used to shift the vco fre- quency and maintain lock between the two signals. the stability of this clock is a very important element in provid- ing the clearest and most stable image. during each pixel time, there is a period during which the signal is slewing from the old pi xel amplitude and settling at its new value. then there is a time when the input voltage is stable, before the signal must slew to a new value (figure 4). the ratio of the slewing time to t he stable time is a function of the bandwidth of the graphics dac and the bandwidth of the transmission system (cable and termination). it is also a function of the overall pixel rate. clearly, if the dynamic characteristics of the system remain fixed, the slewing and settling time is likewise fixed. this time must be subtracted from the total pixel period, leaving the stable period. at higher pixel frequencies, the total cycle time is shorter, and the stable pixel time becomes shorter as well. pixel clock invalid sample times figure 4. pixel sampling times any jitter in the clock reduces the precision with which the sampling time can be determined, and must also be subtracted from the stable pixel time. considerable care has been taken in the design of the ad9883a?s clock generation circuit to minimize jitter. as indicated in figure 5, the clock jitter of the ad9883a is less than 5% of the total pixel time in all operating modes, making the reduction in the valid sampling time due to jitter negligible. frequency e mhz 14 12 0 0 pixel clock jitter (p-p) e % 10 8 6 4 2 31.5 36.0 36.0 50.0 56.25 75.0 85.5 110.0 figure 5. pixel clock jitter vs. frequency
rev. b ad9883a e12e the pll characteristics are determined by the loop filter design, by the pll ch arge pump current, and by the vco range setting. the loop filter design is illustrated in figure 6. recommended settings of vco range and charge pump current for vesa standard display modes are listed in table v. c p 0.0082 f 0.082 f c z 2.7k r z filt pv d figure 6. pll loop filter detail four programmable registers are provided to optimize the per- formance of the pll. these registers are: 1. the 12-bit divisor register. the input hsync frequencies range from 15 khz to 110 khz. the pll multiplies the frequency of the hsync signal, producing pixel clock frequencies in the range of 12 mhz to 110 mhz. the divisor register controls the exact multiplication factor. this register may be set to any value between 221 and 4095. (the divide ratio that is actually used is the programmed divide ratio plus one.) 2. the 2-bit vco range register. to improve the noise performance of the ad9883a, the vco operating frequency range is divided into three overlapping regions. the vco range register sets this operating range. the frequency ranges for the lowest and highest regions are shown in table ii. table ii. vco frequency ranges pixel clock range (mhz) pv1 pv0 ad9883akst ad9883abst 00 12e32 12e30 01 32e64 30e60 10 64e110 60e120 11 110e140 120e140 3. the 3-bit charge pump current register. this register allows the current that drives the low-pass loop filter to be varied. the possible current values are listed in table iii. table iii. charge pump current/control bits ip2 ip1 ip0 current ( a) 00 050 00 1 100 01 0 150 01 1 250 10 0 350 10 1 500 11 0 750 11 1 1500 4. t he 5-bit phase adjust register. the phase of the generated sampling clock may be shifted to locate an optimum sampling point within a clock cycle. the phase adjust register provides 32 phase-shift steps of 11.25 each. the hsync signal with an identical phase shift is available through the hsout pin. the coast pin is used to allow the pll to continue to run at the same frequency, in the absence of the incoming h sync signal or during disturbances in hsync (such as equalization pulses). this may be used during the vertical sync period, or any other time that the hsync signal is unavailable. the polarity of the coast signal may be set through the coast polarity register. also, the polarity of the hsync signal may be set through the hsync polarity register. if not using automatic polarity detection, the hsync and coast polarity bits should be set to match the respective polarities of the input signals. power management the ad9883a uses the activity detect circuits, the active inter- face bits in the serial bus, the active interface override bits, and the power-down bit to determine the correct power state. there are three power states, full-power, seek mode, and power-down. table iv summarizes how the ad9883a determines what power mode to be in and which circuitry is powered on/off in each of these modes. the power-down command has priority over the automatic circuitry. table iv. power-down mode descriptions inputs power- sync powered on or mode down 1 detect 2 comments full-power 1 1 everything seek mode 1 0 serial bus, sync activity detect, sog, band gap reference power-down 0 x serial bus, sync activity detect, sog, band gap reference notes 1 power-down is controlled via bit 1 in serial bus register 0fh. 2 sync detect is determined by or-ing bits 7, 4, and 1 in serial bus register 14h.
rev. b ad9883a e13e table v. recommended vco range and charge pump current settings for standard display formats refresh horizontal ad9883akst ad9883abst standard resolution rate frequency pixel rate vcornge current vcornge current vga 640 480 60 hz 31.5 khz 25.175 mhz 00 110 00 011 72 hz 37.7 khz 31.500 mhz 00 110 01 010 75 hz 37.5 khz 31.500 mhz 00 110 01 010 85 hz 43.3 khz 36.000 mhz 01 100 01 010 svga 800 600 56 hz 35.1 khz 36.000 mhz 01 100 01 010 60 hz 37.9 khz 40.000 mhz 01 100 01 011 72 hz 48.1 khz 50.000 mhz 01 101 01 100 75 hz 46.9 khz 49.500 mhz 01 101 01 100 85 hz 53.7 khz 56.250 mhz 01 101 01 101 xga 1024 768 60 hz 48.4 khz 65.000 mhz 10 101 10 011 70 hz 56.5 khz 75.000 mhz 10 100 10 011 75 hz 60.0 khz 78.750 mhz 10 100 10 011 80 hz 64.0 khz 85.500 mhz 10 101 10 100 85 hz 68.3 khz 94.500 mhz 10 101 10 100 sxga 1280 1024 60 hz 64.0 khz 108.000 mhz 10 110 10 101 75 hz 80.0 khz 135.000 mhz 11 110 11 101 timing the following timing diagrams show the operation of the ad9883a. the output data clock signal is created so that its rising edge always occurs between data transitions, and can be used to latch the output data externally. there is a pipeline in the ad9883a, which must be flushed be fore valid data becomes available. this means four data sets are presented before valid data is available. t per t cycle t skew datack data hsout figure 7. output timing hsync timing horizontal sync (hsync) is processed in the ad9883a to elimi- nate ambiguity in the timing of the leading edge with respect to the phase-delayed pixel clock and data. the hsync input is used as a reference to generate the pixel s ampling clock. the sampling phase can be adjusted, with respect to hsync, through a full 360 in 32 steps via the phase adjust register (to optimize the pixel sampling time). display systems us e hsync to align memory and display write cycles, so it is important to have a stable timing relationship between hsync output (hsout) and data clock (datack). three things happen to horizontal sync in the ad9883a. first, the polarity of hsync input is determined and will thus have a known output polarity. the known output polarity can be pro- grammed either active high or active low (register 0eh, bit 5). second, hsout is aligned with datack and data outputs. third, the duration of hsout (in pixel clocks) is set via regis- ter 07h. hsout is the sync signal that should be used to drive the rest of the display system. coast timing in most computer systems, the hsync signal is provided con- tinuously on a dedicated wire. in these systems, the coast input and function are unnecessary, and should not be used and the pin should be permanently connected to the inactive state. in some systems, however, hsync is disturbed during the vertical sync period (vsync). in some cases, hsync p ulses disappear. in other systems, such as those that employ composite sync (csync) signals or embedded sync-on-green (sog), hsync includes equalization pulses or other distortions during vsync. to avoid upsetting the clock generator during vsync, it is impor- tant to ignore these distortions. if the pixel clock pll sees extraneous pulses, it will attempt to lock to this new fre quency, and will have changed frequency by the end of the vsync period. it will then take a few lines of correct hsync timing to recover at the beginning of a new frame, resulting in a tearing of the image at the top of the display. the coast input is provided to eliminate this problem. it is an asynchronous input that disables the pll input and allows the clock to free-run at its then-current frequency. the pll can free-run for several lines without significant frequency drift.
rev. b ad9883a e14e p0 p1 p2 p3 p4 p5 p6 p7 5-pipe delay d0 d1 d2 d3 d4 d5 d6 d7 rgb in hsync pxck hs adcck datack d outa hsout v ariable duration figure 8. 4:4:4 mode (for rgb and yuv) p0 p1 p2 p3 p4 p5 p6 p7 5-pipe delay y0 y1 y2 y3 y4 y5 y6 y7 rgb in hsync pxck hs adcck datack g outa hsout u0 v1 u2 v3 u4 v5 u6 v7 r outa v ariable duration figure 9. 4:2:2 mode (for yuv only)
rev. b ad9883a e15e table vi. control register map write and hex read or default register address read only bits value name function 00h ro 7:0 chip revision an 8-bit register that represents the silicon revision level. revision 0 = 0000 0000. 01h * r/ w w w w w w w w w w w w w w w
rev. b ad9883a e16e table vi. control register map (continued) write and hex read or default register address read only bits value name function 0fh r/w 7:1 0 ******* bit 7 e clamp function. chooses between hsync for clamp signal or another external signal to be used for clamping. (logic 0 = hsync, logic 1 = clamp.) * 1 ****** bit 6 e clamp polarity. valid only with external clamp signal. (logic 0 = active high, logic 1 selects active low.) ** 0 ***** bit 5 e coast select. logic 0 selects the coast input pins to be used for the pll coast. logic 1 selects vsync to be used for the pll coast. *** 0 **** bit 4 e coast polarity override. (logic 0 = polarity determined by chip, logic 1 = polarity set by bit 3 in register 0fh.) **** 1 *** bit 3 e coast polarity. selects polarity of external coast signal. (logic 0 = active low, logic 1 = active high.) ***** 1 ** bit 2 e seek mode override. (logic 1 = allow low power mode, logic 0 = disallow low power mode.) ****** 1 * bit 1 e pwrdn. full chip power-down, active low. (logic 0 = full chip power-down, logic 1 = normal.) 10h r/w 7:3 10111 *** sync-on-green sync-on-green threshold. sets the voltage level of the sync-on- threshold green slicer?s comparator. ***** 0 ** bit 2 e red clamp select. logic 0 selects clamp to ground. logic 1 selects clamp to midscale (voltage at pin 37). ****** 0 * bit 1 e green clamp select. logic 0 selects clamp to ground. logic 1 selects clamp to midscale (voltage at pin 37). ******* 0 bit 0 e blue clamp select. logic 0 selects clamp to ground. logic 1 selects clamp to midscale (voltage at pin 37). 11h r/w 7:0 00100000 sync separator sync separator threshold. sets how many internal 5 mhz clock threshold periods the sync separator will count to before toggling high or low. this should be set to some number greater than the maximum hsync or equalization pulsewidth. 12h r/w 7:0 00000000 pre-coast pre-coast. sets the number of hsync periods that coast becomes active prior to vsync. 13h r/w 7:0 00000000 post-coast post-coast. sets the number of hsync periods that coast stays active following vsync. 14h ro 7:0 sync detect bit 7 e hsync detect. it is set to logic 1 if hsync is present on the analog interface; otherwise it is set to logic 0. bit 6 e ahs: active hsync. this bit indicates which analog hsync is being used. (logic 0 = hsync input pin, logic 1 = hsync from sync-on-green.) bit 5 e input hsync polarity detect. (logic 0 = active low, logic 1 = active high.) bit 4 e vsync detect. it is set to logic 1 if vsync is present on the analog interface; otherwise it is set to logic 0. bit 3 e avs: active vsync. this bit indicates which analog vsync is being used. (logic 0 = vsync input pin, logic 1 = vsync from sync separator.) bit 2 e output vsync polarity detect. (logic 0 = active low, logic 1 = active high.) bit 1 e sync-on-green detect. it is set to logic 1 if sync is present on the green video input; otherwise it is set to 0. bit 0 e input coast polarity detect. (logic 0 = active low, logic 1 = active high.) 15h r/ w
rev. b ad9883a e17e 2-wire serial control register detail chip identification 00 7e0 chip revision an 8-bit register that represents the silicon revision. revi- sion 0 = 0000 0000, revision 1 = 0000 0001, revision 2 = 0000 0010. pll divider control 01 7e0 pll divide ratio msbs t he 8 most significant bits of the 12-bit pll divide ratio plldiv. (the operational divide ratio is plldiv + 1.) the pll derives a master clock from an incoming hsync signal. the master clock frequency is then divided by an integer value, such that the output is phase-locked to hsync. this plldiv value determines the number of pixel times (pixels plus horizontal blanking overhead) per line. this is typically 20% to 30% more than the number of active pixels in the display. the 12-bit value of the pll divider supports divide ratios from 2 to 4095. the higher the value loaded in this regis- ter, the higher the resulting clock frequency with respect to a fixed hsync frequency. ve sa has established some standard timing specifica tions that assist in determining the value for plldiv as a func tion of horizontal and vertical display resolution and frame rate (table v). however, many computer systems do not conform pre- cisely to the recommendations, and these numbers should be used only as a guide. the display system manufacturer should provide automatic or manual means for optimizing p lldiv. an incorrectly set plldiv will usually produce one or more vertical noise bars on the display. the greater the error, the greater the number of bars produced. t he power-up default value of plldiv is 1693 (plldivm = 69h, p lldivl = dxh). the ad9883a updates the full divide ratio only when the lsbs are changed. writing to the msb by itself will not trigger an update. 02 7e4 pll divide ratio lsbs the 4 least significant bits of the 12-bit pll divide ratio plldiv. the operational divide ratio is plldiv + 1. the power-up default value of plldiv is 1693 (plldivm = 69h, plldivl = dxh). the ad9883a updates the full divide ratio only when this register is written to. clock generator control 03 7e6 vco range select two bits that establish the operating range of the clock generator. vcornge must be set to correspond with the desired operating frequency (incoming pixel rate). th e pll gives the best jitter performance at h igh fre- quencies. for this reason, to output low pixel rates and still get good jitter performance, the pll actually operates at a higher frequency but then divides down the clock rate afterwards. table vii shows the pixel rates for each vco range setting. the pll output divisor is automatically selected with the vco range setting. table vii. vco ranges vcornge pixel rate range 00 12e32 01 32e64 10 64e110 11 110e140 the power-up default value is 01. 03 5e3 current charge pump current three bits that establish the current driving the loop filter in the clock generator. table viii. charge pump currents current current ( a) 000 50 001 100 010 150 011 250 100 350 101 500 110 750 111 1500 current must be set to correspond with the desired operating frequency (incoming pixel rate). the power-up default value is current = 001. table vi. control register map (continued) write and hex read or default register address read only bits value name function 16h r/ w
rev. b ad9883a e18e 04 7e3 clock phase adjust a 5-bit value that adjusts the sampling phase in 32 steps across one pixel time. each step represents an 11.25 shift in sampling phase. the power-up default value is 16. clamp timing 05 7e0 clamp placement an 8-bit register that sets the position of the internally generated clamp. when clamp function (register 0fh, bit 7) = 0, a clamp signal is generated inter nally, at a position established by the clamp placement and for a duration set by the clamp duration. clamping is started (clamp placement) pixel periods after the trailing edge of hsync. the clamp place ment may be programmed to any value between 1 and 255. the clamp should be placed during a time that the input signal presents a stable black-level reference, usually the back porch period between hsync and the image. when clamp function = 1, this register is ignored. 06 7e0 clamp duration an 8-bit register that sets the duration of the internally generated clamp. for the best results, the clamp duration should be set to include the majority of the black reference signal time that f ollows the hsync signal trailing edge. insufficient clamping time can produce brightness changes at the top of the screen, and a slow recovery from large changes in the average picture level (apl), or brightness. when clamp function = 1, this register is ignored. hsync pulsewidth 07 7e0 hsync output pulsewidth an 8-bit register that sets the duration of the hsync out put pulse. the leading edge of the hsync output is triggered by the internally generated, phase-adjusted pll feedback clock. the ad9883a then counts a number of pixel clocks equal to the value in this register. this triggers the trailing edge of the hsync output, which is also phase adjusted. input gain 08 7e0 red channel gain adjust an 8-bit word that sets the gain of the red channel. the ad9883a can accommodate input signals with a full-scale range of between 0.5 v and 1.0 v p-p. setting r edgain to 255 corresponds to a 1.0 v input range. a redgain of 0 establishes a 0.5 v input range. note that increasing redgain results in the pic ture having less contrast (the input signal uses fewer of the available converter codes). see figure 2. 09 7e0 green channel gain adjust an 8-bit word that sets the gain of the green channel. see redgain (08). 0a 7e0 blue channel gain adjust an 8-bit word that sets the gain of the blue channel. see redgain (08). input offset 0b 7e1 red channel offset adjust a 7-bit offset binary word that sets the dc offset of the red channel. one lsb of offset adjustment equals approxim ately one lsb change in the adc offset. therefore, the abso lute magnitude of the offset adjustment scales as the gain of the channel is changed. a nominal setting of 63 results in the channel nominally clamping the back porch (during the clamping interval) to code 00. an offset setting of 127 results in the channel clamping to code 64 of the adc. an offset setting of 0 clamps to code e63 (off the bottom of the range). increasing the value of red offset decreases the brightness of the channel. 0c 7e1 green channel offset adjust a 7-bit offset binary word that sets the dc offset of the green channel. see redofst (0b). 0d 7e1 blue channel offset adjust a 7-bit offset binary word that sets the dc offset of the green channel. see redofst (0b). mode control 1 0e 7 hsync input polarity override t his register is used to override the internal circuitry that determines the polarity of the hsync signal going into the pll. table ix. hsync input polarity override settings override bit function 0h sync polarity determined by chip 1h sync polarity determined by user the default for hsync polarity override is 0 (polarity determined by chip). 0e 6 hspol hsync input polarity a bit that must be set to indicate the polarity of the hsync signal that is applied to the pll hsync input. table x. hsync input polarity settings hspol function 0a ctive low 1a ctive high active low means the leading edge of the hsync pulse is negative going. all timing is based on the leading edge of hsync, which is the falling edge. the rising edge has no effect. active high is inverted from the traditional hsync, with a positive-going pulse. this means that timing will be based on the leading edge of hsync, which is now the rising edge. the device will operate if this bit is set incorrectly, but the internally generated clamp position, as established by clamp placement (register 05h), will not be placed as expected, which may generate clamping errors. the power-up default value is hspol = 1.
rev. b ad9883a e19e 0e 5 hsync output polarity this bit determines the polarity of the hsync output and the sog output. table xi shows the effect of this option. sync indicates the logic state of the sync pulse. table xi. hsync output polarity settings setting sync 0l ogic 1 (positive polarity) 1l ogic 0 (negative polarity) the default setting for this register is 0. 0e 4 active hsync override this bit is used to override the automatic hsync selection, to override, set this bit to logic 1. when overriding, the active hsync is set via bit 3 in this register. table xii. active hsync override settings override result 0a utodetermines the active interface 1 override, bit 3 determines the active inter face the default for this register is 0. 0e 3 active hsync select this bit is used under two conditions. it is used to select t he active hsync when the override bit is set (bit 4). alter- na tely, it is used to determine the active hsync when not overriding but both hsyncs are detected. table xiii. active hsync select settings select result 0h sync input 1 sync-on-green input the default for this register is 0. 0e 2 vsync output invert this bit inverts the polarity of the vsync output. table xiv shows the effect of this option. table xiv. vsync output invert settings setting vsync output 0 invert 1n o invert the default setting for this register is 0. 0e 1 active vsync override this bit is used to override the automatic vsync selection. to override, set this bit to logic 1. when overriding, the active interface is set via bit 0 in this register. table xv. active vsync override settings override result 0a utodetermine the active vsync 1 override, bit 0 determines the active v sync the default for this register is 0. 0e 0 active vsync select this bit is used to select the active vsync when the over- ride bit is set (bit 1). table xvi. active vsync select settings select result 0v sync input 1s ync separator output the default for this register is 0. 0f 7 clamp input signal source this bit determines the source of clamp timing. table xvii. clamp input signal source settings clamp function function 0i nternally generated clamp signal 1 externally provided clamp signal a 0 enables the clamp timing circuitry controlled by clamp placement and clamp duration. the clamp position and duration is counted from the leading edge of hsync. a 1 enables the external clamp input pin. the three channels are clamped when the clamp signal is active. the polarity of clamp is determined by the clamp polarity bit (register 0fh, bit 6). the power-up default value is clamp function = 0. 0f 6 clamp input signal polarity this bit determines the polarity of the externally provided clamp signal. table xviii. clamp input signal polarity settings clamp function function 1a ctive low 0a ctive high a logic 1 means that the circuit will clamp when clamp is low, and it will pass the signal to the adc when clamp is high. a logic 0 means that the circuit will clamp w hen clamp is high, and it will pass the signal to the adc when clamp is low. the power-up default value is clamp polarity = 1. 0f 5 coast select this bit is used to select the active coast source. the choices are the coast input pin or vsync. if vsync is se- lected the additional decision of using the vsync input pin or the output from the sync separator needs to be made (register 0e, bits 1, 0). table xix. power-down settings select result 0c oast input pin 1v sync (see above text)
rev. b ad9883a e20e 0f 4 coast input polarity override this register is used to override the internal circuitry that determines the polarity of the coast signal going into the pll. table xx. coast input polarity override settings override bit result 0d etermined by chip 1d etermined by user the default for coast polarity override is 0. 0f 3 coast input polarity this bit indicates the polarity of the coast signal that is applied to the pll coast input. table xxi. coast input polarity settings coast polarity function 0a ctive low 1a ctive high active low means that the clock generator will ignore hsync inputs when c oast is low, and continue operat ing at the same nominal frequency until c oast goes high. active high means that the clock generator will ignore hsync inputs when c oast is high, and continue operat ing at the same nominal frequency until c oast goes low. this function needs to be used along with the coast po larity override bit (bit 4). the power-up default value is 1. 0f 2 seek mode override this bit is used to either allow or disallow the low power mode. the low power mode (seek mode) occurs when there are no signals on any of the sync inputs. table xxii. seek mode override settings select result 1a llow seek mode 0d isallow seek mode the default for this register is 1. 0f 1 pwrdn p pd r pd n r r r p r p p p n p
rev. b ad9883a e21e 13 7e0 post-coast this register allows the coast signal to be applied follow- ing the vsync signal. this is necessary in cases where post-equalization pulses are present. the step size for this control is one hsync period. the default is 0. 14 7 hsync detect this bit is used to indicate when activity is detected on the hsync input pin (pin 30). if hsync is held high or low, activity will not be detected. table xxvii. hsync detection results detect function 0n o activity detected 1a ctivity detected the sync processing block diagram shows where this function is implemented. 14 6 ahs e active hsync this bit indicates which hsync input source is being used by the pll (hsync input or sync-on-green). bits 7 and 1 in this register determine which source is used. if both hsync and sog are detected, the user can determine which has priority via bit 3 in register 0eh. the user can ove rride this function via bit 4 in register 0eh. if the override bit is set to logic 1, then this bit will be forced to whatever the state of bit 3 in register 0eh is set to. table xxviii. active hsync results bit 7 bit 1 bit 4, (hsync (sog reg 0eh detect) detect) (override) ahs 00 0 b it 3 in 0eh 01 0 1 10 0 0 11 0 b it 3 in 0eh xx 1 b it 3 in 0eh ahs = 0 means use the hsync pin input for hsync. ahs = 1 means use the sog pin input for hsync. the override bit is in register 0eh, bit 4. 14 5 detected hsync input polarity status this bit reports the status of the hsync input polarity detection circuit. it can be used to determine the polarity of the hsync input. the detection circuit?s location is shown in the sync processing block diagram (figure 12). table xxix. detected hsync input polarity status hsync polarity status result 0n egative 1 positive 14 4 vsync detect this bit is used to indicate when activity is detected on the vsync input pin (pin 31). if vsync is held steady high or low, activity will not be detected. table xxx. vsync detection results detect function 0n o activity detected 1a ctivity detected the sync processing block diagram (figure 12) shows where this function is implemented. 14 3 avs e active vsync this bit indicates which vsync source is being used: the vsync input or output from the sync separator. bit 4 in this register determines which is active. if both vsync and sog are detected, the user can determine w hich has priority via bit 0 in register 0eh. the user can o verride this function via bit 1 in register 0eh. if the override bit is set to logic 1, this bit will be forced to whatever the state of bit 0 in register 0eh is set. table xxxi. active vsync results avs = 0 means vsync input. avs = 1 means sync separator. the override bit is in register 0eh, bit 1. 14 2 detected vsync output polarity status this bit reports the status of the vsync output polarity detection circuit. it can be used to determine the polarity of the vsync output. the detection circuit?s location is- shown in the sync processing block diagram (figure 12). table xxxii. detected vsync output polarity status vsync polarity status result 0a ctive low 1a ctive high 14 1 sync-on-green detect this bit is used to indicate when sync activity is detected on the sync-on-green input pin (pin 49). table xxxiii. sync-on-green detection results detect function 0n o activity detected 1a ctivity detected the sync processing block diagram (figure 12) shows where this function is implemented. 14 0 detected coast polarity status t his bit reports the status of the coast input polarity de tection circuit. it can be used to determine the polarity of the coast input. the detection circuit?s location is shown in the sync processing block diagram (figure 12). bit 4, reg 14h bit 1, reg 0eh (vsync detect) (override) avs 100 001 x1b it 0 in 0eh
rev. b ad9883a e22e table xxxiv. detected coast input polarity status polarity status result 0c oast polarity negative 1c oast polarity positive this indicates that bit 1 of register 5 is the 4:2:2 output mode select bit. 15 1 4:2:2 output mode select a bit that configures the output data in 4:2:2 mode. this mode can be used to reduce the number of data lines used from 24 down to 16 for applications using yuv, ycbcr, or ypbpr graphics signals. a timing diagram for this mode is shown in figure 9. recommended input and output configurations are shown in table xxxv. table xxxv. 4:2:2 output mode select select output mode 0 4:2:2 1 4:4:4 table xxxvi. 4:2:2 input/output configuration input channel connection output format red v u/v green y y blue u high impedance 2-wire serial control port a 2-wire serial interface control interface is provided. up to two ad9883a devices may be connected to the 2-wire serial inter face, with each device having a unique address. the 2-wire serial interface comprises a clock (scl) and a bidi- rectional data (sda) pin. the analog flat panel interface acts as a slave for receiving and transmitting data over the serial interface. when the serial interface is not active, the logic levels on scl and sda are pulled high by external pull-up resistors. data received or transmitted on the sda line must be stable for the duration of the positive-going scl pulse. data on sda must change only when scl is low. if sda changes state while scl is high, the serial interface interprets that action as a start or stop sequence. there are five components to serial bus operation: ? start signal ? slave address byte ? base register address byte ? data byte to read or write ? stop signal when the serial interface is inactive (scl and sda are high) communications are initiated by sending a start signal. the start signal is a high-to-low transition on sda while scl is high. this signal alerts all slaved devices that a data transfer sequence is coming. the first eight bits of data transferred after a start signal com- prise a 7-bit slave address (the first seven bits) and a single r/ w w w w
rev. b ad9883a e23e data is read from the control registers of the ad9883a in a similar manner. reading requires two data transfer operations: the base address must be written with the r/ w w w w ? ? w ? ? ? ? ? w ? ? ? ? ? ? ? ? w ? ? ? w ? ? ? ? w ? ? ? w ? ? ? ? ?
rev. b ad9883a e24e table xxxviii. control of the sync block muxes via the serial register serial bus control mux no. control bit bit state result 1 and 2 0eh: bit 3 0 pass hsync 1 pass sync-on-green 3 0fh: bit 5 0 pass coast 1 pass vsync 4 0eh: bit 0 0 pass vsync 1 pass sync separator signal sync slicer the purpose of the sync slicer is to extract the sync signal from the green graphics channel. a sync signal is not present on all graphics systems, only those with sync-on-green. the sync signal is extracted from the green channel in a two-step process. first, the sog input is clamped to its negative peak (typically 0.3 v below the black level). next, the signal goes to a comparator with a variable trigger level, nominally 0.15 v above the clamped level. the sliced sync is typically a composite sync signal containing both hsync and vsync. sync separator a sync separator extracts the vsync signal from a composite sync signal. it does this through a low-pass filter-like or integrator-like operation. it works on the idea that the vsync signal stays a ctive fo r a much longer time than the hsync signal, so it rejects any s ignal shorter than a threshold value, which is somewhere between an hsync pulsewidth and a vsync pulsewidth. the sync separator on the ad9883a is simply an 8-bit digital counter with a 5 mhz clock. it works independently of the polarity of the composite sync signal. (polarities are determined elsewhere on the chip.) the basic idea is that the counter counts up when hsync pulses are present. but since hsync pulses are relatively short in width, the counter only reaches a value of n before the pulse ends. it then starts counting down eventually reaching 0 before the next hsync pulse arrives. the specific value of n will vary for different video modes, but will always be less than 255. for example with a 1 s width hsync, the counter will only reach 5 (1 s/200 ns = 5). now, when vsync is present on the composite sync the counter will also count up. however, since the vsync signal is much longer, it will count to a higher number m. for most video modes, m will be at least 255. so, vsync can be detected on the composite sync signal by detecting when the counter counts to higher than n. the specific count that triggers detection (t) can be programmed through the serial register (11h). once vsync has been detected, there is a similar process to detect when it goes inactive. at detection, the counter first resets to 0, then starts counting up when vsync goes away. similar to the previous case, it will detect the absence of vsync when the counter reaches the threshold count (t). in this way, it will reject noise and/or serration pulses. once vsync is detected to be absent, the counter resets to 0 and begins the cycle again. pcb layout recommendations the ad9883a is a high precision, high speed analog device. as such, to get the maximum performance out of the part, it is important to have a well laid out board. the following is a guide for designing a board using the ad9883a. analog interface inputs using the following layout techniques on the graphics inputs is extremely important. minimize the trace length running into the graphics inputs. this is acc omplished by placing the ad9883a as c lose as possible to the graphics vga connector. long input trace lengths are undesirable because they pick up more noise from the board and other external sources. place the 75 termination resistors (see figure 1) as close to the ad9883a chip as possible. any additional trace length between the termination resistors and the input of the ad9883a in creases t he magnitude of reflections, which will corrupt the graphics signal. use 75 matched impedance traces. trace impedances other than 75 will also increase the chance of reflections. t he ad9883a has very high input bandwidth (500 mhz). while th is is desirable for acquiring a high resolution pc graphics signal with fast edges, it means that it will also capture any high frequency noise present. therefore, it is important to reduce the amount of noise that gets coupled to the inputs. avoid running any digital traces near the analog inputs. due to the high bandwidth of the ad9883a, low- pass filtering the analog inputs can s ometimes help to reduce noise. (for many applications, filtering is unnecessary.) experiments have shown that placing a series ferrite bead prior to the 75 termi- nation resistor is helpful in filtering out excess noise. specifically, the part used was the #2508051217z0 from fair-rite, but each applica tion may work best with a different bead value. alter nately, placing a 100 to 120 resistor between the 75 termination resistor and the input coupling capaci tor can also be beneficial. power supply bypassing it is recommended to bypass each power supply pin with a 0.1 f capacitor. the exception is when two or more supply pins are adjacent to each other. for these groupings of powers/ grounds, it is necessary to have only one bypass ca pacitor. the fundamental idea is to have a bypass capacitor within about 0.5 cm of each power pin. also, avoid placing the capacitor on the opposite side of the pc board from the ad9883a, as that interposes resistive vias in the path. the bypass capacitors should be physically located between the power plane and the power pin. current should flow from the power plane to the capacitor to the power pin. do not make the power connection between the capacitor and the power pin. placing a via underneath the capacitor pads, down to the power plane, is generally the best approach. it is particularly important to maintain low noise and good stability of pv d (the clock generator supply). abrupt changes in pv d can result in similarly abrupt changes in sampling clock phase and frequency. this can be avoided by careful attention to regu- lation, filtering, and bypassing. it is highly desirable to provide separate regulated supplies for each of the analog circuitry groups (v d and pv d ). s ome graphic controllers use substantially different levels of power when active (during active picture time) and when idle (during horizontal and vertical sync periods). this can result in a measurable change in the voltage supplied to the analog supply regulator, which can in turn produce changes in the regulated analog supply voltage. this can be mitigated by regula ting the analog supply, or at least pv d , from a different, cleaner power source (for example, from a 12 v supply).
rev. b ad9883a e25e it is also recommended to use a single ground plane for the entire board. experience has repeatedly shown that the noise perfor- mance is the same or better with a single ground plane. using multiple ground planes can be detrimental because each separate ground plane is smaller, and long ground loops can result. in some cases, using separate ground planes is unavoidable. for those cases, it is recommended to at least place a single ground plane under the ad9883a. the location of the split should be at the receiver of the digital outputs. for this case it is even more important to place components wisely because the current loops will be much longer (current takes the path of least resis- tance). an example of a current loop: p o w e r p l a n e a d 9 8 8 3 a d i g i t a l o u t p u t t r a c e a n a l o g g r o u n d p l a n e d i g i t a l g r o u n d p l a n e d i g i t a l d a t a r e c e i v e r figure 13. current loop pll place the pll loop filter components as close to the filt pin as possible. do not place any digital or other high frequency traces near these components. use the values suggested in the data sheet with 10% tolerances or less. outputs (both data and clocks) try to minimize the trace length that the digital outputs have to drive. longer traces have higher capacitance, which requires more current, which causes more internal digital noise. shorter traces reduce the possibility of reflections. adding a series resistor of value 22 to 100 can suppress reflec- tions, reduce emi, and reduce the current spikes inside of the ad9883a. however, if 50 traces are used on the pcb, the data outputs should not need resistors. a 22 resistor on the datack output should provide good impedance matching that will reduce reflections. if series resistors are used, place them as close to the a d9883a pins as possible (although try not to add vias or extra length to the output trace in order to get the resistors closer). if possible, limit the capacitance that each of the digital outputs d rives to less than 10 pf. this can easily be accomplished by keeping traces short and by connecting the outputs to only one d evice. loading the outputs with excessive capacitance will increase the current transients inside of the ad9883a, creating more digital noise on its power supplies. digital inputs the digital inputs on the ad9883a were designed to work with 3.3 v signals, but are tolerant of 5.0 v signals. therefore, no extra com ponents need to be added if using 5.0 v logic. any noise that gets onto the hsync input trace will add jitter to the system. therefore, minimize the trace length and do not run any digital or other high frequency traces near it. voltage reference bypass with a 0.1 f capacitor. place as close to the ad9883a p in as possible. make the ground connection as short as possible.
rev. b ad9883a e26e 80-lead low profile quad flat package [lqfp] (st-80) dimensions shown in millimeters 61 60 1 80 20 41 21 40 top view (pins down) pin 1 seating plane view a 1.60 max 0.75 0.60 0.45 0.20 0.09 1.45 1.40 1.35 0.10 max coplanarity view a rotated 90 ccw seating plane 10 6 2 7 3.5 0 0.15 0.05 14.00 bsc sq 16.00 bsc sq 0.65 bsc 0.38 0.32 0.22 compliant to jedec standards ms-026-bec outline dimensions
rev. b ad9883a e27e revision history location page 8/03?data sheet changed from rev. a to rev. b. added b grade models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal edits to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 change to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 replaced table ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 edits to table v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 edits to table vi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 edits to sync-on-green slicer threshold section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 edits to table xxxi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 edits to 4:2:2 output mode select section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 edits to sync separator section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 edits to outputs section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5/02?data sheet changed from rev. 0 to rev. a. edits to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 edits to pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 edits to table ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 edits to clock generation section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 edits to figure 8 and figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 edits to table vi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 edits to table vii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 edits to clamp timing section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 edits to table xiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 edits to clamp input signal polarity section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 edits to 4:2:2 output mode select section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 edits to table xxxv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 edits to 2-wire serial control port section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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