1 pxxxx 06/01/00 product features ? all three ports compliant with the pci local bus specification, revision 2.1 ? compliant with pci-to-pci bridge architecture specification, revision 1.0 ? 32-bit primary and two secondary ports ? circular-delta bus architecture ? concurrent primary to secondary bus operation and indepen- dent intra-secondary port channel to reduce traffic on the primary port ? provides arbitration for two sets of 8 secondary bus masters ? programmable 2-level priority arbiters ? disable control for use of external arbiter ? support pci transactions for: ? all i/o and memory commands ? type 1 to type 0 configuration conversion (downstream only) ? type 1 to type 1 configuration forwarding ? type 1 to special cycle configuration conversion ? supports posted memory write buffers in all directions ? implements delayed transactions for all pci configuration, i/o and memory read commands ? supports positive medium decoding ? enhanced address decoding ? 32-bit i/o address range ? 32-bit memory-mapped i/o address range ? vga addressing and vga palette snooping ? isa-aware mode for legacy support in the first 64kb of i/o address range ? ieee 1149.1 jtag interface support ? full scan support ? 3.3v core logic with 5v tolerant 3.3v pci signaling interface ? 256-pin plastic pbga package (na256) ? supports system transaction ordering rules ? hot-plug "ready" 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi7c7100 3 port pci-to-pci bridge datasheet brief product description pericom?s pi7c7100 is the first triple port pci-to-pci bridge device designed to be fully compliant with the 32-bit, 33 mhz implementation of the pci local bus specification, revision 2.1. the pi7c7100 supports synchronous bus transactions between devices on the primary bus and the secondary buses both operating at 33 mhz. the primary and the secondary buses can also operate in concurrent mode, resulting in additional increase in system performance. concurrent bus operation offloads and isolates unnecessary traffic from the primary bus; thereby enabling a master and a target device on the same secondary pci bus to communicate even while the primary bus is busy. product benefits ? triple port pci-to-pci bridge increases the number of pci slots that can be supported in a system. ? single pi7c7100 device instead of two pci-to-pci bridge devices conserves board real estate and provides one less device load on the primary bus. ? concurrent and intra-secondary bus communication increases overall system performance by reducing bus traffic on the primary bus. devices on secondary busses can independently communicate while the primary bus is busy. ? integrated two-level programmable arbiter support for up to 8 devices on each secondary bus maximizes master device control. the internal arbiter can be bypassed with an external arbiter for custom applications. ? synchronous clock operation on the primary and secondary busses ? enhanced pci bridge performance and efficiency through support for delayed transactions.
pi7c7100 3 port pci-to-pci bridge datasheet brief 2 pxxxx 06/01/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi7c7100 block diagram configuration registers a/b primary master/ target interface primary and secondary control primary arbiter req/gnt transaction queue & buffers transaction queue & data buffers 1 transaction queue & data buffers 2 arbiter req/gnt 1 (qty. 8) arbiter req/gnt 2 (qty. 8) master/ target interface 1 master/ target interface 2 clock (qty. 16) primary interface secondary interface 1 secondary interface 2
pi7c7100 3 port pci-to-pci bridge datasheet brief 3 pxxxx 06/01/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi7c7100 pin information p_ad [31:0] p_cbe [3:0] p_par p_frame# p_irdy# p_trdy# p_devsel# p_stop# p_lock# p_idsel p_perr# p_serr# p_req# p_gnt# s1_ad[31:0] s1_cbe [3:0] s1_par s1_frame# s1_irdy# s1_trdy# s1_devsel# s1_stop# s1_lock# s1_idsel s1_perr# s1_serr# s1_req# [7:0] s1_gnt# [7:0] s1_reset# s1_en s_clkout [15:0] s_cfn# s_m66en s2_ad [31:0] s2_cbe [3:0] s2_par s2_frame# s2_irdy# s2_trdy# s2_devsel# s2_stop# s2_lock# s2_idsel s2_perr# s2_serr# s2_req# [7:0] s2_gnt# [7:0] s2_reset# s2_en p_reset# p_m66en p_clk p_flush# tck tms tdo tdi trst# scanen primary bus interface secondary C1 bus interface secondary C2 bus interface clock control control input jtag interface full test scan
pi7c7100 3 port pci-to-pci bridge datasheet brief 4 pxxxx 06/01/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com applications the pi7c7100 extends a system?s pci load capability limit beyond that of a single pci bus. the dual secondary ports on this de vice allows system designers to add more pci devices, or more pci option card slots, than a single pci bus can support. implementing the special concurrent feature in the pi7c7100 enables maximum data through-put between the primary and the second - ary buses with minimal system loading. figure 1, shows the pi7c7100 system block diagram vs the traditional pci bridge applica tion to illustrate the system performance enhancement resulting from implementing a pi7c7100. line interface card line interface card line interface card nb system memory cpu line interface card pericom p2p single pci load for two secondary bus 33 mhz, 32-bit minimal latency between busses concurrent mode. minimal traffic primary pci bus, 33 mhz, 32-bit line interface card line interface card line interface card nb system memory cpu line interface card p2p 2 two pci loads for two secondary bus extra latency between busses traffic on primary pci bus p2p 1 figure 1. pericom's three port pci vs. traditional two port pci in a system architecture
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