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general description the max191 is a monolithic, cmos, 12-bit analog-to- digital converter (adc) featuring differential inputs, track/hold (t/h), internal voltage reference, internal or external clock, and parallel or serial ? interface. the max191 has a 7.5? conversion time, a 2? acquisition time, and a guaranteed 100ksps sample rate. the max191 operates from a single +5v supply or from dual ?v supplies, allowing ground-referenced bipolar input signals. the device features a logic power-down input, which reduces the 3ma v dd supply current to 50? max, including the internal-reference current. decoupling capacitors are the only external compo- nents needed for the power supply and reference. this adc operates with either an external reference, or an internal reference that features an adjustment input for trimming system gain errors. the max191 provides three interface modes: two 8-bit parallel modes, and a serial interface mode that is com- patible with spi tm , qspi tm , and microwire tm serial- interface standards. ________________________applications battery-powered data logging pc pen digitizers high-accuracy process control electromechanical systems data-acquisition boards for pcs automatic testing systems telecommunications digital signal processing (dsp) ____________________________features ? 12-bit resolution, 1/2lsb linearity ? +5v or ?v operation ? built-in track/hold ? internal reference with adjustment capability ? low power: 3ma operating mode 20? power-down mode ? 100ksps tested sampling rate ? serial and 8-bit parallel ? interface ? 24-pin narrow dip and wide so packages max191 low-power, 12-bit sampling adc with internal reference and power-down ________________________________________________________________ maxim integrated products 1 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 v dd clk/sclk par hben ain- ain+ v ss pd top view cs rd d7/dout d6/sclk out bip agnd refadj vref 16 15 14 13 9 10 11 12 d5/sstrb d4 d3/d11 d2/d10 dgnd d1/d9 d0/d8 busy dip/so max191 pin configuration 2.46v ref in ref out 12-bit sar adc osc control logic 3-state output 8-bit bus and serial i/o 18 17 16 15 14 13 11 10 20 19 9 21 d7/dout d6/sclk out d5/sstrb d4 d3/d11 d2/d10 d1/d9 d0/d8 cs rd busy hben refadj vref ain + ain - 5 6 3 4 24 23 v dd clk/sclk 712 pd 1 22 8 agnd dgnd 2 par bip max191 12 v ss functional diagram 19-4506; rev 4; 2/97 part temp. range pin-package max191acng 0? to +70? 24 narrow plastic dip 24 wide so ?/2 ? ?/2 error (lsb) 24 narrow plastic dip max191bcng max191acwg 0? to +70? 0? to +70? max191bcwg 0? to +70? 24 wide so ? max191bc/d dice* ? 0? to +70? max191aeng -40? to +85? 24 narrow plastic dip ?/2 max191beng -40? to +85? 24 narrow plastic dip 1 max191aewg -40? to +85? 24 wide so ?/2 max191amrg 24 narrow cerdip** ?/2 max191bmrg 24 narrow cerdip** 1 -55? to +125? -55? to +125? max191bewg -40? to +85? 24 wide so ? spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 408-737-7600 ext. 3468. evaluation kit manual follows data sheet * dice are specified at t a = +25?, dc parameters only. ** contact factory for availability and processing to mil-std-883. ordering information
max191 low-power , 12-bit sampling adc with inter nal refer ence and power -down 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = 5v 5%, v ss = 0v or -5v 5%, f clk = 1.6mhz, 50% duty cycle, ain- = agnd, bip = 0v, slow-memory mode, internal -reference mode, reference compensation mode?xternal, synchronous operation, figure 6, t a = t min to t max , unless otherwise noted.) (note 1) stresses beyond those listed under ?bsolute maximum ratings" may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to dgnd ............................................................ -0.3v to +7v v ss to agnd ............................................................ -7v to +0.3v v dd to v ss .............................................................................. 12v agnd, vref, refadj to dgnd ................ -0.3v to (v dd + 0.3v) ain+, ain-, pd to v ss ................................. -0.3v to (v dd + 0.3v) cs , rd , clk, bip, hben, par, to dgnd .... -0.3v to (v dd + 0.3v) busy , d0?7 to dgnd .............................. -0.3v to (v dd + 0.3v) continuous power dissipation (t a = +70 c) narrow plastic dip (derate 13.33mw/ c above +70 c) .... 1067mw wide so (derate 11.76mw/ c above +70 c) ...................... 941mw narrow cerdip (derate 12.50mw/ c above +70 c) ........ 1000mw operating temperature ranges max191_c_ _ ................................................................ 0 c to +70 c max191_e_ _ ............................................................. -40 c to +85 c max191_m_ _ .......................................................... -55 c to +125 c storage temperature range ..................................... -65 c to +160 c lead temperature (soldering, 10sec) ..................................... +300 c parameter conditions min typ max units offset error max191b 2 lsb max191a 1 differential nonlinearity no missing codes over temperature 1 lsb integral nonlinearity max191b 1 lsb max191a 2 gain error (note 3) max191b 3 lsb resolution 12 bits max191a 1/2 gain-error tempco (note 4) excludes internal-reference drift 0.2 ppm/ c 1khz input signal, t a = +25 c 70 db 1khz input signal, t a = +25 c -80 db spurious-free dynamic range 1khz input signal, t a = +25 c 80 db synchronous clk (12 to 13 clks) conversion time (note 5) internal clk, c l = 120pf 6 12 18 s track/hold acquisition time 2 s aperture delay 25 ns aperture jitter 50 ps 0.1 1.6 mhz signal-to-noise plus distortion ratio total harmonic distortion (up to the 5th harmonic) external clock frequency range (note 6) symbol dnl inl sinad sfdr thd t conv f clk 7.50 8.125 dc accuracy (note 2) dynamic accuracy (sample rate = 100khz, v in = 4vp-p) conversion rate
ma max191 low-power , 12-bit sampling adc with inter nal refer ence and power -down _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = 5v 5%, v ss = 0v or -5v 5%, f clk = 1.6mhz, 50% duty cycle, ain- = agnd, bip = 0v, slow-memory mode, internal -reference mode, reference compensation mode?xternal, synchronous operation, figure 6, t a = t min to t max , unless otherwise noted.) (note 1) pd external leakage for float state (note 12) v flt v 2.8 reference compensation mode?xternal pd floating-state voltage na 100 maximum current allowed for ?loating state i in a 20 pd = 0v to v dd (note 11) pd input current 200 pd = high/float i in a 0.1 pd = low input current clk c in pf 10 input capacitance (note 6) v il v 0.5 pd input low voltage v ih v 4.5 pd input high voltage i in a 10 v in = 0v to v dd input current v ih v 2.4 cs , rd , clk, hben, par, bip input high voltage v il v 0.8 cs , rd , clk, hben, par, bip input low voltage k 5 10 external-reference mode input resistance ma 1 external-reference = 5v input current refadj input adjustment range (note 10) v 2.5 5.0 external-reference mode input voltage range a 60 refadj = 5v refadj input current v 2.4 refadj output voltage v 4.5 refadj disable threshold mv -60 30 v 300 v dd = 5%, v ss = 5% power-supply rejection f 4.7 reference compensation mode?xternal capacitive load required ma 18 output short-circuit current mv 4 t a = +25 c, i out = 0ma to 2ma load regulation symbol units min typ max conditions parameter input voltage range (note 7) v v ss v dd input capacitance (note 6) pf 45 80 input leakage current a 10 v in = v ss to v dd 50 max191_c vref output voltage v 4.076 4.096 4.116 t a = +25 c small-signal bandwidth mhz 2 60 max191_e output current capability (note 9) ma 2 t a = +25 c vref output tempco (note 8) ppm/ c 80 max191_m analog input internal reference reference input logic inputs
max191 low-power , 12-bit sampling adc with inter nal refer ence and power -down 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 5v 5%, v ss = 0v or -5v 5%, f clk = 1.6mhz, 50% duty cycle, ain- = agnd, bip = 0v, slow-memory mode, internal -reference mode, reference compensation mode?xternal, synchronous operation, figure 6, t a = t min to t max , unless otherwise noted.) (note 1) parameter rd pulse width conditions 150 units max191c/e min typ max 150 ns 140 0 140 max191m min typ max 150 160 0 160 c l = 100pf 120 ns 80 100 ns 120 t 8 110 120 100 ns t 7 100 120 80 ns t 6 0 0 cs to rd hold time 0 ns t 5 symbol rd to busy delay cs to rd setup time 0 ns c l = 50pf 120 ns t 4 t 3 t 2 t 1 timing characteristics (figures 6?0) (v dd =5v 5%, v ss = 0v or -5v 5%, t a = t min to t max , unless otherwise noted.) (note 14) aperture delay jitter < 50ps 25 ns t 12 2 2 2 200 200 200 ns t 10 hben to rd hold time 0 0 ns 0 t 9 data access time (note 15) data setup time after busy (note 15) bus-relinquish time (note 16) hben to rd setup time delay between read operations (note 6) 200 230 ns 260 t 13 clk to busy delay (note 6) 100 130 ns 150 t 14 sclk out to sstrb rise delay sclk out to sstrb fall delay 100 130 ns 150 t 15 t a = +25 c min typ max s t 11 delay between conversions v ss v -5.25 0 negative supply voltage i dd v dd v ol v oh c out i l a 20 50 v 0.4 i out = 1.6ma ma 3 5 v 4.75 5.25 positive supply voltage output low voltage symbol pd = low pd = high/float pd = low lsb 1/2 fs change, v ss = -5v 5% negative supply rejection (note 13) lsb 1/2 fs change, v dd = 5v 5% positive supply rejection (note 13) i ss a v pf 4.0 i out = -200 a output high voltage 1 20 cs = rd = v dd , ain = 5v, d0/d8?7/ dout = 0v or v dd , hben = par = bip = 0v or v dd positive supply current 15 pd = high/float three-state output capacitance (note 6) 20 100 a negative supply current units 10 d0/d8-d7/dout min typ max conditions three-state leakage current parameter logic outputs power requirements
max191 low-power , 12-bit sampling adc with inter nal refer ence and power -down _______________________________________________________________________________________ 5 parameter sclk to sclk out delay conditions 160 units ns cs to dout three-state 100 ns symbol cs or rd setup time cs or rd hold time ns 150 ns t 20 t 19 t 17 t 16 timing characteristics (figures 6?0) (continued) (v dd =5v 5%, v ss = 0v or -5v 5%, t a = t min to t max , unless otherwise noted.) (note 14) 10 max191c/e min typ max 180 110 10 150 max191m min typ max 200 120 10 150 310 350 sclk to sstrb delay 260 ns t 23 260 280 sclk to dout delay 240 ns t 22 130 sclk out to dout delay 100 ns t 21 150 note 1: performance at power-supply tolerance limits guaranteed by power-supply rejection test. note 2: v dd = 5v, v ss = 0v, fs = vref. note 3: fs = vref, offset nulled, ideal last-code transition = fs - 3/2 lsb. note 4: gain-error tempco = ? ge is the gain-error change from t a = +25 c to t min or t max . note 5: conversion time defined as the number of clock cycles times the clock period; clock has a 50% duty cycle. note 6: guaranteed by design, not production tested. note 7: ain+, ain- must not exceed supplies for specified accuracy. note 8: vref tc = ? t, where ? vref is reference-voltage change from t a = +25 c to t min or t max . note 9: output current should not change during conversion. this current is in addition to the current required by the internal dac. note 10: refadj adjustment range is defined as the allowed voltage excursion on refadj relative to its unadjusted value of 2.4v. this will typically result in a 1.7 times larger change in the ref output (figure 19a). note 11: this current is included in the pd supply current specification. note 12: floating the pd pin guarantees external compensation mode. note 13: v ref = 4.096v, external reference. note 14: all input control signals are specified with t r = t f = 5ns (10% to 90% of 5v) and timed from a voltage level of 1.6v. note 15: t 3 and t 6 are measured with the load circuits of figure 1 and defined as the time required for an output to cross 0.8v or 2.4v. note 16: t 7 is defined as the time required for the data lines to change 0.5v when loaded with the circuits of figure 2. t a = +25 c min typ max
max191 low-power , 12-bit sampling adc with inter nal refer ence and power -down 6 _______________________________________________________________________________________ __________________________________________ t ypical operating characteristics 10 0.01 0.1 10 clock frequency vs. timing capacitor 0.1 1 timing capacitor (nf) clock frequency (mhz) 1 see figure 5 t a = +25?c gr191-a 0 -60 150 5 25 temperature (?) supply current ( m a) 120 15 10 0 60 20 -30 30 90 v dd = +5v v ss = -5v pd = 0v i ss i dd power-down supply current vs. temperature gr191-b 0 -60 150 5 25 temperature (?) i ss ( m a) 120 15 10 0 60 20 -30 30 90 negative supply current vs. temperature gr191-c 3.5 0.5 -60 -30 30 60 1.0 2.0 temperature (?) i dd (ma) 0 1.5 90 120 150 2.5 3.0 0 positive supply current vs. temperature gr191-d 0 -140 0 2 6 1khz fft plot -100 -40 gr191-e frequency (khz) signal amplitude (db) 4 -80 1 3 5 -120 -60 -20 f in = 1khz f s = 100khz snr = 72db t a = +25?c -94.3db -96.1db -98.0db -93.8db 0 -140 0 10 30 40 10khz fft plot -100 -60 gr191-f frequency (khz) signal amplitude (db) 15 -80 -120 -40 -20 f in = 10khz f s = 100khz snr = 71.2db t a = +25?c 5 20 25 35 -86.0db -90.8db
max191 low-power , 12-bit sampling adc with inter nal refer ence and power -down _______________________________________________________________________________________ 7 pin description clock input/serial clock input in serial mode. an external ttl-/cmos-compatible clock may be applied to this pin, or a capacitor (120pf nominal) may be connected between clk and dgnd to operate the internal oscillator. high-byte enable input. in parallel mode, hben = high multiplexes the 4 msbs of the conversion result into the lower bit outputs. hben = high also disables conversion starts. hben = low places the 8 lsbs onto the data bus. in serial mode, hben = low enables sclk out to operate during the conversion only, hben = high enables sclk out to operate continuously, provided cs is low. chip-select input must be low for the adc to recognize rd and hben inputs in parallel mode. the falling edge of cs starts a conversion in serial mode. cs = high in serial mode forces sclk out , sstrb, and dout into a high-impedance state. read input. in parallel mode, a low signal starts a conversion when cs and hben are low (memory mode). rd also enables the outputs when cs is low. in serial mode, rd = low enables sclk out and sstrb when cs is low. rd = high forces sclk out and sstrb into a high-impedance state. d6/sclk out 7 analog ground agnd 24 positive supply, +5v 5% v dd 23 clk/sclk 22 sets the output mode. par = high selects parallel output mode. par = low selects serial output mode. par 21 hben 20 cs 19 rd 18 three-state data output/data output in serial mode d7/dout 13 three-state data outputs d2/d10 14 three-state data outputs: msb = d11 d3/d11 15 three-state data output d4 16 three-state data output/serial strobe output in serial mode d5/sstrb 17 three-state data output/serial clock output in serial mode 10 three-state data outputs: lsb = d0 d0/d8 11 three-state data outputs d1/d9 12 digital ground dgnd power-down input. a logic low at pd deactivates the adc?nly the bandgap reference is active. a logic high selects normal operation, internal-reference compensation mode. an open-circuit condition selects normal operation, external-reference compensation mode. pin 9 8 6 busy output is low during a conversion. busy bip = low selects unipolar mode bip = high selects bipolar mode (see gain and offset adjustment section) bip 5 4 3 reference adjust. connect to v dd to use an extended reference at vref. refadj reference-buffer output for internal reference. input for external reference when refadj is connected to v dd . vref analog input return. pseudo-differential (see gain and offset adjustment section). ain- 2 1 sampled analog input ain+ negative supply, 0v to -5.25v v ss pd function name
_______________ detailed description the max191 uses successive approximation and input track/hold (t/h) circuitry to convert an analog input sig - nal to a 12-bit digital output. flexible control logic pro - vides easy interface to microprocessors ( ps), so most applications require only the addition of passive com - ponents. no external hold capacitor is required for the t/h. figure 3 shows the max191 in its simplest opera - tional configuration. pseudo-differential input the sampling architecture of the adc? analog com - parator is illustrated in the equivalent input circuit (figure 4). a capacitor switching between the ain+ and ain- inputs acquires the signal at the adc? ana - log input. at the end of the conversion, the capacitor reconnects to ain+ and charges to the input signal. an external input buffer is usually not needed for low- bandwidth input signals (<100hz) because the adc disconnects from the input during the conversion. in unbuffered applications, an input filter capacitor reduces conversion noise, but also may limit input bandwidth. when converting a single-ended input signal, ain- should be connected to agnd. if a differential signal is connected, consider that the configuration is pseudo differential?nly the signal side to the input channel is held by the t/h. the return side (ain-) must remain sta - ble within 0.5lsb ( 0.1lsb for best results) with respect to agnd during a conversion. accomplish this by connecting a 0.1 f capacitor from ain- to agnd. analog input?rack/hold the t/h enters its tracking mode when the adc is des - elected ( cs pin is held high and busy pin is high). hold mode starts approximately 25ns after a conver - sion is initiated. the variation in this delay from one conversion to the next (aperture jitter) is about 50ps. figures 6?0 detail the t/h and interface timing for the max191 low-power , 12-bit sampling adc with inter nal refer ence and power -down 8 _______________________________________________________________________________________ dn 3k c l dgnd +5v 3k dn c l dgnd a. high-z to v oh and v ol to v oh b. high-z to v ol and v oh to v ol figure 1. load circuits for access time dn 3k 10pf dgnd +5v 3k dn 10pf dgnd a. v oh to high-z b. v ol to high-z figure 2. load circuits for bus-relinquish time 1 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 pd ain+ ain- vref refadj agnd bip busy do/db d1/d9 dgnd v ss 2 v dd clk/sclk par hben cs rd d7/dout d6/sclk out d5/sstrb d4 d3/d11 d2/d10 open output status 4.7 m f 0.1 m f 0.1 m f 0v to -5v +5v serial/parallel interface mode m p control inputs max191 c1 note: c1 120pf generates 1mhz nominal clock. m p data bus figure 3. operational diagram
various interface modes. the time required for the t/h to acquire an input signal is a function of how quickly its input capacitance is charged. if the input signal? source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. acquisition time is cal - culated by: t acq = 10(r s + r in )c hold (but never less than 2 s), where r in = 2k , r s = source impedance of the input signal, and c hold = 32pf (see figure 4). input bandwidth the adc? input tracking circuitry has a 1mhz typical large-signal bandwidth characteristic, and a 30v/ s slew rate. it is possible to digitize high-speed transients and measure periodic signals with bandwidths exceed - ing the adc? sample rate of 100ksps by using under - sampling techniques. note that if undersampling is used to measure high-frequency signals, special care must be taken to avoid aliasing errors. without ade - quate input bandpass filtering, out-of-band signals and noise may be aliased into the measurement band. input protection internal protection diodes, which clamp the analog input to v dd and v ss , allow ain+ to swing from (v ss - 0.3v) to (v dd + 0.3v) with no risk of damage to the adc. however, for accurate conversions near full scale, ain+ should not exceed the power supplies by more than 50mv because adc accuracy is affected when the pro - tection diodes are even slightly forward biased. digital inter face starting a conversion in parallel mode, the adc is controlled by the cs , rd , and hben inputs, as shown in figure 6. the t/h enters hold mode and a conversion starts at the falling edge of cs and rd while hben (not shown) is low. busy goes low as soon as the conversion starts. on the falling edge of the 13th input clock pulse after the conversion starts, busy goes high and the conversion result is latched into three-state output buffers. in seri - al mode, the falling edge of cs initiates a conversion, and the t/h enters hold mode. data is shifted out seri - ally as the conversion proceeds (figure 10). see the parallel digital-interface mode and serial-interface mode sections for details. internal/external clock figure 5 shows the max191 clock circuitry. the adc includes internal circuitry to generate a clock with an external capacitor. as indicated in the typical operating characteristics , a 120pf capacitor con - nected between the clk and dgnd pins generates a 1mhz nominal clock frequency (figure 5). alternatively, an external clock (between 100khz and 1.6mhz) can be applied to clk. when using an exter - nal clock source, acceptable clock duty cycles are max191 low-power , 12-bit sampling adc with inter nal refer ence and power -down _______________________________________________________________________________________ 9 12-bit dac track c hold comparator hold 32pf hold c switch 10pf c package 5pf ain + ain - r in figure 4. equivalent input circuit c ext dgnd clk +1.6v clock max191 note: c ext = 120pf generates 1mhz nominal clock figure 5. internal clock circuit
max191 between 45% and 55%. clock and control synchronization for best analog performance on the max191, the clock should be synchronized to the conversion start signals ( cs and rd ) as shown in figure 6. a conversion should not be started in the 50ns before a clock edge nor in the 100ns after it. this ensures that clk transitions are not coupled to the analog input and sampled by the t/h. the magnitude of this feedthrough can be a few millivolts. when the clock and conversion start signals are synchronized, small end-point errors (offset and full-scale) are the most that can be generated by clock feedthrough. even these errors (which can be trimmed out) can be avoided by ensuring that the start of a con - version ( rd or cs falling edge) does not occur close to a clock transition (figure 6), as described above. parallel digital-interface mode output-data format the data output from the max191 is straight binary in the unipolar mode. in the bipolar mode, the msb is inverted (see figure 22). the 12 data bits can be out - put either in two 8-bit bytes or as a serial output. table 1 shows the data-bus output format. a 2-byte read uses outputs d7?0. byte selection is controlled by hben. when hben is low, the lower 8 bits appear at the data outputs. when hben is high, the upper 4 bits appear at d0-d3 with the leading 4 bits low in locations d4?7. timing and control conversion-start and data-read operations are con - trolled by the hben, cs , and rd digital inputs. a logic low is required on all three inputs to start a conversion, and once the conversion is in progress it cannot be restarted. busy remains low during the entire conver - sion cycle. the timing diagrams of figures 7?0 outline two paral - lel-interface modes and one serial mode. slow-memory mode in slow-memory mode, the device appears to the p as a slow peripheral or memory. conversion is initiated with a read instruction (see figure 7 and table 2). set the par pin high for parallel interface mode. beginning with hben low, taking cs and rd low starts the con - version. the analog input is sampled on the falling edge of rd . busy remains low while the conversion is in progress. the previous conversion result appears at the digital outputs until the end of conversion, when busy returns high. the output latches are then updat - ed with the newest results of the 8 lsbs on d7?0. a second read operation with hben high places the 4 msbs, with 4 leading 0s, on data outputs d7?0. the second read operation does not start a new conversion because hben is high. rom mode as in slow-memory mode, d7?0 are used for 2-byte reads. a conversion starts with a read instruction with hben and cs low. the t/h samples the input on the falling edge of rd (see figure 8 and table 3). par is set high. at this point the data outputs contain the 8 lsbs from the previous conversion. two more read operations are needed to access the conversion result. the first occurs with hben high, where the 4 msbs with 4 leading 0s are accessed. the second read, with hben low, out - puts the 8 lsbs and also starts a new conversion. figure 9 and table 4 show how to read output data within one conversion cycle without starting another conversion. trigger the falling edge of a read on the ris - low-power , 12-bit sampling adc with inter nal refer ence and power -down 10 ______________________________________________________________________________________ t conv cs + rd busy t 16 clk t 17 t 2 t 13 t 2 t conv figure 6. cs , rd , and clk synchronous operation
max191 low-power , 12-bit sampling adc with inter nal refer ence and power -down ______________________________________________________________________________________ 11 data hold* track new data d11?8 *internal signal. tracking input signal when hold = low, holding when hold = hi gh. t 8 t conv busy rd cs hben t 1 t 2 t 3 t 12 new data d7?0 old data d7?0 t 6 t 7 t 3 t 7 t 10 t 11 t 10 t 12 t 4 t 1 t 5 t 5 t 9 t 8 t 9 figure 7. slow-memory mode timing hben cs rd busy data hold* track t 12 t 3 t 7 t 12 t 3 t 7 t 3 t 7 t 11 t 10 t 2 t 2 t conv t 5 t 4 t 1 t 5 t 4 t 1 t 5 t 4 t 1 t 8 t 9 t 8 t 9 t 8 t 9 old data d7?0 new data d11?8 new data d7?0 *internal signal. tracking input signal when hold = low, holding when hold = hi gh. figure 8. rom mode timing
max191 low-power , 12-bit sampling adc with inter nal refer ence and power -down 12 ______________________________________________________________________________________ hben clk cs rd busy data hold* track t 8 t 1 t 4 t 5 t 2 t conv t 12 t 3 t 7 t 3 t 7 t 10 t 9 t 8 *internal signal. tracking input signal when hold = low, holding when hold = hi gh new data d7?0 new data d11?8 t 7 t 3 old data d7?0 figure 9. rom mode timing, reading data without starting a conversion sclk out sclk cs sstrb dout t 20 t 20 t 22 t 16 t 23 t 14 t 15 t 22 t 21 t 19 three state three state t 23 t 17 t 12 12 sclk cycles hold track three state three state figure 10. serial-interface mode timing diagram ( rd = low)
max191 low-power , 12-bit sampling adc with inter nal refer ence and power -down ______________________________________________________________________________________ 13 table 1. data-bus output, cs = rd = low pin name d7/dout d4 d3/d11 d2/d10 d1/d9 d0/d8 d7 d6 d5 d4 d3 d2 d1 d0 hben = 1, par = 1, parallel mode low low low low d11 d10 d9 d8 dout sclk out sstrb low low low low low hben = x, par = 0, serial mode, rd = 1 dout three- stated low low low low low d6/sclk out d5/sstrb three- stated hben = x, par = 0, serial mode, rd = 0 note: d7/dout?0/d8 are the adc data output pins. d11?0 are the 12-bit conversion results. d11 is the msb. dout = three-state data output. data output in serial mode. sclk out = three-state data output. clock output in serial mode. sstrb = three-state data output. strobe output in serial mode. table 2. slow-memory mode, 2-byte read data-bus status hben = 0, par = 1, parallel mode pin name d7/dout d6/sclk out d5/sstrb d4 d3/d11 d2/d10 d1/d9 d0/d8 first read (new data) d7 d6 d5 d4 d3 d2 d1 d0 low low low low d11 d10 d9 d8 second read (new data) table 3. rom mode, 2-byte read data-bus status pin name d7/dout d6/sclk out d5/sstrb d4 d3/d11 d2/d10 d1/d9 d0/d8 d7 d6 d5 d4 d3 d2 d1 d0 second read (new data) low low low low d11 d10 d9 d8 third read (new data) d7 d6 d5 d4 d3 d2 d1 d0 table 4. rom mode, 2-byte read data-bus status without starting a conversion cycle pin name d7/dout d6/sclk out d5/sstrb d4 d3/d11 d2/d10 d1/d9 d0/d8 first read (old data) d7 d6 d5 d4 d3 d2 d1 d0 second read (new data) d7 d6 d5 d4 d3 d2 d1 d0 third read (new data) low low low low d11 d10 d9 d8 first read (old data)
max191 low-power , 12-bit sampling adc with inter nal refer ence and power -down 14 ______________________________________________________________________________________ 3 4 5 6 10 11 12 13 1 2 8 9 18 17 21 23 20 19 16 1 2 8 9 3 4 5 6 10 11 12 13 sclk cs rd dout sclk out hben sstrb +5v logic input a b clock clear q a q b q c q d q e q f q g q h a b clock clear q a q b q c q d q e q f q g q h +5v note: use sstrb to gate parallel data transfer from shift register, or to clear shift registers if desired. max191 74hc164 74hc164 +5v t 19 do d11 cs sstrb sclk out sclk dout figure 11. simple serial-to-parallel interface
max191 low-power , 12-bit sampling adc with inter nal refer ence and power -down ______________________________________________________________________________________ 15 ing edge of the first clock cycle after conversion end (when busy goes high). as mentioned previously, two more read operations (after busy goes high) are needed to access the conversion results. the only dif - ference is that now the low byte can be read first. this happens by allowing the first read operation to occur with hben low, where the 8 lsbs are accessed. the second read, with hben high, accesses the 4 msbs with 4 leading 0s. serial-interface mode the serial mode is compatible with microwire, spi and qspi serial interfaces. in addition, a framing signal (sstrb) is provided that allows the devices to interface with the tms320 family of dsps. set par low for serial mode. a falling edge on cs causes the t/h to sample the input (figure 10). conversion always begins on the next falling edge of sclk, regardless of where cs occurs. the dout line remains high-impedance until a conversion begins. during the msb decision, dout remains low (leading 0), while sstrb goes high to indi - cate that a data frame is beginning. the data is avail - able at dout on the rising edge of sclk (sclk out when using an internal clock) and transitions on the falling edge. dout remains low after all data bits have been shifted out, inserting trailing 0s in the data stream until cs returns high. the sclk out signal is synchro - nous with the internal or external clock. for interface flexibility, dout, sclk out and sstrb signals enter a high-impedance state when cs is high. when cs is low, rd controls the status of sclk out and sstrb outputs. a logic low rd enables sclk out and sstrb, while a logic high forces both outputs into a high-impedance state. also, with cs low and hben high, sclk out drives continuously, regardless of con - version status. this is useful with ps that require a continuous serial clock. if cs and hben are low, sclk out is output only during the conversion cycle, while the converter internal clock runs continuously. this is useful for creating a simple serial-to-parallel interface without shift-register overflow (figure 11). maximum clock rate in serial mode the maximum sclk rate depends on the minimum setup time required at the serial data input to the p and the adc? dout to sclk delay (t 22 ) (see figure 12). the maximum f sclk is as follows: dout sclk t setup (min) t 22 1 1 f sclk (max) = 2 t su (m) + t 22 ( ) t su (m) is the setup time required at the serial data input to the m p. t 22 is the maximum sclk to dout delay. figure 12. f sclk (max) is limited by the setup time required by the serial data input to the p. i/o cs sck miso ss sclk dout +5v cs sck miso cs sclk dout +5v cs sclk dout cs sclk sstrb i/o sk si i/o clkx clkr dr fsr max191 max191 max191 max191 a. spi b. qspi c. microwire d. tms320 serial interface dout ss figure 13. common serial-interface connections to the max191
max191 f sclk (max) = (1/2) x 1/ (t su (m) + t 22 ) where t su (m) is the minimum data-setup time re- quired at the serial data input to the p. for example, motorola? mc68hc11a8 data book specifies a 100ns minimum data-setup time. using the worst case for a military grade part of t 22 = 280ns (see timing characteristics ) and substituting in the above equation indicates a maximum sclk frequency of 1.3mhz. using the max191 with spi, qspi and microwire serial interfaces figure 13 shows interface connections to the max191 for common serial-interface standards. spi and microwire (cpol=0, cpha=0) the max191 is compatible with spi, qspi and microwire serial-interface standards. when using spi or qspi, two modes are available to interface with the max191. you can set cpol = 0 and cpha = 0 (figure 14a), or set cpol = 1 and cpha = 1 (figure 14b). when using cpol = 0 and cpha = 0, the conversion begins on the first falling edge of sclk following cs going low. data is available from dout on the rising edge of sclk, and transitions on the falling edge. two consecutive 1-byte reads are required to get the full 12 bits from the adc. the first byte contains the following, in this order: a leading unknown bit (dout will still be high-impedance on the first bit), a 0, and the six msbs. the second byte contains the remaining six lsbs and two trailing 0s. spi (cpol=1, cpha=1) setting cpol = 1 and cpha = 1 starts the clock high during a read instruction. the max191 will shift out a leading 0 followed by the 12 data bits and three trailing 0s (figure 14b). qspi unlike spi, which requires two 1-byte reads to acquire the 12 bits of data from the adc, qspi allows the mini - mum number of clock cycles required to clock in the data (figure 15). tms320 serial interface figure 13d shows the pin connections to interface the max191 to the tms320. since the max191 makes data available on the rising edge of sclk and the tms320 shifts data in on the falling edge of clkr, use clkx of the dsp to drive sclk, and clkx to drive the dsp? clkr input. the inverter? propagation delay also provides more data-setup time at the dsp. for example, with no inverter delay, and using t 22 = 280ns and f sclk = 1.6mhz, the available setup time before the sclk transition is: setup time = 1/ (2 x f sclk ) - t 22 = 1/ (2 x 1.6e6) - 280ns = 32ns this still exceeds the 13ns minimum dr setup time before the clkr goes low (tsu(dr)), however, a generic 74hc04 provides an additional 20ns setup time (see figure 13d). figure 16 shows the dsp interface timing characteris - tics. the dsp begins clocking data in on the falling edge of clkr after the falling edge of sstrb. low-power , 12-bit sampling adc with inter nal refer ence and power -down 16 ______________________________________________________________________________________ dout leading zero msb d9 d10 d7 d8 d5 d6 d3 d4 d1 d2 lsb cs sclk high-z 1st byte read 2nd byte read high-z a. cpol = 0, cpha = 0 dout leading zero msb d9 d10 d7 d8 d5 d6 d3 d4 d1 d2 lsb cs sclk high-z high-z b. cpol = 1, cpha = 1 figure 14. spi/microwire serial-interface timing
max191 low-power , 12-bit sampling adc with inter nal refer ence and power -down ______________________________________________________________________________________ 17 dout msb d9 d10 d7 d8 d5 d6 d3 d4 d1 d2 lsb cs sclk high-z high-z a. cpol = 0, cpha = 0 dout msb d9 d10 d7 d8 d5 d6 d3 d4 d1 d2 lsb cs sclk high-z high-z b. cpol = 1, cpha = 1 figure 15. qspi serial-interface timing dout msb d9 d10 d7 d8 d5 d6 d3 d4 d1 d2 lsb cs high-z high-z clkr sstrb sclk high-z high-z figure 16. tms320 interface timing
max191 following the data transfer, the dsp receive shift regis - ter (rsr) contains a 16-bit word consisting of the 12 data bits, msb first, followed by four trailing 0s. applications infor mation power-on initialization when the +5v power supply is first applied to the max191, perform a single conversion to initialize the adc (the busy signal status is undefined at power-on). disregard the data outputs. power-down mode in some battery-powered systems, it is desirable to power down or remove power from the adc during inactive periods. to power down the max191, drive pd low. in this mode, all internal adc circuitry is off except the reference, and the adc consumes less than 50 a max (assuming all signals cs , rd , clk, and hben are static and within 200mv of the supplies). figure 17 shows a practical way to drive the pd pin. if using inter - nal reference compensation, drive pd between v dd and dgnd with a p i/o pin or other logic device (figure 17a). for external-reference compensation mode, use the circuit in figure 17b to drive pd between dgnd and the floating voltage of pd . an alternative is to drive pd with three-state logic or a switch, provided the off leakage does not exceed 100na. internal reference the internal 4.096v reference is available at vref and must be bypassed to agnd with a 4.7 f low-esr capacitor (less than 1/2 ) in parallel with a 0.1 f capaci - tor, unless internal-reference compensation mode is used (see the internal reference compensation section). this minimizes noise and maintains a low reference impedance at high frequencies. the reference output can be disabled by connecting refadj to v dd when using an external reference. reference-compensation modes power-down performance can be optimized for a given conversion rate by selecting either internal or external reference compensation. internal compensation the connection for internal compensation is shown in figure 18a. in this mode, the reference stabilizes quick - ly enough so that a conversion typically starts within 35 s after the adc is reactivated ( pd pulled high). in this compensation mode, the reference buffer requires longer recovery time from sar transients, therefore requiring a slower clock (and conversion time). with internal reference compensation, the typical conversion time rises to 25 s (figure 18b). figure 18c illustrates the typical average supply current vs. conversion rate, low-power , 12-bit sampling adc with inter nal refer ence and power -down 18 ______________________________________________________________________________________ max191 max191 a. internal-reference compensation mode b. external-reference compensation mode pd 1 1 pd open-drain buffer figure 17. drive circuits for pd pin max191 +5v pd vref refadj 0.1 m f 1 5 6 figure 18a. internal-compensation mode circuit
which can be achieved using power-down between conversions. external compensation figure 19a shows the connection for external compensa - tion with reference adjustment. in this mode, an external 4.7 f capacitor compensates the reference output amplifier, allowing for maximum conversion speed and lowest conversion noise. however, when reactivating the adc after power-down, the reference takes typically 2ms to fully charge the 4.7 f capacitor, so more time is required before a conversion can start (figure 19b). thus, the average current consumed in power-up/power- down operations is higher in external compensation mode than in internal compensation mode. gain and offset adjustment figure 20 depicts the nominal, unipolar input/output (i/o) transfer function, and figure 22 shows the bipolar i/o transfer function. code transitions occur halfway between successive integer lsb values. note that 1lsb = 1.00mv (4.096v/4096) for unipolar operation and 1lsb = 1.00mv ((4.096v/2 - -4.096v/2)/4096) for bipolar operation. figures 19a and 21a show how to adjust the adc gain in applications that require full-scale range adjustment. the connection shown in figure 21a provides 0.5% for 20lsbs of adjustment range and is recommended for applications that use an external reference. on the other hand, figure 19a is recommended for applica - tions that use the internal reference, because it uses fewer external components. if both offset and full scale need adjustment, the circuit in figure 21b is recommended. for single-supply adcs, it is virtually impossible to null system negative offset errors. however, the max191 input configuration is pseudo-differential?nly the difference in voltage between ain+ and ain- will be converted into its digital representation. by applying a small positive voltage to ain-, the 0 input voltage at ain+ can be adjusted to above or below ain- voltage, thus nulling positive or negative system offset errors. r9 and r10 can be removed for applications that require only positive sys - tem errors to be nulled. to trim the offset error of the max191, apply 1/2lsb to the analog input and adjust r6 so the digital output code changes between 000 (hex) and 001 (hex). to adjust full scale, apply fs - 1 1/2lsbs and adjust r2 until the output code changes max191 low-power , 12-bit sampling adc with inter nal refer ence and power -down ______________________________________________________________________________________ 19 25 m s rd 0 1 pd 20 m s 15 m s vref figure 18b. low average-power mode operation (internal compensation) 10,000 10 10 100 1000 fg18c conversions per second supply current ( m a) 50 200 1k 5k 20k 100k figure 18c. average supply current vs. conversion rate, powering down between conversions max191 vref refadj pd 1 5 6 0.1 m f 4.7 m f 5k 11k 15k 100k 0.01 m f figure 19a. external-compensation mode with internal reference adjustment circuit
max191 between ffe (hex) and fff (hex). because interaction occurs between adjustments, offset should be adjusted before gain. for an input gain of two, remove r7 and r8. the max191 accepts input voltages from agnd to v dd while operating from a single supply, and v ss to v dd when operating from dual supplies. figure 22 shows the bipolar input transfer function with ain- connected to midscale for single-supply operation and connected to gnd operating from dual supplies. when operating from a single supply, the max191 can be configured for bipolar operation on its pseudo-differential input. instead of using ain- as an analog input return, ain- can be set to a different positive potential voltage above ground (bip pin is set high). the sampled ana - log input (ain+) can swing to any positive voltage above and below ain-, and the adc performs bipolar conversions with respect to ain-. when operating from dual supplies, the max191 full-scale range is from -v ref /2 to +v ref /2. digital bus noise if the data bus connected to the adc is active during a conversion, crosstalk from the data pins to the adc comparator may generate errors. slow-memory mode avoids this problem by placing the p in a wait state during the conversion. in rom mode, if the data bus is active during the conversion, it should be isolated from the adc using three-state drivers. the adc generates considerable digital noise in rom mode when rd or cs go high and the output data dri - vers are disabled after a conversion has started. this noise can cause large errors if it occurs when the sar latches a comparator decision. to avoid this problem, rd and cs should be active for less than one clock cycle. if this is not possible, rd or cs should go high at the rising edge of clk, since the comparator output is always latched on falling edges of clk. layout, grounding, bypassing use printed circuit boards for best system performance. low-power , 12-bit sampling adc with inter nal refer ence and power -down 20 ______________________________________________________________________________________ rd 0 open circuit (float) pd 12.5 m s 2ms vref 200ms figure 19b. low average-power mode operation (external compensation) 11 . . . 111 11 . . . 110 11 . . . 101 00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 0 1 2 3 fs fs?lsb output code full-scale transition fs = vref 1lsb = 4096 fs ain input voltage (lsb) figure 20. unipolar transfer function v in r3 10k r1 100 w r2 49.9 w r4 10k to ain+ max480 figure 21a. trim circuit for gain ( 0.5%)
wire-wrap boards are not recommended. board layout should ensure that digital- and analog-signal lines are separated from each other. do not run analog and digi - tal (especially clock) lines parallel to one another, or digital lines underneath the adc package. figure 23 shows the recommended system ground connections. establish a single-point ground (?tar ground point) at agnd, separate from the logic ground. connect all other analog grounds and dgnd to it. no other digital-system ground should be con - nected to this single-point analog ground. the ground return to the power supply for this star ground should be low impedan ce and as short as possible for noise- free operation. high-frequency noise in the v dd power supply may affect the high-speed comparator in the adc. bypass these supplies to the single-point analog ground with max191 low-power , 12-bit sampling adc with inter nal refer ence and power -down ______________________________________________________________________________________ 21 max191 ain + ain - d0?11 v in r7 10k r8 10k vref r6 10k r5 10k r1 10k r2 100 w r3 10k r4 49.9 w vref r9* 20k 0.1 m f* r10* 49.9 w * connect ain- to agnd when using dual supplies max480 figure 21b. offset ( 10mv) and gain ( 1%) trim circuit 01 . . . 111 01 . . . 110 00 . . . 010 00 . . . 001 11 . . . 111 11 . . . 110 00 . . . 000 10 . . . 001 10 . . . 000 11 . . . 101 0v vref - 1lsb vref 2 0v single supply vref ain- = 2 ( ) dual supply ain- = 0v vref - 1lsb 2 -vref 2 figure 22. bipolar transfer function supplies +5v -5v gnd v dd agnd v ss dgnd +5v dgnd r* = 10 w digital circuitry *optional max191 figure 23. power-supply grounding connection
max191 0.01 f and 10 f bypass capacitors. minimize capaci - tor lead lengths for best supply-noise rejection. if the +5v power supply is very noisy, a 10 resistor can be connected as a lowpass filter to filter out supply noise (figure 23). _____________ dynamic per for mance high-speed sampling capability and throughput make the max191 ideal for wideband signal processing. to support these and other related applications, fast fourier transform (fft) test techniques guarantee the adc's dynamic frequency response, distortion, and noise at the rated throughput. specifically, this involves applying a low-distortion sine wave to the adc input and recording the digital conversion results for a speci - fied time. the data is then analyzed using an fft algo - rithm, which determines its spectral content. conversion errors are then seen as spectral elements outside the fundamental input frequency. fft plots are shown in the typical operating characteristics . adcs have traditionally been evaluated by specifica - tions such as zero and full-scale error, integral nonlin - earity (inl), and differential nonlinearity (dnl). such parameters are widely accepted for specifying perfor - mance with dc and slowly varying signals, but are less useful in signal-processing applications where the adc? impact on the system transfer function is the main concern. the significance of various dc errors does not translate well to the dynamic case, so different tests are required. signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other a/d output signals, except signal harmonics. signal-to-noise + distortion ratio (sinad) is the same as the snr, but includes sig - nal harmonics. the theoretical minimum a/d noise is caused by quan - tization error and is a direct result of the adc? resolu - tion: snr = (6.02n + 1.76) db, where n is the number of bits of resolution. 74db is the snr of a perfect 12-bit adc. by transposing the equation that converts resolution to snr we can compute the effective resolution or the ?ffective number of bits?the adc provides from the measured snr: n = (snr 1.76)/6.02 total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal (in the frequen - cy band above dc and below one-half the sample rate) to the fundamental itself. this expressed as: thd = 20log [ (v 2 2 + v 3 2 + v 4 2 + v 5 2 + . . . + v n 2 ) /v 1 ] where v 1 is the fundamental rms amplitude and v 2 to v n are the amplitudes of the 2nd through n th harmonics. spurious-free dynamic range spurious-free dynamic range is the ratio of the funda - mental rms amplitude to the amplitude of the next largest spectral component (in the frequency band above dc and below one-half the sample rate). usually this peak occurs at some harmonic of the input fre - quency. but if the adc is exceptionally linear, it can occur at a random peak in the adc? noise floor. opto-isolated a/d interface many industrial applications require isolation to prevent excessive current flow where ground disparities exist between the adc and the rest of the system. in figure 24, a max250 and four 6n136 opto-couplers create an low-power , 12-bit sampling adc with inter nal refer ence and power -down 22 ______________________________________________________________________________________
max191 low-power , 12-bit sampling adc with inter nal refer ence and power -down ______________________________________________________________________________________ 23 en gnd 9 12 4 1 5 ttl/cmos outputs ttl/cmos inputs 11 3 6 10 d1 v cc d2 2 14 13 5v 1k 1k 1k 1k 1 2 4 3 t 1 602117970 (schott) 8 7 6 5 ic 3 isolation barrier 5 8 7 ic 2 1 2 4 3 8 7 6 1k 1k 1k 1k 1k 1k q 1 2n3906 q 2 2n3906 in out gnd 100 m f 16v 5v 100 m f 6v 24 ain+ ain- hben rd par bip agnd v in 18 16 20 23 5 6 4.7 m f 0.1 m f 0.1 m f 2 12 refadj v ss dgnd vref cs sstrb dout v dd 3 4 21 19 22 8 7 0.1 m f ic 4 74l05 ic 5 max191 ic 1 max250 shdn clk ic 2-3 hcpl2630 (quality technologies) figure 24. isolated data-acquisition circuit
max191 low-power , 12-bit sampling adc with inter nal refer ence and power -down 24 ______________________________________________________________________________________ ___________________ chip t opography hben bip vref refadj agnd 0.198" (5.0292mm) 0.142" (3.6065mm) busy d0/d8 d1/d9 dgnd d3/d11 d4 d5/sstrb d2/d10 cs rd d7/dout d6/sclk out ain- ain+ agnd pd v dd clk/sclk par ________________________________________________________ package infor mation substrate connected to v dd pdipn.eps

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