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150 ma, low dropout, cmos linear regulator ADP1710/adp1711 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features maximum output current: 150 ma input voltage range: 2.5 v to 5.5 v light load efficient i gnd = 35 a with zero load i gnd = 40 a with 100 a load low shutdown current: <1 a low dropout voltage: 150 mv @ 150 ma load initial accuracy: 1% accuracy over line, load, and temperature: 2% stable with small 1f ceramic output capacitor 16 fixed output voltage options: 0.75 v to 3.3 v (ADP1710) adjustable output voltage option: 0.8 v to 5.0 v (ADP1710 adjustable) 16 fixed output voltage options with reference bypass: 0.75 v to 3.3 v (adp1711) high psrr: 69 db @ 1 khz low noise: 40 v rms excellent load/line transient response current limit and thermal overload protection logic controlled enable 5-lead tsot package applications mobile phones digital camera and audio devices portable and battery-powered equipment post dc-dc regulation typical application circuits in gnd en out nc 1 2 3 5 4 ADP1710 nc = no connect 1f 1f v in = 5v v out = 3.3v 06310-001 figure 1. ADP1710 with fixed output voltage, 3.3 v in gnd en out adj 1 2 3 5 4 a dp1710 adjustable 1f 1f v in = 5.5v r1 r2 v out = 0.8v(1 + r1/r2) 06310-002 figure 2. ADP1710 with adjustable output voltage, 0.8 v to 5.0 v in gnd en out byp 1 2 3 5 4 adp1711 1f 1f 10nf v in = 5v v out = 3.3v 0 6310-003 figure 3. adp1711 with fixed output voltage and bypass capacitor, 3.3 v general description the ADP1710/adp1711 are low dropout linear regulators that operate from 2.5 v to 5.5 v and provide up to 150 ma of output current. utilizing a novel scaling architecture, ground current drawn is a very low 40 a, when driving a 100 a load, making the ADP1710/adp1711 ideal for battery- operated portable equipment. the ADP1710 and the adp1711 are each available in sixteen fixed output voltage options. the ADP1710 is also available in an adjustable version, which allows output voltages that range from 0.8 v to 5 v via an external divider. the adp1711 allows for a reference bypass capacitor to be connected, which reduces output voltage noise and improves power supply rejection. the ADP1710/adp1711 are optimized for stable operation with small 1 f ceramic output capacitors, allowing for good transient performance while occupying minimal board space. an enable pin controls the output voltage on both devices. there is also an under-voltage lockout circuit on both devices, which disables the regulator if in drops below a minimum threshold. an internal soft start gives a typical start-up time of 80 s. short-circuit protection and thermal overload protection circuits prevent damage to the devices in adverse conditions. both the ADP1710 and the adp1711 are available in tiny 5-lead tsot packages, for the smallest footprint solution to all your power needs.
ADP1710/adp1711 rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical application circuits ............................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 4 thermal resistance ...................................................................... 4 esd caution .................................................................................. 4 pin configurations and function descriptions ........................... 5 typical performance characteristics ............................................. 6 theory of operation ........................................................................ 8 adjustable output voltage (ADP1710 adjustable) ................. 8 bypass capacitor (adp1711) ..................................................... 8 enable feature ...............................................................................8 undervoltage lockout (uvlo) ..................................................9 application information ................................................................ 10 capacitor selection .................................................................... 10 current limit and thermal overload protection ................. 10 thermal considerations ............................................................ 11 printed circuit board layout considerations ....................... 12 outline dimensions ....................................................................... 13 ordering guide .......................................................................... 14 revision history 10/06revision 0: initial version
ADP1710/adp1711 rev. 0 | page 3 of 16 specifications v in = (v out + 0.5 v) or 2.5 v (whichever is greater), i out = 1 ma, c in = c out = 1 f, t a = 25c, unless otherwise noted. table 1. parameter symbol conditions min typ max unit input voltage range v in t j = C40c to +125c 2.5 5.5 v operating supply current i gnd i out = 0 a 35 a i out = 0 a, t j = C40c to +125c 50 a i out = 100 a 40 a i out = 100 a, t j = C40c to +125c 80 a i out = 100 ma 665 a i out = 100 ma, t j = C40c to +125c 860 a i out = 150 ma 1 ma i out = 150 ma, t j = C40c to +125c 1.3 ma shutdown current i gnd-sd en = gnd 0.1 a en = gnd, t j = C40c to +125c 1.0 a fixed output voltage accuracy v out i out = 1 ma C1 +1 % (ADP1710 and adp1711) 100 a < i out < 150 ma, t j = C40c to +125c C2 +2 % adjustable output voltage v out i out = 1 ma 0.792 0.8 0.808 v accuracy (ADP1710 adjustable) 1 100 a < i out < 150 ma, t j = C40c to +125c 0.784 0.816 v line regulation ?v out /?v in v in = (v out + 0.5 v) to 5.5 v, t j = C40c to +125c C0.1 +0.1 %/ v load regulation 2 ?v out /?i out i out = 10 ma to 150 ma 0.002 %/ma i out = 10 ma to 150 ma, t j = C40c to +125c 0.004 %/ma dropout voltage 3 v dropout i out = 100 ma, v out 3.0 v 100 mv i out = 100 ma, v out 3.0 v, t j = C40c to +125c 175 mv i out = 150 ma, v out 3.0 v 150 mv i out = 150 ma, v out 3.0 v, t j = C40c to +125c 250 mv i out = 100 ma, 2.5 v v out < 3.0 v 120 mv i out = 100 ma, 2.5 v v out < 3.0 v, t j = C40c to +125c 200 mv i out = 150 ma, 2.5 v v out < 3.0 v 180 mv i out = 150 ma, 2.5 v v out < 3.0 v, t j = C40c to +125c 300 mv start-up time 4 t start-up ADP1710 80 s adp1711 with 10 nf bypass capacitor 100 s current limit threshold 5 i limit 180 270 360 ma thermal shutdown threshold ts sd t j rising 150 c thermal shutdown hysteresis ts sd-hys 15 c uvlo active threshold uvlo active v in falling 1.95 v uvlo inactive threshold uvlo inactive v in rising 2.45 v uvlo hysteresis uvlo hys 250 mv en input logic high v ih 2.5 v v in 5.5 v 1.8 v en input logic low v il 2.5 v v in 5.5 v 0.4 v en input leakage current v i-leakage en = in or gnd 0.1 1 a adj input bias current (ADP1710 adjustable) adj i-bias 30 100 na output noise out noise ADP1710 10 hz to 100 khz, v out = 3.3 v 330 vrms adp1711 10 hz to 100 khz, v out = 0.75 v, with 10 nf bypass capacitor 40 vrms power supply rejection ratio psrr ADP1710 1 khz, v out = 3.3 v 58 db adp1711 1 khz, v out = 0.75 v, with 10 nf bypass capacitor 69 db 1 accuracy when out is connected directly to adj. when out voltage is set by external feedback resistors, absolute accuracy in a djust mode depends on the tolerances of resistors used. 2 based on an en d-point calculation using 10 ma and 150 ma loads. see figure 8 for typical lo ad regulation performance for loads less than 10 ma. 3 dropout voltage is defined as the input-to-output voltage differe ntial when the input voltage is set to the nominal output vol tage. this applies only for output voltages above 2.5 v. 4 start-up time is defined as the time between the rising edge of en to out being at 90% of its nominal value. 5 current limit threshold is defi ned as the current at which the output voltage dr ops to 90% of the specif ied typical value. for example, the current limit for a 1.0 v output voltage is defined as the curre nt that causes the output voltage to drop to 90% of 1.0 v, or 0.9 v.
ADP1710/adp1711 rev. 0 | page 4 of 16 absolute maximum ratings table 2. parameter rating in to gnd C0.3 v to +6 v out to gnd C0.3 v to in en to gnd C0.3 v to +6 v adj/byp to gnd C0.3 v to +6 v storage temperature range C65c to +150c operating junction temperature range C40c to +125c soldering conditions jedec j-std-020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja unit 5-lead tsot 170 c/w esd caution
ADP1710/adp1711 rev. 0 | page 5 of 16 pin configurations and function descriptions in g nd en out nc 1 2 3 5 4 nc = no connect ADP1710 fixed top view (not to scale) 06310-004 in g nd en out adj 1 2 3 5 4 ADP1710 adjustable top view (not to scale) 06310-005 in gnd en out byp 1 2 3 5 4 adp1711 top view (not to scale) 06310-006 figure 4. 5-lead tsot (uj-suffix) figure 5. 5-lead tsot (uj-suffix) figure 6. 5-lead tsot (uj-suffix) table 4. pin function descriptions ADP1710 fixed pin no. ADP1710 adjustable pin no. adp1711 pin no. mnemonic description 1 1 1 in regulator input supply. bypass in to gnd with a 1 f or greater capacitor. 2 2 2 gnd ground. 3 3 3 en enable input. drive en high to turn on th e regulator; drive it low to turn off the regulator. for automatic startup, connect en to in. 4 nc no connect. 4 adj adjust. a resistor divider from out to adj sets the output voltage. 4 byp connect a 1 nf or greater capacitor (10 nf is recommended) between byp and gnd to reduce the internal reference noise for low noise applications. 5 5 5 out regulated output voltage. bypass out to gnd with a 1 f or greater capacitor.
ADP1710/adp1711 rev. 0 | page 6 of 16 typical performance characteristics v in = 3.8 v, i out = 1 ma, c in = c out = 1 f, t a = 25c, unless otherwise noted. 3.34 3.23 ?40 t j (c) v out (v) 3.33 3.32 3.31 3.30 3.29 3.28 3.27 3.26 3.25 3.24 ?5 25 85 125 i load = 150ma i load = 100ma i load = 50ma i load = 100a i load = 1ma i load = 10ma 06310-007 figure 7. output voltage vs. junction temperature 3.32 3.26 0.1 1000 i load (ma) v out (v) 1 10 100 3.31 3.30 3.29 3.28 3.27 06310-008 figure 8. output voltage vs. load current 3.32 3.26 3.3 3.8 4.3 4.8 5.3 v in (v) v out (v) 3.31 3.30 3.29 3.28 3.27 i load = 150ma i load = 100ma i load = 50ma i load = 10ma i load = 1ma i load = 100a 06310-009 figure 9. output volt age vs. input voltage 1100 0 ?40 t j (c) i gnd (a) 1000 900 800 700 600 500 400 300 200 100 ?5 25 85 125 i load = 100a i load = 1ma i load = 10ma i load = 50ma i load = 100ma i load = 150ma 06310-010 figure 10. ground current vs. junction temperature 1100 0 0.1 i load (ma) i gnd (a) 1000 900 800 700 600 500 400 300 200 100 1000 11 01 0 0 06310-011 figure 11. ground current vs. load current 1500 0 3.3 3.8 4.3 4.8 5.3 v in (v) i gnd (a) 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 i load = 150ma i load = 100ma i load = 50ma i load = 10ma i load = 1ma i load = 100a 06310-012 figure 12. ground current vs. input voltage
ADP1710/adp1711 rev. 0 | page 7 of 16 180 0 0.1 1000 i load (ma) v dropout (mv) 1 10 100 160 140 120 100 80 60 40 20 06310-013 figure 13. dropout voltage vs. load current 3.35 2.95 3.2 3.6 v in (v) v out (v) 3.30 3.25 3.20 3.15 3.10 3.05 3.00 3.3 3.4 3.5 i load = 100a i load = 1ma i load = 10ma i load = 50ma i load = 100ma i load = 150ma 06310-014 figure 14. output voltage vs. input voltage (in dropout) 7 0 3.20 3.60 v in (v) i gnd (ma) 6 5 4 3 2 1 3.25 3.30 3.35 3.40 3.45 3.50 3.55 i load = 100a i load = 1ma i load = 10ma i load = 150ma i load = 100ma i load = 50ma 06310-015 figure 15. ground current vs. input voltage (in dropout) 0 10 10m frequency (hz) psrr (db) 100 1k 10k 100k 1m ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 v ripple = 50mv v in = 5v v out = 0.75v c out = 1f i load = 50ma i load = 10ma i load = 100a 06310-016 figure 16. adp1711 power supply rejection ratio vs. frequency (10 nf bypass capacitor) 0 10 10m frequency (hz) psrr (db) 100 1k 10k 100k 1m ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 v ripple = 50mv v in = 5v v out = 3.3v c out = 1f i load = 100a i load = 50ma i load = 10ma 06310-017 figure 17. ADP1710 power supply rejection ratio vs. frequency
ADP1710/adp1711 rev. 0 | page 8 of 16 theory of operation the ADP1710/adp1711 are low dropout, cmos linear regulators that use an advanced, proprietary architecture to provide high power supply rejection ratio (psrr) and excellent line and load transient response with just a small 1 f ceramic output capacitor. both devices operate from a 2.5 v to 5.5 v input rail and provide up to 150 ma of output current. incorporating a novel scaling architecture, ground current is very low when driving light loads. ground current in shutdown mode is typically 100 na. reference current limit thermal protect shutdown and uvlo gnd out nc/ a dj/ byp nc = no connect in en 06310-018 + figure 18. internal block diagram internally, the ADP1710/adp1711 each consist of a reference, an error amplifier, a feedback voltage divider, and a pmos pass transistor. output current is delivered via the pmos pass device, which is controlled by the error amplifier. the error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. if the feedback voltage is lower than the reference voltage, the gate of the pmos device is pulled lower, allowing more current to pass and increasing the output voltage. if the feedback voltage is higher than the reference voltage, the gate of the pmos device is pulled higher, allowing less current to pass and decreasing the output voltage. the ADP1710 is available in two versions, one with fixed output voltage options and one with an adjustable output voltage. the fixed output voltage option is set internally to one of sixteen values between 0.75 v and 3.3 v, using an internal feedback network. the adjustable output voltage can be set to between 0.8 v and 5.0 v by an external voltage divider connected from out to adj. the adp1711 is available with fixed output voltage options and features a bypass pin, which allows an external capacitor to be connected, which reduces internal reference noise. all devices are controlled by an enable pin (en). adjustable output voltage (ADP1710 adjustable) the ADP1710 adjustable version can have its output voltage set over a 0.8 v to 5.0 v range. the output voltage is set by connecting a resistive voltage divider from out to adj. the output voltage is calculated using the equation v out = 0.8 v (1 + r1 / r2 ) (1) where: r1 is the resistor from out to adj. r2 is the resistor from adj to gnd. the maximum bias current into adj is 100 na, so for less than 0.5% error due to the bias current, use values less than 60 k for r2. bypass capacitor (adp1711) the adp1711 allows for an external bypass capacitor to be connected to the internal reference, which reduces output voltage noise and improves power supply rejection. a low leakage capacitor of 1 nf or greater (10 nf is recommended) must be connected between the byp and gnd pins. enable feature the ADP1710/adp1711 use the en pin to enable and disable the out pin under normal operating conditions. as shown in figure 19, when a rising voltage on en crosses the active threshold, out turns on. when a falling voltage on en crosses the inactive threshold, out turns off. 2 en out v in = 5v v out = 1.6v c in = 1f c out = 1f i load = 10ma time (1ms/div) ch1, ch2 (500mv/div) 06310-019 figure 19. ADP1710 adjustable typical en pin operation
ADP1710/adp1711 rev. 0 | page 9 of 16 as can be seen, the en pin has hysteresis built in. this prevents on/off oscillations that can occur due to noise on the en pin as it passes through the threshold points. the en pin active/inactive thresholds are derived from the in voltage. therefore, these thresholds vary with changing input voltage. figure 20 shows typical en active/inactive thresholds when the input voltage varies from 2.5 v to 5.5 v. 1.4 0.5 2.50 5.50 v in (v) typical en thresholds (v) 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 en inactive en active hysteresis 06310-020 figure 20. typical en pin thresholds vs. input voltage undervoltage lockout (uvlo) the ADP1710/adp1711 have an undervoltage lockout circuit, which monitors the voltage on the in pin. when the voltage on in drops below 1.95 v (minimum), the circuit activates, disabling the out pin.
ADP1710/adp1711 rev. 0 | page 10 of 16 application information capacitor selection output capacitor the ADP1710/adp1711 are designed for operation with small, space-saving ceramic capacitors, but they will function with most commonly used capacitors as long as care is taken about the effective series resistance (esr) value. the esr of the output capacitor affects stability of the ldo control loop. a minimum of 1 f capacitance with an esr of 500 m or less is recommended to ensure stability of the ADP1710/adp1711. transient response to changes in load current is also affected by output capacitance. using a larger value of output capacitance improves the transient response of the ADP1710/adp1711 to large changes in load current. figure 21 and figure 22 show the transient responses for output capacitance values of 1 f and 22 f, respectively. v in = 5v v out = 3.3v c in = 1f c out = 1f time (4s/div) 1 10mv/di v v out response to load step from 7.5ma to 142.5ma 06310-021 figure 21. output transient response, c out = 1 f v in = 5v v out = 3.3v c in = 22f c out = 22f time (4s/div) 1 10mv/di v v out response to load step from 7.5ma to 142.5ma 06310-022 figure 22. output transient response, c out = 22 f input bypass capacitor connecting a 1 f capacitor from in to gnd reduces the circuit sensitivity to printed circuit board (pcb) layout, especially when long input traces or high source impedance are encountered. if greater than 1 f of output capacitance is required, the input capacitor should be increased to match it. input and output capacitor properties any good quality ceramic capacitors can be used with the ADP1710/adp1711, as long as they meet the minimum capacitance and maximum esr requirements. ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recommended. y5v and z5u dielectrics are not recommended, due to their poor temperature and dc bias characteristics. current limit and thermal overload protection the ADP1710/adp1711 are protected against damage due to excessive power dissipation by current and thermal overload protection circuits. the ADP1710/adp1711 are designed to current limit when the output load reaches 270 ma (typical). when the output load exceeds 270 ma, the output voltage is reduced to maintain a constant current limit. thermal overload protection is included, which limits the junction temperature to a maximum of 150c (typical). under extreme conditions (that is, high ambient temperature and power dissipation) when the junction temperature starts to rise above 150c, the output is turned off, reducing the output current to zero. when the junction temperature drops below 135c, the output is turned on again and output current is restored to its nominal value. consider the case where a hard short from out to ground occurs. at first the ADP1710/adp1711 current limits, so that only 270 ma is conducted into the short. if self heating of the junction is great enough to cause its temperature to rise above 150c, thermal shutdown activates, turning off the output and reducing the output current to zero. as the junction temperature cools and drops below 135c, the output turns on and conducts 270 ma into the short, again causing the junction temperature to rise above 150c. this thermal oscillation between 135c and 150c causes a current oscillation between 270 ma and 0 ma, which continues as long as the short remains at the output.
ADP1710/adp1711 rev. 0 | page 11 of 16 current and thermal limit protections are intended to protect the device against accidental overload conditions. for reliable operation, device power dissipation must be externally limited so junction temperatures do not exceed 125c. thermal considerations to guarantee reliable operation, the junction temperature of the ADP1710/adp1711 must not exceed 125c. to ensure the junction temperature stays below this maximum value, the user needs to be aware of the parameters that contribute to junction temperature changes. these parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air ( ja ). the ja number is dependent on the package assembly compounds used and the amount of copper to which the gnd pins of the package are soldered on the pcb. table 5 shows typical ja values of the 5-lead tsot package for various pcb copper sizes. table 5. copper size (mm 2 ) ja (c/w) 0 1 170 50 152 100 146 300 134 500 131 1 device soldered to minimum size pin traces. the junction temperature of the ADP1710/adp1711 can be calculated from the following equation: t j = t a + ( p d ja ) (2) where: t a is the ambient temperature. p d is the power dissipation in the die, given by p d = [( v in C v out ) i load ] + ( v in i gnd ) (3) where: i load is the load current. i gnd is the ground current. v in and v out are the input voltage and output voltage, respectively. power dissipation due to ground current is quite small and can be ignored. therefore, the junction temperature equation simplifies to the following: t j = t a + {[( v in C v out ) i load ] ja } (4) as shown in equation 4, for a given ambient temperature, input to output voltage differential, and continuous load current, there exists a minimum copper size requirement for the pcb to ensure the junction temperature does not rise above 125c. the following figures show junction temperature calculations for different ambient temperatures, load currents, v in to v out differentials, and areas of pcb copper. 140 0 0.5 5.0 v in ? v out (v) t j (c) 120 100 80 60 40 20 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 1ma 10ma 30ma 80ma 100ma 125ma 150ma (load current) max t j (do not operate above this point) 06310-023 figure 23. 500 mm 2 of pcb copper, t a = 25c 140 0 0.5 5.0 v in ? v out (v) t j (c) 120 100 80 60 40 20 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 1ma 10ma 30ma 80ma 100ma 125ma 150ma (load current) max t j (do not operate above this point) 06310-024 figure 24. 100 mm 2 of pcb copper, t a = 25c 140 0 0.5 5.0 v in ? v out (v) t j (c) 120 100 80 60 40 20 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 1ma 10ma 30ma 80ma 100ma 125ma 150ma (load current) max t j (do not operate above this point) 06310-025 figure 25. 0 mm 2 of pcb copper, t a = 25c
ADP1710/adp1711 rev. 0 | page 12 of 16 140 0 0.5 5.0 v in ? v out (v) t j (c) 120 100 80 60 40 20 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 1ma 10ma 30ma 80ma 100ma 125ma 150ma (load current) max t j (do not operate above this point) 06310-026 figure 26. 500 mm 2 of pcb copper, t a = 50c 140 0 0.5 5.0 v in ? v out (v) t j (c) 120 100 80 60 40 20 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 1ma 10ma 30ma 80ma 100ma 125ma 150ma (load current) max t j (do not operate above this point) 06310-027 figure 27. 100 mm 2 of pcb copper, t a = 50c 140 0 0.5 5.0 v in ? v out (v) t j (c) 120 100 80 60 40 20 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 1ma 10ma 30ma 80ma 100ma 125ma 150ma (load current) max t j (do not operate above this point) 06310-028 figure 28. 0 mm 2 of pcb copper, t a = 50c printed circuit board layout considerations heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the ADP1710/ adp1711. however, as can be seen from table 5 , a point of diminishing returns eventually is reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. place the input capacitor as close as possible to the in and gnd pins. place the output capacitor as close as possible to the out and gnd pins. for adp1711, place the internal reference bypass capacitor as close as possible to the byp pin. use of 0402 or 0603 size capacitors and resistors achieves the smallest possible footprint solution on boards where area is limited. gnd (bottom) gnd (top) ADP1710/ adp1711 in en r2 r1 c3 out c2 c1 06310-029 figure 29. example pcb layout
ADP1710/adp1711 rev. 0 | page 13 of 16 outline dimensions * compliant to jedec standards mo-193-ab with the exception of package height and thickness. pin 1 1.60 bsc 2.80 bsc 1.90 bsc 0.95 bsc 0.20 0.08 0.60 0.45 0.30 8 4 0 0.50 0.30 0.10 max seating plane * 1.00 max * 0.90 0.87 0.84 2.90 bsc 54 12 3 figure 30. 5-lead thin small outline transistor package [tsot] (uj-5) dimensions show in millimeters
ADP1710/adp1711 rev. 0 | page 14 of 16 ordering guide model temperature range output voltage (v) package description package option branding ADP1710aujz-0.75r7 1 C40c to +125c 0.75 5-lead tsot uj-5 l4s ADP1710aujz-0.8-r7 1 C40c to +125c 0.80 5-lead tsot uj-5 l0d ADP1710aujz-0.85r7 1 C40c to +125c 0.85 5-lead tsot uj-5 l40 ADP1710aujz-0.9-r7 1 C40c to +125c 0.90 5-lead tsot uj-5 l41 ADP1710aujz-0.95r7 1 C40c to +125c 0.95 5-lead tsot uj-5 l42 ADP1710aujz-1.0-r7 1 C40c to +125c 1.00 5-lead tsot uj-5 l0e ADP1710aujz-1.05r7 1 C40c to +125c 1.05 5-lead tsot uj-5 l43 ADP1710aujz-1.10r7 1 C40c to +125c 1.10 5-lead tsot uj-5 l47 ADP1710aujz-1.15r7 1 C40c to +125c 1.15 5-lead tsot uj-5 l44 ADP1710aujz-1.2-r7 1 C40c to +125c 1.20 5-lead tsot uj-5 l45 ADP1710aujz-1.3-r7 1 C40c to +125c 1.30 5-lead tsot uj-5 l46 ADP1710aujz-1.5-r7 1 C40c to +125c 1.50 5-lead tsot uj-5 l0f ADP1710aujz-1.8-r7 1 C40c to +125c 1.80 5-lead tsot uj-5 l0g ADP1710aujz-2.5-r7 1 C40c to +125c 2.50 5-lead tsot uj-5 l0h ADP1710aujz-3.0-r7 1 C40c to +125c 3.00 5-lead tsot uj-5 l0j ADP1710aujz-3.3-r7 1 C40c to +125c 3.30 5-lead tsot uj-5 l0k ADP1710aujz-r7 1 C40c to +125c 0.8 to 5.0 5-lead tsot uj-5 l0l adp1711aujz-0.75r7 1 C40c to +125c 0.75 5-lead tsot uj-5 l4t adp1711aujz-0.8-r7 1 C40c to +125c 0.80 5-lead tsot uj-5 l0m adp1711aujz-0.85r7 1 C40c to +125c 0.85 5-lead tsot uj-5 l48 adp1711aujz-0.9-r7 1 C40c to +125c 0.90 5-lead tsot uj-5 l49 adp1711aujz-0.95r7 1 C40c to +125c 0.95 5-lead tsot uj-5 l4a adp1711aujz-1.0-r7 1 C40c to +125c 1.00 5-lead tsot uj-5 l0n adp1711aujz-1.05r7 1 C40c to +125c 1.05 5-lead tsot uj-5 l4c adp1711aujz-1.10r7 1 C40c to +125c 1.10 5-lead tsot uj-5 l4g adp1711aujz-1.15r7 1 C40c to +125c 1.15 5-lead tsot uj-5 l4d adp1711aujz-1.2-r7 1 C40c to +125c 1.20 5-lead tsot uj-5 l4e adp1711aujz-1.3-r7 1 C40c to +125c 1.30 5-lead tsot uj-5 l4f adp1711aujz-1.5-r7 1 C40c to +125c 1.50 5-lead tsot uj-5 l0p adp1711aujz-1.8-r7 1 C40c to +125c 1.80 5-lead tsot uj-5 l0q adp1711aujz-2.5-r7 1 C40c to +125c 2.50 5-lead tsot uj-5 l0r adp1711aujz-3.0-r7 1 C40c to +125c 3.00 5-lead tsot uj-5 l0s adp1711aujz-3.3-r7 1 C40c to +125c 3.30 5-lead tsot uj-5 l0u 1 z = pb-free part.
ADP1710/adp1711 rev. 0 | page 15 of 16 notes
ADP1710/adp1711 rev. 0 | page 16 of 16 ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06310-0-10/06(0) notes

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