rev.a 6-2000 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 analog devices, inc., 2000 AD73360 rev. 1 errata document errata document a. this document details the limitations of the cascading option of the AD73360 due to a bug in the current silicon. b. analog devices inc. is committed, through future silicon revisions to continuously improve silicon functionality. analog devices inc. will use its best endeavors to ensure that these future silicon revisions remain compatible with your present software/systems implementing the recommended work-arounds outlined in this document. background the AD73360 has the option of being cascaded allowing additional analog input channels to be easily be added as re- quired. due to a bug in the present silicon there are limitations on how many devices can be cascaded together and is also dependent on the sample rate and serial clock rate used. issue description when a number of AD73360s are cascaded together they each output adc channel data in a time-division multiplexed (tdm) format. for a cascade of n devices with all channels enabled the output sequence read by a dsp or micro-con- troller would be device n ? channel 1, device n-1 - channel 1? device 1 - channel 1, device n - channel 2, device n-1 ? channel 2 ? device 1 ? channel 2?, ?, device n ? channel 6, device n-1 ? channel6 ?, device 1 ? channel 6 as each device is programmed with the number of devices in the cascade it should therefore allow sufficient sclks for all other devices to transmit the adc result of one channel before starting to transmit the next. for example in a cascade of two devices, device 1 will transmit its channel 1 result to device 2 in 16 sclk cycles. at the same time device 2 is transmitting its channel 1 result to the dsp or microcontroller. device 1 will then allow 16 sclks, when it does not transmit anything, allowing device 2 to transmit the channel 1 data from device 1 to the dsp. an additional sclk cycle is added to allow the next channels data to begin being transmitted on the falling edge of the sdofs pulse. figure 1 shows the timing for a two device cascade. 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 device 2 - channel 1 device 1 - channel 1 12 3 4 5 6 78 device 2 - channel 2 figure 1. cascade timing for a two-device cascade for cascades of more than two devices the AD73360 will leave too many sclks between transmitting channel information. this increases the time it takes to transmit the adc data and since a dsp or microcontroller must read data from all the adcs in the cascade in one sample period the number of devices which can be cascaded will be limited. figure 2 shows the effect the additional sclks have on a cascade of three devices.
errata document ?2? AD73360 rev.1 errata document rev.a device 3 - channel 1 device 2 - channel 1 device 1 - channel 1 device 3 - channel 2 device 2 - channel 2 4 8 12 16 device 1 - channel 1 1 64 sclks sclk sdofs sdo figure 2. cascade timing for a three-device cascade choosing sclk rate and sample period for a cascade of a given length, the sclk rate and sample period will determine if the cascade can be used successfully. a low sample rate will allow more time for the adc data to be read. similarly a high sclk rate will transmit the data in a shorter time. since both the sclk rate and sample rate are derived from the same dmclk the number of combinations is limited. as most applications will require a predetermined sample rate, the sclk speed will be the limitating factor in the cascade length that can be used. table i shows the maximum cascade length for a given sclk and sample rate. the table assumes that a mclk of 16.384mhz is used. table i. maximum cascade length with various sclk and sample rates sclk (mhz) max. number sample rate of devices (khz) 16.384 2 64 332 416 58 8.192 1 64 232 316 48 4.096 1 32 216 38 2.048 1 16 28
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