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12-bit, 400 msps a/d converter ad12401 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features up to 400 msps sample rate snr of 63 dbfs @128 mhz sfdr of 70 dbfs @128 mhz vswr of 1:1.5 high or low gain grades wideband ac-coupled input signal conditioning enhanced spurious-free dynamic range single-ended or differential encode signal lvds output levels twos complement output data applications communications test equipment radar and satellite subsystems phased array antennas, digital beams multichannel, multimode receivers secure communications wireless and wired broadband communications wideband carrier frequency systems functional block diagram 005649-001 adc a data ready a data ready b da0?da11 dr_en clk distribution ad12401 post- processing adc b a in clock distribution divide by 2 enc enc orout db0?db11 figure 1. general description the ad12401 is a 12-bit analog-to-digital converter (adc) with a transformer-coupled analog input and digital post- processing for enhanced sfdr. the product operates at up to 400 msps conversion rate with outstanding dynamic performance in wideband carrier systems. the ad12401 requires a 3.7 v analog supply and 3.3 v and 1.5 v digital supplies, and provides a flexible encode signal that can be differential or single ended. no external reference is required. the ad12401 package style is an enclosed 2.9" 2.6" 0.6" module. performance is rated over a 0c to 60c case temperature range. product highlights 1. guaranteed sample rate up to 400 msps. 2. input signal conditioning with optimized dynamic performance to 175 mhz. 3. high and low gain grades available. 4. additional performance options available (sample rates >400 msps or second nyquist zone operation); contact sales. 5. proprietary advanced filter bank (afb?) digital post- processing from v corp technologies, inc.
ad12401 rev. a | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 dc specifications ......................................................................... 3 ac specificationsencode = 400 msps .............................. 4 ac specificationsencode = 360 msps .............................. 5 ac specificationsencode = 326 msps .............................. 6 absolute maximum ratings ............................................................ 8 explanation of test levels ........................................................... 8 esd caution .................................................................................. 8 pin configuration and function descriptions ........................... 10 ter mi nolo g y .................................................................................... 13 typical performance characteristics ........................................... 15 theory of operation ...................................................................... 18 time-interleaving adcs ........................................................... 18 analog input ............................................................................... 18 clock input .................................................................................. 18 digital outputs ........................................................................... 19 power supplies ............................................................................ 19 start-up and reset .................................................................. 19 dr_en ......................................................................................... 19 overrange .................................................................................... 19 gain select ................................................................................... 20 thermal considerations ............................................................ 20 package integrity/mounting guidelines ................................. 20 ad12401 evaluation kit ........................................................... 21 data outputs ............................................................................... 21 layout guidelines ........................................................................... 26 pcb interface .............................................................................. 26 outline dimensions ....................................................................... 28 ordering guide .......................................................................... 28 revision history 4/06rev. 0 to rev. a changes to features and product highlights ............................... 1 changes to table 1............................................................................ 3 changes to table 2............................................................................ 4 changes to table 4............................................................................ 6 changes to table 7............................................................................ 9 changes to figure 5........................................................................ 10 changes to table 9.......................................................................... 11 added gain select section ............................................................ 20 added h/l_gain section............................................................ 21 changes to figure 25...................................................................... 23 changes to the ordering guide.................................................... 28 7/05revision 0: initial version
ad12401 rev. a | page 3 of 28 specifications dc specifications va = 3.7 v, vc = 3.3 v, vd = 1.5 v, 0c t case 60c, unless otherwise noted. table 1. ad12401-xxxkws ad12401-xxxjws parameter case temp test level min typ max min typ max unit resolution 12 bits accuracy no missing codes full iv guaranteed offset error full i ?12 +12 ?12 +12 lsb gain error @ 10 mhz full i ?10 +10 ?10 +10 %fs differential nonlinearity (dnl) 60c v 0.3 0.3 lsb integral nonlinearity (inl) 60c v 0.5 0.5 lsb temperature drift gain error 60c v 0.02 0.02 %/c analog input (ain) full-scale input voltage range 60c v 3.2 1.6 v p-p flatness (10 mhz to 175 mhz) full iv 0.5 1 0.5 1 db input vswr, 50 (300 khz to 175 mhz) 60c v 1.5 1.5 analog input bandwidth 60c v 480 480 mhz power supply 1 supply voltage va full iv 3.6 3.8 3.6 3.8 v vc full iv 3.2 3.4 3.2 3.4 v vd full iv 1.45 1.55 1.45 1.55 v supply current i va (va = 3.7 v) full i 0.95 1.2 0.95 1.2 a i vc (vc = 3.3 v) full i 400 500 400 500 ma i vd (vd = 1.5 v) full i 0.8 1.2 0.8 1.2 a total power dissipation full i 5.7 6.8 5.7 6.8 w encode inputs differential inputs (enc, enc ) input voltage full iv 0.4 0.4 v input resistance 60c v 100 100 input capacitance 60c v 35 35 pf common-mode voltage 60c v 3 3 v single-ended inputs (enc) input voltage full iv 0.4 2 0.4 2 v p-p input resistance 60c v 50 50 logic inputs ( reset ) 2 logic 1 voltage full iv 2.0 2.0 v logic 0 voltage full iv 0.8 0.8 v source i ih 60c iv 3.4 6 3.4 6 ma sink i il 60c iv 0.9 1 0.9 1 ma logic inputs (dr_en) logic 1 voltage full iv 1.7 1.7 v logic 0 voltage full iv 0.7 0.7 v source i ih 60c iv 20 50 20 50 a sink i il 60c iv 30 160 30 160 a
ad12401 rev. a | page 4 of 28 ad12401-xxxkws ad12401-xxxjws parameter case temp test level min typ max min typ max unit logic outputs (dra, drb, output bits) 3 differential output voltage full iv 247 350 454 247 350 454 mv output common-mode voltage full iv 1.125 1.25 1.375 1.125 1.25 1.375 v output high voltage 60c iv 1.602 1.602 v output low voltage 60c iv 0.898 0.898 v 1 tested using input frequency of 70 mhz (see figure 17). 2 refer to table 8 for logic convention on all logic inputs. 3 digital output logic levels: vc = 3.3 v, c load = 8 pf, 2.5 v lvds, r t = 100 . ac specifications 1 encode = 400 msps va = 3.7 v, vc = 3.3 v, vd = 1.5 v, encode = 400 msps, 0c t case 60c, unless otherwise noted. table 2. ad12401-400kws ad12401-400jws parameter case temp test level min typ max min typ max unit dynamic performance snr analog input 10 mhz full i 62 64 60 62 dbfs @ ?1.0 dbfs 70 mhz full i 61.5 63.5 59.5 61.5 dbfs 128 mhz full i 60 63 58 61 dbfs 175 mhz full i 60 62.5 57.5 60.5 dbfs sinad 2 analog input 10 mhz full i 59 63.5 57 61.5 dbfs @ ?1.0 dbfs 70 mhz full i 58.5 63 56.5 61 dbfs 128 mhz full i 57.5 61.5 55.5 59.5 dbfs 175 mhz full i 55 60 53 58 dbfs spurious-free dynamic range 3 analog input 10 mhz full i 69 85 69 85 dbfs @ ?1.0 dbfs 70 mhz full i 69 80 69 80 dbfs 128 mhz full i 66 72 66 72 dbfs 175 mhz full i 62 68 62 68 dbfs image spur 4 analog input 10 mhz full i 60 75 60 75 dbfs @ ?1.0 dbfs 70 mhz full i 60 72 60 72 dbfs 128 mhz full i 60 66 60 66 dbfs 175 mhz full i 57 63 57 63 dbfs offset spur 4 analog input @ ?1.0 dbfs 60c v 65 65 dbfs two-tone imd 5 f1, f2 @ ?6 dbfs 60c v ?75 ?75 dbc analog input frequency range full iv 10 175 10 175 mhz digital input (dr_en) minimum time (low) full iv 5.0 5.0 ns switching specifications conversion rate 6 full iv 396 400 404 396 400 404 msps encode pulse width high (t eh ) 1 60c v 1.25 1.25 ns encode pulse width low (t el ) 1 60c v 1.25 1.25 ns
ad12401 rev. a | page 5 of 28 ad12401-400kws ad12401-400jws parameter case temp test level min typ max min typ max unit digital output parameters valid time (t v ) full iv 3.9 3.9 ns propagation delay (t pd ) 60c v 8.7 8.7 ns rise time, t r (20% to 80%) 60c v 0.3 0.3 ns fall time, t f (20% to 80%) 60c v 0.3 0.3 ns dr propagation delay (t edr ) 60c v 11.2 11.2 ns data to dr skew (t edr ? t pd ) 60c v 2.5 2.5 ns pipeline latency 7 full iv 74 74 cycles start-up time full iv 29 44 87 29 44 87 ms postprocessing configuration time full iv 2.8 2.8 sec aperture delay (t a ) 60c v 2.3 2.3 ns aperture uncertainty (jitter, t j ) 60c v 0.4 0.4 ps rms 1 all ac specifications tested with a single-ended, 2.0 v p-p encode on encode and encode floating. 2 the image spur is included in the sinad measurement. 3 the image spur is not included in the sfdr specification. 4 the image spur is at f s /2 C a in ; the offset spur is at f s /2. 5 f1 = 70 mhz, f2 = 73 mhz. 6 parts are tested with 400 msps encode. device can be clocked at lower encode rates, but specifications are not guaranteed. spe cifications are guaranteed by design for encode 400 msps 1%. 7 pipeline latency is exactly 74 cycles with an additional t pd required for data to emerge. ac specifications 1 encode = 360 msps va = 3.7 v, vc = 3.3 v, vd = 1.5 v, encode = 360 msps, 0c t case 60c, unless otherwise noted. table 3. ad12401-360kws parameter case temp test level min typ max unit dynamic performance snr analog input 10 mhz full i 62 64 dbfs @ ?1.0 dbfs 70 mhz full i 61.5 63.5 dbfs 128 mhz full i 60 63 dbfs sinad 2 analog input 10 mhz full i 59 63.5 dbfs @ ?1.0 dbfs 70 mhz full i 58.5 63 dbfs 128 mhz full i 57.5 61.5 dbfs spurious-free dynamic range 3 analog input 10 mhz full i 69 85 dbfs @ ?1.0 dbfs 70 mhz full i 69 80 dbfs 128 mhz full i 66 72 dbfs image spur 4 analog input 10 mhz full i 60 75 dbfs @ ?1.0 dbfs 70 mhz full i 60 72 dbfs 128 mhz full i 60 66 dbfs offset spur 4 analog input @ ?1.0 dbfs 60c v 65 dbfs two-tone imd 5 f1, f2 @ ?6 dbfs 60c v ?75 dbc analog input frequency range full iv 10 160 mhz digital input (dr_en) minimum time (low) full iv 5.6 ns
ad12401 rev. a | page 6 of 28 ad12401-360kws parameter case temp test level min typ max unit switching specifications conversion rate 6 full iv 356 360 364 msps encode pulse width high (t eh ) 1 60c v 1.38 ns encode pulse width low (t el ) 1 60c v 1.38 ns digital output parameters valid time (t v ) full iv 4.5 ns propagation delay (t pd ) 60c v 8.7 ns rise time, t r (20% to 80%) 60c v 0.3 ns fall time, t f (20% to 80%) 60c v 0.3 ns dr propagation delay (t edr ) 60c v 11.5 ns data to dr skew (t edr ? t pd ) 60c v 2.8 ns pipeline latency 7 full iv 74 cycles start-up time full iv 29 44 87 ms postprocessing configuration time full iv 3.1 sec aperture delay (t a ) 60c v 2.3 ns aperture uncertainty (jitter, t j ) 60c v 0.4 ps rms 1 all ac specifications tested with a single-ended, 2.0 v p-p encode on encode and encode floating. 2 the image spur is included in the sinad specification. 3 the image spur is not included in the sfdr specification. 4 the image spur is at f s /2 C a in ; the offset spur is at f s /2. 5 f1 = 70 mhz, f2 = 73 mhz. 6 parts are tested with 360 msps encode. device can be clocked at lower encode rates, but specifications are not guaranteed. spe cifications are guaranteed by design for encode 360 msps 1%. 7 pipeline latency is exactly 74 cycles with an additional t pd required for data to emerge. ac specifications 1 encode = 326 msps va = 3.7 v, vc = 3.3 v, vd = 1.5 v, encode = 326 msps, 0c t case 60c, unless otherwise noted. table 4. ad12401-326kws ad12401-326jws parameter case temp test level min typ max min typ max unit dynamic performance snr analog input 10 mhz full i 62 64 60 62 dbfs @ ?1.0 dbfs 70 mhz full i 61.5 63.5 59.5 61.5 dbfs 128 mhz full i 60 63 58 61 dbfs sinad 2 analog input 10 mhz full i 59 63.5 57 61.5 dbfs @ ?1.0 dbfs 70 mhz full i 58.5 63 56.5 61 dbfs 128 mhz full i 57.5 61.5 55.5 59.5 dbfs spurious-free dynamic range 3 analog input 10 mhz full i 69 85 69 85 dbfs @ ?1.0 dbfs 70 mhz full i 69 80 69 80 dbfs 128 mhz full i 66 72 66 72 dbfs image spur 4 analog input 10 mhz full i 60 75 60 75 dbfs @ ?1.0 dbfs 70 mhz full i 60 72 60 72 dbfs 128 mhz full i 60 66 60 66 dbfs offset spur 5 analog input @ ?1.0 dbfs 60c v 65 65 dbfs two-tone imd 5 f1, f2 @ ?6 dbfs 60c v ?75 ?75 dbc
ad12401 rev. a | page 7 of 28 ad12401-326kws ad12401-326jws parameter case temp test level min typ max min typ max unit analog input frequency range full iv 10 140 10 140 mhz digital input (dr_en) minimum time (low) full iv 6.2 6.2 ns switching specifications conversion rate 6 full iv 323 326 329 323 326 329 msps encode pulse width high (t eh ) 1 60c v 1.53 1.53 ns encode pulse width low (t el ) 1 60c v 1.53 1.53 ns digital output parameters valid time (t v ) full iv 5.0 5.0 ns propagation delay (t pd ) 60c v 8.7 8.7 ns rise time, t r (20% to 80%) 60c v 0.3 0.3 ns fall time, t f (20% to 80%) 60c v 0.3 0.3 ns dr propagation delay (t edr ) 60c v 11.8 11.8 ns data to dr skew (t edr ? t pd ) 60c v 3.1 3.1 ns pipeline latency 7 full iv 74 74 cycles start-up time full iv 29 44 87 29 44 87 ms postprocessing configuration time full iv 3.4 3.4 sec aperture delay (t a ) 60c v 2.3 2.3 ns aperture uncertainty (jitter, t j ) 60c v 0.4 0.4 ps rms 1 all ac specifications tested with a single-ended, 2.0 v p-p encode on encode and encode floating. 2 the image spur is included in the sinad measurement. 3 the image spur is not included in the sfdr specification. 4 the image spur is at f s /2 ? a in ; the offset spur is at f s /2. 5 f1 = 70 mhz, f2 = 73 mhz. 6 parts are tested with 326 msps encode. device can be clocked at lower encode rates, but specifications are not guaranteed. spe cifications are guaranteed by design for encode 326 msps 1%. 7 pipeline latency is exactly 74 cycles with an additional t pd required for data to emerge.
ad12401 rev. a | page 8 of 28 absolute maximum ratings table 5. parameter value va to agnd 5 v vc to dgnd 4 v vd to dgnd 1.6 v max analog input voltage 6 v (dc) analog input power 18 dbm (ac) encode input voltage 6 v (dc) encode input power 12 dbm (ac) logic inputs ?0.3 v to +4 v storage temperature range, ambient ?65c to +150c operating temperature range 0c to 60c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. explanation of test levels table 6. level description i 100% production tested. ii 100% production tested at 25c and samp le tested at specified temperatures. iii sample tested only. iv parameter is guaranteed by desi gn and characterization testing. v parameter is a typical value only. vi 100% production tested at 25c; guaranteed by design and char acterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad12401 rev. a | page 9 of 28 table 7. output coding (twos complement) a in (v) code kws jws digital output 4095 +1.6 +0.8 0111 1111 1111 . . . . . . . . . . . . 2048 0 0 0000 0000 0000 2047 ?0.000781 to +0.0003905 1111 1111 1111 . . . . . . . . 0 ?1.6 to +0.8 1000 0000 0000 table 8. option pin list with necessary associated circuitry pin name active high logic level type default level associated circuitry within part reset low lvttl high 3.74 k pull-up dr_en high lvttl high weak pull-up (>16 k) 05649-002 encode 100 100 100 100 3.3v 3.3v pecl driver encode figure 2. encode equivalent circuit enc 400mhz dra drb drb dra data out b dr_en data out a n ? 74 n? 1 n ? 73 n n n + 2 n + 1 n + 1 n + 2 n + 3 n + 3 n + 5 n + 7 n + 4 n + 6 n + 8 1/f s t el t eh 1 1 74 clock cycles 05649-003 1. data lost due to assertion of dr_en. latency of 74 encode clock cycles before data valid. 2. if a single-ended sine wave is used for encode, use the zero crossing point (ac-coupled) as the 50% point and apply the same timing information. 3. the dr_en pin is used to synchronize the collection of data into external buffer memories. the dr_en pin can be applied synchronously or asynchronously to the ad12401. if applied asynchronously, dr_en must be held low for a minimum of 5ns to ensure correct operation. the function shuts off dra and drb until the dr_en pin is set high again. dra and drb resume on the next valid dra after dr_en is returned high. if this feature is not required, tie this pin to 3.3v through a 3.74k resistor or leave it floating. notes figure 3. timing diagram 05649-004 t pd t vd enc data out dr enc dr t edr figure 4. highlighted timing diagram
ad12401 rev. a | page 10 of 28 pin configuration and fu nction descriptions 05649-005 samtec connector qte-060-01-l-d-a-k-tr bottom view left side view ain enc board note: 1. for mating connector, use samtec, inc. part no. qse-60-01-l-d-a-k. integral ground plane connections. section a = dgnd, pins 121?124. section b = dgnd, pins 125?128. section c = agnd, pins 129?132. enc 2-56 studs 4 ? johnson sma-50 connect no. 142-0711-821 end view top view pin 1 ain enc enc db0 db0 db2 db2 db4 db4 db6 db6 db8 db8 db10 db10 orout orout drb drb dnc dnc vc vc db1 db1 db3 db3 db5 db5 db7 db7 db9 db9 db11 db11 dnc dnc dnc dnc dnc reset vc vc 1 dra dra da0 da0 da2 da2 da4 da4 da6 da6 da8 da8 da10 da10 dnc dnc vd vd vd vd dnc dr_en da1 da1 da3 da3 da5 da5 da7 da7 da9 da9 da11 da11 dnc dnc vd vd vd vd pin 120 pin 2 pin 40 a b c pin 1 pin 119 1 va va va va agnd agnd dnc dnc dnc dnc dnc dnc dnc agnd agnd agnd agnd agnd agnd agnd va va va va agnd agnd dnc dnc h/l_gain dnc dnc dnc agnd agnd agnd agnd agnd agnd agnd agnd 1 pin 80 pin 79 pin 39 figure 5. pin configuration
ad12401 rev. a | page 11 of 28 table 9. pin function descriptions pin no. mnemonic description 1 to 4 vc digital supply, 3.3 v. 5 reset lvttl. 0 = device reset. minimum width = 200 ns. device resumes operation after 600 ms maximum. 6 to 9, 11, 13 ,15, 49 to 52, 79, 96 to 102, 104 to108 dnc do not connect. 10 drb channel b data ready. complement output. 12 drb channel b data ready. true output. 14 orout overrange. complement output. 16 orout overrange. true output 1 = overranged, 0 = normal operation. 17 db11 channel b data bit 11. complement output bit. 18 db10 channel b data bit 10. complement output bit. 19 db11 channel b data bit 11. true output bit. 20 db10 channel b data bit 10. true output bit. 21 db9 channel b data bit 9. complement output bit. 22 db8 channel b data bit 8. complement output bit. 23 db9 channel b data bit 9. true output bit. 24 db8 channel b data bit 8. true output bit. 25 db7 channel b data bit 7. complement output bit. 26 db6 channel b data bit 6. complement output bit. 27 db7 channel b data bit 7. true output bit. 28 db6 channel b data bit 6. true output bit. 29 db5 channel b data bit 5. complement output bit. 30 db4 channel b data bit 4. complement output bit. 31 db5 channel b data bit 5. true output bit. 32 db4 channel b data bit 4. true output bit. 33 db3 channel b data bit 3. complement output bit. 34 db2 channel b data bit 2. complement output bit. 35 db3 channel b data bit 3. true output bit. 36 db2 channel b data bit 2. true output bit. 37 db1 channel b data bit 1. complement output bit. 38 db0 channel b data bit 0. compleme nt output bit. db0 is lsb. 39 db1 channel b data bit 1. true output bit. 40 db0 channel b data bit 0. true output bit. db0 is lsb. 41 to 48 vd digital supply, 1.5 v. 53 da11 channel a data bit 11. complement output bit. 54 da10 channel a data bit 10. complement output bit. 55 da11 channel a data bit 11. true output bit. 56 da10 channel a data bit 10. true output bit. 57 da9 channel a data bit 9. complement output bit. 58 da8 channel a data bit 8. complement output bit. 59 da9 channel a data bit 9. true output bit. 60 da8 channel a data bit 8. true output bit. 61 da7 channel a data bit 7. complement output bit. 62 da6 channel a data bit 6. complement output bit. 63 da7 channel a data bit 7. true output bit. 64 da6 channel a data bit 6. true output bit. 65 da5 channel a data bit 5. complement output bit. 66 da4 channel a data bit 4. complement output bit. 67 da5 channel a data bit 5. true output bit. 68 da4 channel a data bit 4. true output bit.
ad12401 rev. a | page 12 of 28 pin no. mnemonic description 69 da3 channel a data bit 3. complement output bit. 70 da2 channel a data bit 2. complement output bit. 71 da3 channel a data bit 3. true output bit. 72 da2 channel a data bit 2. true output bit. 73 da1 channel a data bit 1. complement output bit. 74 da0 channel a data bit 0. compleme nt output bit. da0 is lsb. 75 da1 channel a data bit 1. true output bit. 76 da0 channel a data bit 0. true output bit. da0 is lsb. 77 dr_en data ready enable, typically dnc. see the dr_en section. 78 dra channel a data ready. complement output. 80 dra channel a data ready. true output. 103 h/l gain gain select pin. ground for low gain mode (kws); pull up to 3.3 v for high gain mode (jws). 81 to 95, 109 to 112, 129 to 132 1 agnd analog ground. 113 to 120 va analog supply, 3.7 v. 121 to 128 1 dgnd digital ground. 1 internal ground plane connectio ns: section a = dgnd, pin 121 to pin 124; section b = dgnd, pin 125 to pin 128; section c = agn d, pin 129 to pin 132.
ad12401 rev. a | page 13 of 28 terminology analog bandwidth the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. aperture delay the delay between the 50% point on the rising edge of the encode command and the instant at which the analog input is sampled. analog input vswr (50 ) vswr is a ratio of the transmitted and reflected signals. the vswr can be related to input impedance. = ( z l ? z s )/( z l + z s ) where: z l = actual load impedance. z s = reference impedance. vswr = (1 ? ||)/(1 +||) aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. differential nonlinearity the deviation of any code width from an ideal 1 lsb step. distortion, image spur the ratio of the rms signal amplitude to the rms signal ampli- tude of the image spur, reported in dbfs. the image spur, a result of gain and phase errors between two time-interleaved conversion channels, is located at f s /2 ? f ain . distortion, offset spur the ratio of the rms signal amplitude to the rms signal ampli- tude of the offset spur, reported in dbfs. the offset spur, a result of offset errors between two time-interleaved conversion channels, is located at f s /2. effective number of bits (enob) calculated from the measured snr based on the equation 026 db761 . . snr enob measured ? = encode pulse width/duty cycle pulse width high is the minimum amount of time the encode pulse should be left in logic 1 state to achieve rated perform- ance; pulse width low is the minimum time the encode pulse should be left in low state. full-scale input power expressed in dbm. computed using the equation power full-scale = 10 log (( v 2 full-scale rms )/(| z input | 0.001)) full-scale input voltage range the maximum peak-to-peak input signal magnitude that results in a full-scale response, 0 dbfs on a single-tone input signal case. any magnitude increase from this value results in an overrange condition. gain error the difference between the measured and ideal full-scale input voltage range of the adc. harmonic distortion, second the ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dbfs. harmonic distortion, third the ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dbfs. integral nonlinearity the deviation of the transfer function from a reference line measured in fractions of 1 lsb using a best straight line determined by a least square curve fit. maximum conversion rate the maximum encode rate at which the image spur calibration degrades no more than 1 db (when the image spur is 70 db). minimum conversion rate the minimum encode rate at which the image spur calibration degrades no more than 1 db (when the image spur is 70 db). offset error the dc offset imposed on the input signal by the adc, reported in lsb (codes). output propagation delay the delay between a differential crossing of encode and encode (or zero crossing of a single-ended encode). pipeline latency the number of clock cycles the output data lags the correspond- ing clock cycle. power supply rejection ratio (psrr) the ratio of power supply voltage change to the resulting adc output voltage change.
ad12401 rev. a | page 14 of 28 signal-to-noise-and-distortion (sinad) the ratio of the rms signal amplitude (set 1 db below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc and image spur. signal-to-noise ratio (snr) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral compo- nents, excluding the first five harmonics and dc. spurious-free dynamic range (sfdr) the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component, except the image spur. the peak spurious component may or may not be a harmonic. it can be reported in dbc (that is, degrades as signal level is lowered) or dbfs (always related back to converter full-scale). tot a l noi s e calculated as ) ( 10001.0 10 dbfs signal snr fs noise dbc dbm zv ?? = where: z is the input impedance. fs is the full scale of the device for the frequency in question. snr is the value of the particular input level. signal is the signal level within the adc reported in db below full scale. this value includes both thermal and quantization noise. two-tone intermodulation distortion rejection the ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product; reported in dbc. two-tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. it can be reported in dbc (that is, degrades as signal level is lowered) or in dbfs (always related back to converter full-scale) .
ad12401 rev. a | page 15 of 28 typical performance characteristics 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 0 20 40 60 80 100 120 140 160 180 200 1 05649-006 frequency (mhz) db snr = 63.26db sfdr = 76.77dbc sinad = 62.97db image spur = ?76.69dbc 2 3 4 5 6 x n figure 6. fft: f s = 400 msps, a in = 10.123 mhz @ C1.0 dbfs; x = image spur, n = interleaved offset spur 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 0 20 40 60 80 100 120 140 160 180 200 05649-007 frequency (mhz) db 1 2 3 5 6 x 4 n snr = 62.61db sfdr = 78.03dbc sinad = 62.41db image spur = ?86.28dbc figure 7. fft: f s = 400 msps, a in = 70.123 mhz @ C1.0 dbfs; x = image spur, n = interleaved offset spur 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 0 20 40 60 80 100 120 140 160 180 200 05649-008 frequency (mhz) db n 5 2 1 4 x 6 3 snr = 61.54db sfdr = 74.03dbc sinad = 60.92db image spur = ?75.09dbc figure 8. fft: f s = 400 msps, a in = 128.123 mhz @ C1.0 dbfs; x = image spur, n = interleaved offset spur 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 0 20 40 60 80 100 120 140 160 180 200 05649-009 frequency (mhz) db n 1 6 3 4 5 2 x snr = 60.74db sfdr = 71.57dbc sinad = 60.29db image spur = ?82.52dbc figure 9. fft: f s = 400 msps, a in = 175.123 mhz @ C1.0 dbfs; x = image spur, n = interleaved offset spur 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 0 20 40 60 80 100 120 140 160 180 200 05649-010 frequency (mhz) db 1 2 2f2 ? f1 f2 + f1 2f1 ? f2 2f2 + f1 2f1 + f2 f2 ? f1 figure 10. two-tone intermodulation distortion (25.1 mhz and 28.1 mhz; f s = 400 msps); x = image spur, n = interleaved offset spur 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 0 20 40 60 80 100 120 140 160 180 200 05649-011 frequency (mhz) db 1 2 f2 + f1 f2 + f1 2f2 ? f1 2f2 + f1 2f1 + f2 2f1 ? f2 figure 11. two-tone intermodulation distortion (70.1 mhz and 73.1 mhz; f s = 400 msps); x = image spur, n = interleaved offset spur
ad12401 rev. a | page 16 of 28 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 0 20 40 60 80 100 120 140 160 180 200 05649-012 frequency (mhz) db 1 2 f2 ? f1 f2 + f1 2f1 + f2 2f2 + f1 2f1 ? f2 2f2 ? f1 figure 12. two-tone intermodulation distortion (172.1 mhz and 175.1 mhz; f s = 400 msps), sfdr = 70 dbc; x = image spur, n = interleaved offset spur 05649-040 frequency (mhz) gain (db) ?0.4 ?0.5 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 10.7 35.0 59.3 83.6 108 132 157 181 205 229 figure 13. interleaved gain flatness 05649-041 analog input level (db) distortion (dbfs) 60 95 90 85 80 75 70 65 100 0 50 40 30 20 10 70 6 0 third harmonic second harmonic image spur figure 14. second/third harmonics and image spur vs. analog input level; f s = 400 msps, a in = 70 mhz 05649-042 analog input frequency (mhz) harmonics (dbc) 60 65 70 75 80 85 90 95 0 20 40 60 80 100 120 140 160 180 second harmonic third harmonic image spur figure 15. harmonics vs. analog input frequency 64.5 64.0 63.5 63.0 62.5 62.0 61.5 61.0 60.5 60.0 59.5 200 150 100 50 0 analog input frequency (mhz) snr (dbfs) 05649-016 figure 16. snr vs. analog input frequency 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 806040200 input frequency (mhz) vd supply current (a) 180160140120100 200 05649-017 figure 17. vd supply current vs. a in frequency
ad12401 rev. a | page 17 of 28 05649-043 analog input frequency analog input level ?4.78 ?5.20 ?4.36 ?3.94 ?3.52 ?3.10 ?2.68 ?2.26 ?1.84 ?1.42 ?1.00 0.100 0.530 0.960 1.390 1.820 2.250 2.680 3.110 3.540 3.970 4.400 figure 18. low frequency gain flatness
ad12401 rev. a | page 18 of 28 theory of operation the ad12401 uses two high speed, 12-bit adcs in a time- interleaved configuration to double the sample rate, while maintaining a high level of dynamic range performance. the digital output of each adc channel is calibrated using a proprietary digital postprocessing technique, advanced filter bank (afb). afb is implemented using a state-of-the-art field programmable gate array (fpga) and provides a wide bandwidth and wide temperature match for any gain, phase, and clock timing errors between each adc channel. time-interleaving adcs when two adcs are time-interleaved, gain and/or phase mismatches between each channel produce an image spur at f s /2 ? f ain and an offset spur, as shown in figure 19 . these mismatches can be the result of any combination of device tolerance, temperature, and frequency deviations. ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 05649-018 0 20 40 60 80 100 120 140 160 180 200 frequency (mhz) db image spur 1 2 3 4 5 6 n offset spur x figure 19. image spur due to mismatches between two interleaved adcs (no afb digital postprocessing) figure 20 shows the performance of a similar converter with on-board afb postprocessing implemented. the C44 dbfs image spur has been reduced to C77 dbfs and, as a result, the dynamic range of this time-interleaved adc is no longer limited by the channel matching. 05649-019 0 20 40 60 80 100 120 140 160 180 200 frequency (mhz) db ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 image spur offset spur 1 2 3 4 5 6 n x figure 20. ad12401 with afb digital postprocessing the relationship between image spur and channel mismatches is captured in table 10 for specific conditions. table 10. image spur vs. channel mismatch gain error (%) aperture delay error (ps) image spur (dbc) 1 15 C40 0.25 2.7 C54 0.2 1.1 C62 0.025 0.5 C70 for a more detailed description of time-interleaving in adcs and a design example using the ad12401, see advanced digital post- processing techniques enhance performance in time-interleaved adc systems , which was published in the august, 2003 edition of the analog dialogue ( www.analog.com/analogdialogue ). analog input the ad12401 analog input is ac-coupled using a proprietary transformer front-end circuit that provides 1 db of gain flatness over the first nyquist zone and a ?3 db bandwidth of 480 mhz. this front-end circuit provides a vswr of 1.5 (50 ) over the first nyquist zone, and the typical full-scale input is 3.2 v p-p. the mini-circuits? hela-10 amplifier module can be used to drive the input at these power levels. clock input the ad12401 requires a 400 msps encode that is divided by 2 and distributed to each adc channel, 180 out of phase from each other. internal ac-coupling and bias networks provide the framework for flexible clock input requirements that include single-ended sine wave, single-ended pecl, and differential pecl. while the ad12401 is tested and calibrated using a single-ended sine wave, properly designed pecl circuits that provide fast slew rates (>1 v/ns) and minimize ringing result in comparable dynamic range performance. aperture jitter and harmonic content are two major factors to consider when designing the input clock circuit for the ad12401. the relationship between aperture jitter and snr can be characterized using the following equation. the equation assumes a full-scale, single-tone input signal. snr = () ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? + + ? 2 2 2 2 22 2 1 5.1 1 020log20 n noiserms n jrms a v tf where: f a = input frequency. t jrms = aperture jitter. n = adc resolution (bits). = adcdnl (lsb). v noiserms = adc input noise (lsb rms).
ad12401 rev. a | page 19 of 28 figure 21 displays the application of this relationship to a full- scale, single-tone input signal on the ad12401, where the dnl was assumed to be 0.4 lsb, and the input noise was assumed to be 0.8 lsb rms. the vertical marker at 0.4 ps displays the snr at the jitter level present in the ad12401 evaluation system, including the jitter associated with the ad12401 itself. 57 58 59 60 61 62 63 64 65 05649-020 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 aperture jitter (ps rms) snr (db) a in = 10mhz a in = 65mhz a in = 128mhz a in = 180mhz figure 21. snr vs. aperture jitter in addition to jitter, the harmonic content of the single-ended sine wave clock sources must be controlled. the clock source used in the test and calibration process has a harmonic per- formance that is better than 60 dbc. additionally, when using pecl or other square-wave clock sources, unstable behavior, such as overshoot and ringing, can affect phase matching and degrade the image spur performance. digital outputs the ad12401s digital postprocessing circuit provides two parallel, 12-bit, 200 msps data output buses. by providing two output busses that operate at one half the conversion rate, the ad12401 eliminates the need for large, expensive, high power demultiplexing circuits. the output data format is twos com- plement, maintaining the standard set by other high speed adcs, such as the ad9430 and ad6645 . data-ready signals are provided for facilitating proper timing in the data capture circuit. power supplies the ad12401 requires three different supply voltages: a 1.5 v supply for the digital postprocessing circuit, a 3.3 v supply to facilitate digital i/o through the system, and a 3.8 v supply for the analog conversion and clock distribution circuits. the ad12401 incorporates two key features that result in solid psrr performance. first, on-board linear regulators are used to provide an extra level of power supply rejection for the analog circuits. the linear regulator used to supply the adcs provides an additional 60 db of rejection at 100 khz. second, to address higher frequency noise (where the linear regulators rejection degrades), the ad12401 incorporates high quality ceramic decoupling capacitors. while this product was designed to provide good psrr performance, system designers need to be aware of the risks associated with switching power supplies and consider using linear regulators in their high speed adc systems. switching power supplies typically produces both conducted and radiated energy that result in common-/differential-mode emi currents. any system that requires 12-bit performance has very little room for errors associated with power supply emi. for exam- ple, a system goal of 74 db dynamic range performance on the ad12401 requires noise currents that are less than 4.5 a and noise voltages of less than 225 v in the analog input path. startup and reset the ad12401s fpga configuration is stored in the on-board eprom and loaded into the fpga when power is applied to the device. the reset pin (active low) allows the user to reload the fpga in case of a low digital supply voltage condition or a power supply glitch. pulling the reset pin low pulls the data- ready and output bits high until the fpga is reloaded. the reset pin should remain low for a minimum of 200 ns. on the rising edge of the reset pulse, the ad12401 starts loading the configuration into the fpga. the reload process requires a maximum of 87 ms to complete. valid signals on the data-ready pins indicate the reset process is complete. in addition, system designers must be aware of the thermal conditions of the ad12401 at startup. if large thermal imbalances are present, the ad12401 can require additional time to stabilize before providing specified image spur performance. dr_en the dr_en pin is used to synchronize the collection of data into external buffer memories. dr_en must be held low for a minimum amount of time (see table 2 through table 4 for each encode rate) to ensure correct operation. the function shuts off dra and drb until the dr_en pin is set high again. dra and drb resume on the next valid dra after dr_en is released. if this feature is not required, tie this pin to 3.3 v through a 3.74 k. overrange the differential orout pins are used to determine if the ad12401 input is overranged. orout timing is identical to the channel b data. if the orout pin is high, then the channel b data coincident with the overra nge indication or the channel a data immediately preceding it resulted from an overrange input. if the orout pin is low, the operation is normal.
ad12401 rev. a | page 20 of 28 gain select the ad12401 is graded out for the gain mode and should be ordered accordingly: the ad12401- xxxkws is calibrated in the low gain mode, and the ad12401-xxxjws is calibrated in the high gain mode. performance is not guaranteed if either grade is used in the wrong gain mode. the high gain mode sets the analog input voltage to approximately 1.6 v p-p. the low gain mode sets the analog input voltage to approximately 3.2 v p-p. for high gain mode, the user should pull pin 103 (h/l_gain) up to 3.3 v using a 4.02 k resistor. for low gain mode, the user should ground pin 103. thermal considerations the module is rated to operate over a case temperature of 0c to 60c. to maintain the tight channel matching and reliability of the ad12401, care must be taken to ensure that proper thermal and mechanical considerations have been made and addressed to ensure case temperature is kept within this range. each application requires evaluation of the thermal manage- ment as applicable to the system design. this section provides information that should be used in the evaluation of the ad12401s thermal management for each specific use. in addition to the radiation of heat into its environment, the ad12401 module enables the flow of heat through the mounting studs and standoffs as they contact the motherboard. as described in the package integrity/mounting guidelines section, the module should be secured to the motherboard using 2-56 nuts (washer use is optional). the torque on the nuts should not exceed 32-inch ounces. using a thermal grease at the standoffs results in better thermal coupling between the board and module. depending on the ambient conditions, airflow can be necessary to ensure the components in the module do not exceed their maximum operating temperature. for reliability, the most sensitive component has a maximum junction temperature rating of 125c. figure 22 and figure 23 provide a basic guideline for two key thermal management decisions: the use of thermal interface material between the module bottom cover/mother board and airflow. figure 21 characterizes the typical thermal profile of an ad12401 that is not using thermal interface material. figure 22 provides the same information for a configuration that uses gap-filling thermal interface material. in this case, thermagon t-flex 600 series?, 0.040 thickness, was used. these profiles show that the maximum die temperature is reduced by approximately 2c when thermal interface material is used. figure 22 and figure 23 also provide a guideline for determining the airflow requirements for given ambient conditions. for example, a goal of 120c die temperature in a 40c ambient environment without the use of thermal interface material requires an airflow of 100 lfm. from a channel-matching perspective, the most important consideration is external thermal influences. it is possible for thermal imbalances in the end application to adversely affect the dynamic performance. due to the temperature dependence of the image spur, substantial deviation from the factory cali- bration conditions can have a detrimental effect. unbalanced thermal influences can cause gradients across the module, and performance degradation can result. examples of unbalanced thermal influences can include large heat dissipating elements near one side of the ad12401, or obstructed airflow that does not flow uniformly across the module. the thermal sensitivity of the module can be affected by a change in thermal gradient across the module of 2c. 05649-021 airflow condition tempe r a ture (c) 20 30 40 50 60 70 80 90 100 110 typical junction case ambient no airflow 100 lfm 300 lfm figure 22. typical temperature vs. airflow with no module/board interface material (normalized to 60c module case temperature) typical junction case ambient 05649-022 airflow condition temperature ( c) 20 30 40 50 60 70 80 90 100 110 no airflow 100 lfm 300 lfm figure 23. typical temperature vs. airflow with t-flex module/board interface material (normalized to 60c module case temperature ambient) package integrity/mounting guidelines the ad12401 is a printed circui t board (pcb)-based module designed to provide mechanical stability and to support the intricate channel-to-channel matching necessary to achieve high dynamic range performance. the module should be secured to the motherboard using 2-56 nuts (washer use is optional). the torque on the nuts should not exceed 32-inch ounces.
ad12401 rev. a | page 21 of 28 the sma edge connectors (ain and enc/ enc ) are surface mounted to the board to achieve minimum height of the module. when attaching and routing the cables, one must ensure they are stress-relieved and do not apply stress to the sma connector/board. the presence of stress on the cables can degrade electrical performance and mechanical integrity of the module. in addition to the routing precautions, the smallest torque necessary to achieve consistent performance should be used to secure the system cable to the ad12401s sma connectors. the torque should never exceed 5-inch pounds. any disturbances to the ad12401 structure, including removing the covers or mounting screws, invalidates the calibration and results in degraded performance. see the outline dimensions section for mounting stud dimensions, see figure 38 for pcb interface locations. mounting stud length typically accommodates a pcb thickness of 0.093". consult sales if board thickness requirements exceed this dimension. ad12401 evaluation kit the ad12401/kit offers an easy way to evaluate the ad12401. the ad12401/kit includes the ad12401 mounted on an adapter card, the ad12401 evaluation board, the power supply cables, a 225 mhz buffer memory fifo board, and the dual analyzer software. the user must supply a clock source, an analog input source, a 1.5 v power supply, a 3.3 v power supply, a 5 v power supply, and a 3.8 v power supply. the clock source and analog input source connect directly to the ad12401. the power supply cables (included) and a parallel port cable (not included) connect to the evaluation board. the ad12401 works on the same evaluation board as the ad12400 and the ad12500: gs08054. power connector power is supplied to the board via a detachable 12-lead power strip (three 4-pin blocks). table 11. power connector supply description va 3.7 v analog supply for the adc (950 ma typ) vc 3.3 v digital supply for the adc outputs (400 ma typ) vd 1.5 v 1 digital supply for the fpga (1.25 a max, 0.7 a typ) vb 5.0 v digital supply for the buffer memory board (400 ma typ) 1 the power supply cable has an approximately 100 mv drop. the vd supply current is dependent on the an alog input frequency (see figure 17 ). analog input the analog input source connects directly to an sma on the ad12401. h/l_gain the h/l_gain select jumper, pin 103, should be on for low gain mode (ad12401-xxxkws). th e h/l_gain select jumper should be removed for high gain mode, ad12401-xxxjws. encode the single-ended or differential encode signal connects directly to sma connector(s) on the ad12401. a single-ended sine wave at 10 dbm connected to the encode sma is recommended. a low jitter clock source (<0.5 ps) is recommended to properly evaluate the ad12401. data outputs the ad12401xxxkws digital outputs are available at the 80-pin connector, p2, on the evaluation board. the ad12401/kit comes with a buffer memory fifo board connected to p2, which provides the interface to the parallel port of a pc. the dual analyzer software is compatible with windows? 95, windows 98, windows 2000, and windows nt?. the buffer memory fifo board can be removed, and an external logic analyzer or other data acquisition module can be connected to this connector, if required. adapter card the ad12401 is attached to an adapter card that interfaces to the evaluation board through a 120-pin connector, p1, which is on the top side of the evaluation board. digital postprocessing control the evaluation board has a 2-pin jumper, labeled afb, that allows the user to enable/disable the digital postprocessing. the digital postprocessing is active when the afb jumper is applied. when the jumper is removed, the fpga is set to a passthrough mode, which demonstrates to the user the performance of the ad12401 without the digital postprocessing. reset the ad12401s fpga configuration is stored in an eeprom and loaded into the fpga when power is applied to the ad12401. the reset switch, sw1 (active low), allows the user to reload the fpga in case of a low voltage condition or a power supply glitch. depressing the reset switch pulls the data-ready and output bits high. the reset switch should remain low for a minimum of 200 ns. on the rising edge of the reset pulse, the ad12401 starts loading the configuration into the on-module fpga. the reload process requires a maximum of 600 ms to complete. valid signals on the data-ready pins indicate the reset process is complete. the ad12401 is not compatible with the hsc-adc-eval- dc/sc hardware or software.
ad12401 rev. a | page 22 of 28 table 12. evaluation board bill of materials (bom) item no. qty. ref-des device package value, mfg 1 2 c3, c5 capacitors 603 0.1 f, 25 v 2 2 c4, c6 capacitors 805 10 f, 6.3 v 3 1 r9 resistor 603 4.02 k, 1% 4 1 afb 2-pin header/jumper pin strip molex/gc/weldon 5 1 p2 80-pin dual connector assembly surface-mount post header amp 6 1 sw1 switch push button spst 6 mm panasonic 7 3 j2, j3, j4 4-pin header power connecters pin strip wieland 8 1 p1 60-pin dual-socket assembly surface-mount samtec 9 1 pcb ad12401 interface board gs08054 pcb 05649-023 afb 3.3vc pass h/l_gain 3.3vc h/l_gain nyq 3.3vc nyq dither jp2 e12 jp3 e13 spare1 e14 spare2 e18 3.3vc other spare1 spare2 dgnd 1.5vd digital j3 1 2 3 4 dgnd +va agnd analog j2 1 2 3 4 digital j4 3.3vc 3.8v dgnd 1 2 3 4 5v c4 10 f c3 0.1 f dgnd dgnd 5v 5v c6 10 f c5 0.1 f 3.3vc dgnd dgnd 3.3vd 3.3vd select d jp4 e17 select d reset 1.5v sense e22 dgnd evq-pac85r 1 2 3 4 e1 r8 4.02k r9 4.02k r10 4.02k r11 4.02k
ad12401 rev. a | page 23 of 28 05649-024 drb dnc 3.3vc dnc dnc 3.3vc dnc reset dnc dnc db8 db9 db10 db11 db4 db5 db6 db7 db2 db3 db0 db1 14 16 18 20 22 24 26 28 30 32 34 36 38 40 122 124 2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 121 123 4 6 8 10 12 p1:a dgnd qse?60?01?l?d?a?k dgnd drb dnc db8 db6 db4 db2 db0 gnd gnd gnd gnd db11 db9 db7 db5 db3 db1 db11 pass 1.5vd 1.5vd da10 da11 dnc da8 da7 da10 da9 da4 da3 da6 da5 da2 da1 da0 dra dr_en 54 56 58 60 62 64 66 68 70 72 74 76 78 80 126 128 42 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 125 127 44 46 48 50 52 p1:b dgnd qse?60?01?l?d?a?k dgnd dnc da8 da6 da4 da2 da0 dra gnd gnd gnd gnd da11 da9 da7 da5 da3 da1 dnc dnc agnd agnd 3.3vc dnc dnc dnc wp 94 96 98 100 102 104 106 108 110 112 114 116 118 120 130 132 82 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 129 131 84 86 88 90 92 p1:c agnd agnd qse?60?01?l?d?a?k agnd agnd dnc gnd gnd gnd e2 e19 dnc dnc dnc h/l_gain dnc +va +va 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 dgnd p2:c amp104655-9 dra da11 da10 dra da11 da10 da9 da9 da8 da8 da7 da7 da6 da6 da5 da5 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 p2:d amp104655-9 da3 da1 da0 da3 da2 da2 da4 da4 da1 da0 or or 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 dgnd p2:a amp104655-9 drb db11 db10 drb db11 db10 db9 db9 db8 db8 db7 db7 db6 db6 db5 db5 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p2:b a mp104655-9 db3 db1 db0 db3 db2 db2 db4 db4 db1 db0 or or ad1240x db10 orout orout figure 25. evaluation board
ad12401 rev. a | page 24 of 28 05649-025 figure 26. power plane 1 05649-026 figure 27. power plane 2 05649-027 figure 28. first ground plane 05649-028 figure 29. second ground plane 05649-029 figure 30. top side copper 05649-030 figure 31. bottom side copper
ad12401 rev. a | page 25 of 28 05649-034 05649-031 figure 32. top mask figure 35. evaluation adapter board, top silkscreen 05649-035 05649-032 figure 36. evaluation adapter board, analog and digital layers figure 33. top silkscreen 05649-037 05649-033 figure 34. bottom silkscreen figure 37. evaluation adapter board, bottom silkscreen
ad12401 rev. a | page 26 of 28 layout guidelines the ad12401 requires a different approach from traditional high speed adc system layouts. while the ad12401s internal pcb isolates digital and analog grounds, these planes are tied together through the products aluminum case structure. therefore, the decision to isolate the analog and digital grounds on the system pcb has additional factors to consider. for example, if the ad12401 is attached with conductive thermal interface material to the system pcb, there is essentially no benefit to keeping the analog and digital ground planes separate. if neither thermal interface material nor nonconductive interface material is used, system architects must consider the ground loop that is created if analog and digital planes are tied together directly under the ad12401. this emi-based decision must be considered on a case-by-case basis and is largely dependent on the other sources of emi in the system. one critical consideration is that a 12-bit perform- ance requirement (C74 dbc) requires keeping conducted emi currents (referenced to the input of the ad12401) below 4.5 a. all the characterization and testing of the ad12401 is performed using a system that isolated these ground planes. if thermal interface material is used in the final system design, the following layout factors need to be considered: open solder mask on the area that contacts the interface material and the thickness of the ground plane. while this should be analyzed in each specific system design, the use of solder mask can negate any advantage achieved by using the thermal interface material, and its use should be carefully considered. the ground plane thickness does not have a major impact on the thermal per- formance, but if design margin is slight, additional thickness can yield incremental improvements. pcb interface figure 38 provides the mounting hole footprint for assembling the ad12401 to the second-level assembly. the diagram is referenced to the center of the mating qte connector. refer to the qte/qse series connector documentation at www.samtec.com for the smt footprint of the mating connector. the top view of the second-level assembly footprint provides a diagram of the second-level assembly locating tab locations for mating the samtec qte-060-01-l-a-k-tr terminal strip on the ad12401 to a qse-060-01-l-a-k-tr socket on the second- level assembly. the diagram is referenced to the center of the qte terminal strip on the ad12401 and the mounting holds for the screws, which holds the ad12401 to the second-level assembly board. the relationship of these locating tabs is based on information provided by samtec (connector supplier) and should be verified with samtec by the customer. mating and unmating forcesthe knifing or peeling action of applying force to one end or one sidemust be avoided to prevent damage to the connector and guidepost.
ad12401 rev. a | page 27 of 28 05649-038 1.184 [30.0673] 1.184 [30.0673] r.0470[r1.19] 6 1.025 [26.0164] 2 0.105 [2.6670] 2 0.396 [10.0456] 2 2.159 [54.8258] 2 1.025 [26.0164] 2 .000 [.0000] 0.000 [.0000] 0, 0 datum = center of connector figure 38. top view of interface pcb assembly
ad12401 rev. a | page 28 of 28 outline dimensions top view side view 3.190 typ pin 1 ain enc enc 2.890 max board 2.328 typ 0.856 typ 0.256 typ 0.267 typ samtec connector qte-060-01-l-d-a-k-tr bottom view 1.773 1.753 2.060 2.040 0.270 2 ? 0.505 typ 2 ? 0 .700 max 0.175 typ 0.200 typ 2-56 studs 4 ? 0.600 max johnson sma-50 ohm connect no. 142-0711-821 2.590 max 2.060 2.040 040606-a figure 39. non-hermetic hybridsurface-mounted parts (ws-suffix) dimensions shown in inches tolerances: 0.xxx = 5 mils ordering guide model temperature range package description ad12401-326kws 0c to 60c (case) 2.9" 2.6" 0.6" module ad12401-326jws 0c to 60c (case) 2.9" 2.6" 0.6" module ad12401-360kws 0c to 60c (case) 2.9" 2.6" 0.6" module ad12401-400kws 0c to 60c (case) 2.9" 2.6" 0.6" module ad12401-400jws 0c to 60c (case) 2.9" 2.6" 0.6" module ad12401/kit 1 evaluation kit 1 the encode rate and gain mode must be selected when ordering the ad12401/kit. the st andard ad12401/kit is configured for low gain mode at 400 msps. ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05649-0-4/06(a)

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